| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.35 | 100.00 | 96.08 | 100.00 | 100.00 | 100.00 | 100.00 |
| T757 | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.977507767 | Jan 17 12:22:45 PM PST 24 | Jan 17 12:23:18 PM PST 24 | 9813788406 ps | ||
| T758 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3120171982 | Jan 17 12:22:19 PM PST 24 | Jan 17 12:22:21 PM PST 24 | 13722851 ps | ||
| T759 | /workspace/coverage/xbar_build_mode/14.xbar_same_source.826708589 | Jan 17 12:24:39 PM PST 24 | Jan 17 12:24:40 PM PST 24 | 56348133 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3356176089 | Jan 17 12:21:29 PM PST 24 | Jan 17 12:21:49 PM PST 24 | 4139586569 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3837931778 | Jan 17 12:20:31 PM PST 24 | Jan 17 12:21:50 PM PST 24 | 4691852057 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1718123117 | Jan 17 12:25:04 PM PST 24 | Jan 17 12:26:05 PM PST 24 | 25902014094 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1733564558 | Jan 17 12:21:07 PM PST 24 | Jan 17 12:22:27 PM PST 24 | 21251177663 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2575497321 | Jan 17 12:24:43 PM PST 24 | Jan 17 12:24:48 PM PST 24 | 99179060 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3917984500 | Jan 17 12:23:27 PM PST 24 | Jan 17 12:23:39 PM PST 24 | 1059605003 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2409333317 | Jan 17 12:24:24 PM PST 24 | Jan 17 12:25:11 PM PST 24 | 795397312 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.285006326 | Jan 17 12:18:20 PM PST 24 | Jan 17 12:18:27 PM PST 24 | 855912659 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3070717758 | Jan 17 12:25:08 PM PST 24 | Jan 17 12:25:16 PM PST 24 | 49337557 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/6.xbar_error_random.696237823 | Jan 17 12:27:09 PM PST 24 | Jan 17 12:27:28 PM PST 24 | 85307173 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3216223440 | Jan 17 12:21:23 PM PST 24 | Jan 17 12:21:37 PM PST 24 | 2201286678 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.503023243 | Jan 17 12:21:39 PM PST 24 | Jan 17 12:23:02 PM PST 24 | 12351867384 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.4179849275 | Jan 17 12:24:48 PM PST 24 | Jan 17 12:24:57 PM PST 24 | 55962762 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1403397874 | Jan 17 12:25:31 PM PST 24 | Jan 17 12:25:42 PM PST 24 | 4029645602 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1261622471 | Jan 17 12:23:59 PM PST 24 | Jan 17 12:24:10 PM PST 24 | 153898878 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.51617473 | Jan 17 12:23:40 PM PST 24 | Jan 17 12:23:44 PM PST 24 | 56983403 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.747854983 | Jan 17 12:25:01 PM PST 24 | Jan 17 12:25:52 PM PST 24 | 10445654650 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/18.xbar_random.2656973289 | Jan 17 12:21:50 PM PST 24 | Jan 17 12:21:53 PM PST 24 | 62641129 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.121319198 | Jan 17 12:21:49 PM PST 24 | Jan 17 12:21:58 PM PST 24 | 2016330572 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1529303173 | Jan 17 12:23:45 PM PST 24 | Jan 17 12:23:55 PM PST 24 | 85540088 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.674317096 | Jan 17 12:24:24 PM PST 24 | Jan 17 12:26:43 PM PST 24 | 1924075105 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1114034721 | Jan 17 12:20:01 PM PST 24 | Jan 17 12:20:04 PM PST 24 | 11113863 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2762077628 | Jan 17 12:24:45 PM PST 24 | Jan 17 12:24:53 PM PST 24 | 47455095 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.450418025 | Jan 17 12:24:37 PM PST 24 | Jan 17 12:24:43 PM PST 24 | 92634171 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1760926806 | Jan 17 12:23:13 PM PST 24 | Jan 17 12:23:25 PM PST 24 | 2047189136 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.522348523 | Jan 17 12:24:54 PM PST 24 | Jan 17 12:24:56 PM PST 24 | 9270621 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1223722015 | Jan 17 12:18:21 PM PST 24 | Jan 17 12:19:00 PM PST 24 | 342517553 ps | ||
| T119 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2145856060 | Jan 17 12:24:52 PM PST 24 | Jan 17 12:28:17 PM PST 24 | 12609932213 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3355898226 | Jan 17 12:25:33 PM PST 24 | Jan 17 12:25:49 PM PST 24 | 1924670013 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1670944679 | Jan 17 12:21:48 PM PST 24 | Jan 17 12:21:50 PM PST 24 | 17858383 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2103204173 | Jan 17 12:25:05 PM PST 24 | Jan 17 12:25:40 PM PST 24 | 1738833078 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.198075273 | Jan 17 12:25:00 PM PST 24 | Jan 17 12:25:11 PM PST 24 | 232183278 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3043918312 | Jan 17 12:25:31 PM PST 24 | Jan 17 12:25:40 PM PST 24 | 1355671465 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2814707876 | Jan 17 12:24:09 PM PST 24 | Jan 17 12:24:17 PM PST 24 | 114102576 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/17.xbar_smoke.2358484087 | Jan 17 12:21:36 PM PST 24 | Jan 17 12:21:41 PM PST 24 | 94394838 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2741661563 | Jan 17 12:24:10 PM PST 24 | Jan 17 12:24:21 PM PST 24 | 1436090708 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2509662351 | Jan 17 12:23:59 PM PST 24 | Jan 17 12:24:11 PM PST 24 | 625611115 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2931148108 | Jan 17 12:23:54 PM PST 24 | Jan 17 12:23:57 PM PST 24 | 153870051 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1670939132 | Jan 17 12:24:13 PM PST 24 | Jan 17 12:24:21 PM PST 24 | 139731310 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3040190478 | Jan 17 12:20:34 PM PST 24 | Jan 17 12:20:37 PM PST 24 | 87014174 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3202428200 | Jan 17 12:24:48 PM PST 24 | Jan 17 12:24:53 PM PST 24 | 11377340 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.303407610 | Jan 17 12:22:27 PM PST 24 | Jan 17 12:22:34 PM PST 24 | 173076498 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1727891093 | Jan 17 12:21:21 PM PST 24 | Jan 17 12:22:42 PM PST 24 | 9259997111 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2369661990 | Jan 17 12:19:40 PM PST 24 | Jan 17 12:19:41 PM PST 24 | 8667444 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2631103175 | Jan 17 12:18:29 PM PST 24 | Jan 17 12:18:39 PM PST 24 | 7002801011 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3416831002 | Jan 17 12:25:25 PM PST 24 | Jan 17 12:25:38 PM PST 24 | 985955559 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3390363442 | Jan 17 12:39:01 PM PST 24 | Jan 17 12:39:15 PM PST 24 | 60448448 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.93136091 | Jan 17 12:22:21 PM PST 24 | Jan 17 12:22:25 PM PST 24 | 35348431 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2673050213 | Jan 17 12:21:02 PM PST 24 | Jan 17 12:21:23 PM PST 24 | 591585481 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.125013212 | Jan 17 12:24:24 PM PST 24 | Jan 17 12:24:36 PM PST 24 | 442702444 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3510681675 | Jan 17 12:21:52 PM PST 24 | Jan 17 12:24:45 PM PST 24 | 29992098377 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2085753955 | Jan 17 12:22:16 PM PST 24 | Jan 17 12:22:31 PM PST 24 | 3050660189 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.591853615 | Jan 17 12:23:01 PM PST 24 | Jan 17 12:23:03 PM PST 24 | 21313947 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4050461054 | Jan 17 12:25:25 PM PST 24 | Jan 17 12:26:11 PM PST 24 | 1892285962 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3698557953 | Jan 17 12:23:27 PM PST 24 | Jan 17 12:23:55 PM PST 24 | 11284338342 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1419978344 | Jan 17 12:24:55 PM PST 24 | Jan 17 12:24:58 PM PST 24 | 139802091 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1322793925 | Jan 17 12:25:08 PM PST 24 | Jan 17 12:25:17 PM PST 24 | 671624684 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3830095721 | Jan 17 12:20:59 PM PST 24 | Jan 17 12:21:11 PM PST 24 | 17946167615 ps | ||
| T172 | /workspace/coverage/xbar_build_mode/2.xbar_random.1892167540 | Jan 17 12:24:30 PM PST 24 | Jan 17 12:24:48 PM PST 24 | 2394173380 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3380895219 | Jan 17 12:25:00 PM PST 24 | Jan 17 12:25:10 PM PST 24 | 71060885 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3445314790 | Jan 17 12:25:30 PM PST 24 | Jan 17 12:27:23 PM PST 24 | 31583621020 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.690295634 | Jan 17 12:24:13 PM PST 24 | Jan 17 12:24:21 PM PST 24 | 1150567677 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2922993711 | Jan 17 12:23:41 PM PST 24 | Jan 17 12:23:44 PM PST 24 | 11598588 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3983383433 | Jan 17 12:21:42 PM PST 24 | Jan 17 12:23:26 PM PST 24 | 12727558205 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1100082600 | Jan 17 12:23:17 PM PST 24 | Jan 17 12:23:24 PM PST 24 | 798244981 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/1.xbar_same_source.3212908529 | Jan 17 12:17:50 PM PST 24 | Jan 17 12:17:53 PM PST 24 | 109245590 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1949952241 | Jan 17 12:22:52 PM PST 24 | Jan 17 12:24:20 PM PST 24 | 5783430242 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3711440497 | Jan 17 12:25:00 PM PST 24 | Jan 17 12:25:26 PM PST 24 | 313802043 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.105935069 | Jan 17 12:24:48 PM PST 24 | Jan 17 12:24:52 PM PST 24 | 10362937 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1139272153 | Jan 17 12:24:33 PM PST 24 | Jan 17 12:24:43 PM PST 24 | 1298898283 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1160328398 | Jan 17 12:24:14 PM PST 24 | Jan 17 12:24:23 PM PST 24 | 3303302456 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/40.xbar_smoke.4270466155 | Jan 17 12:24:57 PM PST 24 | Jan 17 12:24:59 PM PST 24 | 11343861 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.379692673 | Jan 17 12:20:33 PM PST 24 | Jan 17 12:20:35 PM PST 24 | 63579019 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2508628165 | Jan 17 12:22:13 PM PST 24 | Jan 17 12:22:33 PM PST 24 | 6862688450 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4081886978 | Jan 17 12:22:40 PM PST 24 | Jan 17 12:23:36 PM PST 24 | 18648559493 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3807513444 | Jan 17 12:19:43 PM PST 24 | Jan 17 12:20:08 PM PST 24 | 3272266366 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4278859588 | Jan 17 12:25:02 PM PST 24 | Jan 17 12:26:22 PM PST 24 | 2472121670 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/9.xbar_error_random.3153237084 | Jan 17 12:21:02 PM PST 24 | Jan 17 12:21:17 PM PST 24 | 2449617101 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2462012478 | Jan 17 12:22:54 PM PST 24 | Jan 17 12:23:35 PM PST 24 | 469589379 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.4221891624 | Jan 17 12:23:55 PM PST 24 | Jan 17 12:24:04 PM PST 24 | 887929366 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3971233550 | Jan 17 12:25:06 PM PST 24 | Jan 17 12:27:52 PM PST 24 | 27290284705 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1639171575 | Jan 17 12:23:20 PM PST 24 | Jan 17 12:29:11 PM PST 24 | 43745051091 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3498264417 | Jan 17 12:22:40 PM PST 24 | Jan 17 12:22:46 PM PST 24 | 722030250 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/16.xbar_random.492657067 | Jan 17 12:54:44 PM PST 24 | Jan 17 12:54:47 PM PST 24 | 374766648 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1468097169 | Jan 17 12:23:43 PM PST 24 | Jan 17 12:24:26 PM PST 24 | 23964356643 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3857187366 | Jan 17 12:24:02 PM PST 24 | Jan 17 12:24:12 PM PST 24 | 585107535 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.4254914314 | Jan 17 12:21:29 PM PST 24 | Jan 17 12:25:58 PM PST 24 | 137078635362 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2150675978 | Jan 17 12:23:40 PM PST 24 | Jan 17 12:23:54 PM PST 24 | 164976865 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/39.xbar_random.3020236485 | Jan 17 12:24:59 PM PST 24 | Jan 17 12:25:04 PM PST 24 | 111386496 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/24.xbar_error_random.4095046489 | Jan 17 12:23:18 PM PST 24 | Jan 17 12:23:23 PM PST 24 | 356126006 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/22.xbar_error_random.998825841 | Jan 17 12:22:55 PM PST 24 | Jan 17 12:23:07 PM PST 24 | 937499628 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4145763836 | Jan 17 12:19:44 PM PST 24 | Jan 17 12:19:56 PM PST 24 | 2407479939 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2904669284 | Jan 17 12:21:29 PM PST 24 | Jan 17 12:23:00 PM PST 24 | 4053837104 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2389212957 | Jan 17 12:22:00 PM PST 24 | Jan 17 12:22:04 PM PST 24 | 49182647 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2854965738 | Jan 17 12:24:07 PM PST 24 | Jan 17 12:24:09 PM PST 24 | 16942693 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2243122913 | Jan 17 12:24:11 PM PST 24 | Jan 17 12:26:09 PM PST 24 | 23886164549 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/38.xbar_random.3697416490 | Jan 17 12:24:53 PM PST 24 | Jan 17 12:25:01 PM PST 24 | 665536116 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4090806640 | Jan 17 12:24:14 PM PST 24 | Jan 17 12:24:58 PM PST 24 | 7800880180 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3726373751 | Jan 17 12:24:53 PM PST 24 | Jan 17 12:25:33 PM PST 24 | 367865025 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.869046217 | Jan 17 12:24:10 PM PST 24 | Jan 17 12:24:17 PM PST 24 | 54502402 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3672213103 | Jan 17 12:21:10 PM PST 24 | Jan 17 12:21:27 PM PST 24 | 4438234808 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.816793954 | Jan 17 12:18:19 PM PST 24 | Jan 17 12:18:23 PM PST 24 | 20191504 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1626431104 | Jan 17 12:24:20 PM PST 24 | Jan 17 12:24:23 PM PST 24 | 11477426 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3216985824 | Jan 17 12:27:02 PM PST 24 | Jan 17 12:27:23 PM PST 24 | 19788821 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.461535477 | Jan 17 12:24:08 PM PST 24 | Jan 17 12:24:10 PM PST 24 | 13136745 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3094849609 | Jan 17 12:24:01 PM PST 24 | Jan 17 12:24:21 PM PST 24 | 356598692 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3687018399 | Jan 17 12:25:06 PM PST 24 | Jan 17 12:25:38 PM PST 24 | 1501038405 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2889741825 | Jan 17 12:24:21 PM PST 24 | Jan 17 12:24:41 PM PST 24 | 5145276379 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.30721932 | Jan 17 12:25:12 PM PST 24 | Jan 17 12:25:22 PM PST 24 | 43875865 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3609924920 | Jan 17 12:27:10 PM PST 24 | Jan 17 12:27:24 PM PST 24 | 40083998 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/48.xbar_random.1272965185 | Jan 17 12:25:20 PM PST 24 | Jan 17 12:25:24 PM PST 24 | 327746590 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/8.xbar_random.203283408 | Jan 17 12:21:10 PM PST 24 | Jan 17 12:21:13 PM PST 24 | 136014736 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3699962630 | Jan 17 12:20:33 PM PST 24 | Jan 17 12:25:32 PM PST 24 | 80609942641 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1621990212 | Jan 17 12:21:53 PM PST 24 | Jan 17 12:22:38 PM PST 24 | 397843738 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3062112853 | Jan 17 12:24:36 PM PST 24 | Jan 17 12:24:55 PM PST 24 | 5428127885 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.298448958 | Jan 17 12:25:14 PM PST 24 | Jan 17 12:25:31 PM PST 24 | 6054701371 ps | ||
| T10 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.5195238 | Jan 17 12:24:31 PM PST 24 | Jan 17 12:26:14 PM PST 24 | 930941033 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.149507139 | Jan 17 12:25:30 PM PST 24 | Jan 17 12:25:54 PM PST 24 | 7302854116 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2949313141 | Jan 17 12:22:54 PM PST 24 | Jan 17 12:24:59 PM PST 24 | 7315132935 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1292007242 | Jan 17 12:24:14 PM PST 24 | Jan 17 12:24:42 PM PST 24 | 3583890684 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3025788788 | Jan 17 12:24:53 PM PST 24 | Jan 17 12:24:58 PM PST 24 | 76795824 ps | ||
| T163 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2429862029 | Jan 17 12:23:11 PM PST 24 | Jan 17 12:24:11 PM PST 24 | 12962746377 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1519259071 | Jan 17 12:20:27 PM PST 24 | Jan 17 12:20:32 PM PST 24 | 10175396 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/15.xbar_smoke.878638726 | Jan 17 12:21:12 PM PST 24 | Jan 17 12:21:15 PM PST 24 | 193656620 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3306472382 | Jan 17 12:21:49 PM PST 24 | Jan 17 12:23:14 PM PST 24 | 25359006257 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.178595974 | Jan 17 12:26:29 PM PST 24 | Jan 17 12:26:40 PM PST 24 | 558560154 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3300042184 | Jan 17 12:23:40 PM PST 24 | Jan 17 12:23:44 PM PST 24 | 149419840 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1307343783 | Jan 17 12:22:55 PM PST 24 | Jan 17 12:22:57 PM PST 24 | 12537307 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1155109025 | Jan 17 12:23:05 PM PST 24 | Jan 17 12:23:14 PM PST 24 | 997287201 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1541752110 | Jan 17 12:24:52 PM PST 24 | Jan 17 12:25:03 PM PST 24 | 817004555 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3155130316 | Jan 17 12:24:32 PM PST 24 | Jan 17 12:24:41 PM PST 24 | 635818243 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1324721640 | Jan 17 12:24:22 PM PST 24 | Jan 17 12:24:37 PM PST 24 | 1272943446 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.342965887 | Jan 17 12:25:29 PM PST 24 | Jan 17 12:25:38 PM PST 24 | 6809423065 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.147805931 | Jan 17 12:24:49 PM PST 24 | Jan 17 12:25:02 PM PST 24 | 1979782409 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3213051127 | Jan 17 12:23:12 PM PST 24 | Jan 17 12:23:18 PM PST 24 | 8477693 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/26.xbar_same_source.1331242673 | Jan 17 12:24:11 PM PST 24 | Jan 17 12:24:19 PM PST 24 | 3619277651 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3210626501 | Jan 17 12:25:06 PM PST 24 | Jan 17 12:25:18 PM PST 24 | 521560694 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.935287058 | Jan 17 12:24:08 PM PST 24 | Jan 17 12:24:20 PM PST 24 | 1070915570 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2327621351 | Jan 17 12:25:13 PM PST 24 | Jan 17 12:25:22 PM PST 24 | 57582631 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1461950644 | Jan 17 12:23:18 PM PST 24 | Jan 17 12:23:25 PM PST 24 | 1323671808 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.882727635 | Jan 17 12:23:27 PM PST 24 | Jan 17 12:23:35 PM PST 24 | 225279141 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.115453753 | Jan 17 12:25:04 PM PST 24 | Jan 17 12:25:12 PM PST 24 | 42389372 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2885551762 | Jan 17 12:24:42 PM PST 24 | Jan 17 12:24:56 PM PST 24 | 872600519 ps | ||
| T155 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.260328530 | Jan 17 12:25:17 PM PST 24 | Jan 17 12:27:00 PM PST 24 | 6749798243 ps | ||
| T120 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1372010259 | Jan 17 12:24:15 PM PST 24 | Jan 17 12:24:54 PM PST 24 | 5815423244 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2234028949 | Jan 17 12:24:37 PM PST 24 | Jan 17 12:27:32 PM PST 24 | 5352406894 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.423976136 | Jan 17 12:24:33 PM PST 24 | Jan 17 12:26:00 PM PST 24 | 13264396460 ps |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.4258605135 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2535907161 ps |
| CPU time | 11.13 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-7a16b4c1-518e-45f5-b458-ba951f8b2b7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4258605135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.4258605135 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2820569910 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 49943005457 ps |
| CPU time | 335.49 seconds |
| Started | Jan 17 12:18:22 PM PST 24 |
| Finished | Jan 17 12:23:59 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-cbe94dd0-3db8-4c77-a1d9-cc9893722b9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2820569910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2820569910 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.4006130554 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 145283851723 ps |
| CPU time | 357.32 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:30:46 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-90fdbc25-5a84-41c1-867b-6ec5adab166d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4006130554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.4006130554 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3270150313 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 221590522247 ps |
| CPU time | 371.38 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:31:06 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-ebf372d3-c636-4fed-a720-fc8b4dad238b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3270150313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.3270150313 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1852613552 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 590097608 ps |
| CPU time | 39.76 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:26:00 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-9fe266e5-24d4-4e4e-a15b-716ae079089c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1852613552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1852613552 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3956316690 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 142496212967 ps |
| CPU time | 334.95 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:30:53 PM PST 24 |
| Peak memory | 202948 kb |
| Host | smart-eda32c21-1ee0-4168-aa8a-151ae6861dec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3956316690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3956316690 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3124352188 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 34344398401 ps |
| CPU time | 191.44 seconds |
| Started | Jan 17 12:21:10 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-7e7189ba-6dc7-4763-b524-c86d5396bc9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3124352188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3124352188 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1779274521 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 45315005792 ps |
| CPU time | 235.34 seconds |
| Started | Jan 17 12:17:30 PM PST 24 |
| Finished | Jan 17 12:21:27 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-8123eb3b-8916-4f3e-954c-10b95479a323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1779274521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1779274521 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.647826060 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 97251585 ps |
| CPU time | 6.11 seconds |
| Started | Jan 17 12:25:35 PM PST 24 |
| Finished | Jan 17 12:25:41 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-f4060f36-e4b4-4c6b-b9bc-aa177c499845 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647826060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.647826060 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3008564984 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3165954598 ps |
| CPU time | 46.58 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:25:06 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-2ff6b1fa-275b-4ea4-afdb-9346beb71994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008564984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.3008564984 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3353814622 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 608872538 ps |
| CPU time | 69.37 seconds |
| Started | Jan 17 12:22:42 PM PST 24 |
| Finished | Jan 17 12:23:53 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-480339e6-6b7f-4745-86ad-5f8f387db461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353814622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3353814622 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3971996227 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2991150734 ps |
| CPU time | 107.14 seconds |
| Started | Jan 17 12:24:39 PM PST 24 |
| Finished | Jan 17 12:26:27 PM PST 24 |
| Peak memory | 204096 kb |
| Host | smart-baee6ac9-16bc-49bb-9aff-cf5e113a62df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3971996227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3971996227 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1347570447 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 39412375838 ps |
| CPU time | 162.15 seconds |
| Started | Jan 17 12:26:29 PM PST 24 |
| Finished | Jan 17 12:29:12 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-65befb6d-d175-442f-87ae-8ab55e8e6dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347570447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1347570447 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3483929370 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 201280832311 ps |
| CPU time | 371.56 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:29:06 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-a671787a-d858-406b-9932-f84a7cbe5572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3483929370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3483929370 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1131613211 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1518940821 ps |
| CPU time | 20.22 seconds |
| Started | Jan 17 12:23:57 PM PST 24 |
| Finished | Jan 17 12:24:18 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-7e74a05b-7201-45c9-9611-e2f0f542d260 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1131613211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1131613211 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3274269452 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1088319247 ps |
| CPU time | 117.18 seconds |
| Started | Jan 17 12:25:07 PM PST 24 |
| Finished | Jan 17 12:27:06 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-ed5d49ea-41ca-46d8-9da8-7a3e4a822c9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3274269452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3274269452 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2411007020 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 19471333397 ps |
| CPU time | 135.07 seconds |
| Started | Jan 17 12:22:45 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-6cc8e13d-aec4-4a2b-b62a-78a0034a9fd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2411007020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2411007020 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.5195238 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 930941033 ps |
| CPU time | 102.6 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:26:14 PM PST 24 |
| Peak memory | 204056 kb |
| Host | smart-55c35a7f-7a65-455e-bbfd-014f8d6d9646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5195238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset _error.5195238 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2585269649 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1159701272 ps |
| CPU time | 12.84 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:24:59 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-ebe2b877-7aba-402e-b678-47830b2b94d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2585269649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2585269649 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3163894117 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3162070874 ps |
| CPU time | 119.15 seconds |
| Started | Jan 17 12:21:57 PM PST 24 |
| Finished | Jan 17 12:23:57 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-daa4045d-5d0b-4d81-9a92-e07497b79e4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163894117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3163894117 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1211259957 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 18874289673 ps |
| CPU time | 226.95 seconds |
| Started | Jan 17 12:24:56 PM PST 24 |
| Finished | Jan 17 12:28:44 PM PST 24 |
| Peak memory | 205296 kb |
| Host | smart-4d511ab3-1687-42e4-9a82-a5d21963b8ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1211259957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1211259957 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.311131647 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2156886765 ps |
| CPU time | 80.94 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:26:39 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-e33ea85c-68ff-4800-9c60-6a238fc798e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=311131647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.311131647 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3366321834 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 56023503185 ps |
| CPU time | 166.43 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:27:19 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-9c94c8cb-e53f-4a1d-98a2-c3685c0c7506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3366321834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3366321834 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.117656196 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 658024911 ps |
| CPU time | 96.02 seconds |
| Started | Jan 17 12:26:17 PM PST 24 |
| Finished | Jan 17 12:27:54 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-0d672b4a-c9b2-4797-998b-35308f6e4c0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117656196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.117656196 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3756145875 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 67920395 ps |
| CPU time | 8.57 seconds |
| Started | Jan 17 12:18:03 PM PST 24 |
| Finished | Jan 17 12:18:14 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-365b40ee-f71c-4124-88ba-6dbb94966b58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756145875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3756145875 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2938086578 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 674401817 ps |
| CPU time | 14.34 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-aa00b401-e072-4431-b592-a67a225af06b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2938086578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2938086578 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2721624943 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 44845289008 ps |
| CPU time | 301.03 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:29:48 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-929c38b4-a7bf-4048-993d-a269deec34e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2721624943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2721624943 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.935970563 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 178275638 ps |
| CPU time | 3.64 seconds |
| Started | Jan 17 12:18:23 PM PST 24 |
| Finished | Jan 17 12:18:28 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-ae9c69a3-bbca-4f90-9a16-c340372c816f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935970563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.935970563 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1477364348 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 294439135 ps |
| CPU time | 5.43 seconds |
| Started | Jan 17 12:18:24 PM PST 24 |
| Finished | Jan 17 12:18:31 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-115882d3-e40d-4412-b053-a5f09b20e560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1477364348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1477364348 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.4073813536 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 30781773 ps |
| CPU time | 2.6 seconds |
| Started | Jan 17 12:18:32 PM PST 24 |
| Finished | Jan 17 12:18:39 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-f3b53f9b-8553-4c15-8c4e-f5f5c6f0d576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073813536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4073813536 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2652181204 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 32317904176 ps |
| CPU time | 42.81 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:25:30 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-5363ce35-2c39-4ab7-a848-4e56f00bff79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652181204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2652181204 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3425008375 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 154943274528 ps |
| CPU time | 166.36 seconds |
| Started | Jan 17 12:18:25 PM PST 24 |
| Finished | Jan 17 12:21:13 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-3610ecd9-7628-47d1-b796-48d02ce3c2bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425008375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3425008375 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1529303173 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 85540088 ps |
| CPU time | 3.6 seconds |
| Started | Jan 17 12:23:45 PM PST 24 |
| Finished | Jan 17 12:23:55 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-4fe7f0f4-8934-43e1-ab3e-fc84284e0ca4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529303173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1529303173 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.816793954 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 20191504 ps |
| CPU time | 1.92 seconds |
| Started | Jan 17 12:18:19 PM PST 24 |
| Finished | Jan 17 12:18:23 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-3c39b87b-781b-455a-ad46-9de1b3e324bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=816793954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.816793954 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.2578462550 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9023211 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:21:03 PM PST 24 |
| Finished | Jan 17 12:21:04 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-c396155b-393d-4d4b-9af8-7a4a471a3fe9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2578462550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2578462550 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2903747357 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2328581634 ps |
| CPU time | 6.74 seconds |
| Started | Jan 17 12:24:25 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 200776 kb |
| Host | smart-198b7ff6-1de3-4ea3-9f46-450e486e13a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903747357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2903747357 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.4224738984 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 941127734 ps |
| CPU time | 8.16 seconds |
| Started | Jan 17 12:19:23 PM PST 24 |
| Finished | Jan 17 12:19:36 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-a8b2507d-7302-47ce-8f19-564a9e1568f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4224738984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.4224738984 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.984166268 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 10086198 ps |
| CPU time | 1.3 seconds |
| Started | Jan 17 12:18:12 PM PST 24 |
| Finished | Jan 17 12:18:14 PM PST 24 |
| Peak memory | 201940 kb |
| Host | smart-ec05b366-c064-450c-b726-e50e9eed57d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984166268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.984166268 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1790887850 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 18837882 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 12:18:22 PM PST 24 |
| Finished | Jan 17 12:18:24 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-de182286-c2ee-4b7a-ba72-ec40ed298c41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1790887850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1790887850 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1633275325 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 201270734 ps |
| CPU time | 12.54 seconds |
| Started | Jan 17 12:19:34 PM PST 24 |
| Finished | Jan 17 12:19:47 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-06fe9c08-d49e-4aa1-a03d-72b581114cdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633275325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1633275325 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1982422812 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 423982260 ps |
| CPU time | 70.06 seconds |
| Started | Jan 17 12:18:38 PM PST 24 |
| Finished | Jan 17 12:19:49 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-c27267a9-c422-429c-b9c2-16990e73cbe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1982422812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1982422812 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3477826734 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2408089722 ps |
| CPU time | 125.96 seconds |
| Started | Jan 17 12:19:24 PM PST 24 |
| Finished | Jan 17 12:21:34 PM PST 24 |
| Peak memory | 208372 kb |
| Host | smart-bf2073af-1244-4c24-83da-7dc4e44cbc98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477826734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3477826734 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.625862809 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 146407067 ps |
| CPU time | 5.3 seconds |
| Started | Jan 17 12:18:40 PM PST 24 |
| Finished | Jan 17 12:18:47 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-7ae794e6-8f76-4ad5-acfb-b94f87104fba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625862809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.625862809 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2849908693 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 50360970 ps |
| CPU time | 10.28 seconds |
| Started | Jan 17 12:18:07 PM PST 24 |
| Finished | Jan 17 12:18:23 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-3b14d505-f873-4862-9c6f-e868811d78d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2849908693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2849908693 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3498770055 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 40988128 ps |
| CPU time | 3.35 seconds |
| Started | Jan 17 12:24:38 PM PST 24 |
| Finished | Jan 17 12:24:42 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-1eb853f1-d096-4355-8c9d-60d21fc0a98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498770055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3498770055 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2694993500 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 117087037 ps |
| CPU time | 4.99 seconds |
| Started | Jan 17 12:19:35 PM PST 24 |
| Finished | Jan 17 12:19:41 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-33e64c3d-2987-4ac3-9879-1fc837881ff8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694993500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2694993500 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.1441285135 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1319508039 ps |
| CPU time | 9.42 seconds |
| Started | Jan 17 12:19:35 PM PST 24 |
| Finished | Jan 17 12:19:45 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-32ba5e25-4f93-472d-aa74-6fd4f06c57ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1441285135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1441285135 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1220424610 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 78227902209 ps |
| CPU time | 109.36 seconds |
| Started | Jan 17 12:18:08 PM PST 24 |
| Finished | Jan 17 12:20:02 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-dcf70b69-a776-4dc2-a379-6687078d0003 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220424610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1220424610 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3303570316 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 33784011870 ps |
| CPU time | 200.07 seconds |
| Started | Jan 17 12:18:42 PM PST 24 |
| Finished | Jan 17 12:22:03 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-3d5a23b5-20ec-42dc-bd61-c0da7bfb050f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3303570316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3303570316 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.3212908529 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 109245590 ps |
| CPU time | 1.88 seconds |
| Started | Jan 17 12:17:50 PM PST 24 |
| Finished | Jan 17 12:17:53 PM PST 24 |
| Peak memory | 201260 kb |
| Host | smart-cd753052-c140-4754-a01e-74a870e18887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3212908529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3212908529 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.4006483646 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 228223326 ps |
| CPU time | 1.58 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 199672 kb |
| Host | smart-92740c54-e29d-44af-82f5-21e6fe9f3637 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4006483646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4006483646 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2631103175 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 7002801011 ps |
| CPU time | 9.08 seconds |
| Started | Jan 17 12:18:29 PM PST 24 |
| Finished | Jan 17 12:18:39 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-5850225a-2382-4b3a-b5b6-0ae184b33d0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631103175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2631103175 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3328195507 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1642841162 ps |
| CPU time | 7.66 seconds |
| Started | Jan 17 12:18:42 PM PST 24 |
| Finished | Jan 17 12:18:50 PM PST 24 |
| Peak memory | 201308 kb |
| Host | smart-aba63846-1aff-4113-9a0f-96e38dee1ff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3328195507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3328195507 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3216985824 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 19788821 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 12:27:02 PM PST 24 |
| Finished | Jan 17 12:27:23 PM PST 24 |
| Peak memory | 200720 kb |
| Host | smart-f0d86521-38d4-4add-aa9d-e6647a829749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216985824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3216985824 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1938857301 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 320077382 ps |
| CPU time | 45.81 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 202036 kb |
| Host | smart-e2c8cb39-f952-4173-aa39-449a469fb400 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1938857301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1938857301 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2409333317 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 795397312 ps |
| CPU time | 40.56 seconds |
| Started | Jan 17 12:24:24 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-bf1a4dbd-bc0a-4d13-beaf-64f7e83d359a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409333317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2409333317 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.521860513 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2884514703 ps |
| CPU time | 134.65 seconds |
| Started | Jan 17 12:26:42 PM PST 24 |
| Finished | Jan 17 12:28:58 PM PST 24 |
| Peak memory | 208032 kb |
| Host | smart-09a2d4d7-ee04-4e41-bc73-6be3e8d975b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=521860513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.521860513 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1386391067 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 93504969 ps |
| CPU time | 1.97 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 199372 kb |
| Host | smart-bc69a9da-9ac7-4f5e-8487-921960773be9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1386391067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1386391067 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3498264417 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 722030250 ps |
| CPU time | 5.55 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:22:46 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-bce79415-7063-48a7-8979-00fb642f7f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498264417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3498264417 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3699962630 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 80609942641 ps |
| CPU time | 298.94 seconds |
| Started | Jan 17 12:20:33 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-edb4b700-3fe4-4f90-9f99-70009b1087fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3699962630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.3699962630 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1936117747 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 515752719 ps |
| CPU time | 6.83 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-30509eec-8b4e-4436-9a44-7894979bb77f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1936117747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1936117747 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2761980202 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 212102733 ps |
| CPU time | 4.37 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-0298e87d-9cd6-47e0-b2d1-24619544ce02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761980202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2761980202 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.136892927 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 908285149 ps |
| CPU time | 8.12 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-52ba9ee0-12f9-430d-b088-ebf4fc6f4341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=136892927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.136892927 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2804121827 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 57370423886 ps |
| CPU time | 132.71 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:26:20 PM PST 24 |
| Peak memory | 200068 kb |
| Host | smart-b3b81898-2fe2-4e03-b791-a65a090294a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804121827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2804121827 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3081501162 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 26344070708 ps |
| CPU time | 105.67 seconds |
| Started | Jan 17 12:20:58 PM PST 24 |
| Finished | Jan 17 12:22:45 PM PST 24 |
| Peak memory | 201740 kb |
| Host | smart-8359c6aa-f6b3-4fe5-aa9e-73e43170c165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3081501162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3081501162 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1925012120 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 190656157 ps |
| CPU time | 6.25 seconds |
| Started | Jan 17 12:23:02 PM PST 24 |
| Finished | Jan 17 12:23:09 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-ef734730-668e-44d0-9018-dd816dd29382 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925012120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1925012120 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2549821546 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3778540932 ps |
| CPU time | 11.76 seconds |
| Started | Jan 17 12:20:31 PM PST 24 |
| Finished | Jan 17 12:20:43 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-335f212f-f64f-404e-ba2c-6f8625f3519b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549821546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2549821546 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.379692673 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 63579019 ps |
| CPU time | 1.45 seconds |
| Started | Jan 17 12:20:33 PM PST 24 |
| Finished | Jan 17 12:20:35 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-600e558e-c595-4870-98b5-1069139c8d6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379692673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.379692673 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1158737898 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2051379472 ps |
| CPU time | 9.07 seconds |
| Started | Jan 17 12:20:37 PM PST 24 |
| Finished | Jan 17 12:20:46 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-a89729ca-6ee3-4898-bb9c-539fa1efced6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158737898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1158737898 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.128895222 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2615848265 ps |
| CPU time | 7.18 seconds |
| Started | Jan 17 12:20:33 PM PST 24 |
| Finished | Jan 17 12:20:41 PM PST 24 |
| Peak memory | 201600 kb |
| Host | smart-f938cf8d-2ce3-42b3-99cc-ce0ced4825eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=128895222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.128895222 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1221626984 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 8087076 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:09 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-0e46f3a7-3c6f-40dc-92e1-f7dae48be424 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221626984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1221626984 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.8137554 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 244319435 ps |
| CPU time | 29.48 seconds |
| Started | Jan 17 12:21:33 PM PST 24 |
| Finished | Jan 17 12:22:03 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-2c29a24f-906e-4023-b99b-9dc255a15e15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8137554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.8137554 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1037915145 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 354169217 ps |
| CPU time | 15.78 seconds |
| Started | Jan 17 12:20:30 PM PST 24 |
| Finished | Jan 17 12:20:47 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-a5fdfa63-68ab-457e-8bab-62e9da335100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037915145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1037915145 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.147746377 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 180438251 ps |
| CPU time | 23.68 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-d03ebf03-4c49-4ed4-8a4e-7a664e8e65ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=147746377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.147746377 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2066215917 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4055479972 ps |
| CPU time | 125.79 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:26:16 PM PST 24 |
| Peak memory | 206028 kb |
| Host | smart-27755aef-2b17-4d6c-92de-4214c7456a4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2066215917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2066215917 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3040190478 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 87014174 ps |
| CPU time | 2.02 seconds |
| Started | Jan 17 12:20:34 PM PST 24 |
| Finished | Jan 17 12:20:37 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-5a3e1483-224c-4b15-a758-d3a533898c2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3040190478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3040190478 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.74684440 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 33778215 ps |
| CPU time | 4.26 seconds |
| Started | Jan 17 12:20:34 PM PST 24 |
| Finished | Jan 17 12:20:39 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-1b444c05-29c7-4077-9435-0d2841a23461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=74684440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.74684440 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3326483564 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 171595774552 ps |
| CPU time | 339.95 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:29:47 PM PST 24 |
| Peak memory | 200864 kb |
| Host | smart-c27d6125-1ed3-4c8f-a3cf-aab9ea019d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3326483564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3326483564 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.256276610 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 368027121 ps |
| CPU time | 7.11 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-e1e8ff88-5287-4eb6-9a61-509c8ba8a123 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=256276610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.256276610 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1450974184 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 317557817 ps |
| CPU time | 5.88 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-cbee8126-5dc5-42fb-b349-d3dcb37ff68d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450974184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1450974184 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.3512189454 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 960658736 ps |
| CPU time | 15.45 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-069910d0-ec77-40af-8b86-d355c095d98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3512189454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3512189454 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3288819377 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 8227544192 ps |
| CPU time | 24.12 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:32 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-376136cb-351d-4415-b18b-8cf8eccaa120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288819377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3288819377 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1822043889 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 21607862517 ps |
| CPU time | 59.29 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:25:07 PM PST 24 |
| Peak memory | 199864 kb |
| Host | smart-136982ef-46c4-42ad-a13c-5ce6cfc50a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1822043889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1822043889 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.869046217 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 54502402 ps |
| CPU time | 6.24 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-35c1c92a-13e1-4ed1-bb73-ed26c8c2f472 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869046217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.869046217 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2289913940 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 862186319 ps |
| CPU time | 6.15 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:38 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-27ea4f7c-e2f3-4963-b822-40157eef1150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2289913940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2289913940 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.530100845 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 215038797 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:09 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-e44b4f53-7df9-4639-ae13-41789d7204bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=530100845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.530100845 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2516263158 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1484760903 ps |
| CPU time | 6.08 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 200788 kb |
| Host | smart-58342327-e35e-49df-82bb-0a679fbbec7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516263158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2516263158 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2741661563 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1436090708 ps |
| CPU time | 10.83 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-5147c36b-5b3c-4334-b06e-49cfb0fb80cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2741661563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2741661563 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2696810593 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7942367 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-e7465caf-e259-4b94-a123-0ae9037546bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696810593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2696810593 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.461535477 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 13136745 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:24:10 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-7aec71c2-8286-49cd-9934-91aaafaad41b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461535477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.461535477 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2150675978 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 164976865 ps |
| CPU time | 11.21 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:54 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-eb809a53-dfd9-46de-869b-0b45ae8fca5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2150675978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2150675978 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.833132740 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4334727753 ps |
| CPU time | 70.07 seconds |
| Started | Jan 17 12:23:02 PM PST 24 |
| Finished | Jan 17 12:24:13 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-f6a517a3-dc4c-4c3a-9063-84e47b4abe00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833132740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.833132740 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2879426138 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 7547067 ps |
| CPU time | 2.65 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:45 PM PST 24 |
| Peak memory | 201164 kb |
| Host | smart-a10ef949-5f66-495c-92ef-b8631e56df38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879426138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2879426138 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2710629722 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 487248041 ps |
| CPU time | 4.9 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-ab5037f1-d83f-4d33-aaf6-20678745e122 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2710629722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2710629722 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.51617473 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 56983403 ps |
| CPU time | 1.78 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-ed64bc9d-df03-452e-a158-0c1b5e1d9dbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51617473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.51617473 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4105259145 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 78198649174 ps |
| CPU time | 289.14 seconds |
| Started | Jan 17 12:23:14 PM PST 24 |
| Finished | Jan 17 12:28:06 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-77254d58-7863-4285-b214-ac065d27df53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4105259145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.4105259145 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4156360210 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 323006875 ps |
| CPU time | 5.93 seconds |
| Started | Jan 17 12:23:39 PM PST 24 |
| Finished | Jan 17 12:23:48 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-2de82dc0-889d-4489-8c8c-60f7481ee172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156360210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4156360210 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1376103722 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1621265764 ps |
| CPU time | 12.34 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:23:08 PM PST 24 |
| Peak memory | 198828 kb |
| Host | smart-93995d2f-d32f-44e1-ba60-5ab66f3c52b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1376103722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1376103722 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.1456767635 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 238139952 ps |
| CPU time | 2.66 seconds |
| Started | Jan 17 12:23:39 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-0e57fc69-8b65-4764-99fa-b8e9a0ef19d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456767635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1456767635 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.861424999 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9747027234 ps |
| CPU time | 27.83 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:24:10 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-f4db3262-f637-4597-a5bd-a7aa860f7dc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=861424999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.861424999 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.449121902 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 45608508919 ps |
| CPU time | 129.98 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:25:05 PM PST 24 |
| Peak memory | 198180 kb |
| Host | smart-72de44c4-3360-443d-a060-3e5649344c08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=449121902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.449121902 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3512460590 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 41209163 ps |
| CPU time | 2.12 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:24:24 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-f0581d3b-7da5-4b6b-b8d7-0803b97340a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512460590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3512460590 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.182944437 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1437150195 ps |
| CPU time | 8.66 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:23:04 PM PST 24 |
| Peak memory | 197924 kb |
| Host | smart-39a12252-c0f6-4275-8717-b80f8fd0d0b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182944437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.182944437 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2761830501 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 55507948 ps |
| CPU time | 1.51 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:03 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-97573691-d244-4335-807c-0c02aff25606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761830501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2761830501 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3894338642 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3142202644 ps |
| CPU time | 10.81 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:41 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-8a5d402b-a20f-441c-9858-d6a2810e29f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894338642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3894338642 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.893860970 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 13442999924 ps |
| CPU time | 10.92 seconds |
| Started | Jan 17 12:20:48 PM PST 24 |
| Finished | Jan 17 12:21:04 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-61b5e728-eafd-4df8-8419-262de89e5ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=893860970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.893860970 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2600741595 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 11753498 ps |
| CPU time | 1.32 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:22:42 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-d6861f6a-5ebd-47eb-a942-5d6198742291 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600741595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2600741595 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2150476120 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 17761454696 ps |
| CPU time | 37.81 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-6851e7a4-2558-430f-b883-b9559ccee7b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2150476120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2150476120 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3854043612 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2571533965 ps |
| CPU time | 37.47 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:56 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-a9007255-ee5d-4009-9afb-5d5f1be04a0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3854043612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3854043612 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3711440497 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 313802043 ps |
| CPU time | 25.58 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-4da7e7ec-89cb-403f-b7f3-c8495ce0d522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3711440497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3711440497 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.188469155 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 225360595 ps |
| CPU time | 9.27 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:52 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-42930894-488e-4d86-9b8f-e46b68e5cf1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188469155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.188469155 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3300042184 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 149419840 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-23d63bff-3b6a-4c8f-b604-8ecbe24468f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3300042184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3300042184 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1879569258 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 55766960 ps |
| CPU time | 9.21 seconds |
| Started | Jan 17 12:23:41 PM PST 24 |
| Finished | Jan 17 12:23:52 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-8a82280c-d147-4e32-84b0-abbd919b09f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1879569258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1879569258 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1496348911 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 72230301961 ps |
| CPU time | 153.36 seconds |
| Started | Jan 17 12:23:54 PM PST 24 |
| Finished | Jan 17 12:26:29 PM PST 24 |
| Peak memory | 199872 kb |
| Host | smart-62bc45f0-a0a9-4ed6-a774-48f716ff7e25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1496348911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1496348911 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2809956603 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 59700163 ps |
| CPU time | 5.35 seconds |
| Started | Jan 17 12:24:16 PM PST 24 |
| Finished | Jan 17 12:24:25 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-8ff18c76-2dc3-46ea-b39f-a017f7540c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809956603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2809956603 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.4242379104 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 26238589 ps |
| CPU time | 1.95 seconds |
| Started | Jan 17 12:23:18 PM PST 24 |
| Finished | Jan 17 12:23:21 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-64d64086-c5f4-49e2-9bdd-234535b1a158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242379104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4242379104 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.1924976456 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 60815458 ps |
| CPU time | 2.39 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-a4fb0fdf-a864-4fca-ba69-684366acfb14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924976456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1924976456 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.357806807 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 26120989171 ps |
| CPU time | 88.35 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-74aed87e-be86-414e-9cd9-c939bed17491 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=357806807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.357806807 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1733564558 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 21251177663 ps |
| CPU time | 79.69 seconds |
| Started | Jan 17 12:21:07 PM PST 24 |
| Finished | Jan 17 12:22:27 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-fa4c3a37-a514-4b11-9f72-b8e009302bfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1733564558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1733564558 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1648122075 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 51219137 ps |
| CPU time | 3.87 seconds |
| Started | Jan 17 12:23:14 PM PST 24 |
| Finished | Jan 17 12:23:21 PM PST 24 |
| Peak memory | 200108 kb |
| Host | smart-c06af16d-ce29-4eed-96b2-a30ac047e522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648122075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1648122075 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2774465994 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 469288580 ps |
| CPU time | 6.57 seconds |
| Started | Jan 17 12:23:41 PM PST 24 |
| Finished | Jan 17 12:23:49 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5a47524a-89ea-456d-a1f3-97a184ef3afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2774465994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2774465994 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2783083814 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 184982541 ps |
| CPU time | 1.41 seconds |
| Started | Jan 17 12:23:39 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-a03a0757-89a8-4028-bb26-29126c4ca100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2783083814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2783083814 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1479757399 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3651708918 ps |
| CPU time | 10.26 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:12 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-35b336d6-1660-4b2a-891f-67bc717ce2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479757399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1479757399 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1484447482 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 6590955884 ps |
| CPU time | 12.82 seconds |
| Started | Jan 17 12:23:39 PM PST 24 |
| Finished | Jan 17 12:23:55 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-01b8546f-6ed9-45dd-8ad0-638cd51cf44f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1484447482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1484447482 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1955942862 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 19450940 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 12:25:01 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-dfe2472d-4953-4fda-8dd9-d26abb3879af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955942862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1955942862 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1143953138 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3871261545 ps |
| CPU time | 54.37 seconds |
| Started | Jan 17 12:24:16 PM PST 24 |
| Finished | Jan 17 12:25:14 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-96e474fa-3ac1-4262-b464-6b01901ece29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1143953138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1143953138 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3360709396 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 838665907 ps |
| CPU time | 43.47 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:24:13 PM PST 24 |
| Peak memory | 198640 kb |
| Host | smart-fdae30b5-97e5-448c-8af4-139d82d3ead3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3360709396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3360709396 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1938524050 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 867527508 ps |
| CPU time | 53 seconds |
| Started | Jan 17 12:23:43 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-02ec26f6-0740-4640-ba1a-02c356637a60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1938524050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1938524050 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2532709145 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 52059857 ps |
| CPU time | 10.04 seconds |
| Started | Jan 17 12:23:18 PM PST 24 |
| Finished | Jan 17 12:23:29 PM PST 24 |
| Peak memory | 200916 kb |
| Host | smart-6ca879dc-e541-4057-b823-98a2c72d8ab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2532709145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.2532709145 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3004145456 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 600361800 ps |
| CPU time | 5.67 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:25 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-42c16e19-fdb2-4e4b-a07d-9a184454a9d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3004145456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3004145456 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1894528256 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 995815965 ps |
| CPU time | 10.41 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:24:19 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-10000539-a622-4ca4-9995-54801310cdc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894528256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1894528256 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3307254180 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 9456543763 ps |
| CPU time | 51.61 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-47820011-683c-4081-a2be-9b8aff58bbaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3307254180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3307254180 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3917984500 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1059605003 ps |
| CPU time | 9.33 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:23:39 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-30449d97-5793-4ef3-8bdd-deb57e104af8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3917984500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3917984500 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.374415021 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 10410119 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 12:23:44 PM PST 24 |
| Finished | Jan 17 12:23:52 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-529dbc40-8c6f-4151-85fc-4ca12ea4b788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=374415021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.374415021 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3024258677 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 231138583 ps |
| CPU time | 4.45 seconds |
| Started | Jan 17 12:23:18 PM PST 24 |
| Finished | Jan 17 12:23:23 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-a93c7800-89d4-4fc7-92ac-8b81d23c0ed9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3024258677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3024258677 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2040283144 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49623252334 ps |
| CPU time | 97.19 seconds |
| Started | Jan 17 12:23:42 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-2900067c-c9b1-461d-81a8-99b486657177 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040283144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2040283144 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3698557953 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 11284338342 ps |
| CPU time | 25.19 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:23:55 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-67c6604a-5645-49d2-956b-c3d419c20685 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3698557953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3698557953 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2395570878 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 93177951 ps |
| CPU time | 5.87 seconds |
| Started | Jan 17 12:24:16 PM PST 24 |
| Finished | Jan 17 12:24:25 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-c92d5d17-ec8f-4c37-8fba-f4419b69fefe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395570878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2395570878 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.826708589 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 56348133 ps |
| CPU time | 1.23 seconds |
| Started | Jan 17 12:24:39 PM PST 24 |
| Finished | Jan 17 12:24:40 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-06c20fcc-c3c2-44c1-b72e-43c819c45cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=826708589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.826708589 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2931148108 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 153870051 ps |
| CPU time | 1.81 seconds |
| Started | Jan 17 12:23:54 PM PST 24 |
| Finished | Jan 17 12:23:57 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-b1efb507-89e3-4896-b9b9-7fd03f790dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931148108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2931148108 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1579738101 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2112810158 ps |
| CPU time | 8.86 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:28 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-3fd374a7-1dc8-4843-a254-33eb49a245f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579738101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1579738101 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2336507662 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 829860722 ps |
| CPU time | 5.35 seconds |
| Started | Jan 17 12:24:16 PM PST 24 |
| Finished | Jan 17 12:24:25 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-3767762c-c20c-4bd4-946a-eb7e4b1a6750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2336507662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2336507662 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2922993711 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 11598588 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 12:23:41 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-5c2e7326-3aff-4df6-94b2-6bec88ff45f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922993711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2922993711 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2163291800 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 67061495 ps |
| CPU time | 1.74 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:33 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-9f127767-6145-498a-9a2c-8d55d71e6f34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2163291800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2163291800 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.900839972 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2746603595 ps |
| CPU time | 34.19 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:24:04 PM PST 24 |
| Peak memory | 198628 kb |
| Host | smart-6ea67d94-62b3-49e4-98d3-e524f1473e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900839972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.900839972 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3873628252 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1191450194 ps |
| CPU time | 118.75 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201688 kb |
| Host | smart-2d81434b-dff5-4640-8fb9-766e08a0472a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3873628252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3873628252 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2016023057 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 175341088 ps |
| CPU time | 25.62 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:24:47 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-a9f86002-cf47-4f8a-953d-9c8c360d6ce4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2016023057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2016023057 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.882727635 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 225279141 ps |
| CPU time | 4.73 seconds |
| Started | Jan 17 12:23:27 PM PST 24 |
| Finished | Jan 17 12:23:35 PM PST 24 |
| Peak memory | 198824 kb |
| Host | smart-6dd60142-6c51-4249-9c45-9c4309c21be7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=882727635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.882727635 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3514688130 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 628333268 ps |
| CPU time | 6.22 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-240fe92e-a4ef-48b6-8357-c9524674bbe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3514688130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3514688130 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.4254914314 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 137078635362 ps |
| CPU time | 268.66 seconds |
| Started | Jan 17 12:21:29 PM PST 24 |
| Finished | Jan 17 12:25:58 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-9486432e-147e-4387-9cf3-cf2e42645174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4254914314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.4254914314 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3745472504 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 83845848 ps |
| CPU time | 5.46 seconds |
| Started | Jan 17 12:21:21 PM PST 24 |
| Finished | Jan 17 12:21:29 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-cb109ec5-2568-4a6a-a012-a4d735af8453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745472504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3745472504 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2249576257 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 989150034 ps |
| CPU time | 5.42 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-852c8a57-2ebe-49bd-a7cd-07c404b16951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2249576257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2249576257 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2732004301 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1002405861 ps |
| CPU time | 5.08 seconds |
| Started | Jan 17 12:23:42 PM PST 24 |
| Finished | Jan 17 12:23:49 PM PST 24 |
| Peak memory | 199652 kb |
| Host | smart-78caa08c-6350-4d31-a8bf-dbf10e1e96f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2732004301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2732004301 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2979599484 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 268562890717 ps |
| CPU time | 143.52 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:26:33 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-f152895a-feca-4254-b9e5-94da0b5fcc92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979599484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2979599484 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3497008196 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 12926794189 ps |
| CPU time | 80.83 seconds |
| Started | Jan 17 12:21:18 PM PST 24 |
| Finished | Jan 17 12:22:44 PM PST 24 |
| Peak memory | 201624 kb |
| Host | smart-9529df6c-3b36-4e9c-a1e6-e4c195bb5d19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3497008196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3497008196 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1275017250 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 62059663 ps |
| CPU time | 8.94 seconds |
| Started | Jan 17 12:21:22 PM PST 24 |
| Finished | Jan 17 12:21:33 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-d38aa999-1744-46fe-bbad-b49b37dd5a5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275017250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1275017250 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.2509288244 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 163245882 ps |
| CPU time | 4.52 seconds |
| Started | Jan 17 12:21:20 PM PST 24 |
| Finished | Jan 17 12:21:28 PM PST 24 |
| Peak memory | 201688 kb |
| Host | smart-46360983-c98b-44ca-ae2a-cdf10705526b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2509288244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2509288244 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.878638726 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 193656620 ps |
| CPU time | 1.77 seconds |
| Started | Jan 17 12:21:12 PM PST 24 |
| Finished | Jan 17 12:21:15 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-23195a1f-c89c-411e-b89a-16caf47d0fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=878638726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.878638726 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1274828972 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3720664484 ps |
| CPU time | 7.12 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-37fc2f38-8614-4cff-81fb-652210259db2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274828972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1274828972 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3216223440 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2201286678 ps |
| CPU time | 13.13 seconds |
| Started | Jan 17 12:21:23 PM PST 24 |
| Finished | Jan 17 12:21:37 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-2509cb60-a317-4382-bc8e-8478e665037b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3216223440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3216223440 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1120181845 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 9697671 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-b3335b79-0d29-475d-bf7b-1b4a8a74673a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120181845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1120181845 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1253081904 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 433931080 ps |
| CPU time | 45.02 seconds |
| Started | Jan 17 12:21:17 PM PST 24 |
| Finished | Jan 17 12:22:08 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-394ade58-ba57-464a-bb7b-f962aed56f63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1253081904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1253081904 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.80499697 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 122624558 ps |
| CPU time | 14.95 seconds |
| Started | Jan 17 12:21:23 PM PST 24 |
| Finished | Jan 17 12:21:39 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-6f4ebd6a-a4f8-455d-891f-731e0d53e99f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=80499697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.80499697 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2904669284 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 4053837104 ps |
| CPU time | 90.65 seconds |
| Started | Jan 17 12:21:29 PM PST 24 |
| Finished | Jan 17 12:23:00 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-7e6e6695-8882-4425-a629-b34069b2d7f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2904669284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2904669284 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1727891093 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 9259997111 ps |
| CPU time | 78.36 seconds |
| Started | Jan 17 12:21:21 PM PST 24 |
| Finished | Jan 17 12:22:42 PM PST 24 |
| Peak memory | 204056 kb |
| Host | smart-92055766-e3a3-4af6-acef-46f4921c5ebe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1727891093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1727891093 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3246398689 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 127972490 ps |
| CPU time | 3.07 seconds |
| Started | Jan 17 12:21:21 PM PST 24 |
| Finished | Jan 17 12:21:27 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-d993a446-b704-4161-9d4c-9b03cd54e7d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3246398689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3246398689 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3429052897 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 64464794 ps |
| CPU time | 7.55 seconds |
| Started | Jan 17 12:21:33 PM PST 24 |
| Finished | Jan 17 12:21:41 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-cccf9b9e-9c07-4fb6-9171-53a7876a1542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3429052897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3429052897 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2814707876 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 114102576 ps |
| CPU time | 6.38 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-c1d44efd-b09f-4d40-b883-853e497e4e75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2814707876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2814707876 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.747187765 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 25012942 ps |
| CPU time | 2.49 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-87cd45bf-879e-40fd-bc4a-f925e0fffc53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=747187765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.747187765 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.492657067 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 374766648 ps |
| CPU time | 2.31 seconds |
| Started | Jan 17 12:54:44 PM PST 24 |
| Finished | Jan 17 12:54:47 PM PST 24 |
| Peak memory | 201692 kb |
| Host | smart-109e3825-b998-40ce-962c-2ec214878759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=492657067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.492657067 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1309613419 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5967586104 ps |
| CPU time | 28.73 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-da02fef1-a29c-4b11-9f58-e6b6859b41e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309613419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1309613419 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2934645832 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 10589359108 ps |
| CPU time | 77.57 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:25:50 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-66aa25a9-c2b0-468b-8bf9-ac9d3fa87627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2934645832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2934645832 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.980332060 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 41042203 ps |
| CPU time | 3.93 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-4355f12f-0194-4618-95f2-e4ac90fa9dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980332060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.980332060 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.4135560062 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 236600639 ps |
| CPU time | 1.57 seconds |
| Started | Jan 17 12:21:32 PM PST 24 |
| Finished | Jan 17 12:21:34 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-1f31db24-3f15-4571-8211-e5b2f793750d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4135560062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4135560062 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1283054177 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 12601371 ps |
| CPU time | 1.22 seconds |
| Started | Jan 17 12:23:42 PM PST 24 |
| Finished | Jan 17 12:23:45 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-1ad64e5c-fa6d-43b7-a0d3-084349dec868 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1283054177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1283054177 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2264036795 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 7857581686 ps |
| CPU time | 10.39 seconds |
| Started | Jan 17 12:21:33 PM PST 24 |
| Finished | Jan 17 12:21:44 PM PST 24 |
| Peak memory | 201600 kb |
| Host | smart-de28c9f7-f5cd-49ac-92ba-24a22bdec801 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264036795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2264036795 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1139861179 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 7039782364 ps |
| CPU time | 12.48 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-d5a8b778-d6ab-4c98-b90f-9027203bcf0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1139861179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1139861179 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.603601976 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 11375437 ps |
| CPU time | 1.27 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-1059c6bf-30e1-4071-a464-e1ea68a4e7cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603601976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.603601976 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3398870384 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8677104441 ps |
| CPU time | 63 seconds |
| Started | Jan 17 12:21:39 PM PST 24 |
| Finished | Jan 17 12:22:43 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-2d430858-c0a2-4f86-ab2e-ca7d650aad57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3398870384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3398870384 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3592784925 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1968537156 ps |
| CPU time | 29.59 seconds |
| Started | Jan 17 12:21:32 PM PST 24 |
| Finished | Jan 17 12:22:02 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-0ef66e9a-4dca-4cf0-af0e-b8aae63466d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3592784925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3592784925 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4005652361 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 271407721 ps |
| CPU time | 26.89 seconds |
| Started | Jan 17 12:21:39 PM PST 24 |
| Finished | Jan 17 12:22:07 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-16b0755e-e1c0-489e-9b04-23f8f75de266 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005652361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.4005652361 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2734128282 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 384335874 ps |
| CPU time | 27.33 seconds |
| Started | Jan 17 12:21:34 PM PST 24 |
| Finished | Jan 17 12:22:03 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-05467128-6999-4097-9383-547dee097069 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2734128282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2734128282 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2438108889 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2733703515 ps |
| CPU time | 8.73 seconds |
| Started | Jan 17 12:24:12 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-597b80e1-dadc-4ff1-a893-6872ad586205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2438108889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2438108889 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1274438536 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 525506140 ps |
| CPU time | 12.44 seconds |
| Started | Jan 17 12:21:39 PM PST 24 |
| Finished | Jan 17 12:21:52 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-005c4e25-edfc-4cfe-941b-a6edddcc0549 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1274438536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1274438536 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3983383433 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 12727558205 ps |
| CPU time | 99.08 seconds |
| Started | Jan 17 12:21:42 PM PST 24 |
| Finished | Jan 17 12:23:26 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-d4aeb459-4bd0-4f8a-a3b1-6bb9340993f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3983383433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3983383433 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2356654246 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 245921224 ps |
| CPU time | 2.82 seconds |
| Started | Jan 17 12:21:51 PM PST 24 |
| Finished | Jan 17 12:21:54 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-f92c5661-46db-4759-bc2a-c570959c2007 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2356654246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2356654246 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.1185509529 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 75089490 ps |
| CPU time | 1.43 seconds |
| Started | Jan 17 12:21:39 PM PST 24 |
| Finished | Jan 17 12:21:41 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-2f934f6e-4bfd-4f87-b36b-cff77d9adc5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1185509529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1185509529 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.644686560 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 87810813 ps |
| CPU time | 7.33 seconds |
| Started | Jan 17 01:10:55 PM PST 24 |
| Finished | Jan 17 01:11:10 PM PST 24 |
| Peak memory | 201728 kb |
| Host | smart-3a870f8c-0b5b-43a9-b338-21b302510cf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=644686560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.644686560 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.566860535 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 16011787176 ps |
| CPU time | 41.18 seconds |
| Started | Jan 17 12:36:33 PM PST 24 |
| Finished | Jan 17 12:37:15 PM PST 24 |
| Peak memory | 201604 kb |
| Host | smart-22d32a15-4965-42de-87c5-32a32d89050d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=566860535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.566860535 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.503023243 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 12351867384 ps |
| CPU time | 81.61 seconds |
| Started | Jan 17 12:21:39 PM PST 24 |
| Finished | Jan 17 12:23:02 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-5f4a73ea-0484-48a7-a2f1-61e5c5acf832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=503023243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.503023243 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3390363442 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 60448448 ps |
| CPU time | 7.51 seconds |
| Started | Jan 17 12:39:01 PM PST 24 |
| Finished | Jan 17 12:39:15 PM PST 24 |
| Peak memory | 201692 kb |
| Host | smart-22065735-c259-4d0f-97f3-7bf768ce25b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390363442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3390363442 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1683798633 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 39409943 ps |
| CPU time | 2.79 seconds |
| Started | Jan 17 12:58:48 PM PST 24 |
| Finished | Jan 17 12:58:52 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-8b370647-d7fe-462b-b6f1-8c8214cad02e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683798633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1683798633 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.2358484087 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 94394838 ps |
| CPU time | 1.36 seconds |
| Started | Jan 17 12:21:36 PM PST 24 |
| Finished | Jan 17 12:21:41 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-914c0e76-2432-4cdc-92c3-c3c76c1dd48f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2358484087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2358484087 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3873907056 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 10595483647 ps |
| CPU time | 10.36 seconds |
| Started | Jan 17 01:09:23 PM PST 24 |
| Finished | Jan 17 01:09:35 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-3d09e500-319b-47be-91c8-fad7b4cc2cd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873907056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3873907056 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1092842727 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 567285600 ps |
| CPU time | 4.94 seconds |
| Started | Jan 17 12:21:36 PM PST 24 |
| Finished | Jan 17 12:21:44 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-853fb2bc-55dd-4833-85ae-84a4d216db7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1092842727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1092842727 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2124309028 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 31088249 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:21:41 PM PST 24 |
| Finished | Jan 17 12:21:48 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-4ad613d2-0968-42ec-b3d1-222c7b9a6cd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124309028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2124309028 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.978974570 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 399781692 ps |
| CPU time | 4.38 seconds |
| Started | Jan 17 01:11:04 PM PST 24 |
| Finished | Jan 17 01:11:09 PM PST 24 |
| Peak memory | 201676 kb |
| Host | smart-093212bd-ec04-44e0-ad37-21f76cd44e96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=978974570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.978974570 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3306472382 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 25359006257 ps |
| CPU time | 83.87 seconds |
| Started | Jan 17 12:21:49 PM PST 24 |
| Finished | Jan 17 12:23:14 PM PST 24 |
| Peak memory | 201644 kb |
| Host | smart-5e3e4b58-8dfb-4812-93cf-a90e53b86730 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3306472382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3306472382 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1621990212 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 397843738 ps |
| CPU time | 42.69 seconds |
| Started | Jan 17 12:21:53 PM PST 24 |
| Finished | Jan 17 12:22:38 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-7b3ec774-1aa3-4cf9-b58a-ba6e42fb4001 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1621990212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1621990212 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1432587465 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 527604453 ps |
| CPU time | 43.65 seconds |
| Started | Jan 17 12:21:55 PM PST 24 |
| Finished | Jan 17 12:22:40 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-e22f50da-f9df-4524-b17a-bc65a88f671a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432587465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1432587465 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.599341808 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 26254561 ps |
| CPU time | 3.14 seconds |
| Started | Jan 17 12:21:42 PM PST 24 |
| Finished | Jan 17 12:21:49 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-45eb47c8-f4e5-4a52-a7a5-2c13275b33e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599341808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.599341808 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.430696316 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 325969909 ps |
| CPU time | 6.6 seconds |
| Started | Jan 17 12:21:49 PM PST 24 |
| Finished | Jan 17 12:21:57 PM PST 24 |
| Peak memory | 201676 kb |
| Host | smart-4766eec0-edd4-4c48-a940-187f3f8a6edb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=430696316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.430696316 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.743823276 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 23795259332 ps |
| CPU time | 126.48 seconds |
| Started | Jan 17 01:07:01 PM PST 24 |
| Finished | Jan 17 01:09:08 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-7b9deac7-c93e-4400-832a-5500496ce2ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=743823276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo w_rsp.743823276 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.4235376035 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 163317401 ps |
| CPU time | 3.96 seconds |
| Started | Jan 17 12:22:02 PM PST 24 |
| Finished | Jan 17 12:22:06 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-3df0e998-0f8c-4b65-a058-dfcdd21b8deb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4235376035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4235376035 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.376727787 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 342157468 ps |
| CPU time | 5.06 seconds |
| Started | Jan 17 01:09:20 PM PST 24 |
| Finished | Jan 17 01:09:30 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-e8032613-ace7-4aad-8795-959091463501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=376727787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.376727787 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2656973289 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 62641129 ps |
| CPU time | 3.03 seconds |
| Started | Jan 17 12:21:50 PM PST 24 |
| Finished | Jan 17 12:21:53 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-1d00c664-66e6-4fc0-bd71-c64227d94852 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2656973289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2656973289 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3495119286 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 75178021030 ps |
| CPU time | 122.34 seconds |
| Started | Jan 17 12:21:57 PM PST 24 |
| Finished | Jan 17 12:24:00 PM PST 24 |
| Peak memory | 202004 kb |
| Host | smart-8fcdffdd-8b1f-4e44-8b8b-5312ceecb588 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495119286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3495119286 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3510681675 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 29992098377 ps |
| CPU time | 171.34 seconds |
| Started | Jan 17 12:21:52 PM PST 24 |
| Finished | Jan 17 12:24:45 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-4a7c354c-c7d8-4153-9793-948b26520af3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3510681675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3510681675 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.944637087 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 194204485 ps |
| CPU time | 9.88 seconds |
| Started | Jan 17 12:21:55 PM PST 24 |
| Finished | Jan 17 12:22:06 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-d07a89b1-357a-44e3-bd21-8abbea0fc028 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944637087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.944637087 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1418683130 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2410045861 ps |
| CPU time | 9.68 seconds |
| Started | Jan 17 12:21:57 PM PST 24 |
| Finished | Jan 17 12:22:07 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-9a2c4e85-a5d9-4628-a0fa-f83e32b4fc43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1418683130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1418683130 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.2971843149 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 12606524 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 12:21:56 PM PST 24 |
| Finished | Jan 17 12:21:58 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-a8c1fb56-0877-4e8b-9c72-26c21fb8d4c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971843149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2971843149 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.121319198 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2016330572 ps |
| CPU time | 7.95 seconds |
| Started | Jan 17 12:21:49 PM PST 24 |
| Finished | Jan 17 12:21:58 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-cf614617-0c0a-47b6-9145-c00ee448d51e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=121319198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.121319198 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1835017421 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1658328976 ps |
| CPU time | 12.57 seconds |
| Started | Jan 17 12:21:49 PM PST 24 |
| Finished | Jan 17 12:22:02 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-0396c409-e53d-4084-a38c-05367aa43f06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1835017421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1835017421 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1670944679 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 17858383 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 12:21:48 PM PST 24 |
| Finished | Jan 17 12:21:50 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-0748fd37-fa7c-4436-bdde-0205cc9905cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670944679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1670944679 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1163129517 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2335670113 ps |
| CPU time | 18.69 seconds |
| Started | Jan 17 12:22:02 PM PST 24 |
| Finished | Jan 17 12:22:21 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-ea979113-ec61-4c7e-8876-900dd3b6b249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1163129517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1163129517 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1674363012 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5158606605 ps |
| CPU time | 48.83 seconds |
| Started | Jan 17 12:21:58 PM PST 24 |
| Finished | Jan 17 12:22:47 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-388ee249-2baa-4d40-9adf-257ee10f0d33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1674363012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1674363012 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1508882658 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 11834031190 ps |
| CPU time | 106.3 seconds |
| Started | Jan 17 12:22:01 PM PST 24 |
| Finished | Jan 17 12:23:48 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-201a87a4-7eaa-43af-aa12-9a53a2fdf2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508882658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1508882658 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1743373386 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 513673156 ps |
| CPU time | 11.5 seconds |
| Started | Jan 17 01:02:35 PM PST 24 |
| Finished | Jan 17 01:02:48 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-5ec13aff-2b23-412e-ab1b-593fdeaafb97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1743373386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1743373386 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1484734098 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 607119365 ps |
| CPU time | 6.13 seconds |
| Started | Jan 17 12:22:07 PM PST 24 |
| Finished | Jan 17 12:22:14 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-02acdfce-ec45-4ec3-9812-8f49cd6f884a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484734098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1484734098 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3805415945 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 51999046828 ps |
| CPU time | 328.19 seconds |
| Started | Jan 17 12:22:03 PM PST 24 |
| Finished | Jan 17 12:27:31 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-61a49fcf-90a5-4f86-8339-c1985b7f8f96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3805415945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3805415945 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2261177964 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 48145617 ps |
| CPU time | 2.59 seconds |
| Started | Jan 17 12:22:14 PM PST 24 |
| Finished | Jan 17 12:22:22 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-59957e78-b42e-49aa-8049-b65f03faba6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261177964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2261177964 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.3569372352 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 12529980 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 12:22:16 PM PST 24 |
| Finished | Jan 17 12:22:21 PM PST 24 |
| Peak memory | 201688 kb |
| Host | smart-4aaa28d1-653d-42b3-a18d-64a8a6b0c6f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569372352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3569372352 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.409352242 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 83400678 ps |
| CPU time | 5.21 seconds |
| Started | Jan 17 12:35:47 PM PST 24 |
| Finished | Jan 17 12:35:54 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-755cfd85-731c-41c6-a813-d85a94f469f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409352242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.409352242 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2687001944 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 23206864390 ps |
| CPU time | 69.19 seconds |
| Started | Jan 17 12:22:04 PM PST 24 |
| Finished | Jan 17 12:23:14 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-f268eea9-eeb4-41d6-a748-e6f10164453d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687001944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2687001944 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1228787985 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 27932053576 ps |
| CPU time | 64.84 seconds |
| Started | Jan 17 12:22:08 PM PST 24 |
| Finished | Jan 17 12:23:15 PM PST 24 |
| Peak memory | 201624 kb |
| Host | smart-f22abe0e-0271-43b1-a9d1-7c050d2deadc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1228787985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1228787985 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2389212957 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 49182647 ps |
| CPU time | 3.67 seconds |
| Started | Jan 17 12:22:00 PM PST 24 |
| Finished | Jan 17 12:22:04 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-393d1a0f-bb73-4692-9c47-f1bcac827ca6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389212957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2389212957 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.36145414 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 11405071 ps |
| CPU time | 1.37 seconds |
| Started | Jan 17 12:22:08 PM PST 24 |
| Finished | Jan 17 12:22:09 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-bab6e521-1393-4fff-b30a-9ef245f25d57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36145414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.36145414 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.903591047 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 55740431 ps |
| CPU time | 1.54 seconds |
| Started | Jan 17 12:21:58 PM PST 24 |
| Finished | Jan 17 12:22:00 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-348825be-e007-4b74-8048-eed448e60e86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=903591047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.903591047 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3168213682 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8188301336 ps |
| CPU time | 11.17 seconds |
| Started | Jan 17 12:21:57 PM PST 24 |
| Finished | Jan 17 12:22:09 PM PST 24 |
| Peak memory | 201632 kb |
| Host | smart-fb9d50ac-4ea6-4b9b-8c93-1edf20a6e3c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168213682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3168213682 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2613762208 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1045931421 ps |
| CPU time | 8.64 seconds |
| Started | Jan 17 12:22:00 PM PST 24 |
| Finished | Jan 17 12:22:09 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ccbc87fc-138b-4bb9-9609-1c6b77fe2877 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2613762208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2613762208 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3698502385 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 14000130 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 12:22:00 PM PST 24 |
| Finished | Jan 17 12:22:02 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-95c18502-68fc-43fd-ad04-c49e44b4eeb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698502385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3698502385 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1530801029 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 877413724 ps |
| CPU time | 29.78 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:22:50 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-fefd81c5-36b1-455c-a893-3e9958595e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1530801029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1530801029 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3120145070 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 17547985370 ps |
| CPU time | 56 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:23:16 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-232000c5-ff9d-4af3-8379-2fe12cb1d104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3120145070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3120145070 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3140545761 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 442497382 ps |
| CPU time | 48.17 seconds |
| Started | Jan 17 12:22:16 PM PST 24 |
| Finished | Jan 17 12:23:08 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-bb548c9b-b504-40a5-81e3-602f790843a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3140545761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3140545761 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3132366541 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 207985775 ps |
| CPU time | 25.83 seconds |
| Started | Jan 17 12:22:15 PM PST 24 |
| Finished | Jan 17 12:22:46 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-f818b680-3f7b-4d0b-9564-840b5d5541aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3132366541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3132366541 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3574864426 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 43834891 ps |
| CPU time | 1.43 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:22:21 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-8960811a-f0d8-4bfc-8715-38ca671118f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3574864426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3574864426 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3385715721 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 35555336 ps |
| CPU time | 6.06 seconds |
| Started | Jan 17 12:27:11 PM PST 24 |
| Finished | Jan 17 12:27:29 PM PST 24 |
| Peak memory | 200128 kb |
| Host | smart-4f945138-28e2-4a66-8d0b-9d9fca3ef940 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3385715721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3385715721 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3356176089 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4139586569 ps |
| CPU time | 19.81 seconds |
| Started | Jan 17 12:21:29 PM PST 24 |
| Finished | Jan 17 12:21:49 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-7097291a-9405-40fb-a887-3d7d355c4d3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3356176089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3356176089 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2067177015 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 86337646 ps |
| CPU time | 2.11 seconds |
| Started | Jan 17 12:20:33 PM PST 24 |
| Finished | Jan 17 12:20:36 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-04d47891-490b-49bb-bc3a-aa5c9c656f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2067177015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2067177015 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1120798819 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1251800539 ps |
| CPU time | 7.55 seconds |
| Started | Jan 17 12:18:19 PM PST 24 |
| Finished | Jan 17 12:18:28 PM PST 24 |
| Peak memory | 200312 kb |
| Host | smart-aa79e198-c023-4090-9678-bf10123ccc4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1120798819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1120798819 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1892167540 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2394173380 ps |
| CPU time | 16.4 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 199348 kb |
| Host | smart-e237e7d5-1f57-4a9e-9bab-c7dd83467d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1892167540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1892167540 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3216553425 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 40999842158 ps |
| CPU time | 157.52 seconds |
| Started | Jan 17 12:18:24 PM PST 24 |
| Finished | Jan 17 12:21:02 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-28ed096d-1b5c-482b-830a-e0c990a62d0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216553425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3216553425 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.223492483 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 15151366511 ps |
| CPU time | 55.75 seconds |
| Started | Jan 17 12:20:04 PM PST 24 |
| Finished | Jan 17 12:21:01 PM PST 24 |
| Peak memory | 199580 kb |
| Host | smart-1256c5b9-51cf-4191-9869-0743141b42dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=223492483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.223492483 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2471610492 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 40539868 ps |
| CPU time | 3.95 seconds |
| Started | Jan 17 12:27:27 PM PST 24 |
| Finished | Jan 17 12:27:31 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-50ab98fb-8736-471b-b147-0e794f8045bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471610492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2471610492 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.2990926764 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 560915507 ps |
| CPU time | 4.94 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 199356 kb |
| Host | smart-193e96cb-0df8-4894-819e-bfc01d563f5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990926764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2990926764 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3609924920 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 40083998 ps |
| CPU time | 1.41 seconds |
| Started | Jan 17 12:27:10 PM PST 24 |
| Finished | Jan 17 12:27:24 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-fadb24b0-cb04-4a93-8f2e-2dab970cfe4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3609924920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3609924920 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1417273605 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1108519753 ps |
| CPU time | 5.59 seconds |
| Started | Jan 17 12:26:42 PM PST 24 |
| Finished | Jan 17 12:26:49 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-d26a4521-dcfe-498f-a26f-7ac8ac43460e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417273605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1417273605 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1324721640 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1272943446 ps |
| CPU time | 6.62 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-84865788-3cc3-477f-b106-851e11dd2d67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1324721640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1324721640 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1519259071 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 10175396 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 12:20:27 PM PST 24 |
| Finished | Jan 17 12:20:32 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-549def04-f7bc-4094-928d-fc07e710f48c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519259071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1519259071 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3837931778 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4691852057 ps |
| CPU time | 78.46 seconds |
| Started | Jan 17 12:20:31 PM PST 24 |
| Finished | Jan 17 12:21:50 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-9566a79c-56c9-47cd-8101-07213a9c7e45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3837931778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3837931778 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3163814802 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1969555213 ps |
| CPU time | 26.22 seconds |
| Started | Jan 17 12:18:10 PM PST 24 |
| Finished | Jan 17 12:18:39 PM PST 24 |
| Peak memory | 201724 kb |
| Host | smart-e6e531ce-839b-450a-828f-1a3a22beb91b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163814802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3163814802 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1704210858 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 406120814 ps |
| CPU time | 41.47 seconds |
| Started | Jan 17 12:23:58 PM PST 24 |
| Finished | Jan 17 12:24:42 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-88560bdc-6074-47f2-bd4f-64a7bdd4b9d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1704210858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1704210858 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.244137669 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 173600231 ps |
| CPU time | 40.82 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:25:12 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-ea5a0352-97ae-4694-ad19-b774950eddf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=244137669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.244137669 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2589518845 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 46297366 ps |
| CPU time | 3.75 seconds |
| Started | Jan 17 12:21:29 PM PST 24 |
| Finished | Jan 17 12:21:33 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-1b3fe0fa-b803-47c3-86b5-e3fe47377f50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589518845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2589518845 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1661443504 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1258620438 ps |
| CPU time | 21.46 seconds |
| Started | Jan 17 12:22:22 PM PST 24 |
| Finished | Jan 17 12:22:45 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-98f19447-3154-40c2-87af-9a3c99f02586 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1661443504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1661443504 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2088132288 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 14946503257 ps |
| CPU time | 70.09 seconds |
| Started | Jan 17 12:22:23 PM PST 24 |
| Finished | Jan 17 12:23:33 PM PST 24 |
| Peak memory | 201612 kb |
| Host | smart-3fbaf3d7-7f32-4f2c-a793-29be3b411978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2088132288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2088132288 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1890604616 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 371387220 ps |
| CPU time | 3.73 seconds |
| Started | Jan 17 12:22:22 PM PST 24 |
| Finished | Jan 17 12:22:27 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-ccf305dd-6f8b-447f-93a9-d635b97ae644 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890604616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1890604616 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.222951847 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 900042239 ps |
| CPU time | 7.84 seconds |
| Started | Jan 17 12:22:26 PM PST 24 |
| Finished | Jan 17 12:22:34 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-136721d9-18b4-4185-af7e-09fa0a795ed7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=222951847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.222951847 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.2649572737 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 769496695 ps |
| CPU time | 2.87 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:22:23 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-ce540855-d3e3-4643-a333-35bf7ddbde84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649572737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2649572737 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2508628165 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 6862688450 ps |
| CPU time | 19.01 seconds |
| Started | Jan 17 12:22:13 PM PST 24 |
| Finished | Jan 17 12:22:33 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-7be711db-aed1-4746-a892-1a645f33e06e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508628165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2508628165 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1322750905 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 7768244382 ps |
| CPU time | 51.32 seconds |
| Started | Jan 17 12:22:21 PM PST 24 |
| Finished | Jan 17 12:23:13 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-99919fc7-4b70-4b05-9b17-1680a1e29d09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1322750905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1322750905 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2066899404 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 90431415 ps |
| CPU time | 3.33 seconds |
| Started | Jan 17 12:22:11 PM PST 24 |
| Finished | Jan 17 12:22:16 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-c11f3910-f695-404f-a4ca-33521ad2b359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066899404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2066899404 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.2878613141 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2281997183 ps |
| CPU time | 9.74 seconds |
| Started | Jan 17 12:22:22 PM PST 24 |
| Finished | Jan 17 12:22:33 PM PST 24 |
| Peak memory | 201648 kb |
| Host | smart-cbcdd99f-bf9d-46b5-82a2-0e559b29fbfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878613141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2878613141 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2857732972 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 147166695 ps |
| CPU time | 1.62 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:22:22 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-74c7d622-f75e-4b82-80c3-66366654d8ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2857732972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2857732972 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2085753955 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3050660189 ps |
| CPU time | 10.66 seconds |
| Started | Jan 17 12:22:16 PM PST 24 |
| Finished | Jan 17 12:22:31 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-adbac10f-c491-424c-a1a2-cc7e469064bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085753955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2085753955 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.978238950 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1606652783 ps |
| CPU time | 4.84 seconds |
| Started | Jan 17 12:22:16 PM PST 24 |
| Finished | Jan 17 12:22:25 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-64e83c17-f5be-499c-bb48-de9aa8164a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=978238950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.978238950 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3120171982 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 13722851 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:22:19 PM PST 24 |
| Finished | Jan 17 12:22:21 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-a24d070a-879f-4734-b704-85a451b6a31f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120171982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3120171982 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3105056580 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 494025697 ps |
| CPU time | 22.62 seconds |
| Started | Jan 17 12:22:26 PM PST 24 |
| Finished | Jan 17 12:22:49 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-8346da0b-67fc-47f0-8291-238d3f83cac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3105056580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3105056580 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.303407610 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 173076498 ps |
| CPU time | 6.31 seconds |
| Started | Jan 17 12:22:27 PM PST 24 |
| Finished | Jan 17 12:22:34 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-0d8f28a4-5a8b-42e4-8536-27a537ffb693 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303407610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.303407610 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4277085082 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1705577386 ps |
| CPU time | 64.05 seconds |
| Started | Jan 17 12:22:22 PM PST 24 |
| Finished | Jan 17 12:23:27 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-e549dec9-10a3-4730-871c-45fa401674e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4277085082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.4277085082 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2774928584 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 488092572 ps |
| CPU time | 62.92 seconds |
| Started | Jan 17 12:22:21 PM PST 24 |
| Finished | Jan 17 12:23:24 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-f35e270a-cc4d-4b1c-b8b0-41daf6f84b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2774928584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2774928584 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.93136091 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 35348431 ps |
| CPU time | 3.59 seconds |
| Started | Jan 17 12:22:21 PM PST 24 |
| Finished | Jan 17 12:22:25 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-d0f37695-448b-45a0-aedf-9b73342720ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=93136091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.93136091 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.851378992 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 151326579 ps |
| CPU time | 1.78 seconds |
| Started | Jan 17 12:22:37 PM PST 24 |
| Finished | Jan 17 12:22:40 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-5b11aa4b-1a83-4c02-a23b-f682867daa57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851378992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.851378992 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2169530467 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 105098540 ps |
| CPU time | 4.19 seconds |
| Started | Jan 17 12:22:45 PM PST 24 |
| Finished | Jan 17 12:22:51 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-22f55652-0e6f-4de0-92a7-284f25c3793b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2169530467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2169530467 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.958345543 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 736696825 ps |
| CPU time | 9.09 seconds |
| Started | Jan 17 12:22:43 PM PST 24 |
| Finished | Jan 17 12:22:53 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-39df0a43-f340-4b6c-ae9f-97305334e0b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958345543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.958345543 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.474726451 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 241311141 ps |
| CPU time | 3.39 seconds |
| Started | Jan 17 12:22:28 PM PST 24 |
| Finished | Jan 17 12:22:34 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-49f94476-24bb-4307-ab3e-0390f07b1e7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=474726451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.474726451 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.977507767 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 9813788406 ps |
| CPU time | 31.28 seconds |
| Started | Jan 17 12:22:45 PM PST 24 |
| Finished | Jan 17 12:23:18 PM PST 24 |
| Peak memory | 201644 kb |
| Host | smart-b24f80cc-2b4f-4457-9351-672968ca7609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=977507767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.977507767 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1443000916 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15156310771 ps |
| CPU time | 83.57 seconds |
| Started | Jan 17 12:22:39 PM PST 24 |
| Finished | Jan 17 12:24:03 PM PST 24 |
| Peak memory | 201736 kb |
| Host | smart-516e42f6-6469-4b36-ba89-ebe18f6563e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1443000916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1443000916 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.500481646 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 100771371 ps |
| CPU time | 5.9 seconds |
| Started | Jan 17 12:22:34 PM PST 24 |
| Finished | Jan 17 12:22:41 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-897defef-5b4a-4b55-8358-6acbbfabb8ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500481646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.500481646 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2327049111 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 9471110 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:22:41 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-14f09081-431c-45ea-a9f1-dbcb888cc8c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327049111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2327049111 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.388610667 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 40106833 ps |
| CPU time | 1.57 seconds |
| Started | Jan 17 12:22:27 PM PST 24 |
| Finished | Jan 17 12:22:29 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-36ea290f-74c3-466e-a7f8-4a811c4b1f39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=388610667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.388610667 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2598173869 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2028249349 ps |
| CPU time | 6.5 seconds |
| Started | Jan 17 12:22:28 PM PST 24 |
| Finished | Jan 17 12:22:37 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-5c0a2d3b-7b49-42a7-97d2-51128fe26f33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598173869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2598173869 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2658807307 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 15588046489 ps |
| CPU time | 14.34 seconds |
| Started | Jan 17 12:22:29 PM PST 24 |
| Finished | Jan 17 12:22:45 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ed4b66ce-7ac4-42cc-a17d-8565961371e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2658807307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2658807307 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2562060517 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 24267920 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 12:22:27 PM PST 24 |
| Finished | Jan 17 12:22:29 PM PST 24 |
| Peak memory | 201944 kb |
| Host | smart-a84c7ab7-64af-4d97-8d60-9bb094d05b7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562060517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2562060517 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1257534100 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 410159346 ps |
| CPU time | 29.68 seconds |
| Started | Jan 17 12:22:45 PM PST 24 |
| Finished | Jan 17 12:23:16 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-ad2859ce-622e-4328-b39b-5dc93a089d5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1257534100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1257534100 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3810272466 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 210530057 ps |
| CPU time | 16.28 seconds |
| Started | Jan 17 12:22:43 PM PST 24 |
| Finished | Jan 17 12:23:00 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-847086fa-fe7d-4891-8c29-9c8c411a36aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810272466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3810272466 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2943259883 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 346296882 ps |
| CPU time | 44.87 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:23:25 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-260df15e-b2dd-47f2-971f-c9211ab8f525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2943259883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2943259883 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1720931368 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4819429378 ps |
| CPU time | 32.35 seconds |
| Started | Jan 17 12:22:48 PM PST 24 |
| Finished | Jan 17 12:23:26 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-7cf76e51-bf8d-43f5-8dac-1b69cbf4d5ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1720931368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1720931368 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.4132793063 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 169876857 ps |
| CPU time | 2.53 seconds |
| Started | Jan 17 12:22:35 PM PST 24 |
| Finished | Jan 17 12:22:38 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-15ef6f23-018b-4711-9e22-e4d747e9cef7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4132793063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4132793063 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3534870079 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 183782485 ps |
| CPU time | 2.69 seconds |
| Started | Jan 17 12:22:57 PM PST 24 |
| Finished | Jan 17 12:23:00 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-c8cb1ee4-530a-4e5e-8479-a36f2ba3c149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534870079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3534870079 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3000004046 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 788545153 ps |
| CPU time | 5.41 seconds |
| Started | Jan 17 12:22:56 PM PST 24 |
| Finished | Jan 17 12:23:01 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-2957e0f8-11a4-46b3-abe6-a775af690b48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3000004046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3000004046 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.998825841 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 937499628 ps |
| CPU time | 11.07 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:23:07 PM PST 24 |
| Peak memory | 201212 kb |
| Host | smart-feafee27-963d-46b8-ae1e-2d7abbad4d8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=998825841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.998825841 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1333026914 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2362104859 ps |
| CPU time | 10.8 seconds |
| Started | Jan 17 12:22:48 PM PST 24 |
| Finished | Jan 17 12:23:04 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-f4cd8147-d3a9-4973-b5aa-96cb07b090d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1333026914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1333026914 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1818408250 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 33748056341 ps |
| CPU time | 146.11 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-1b413560-6dfd-429d-b27f-0c20ea61364e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818408250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1818408250 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3040014200 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 31356649412 ps |
| CPU time | 75.15 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:24:10 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-4e17df6f-4008-4636-87de-28a37ae0abee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3040014200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3040014200 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1179353033 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 61308859 ps |
| CPU time | 7.89 seconds |
| Started | Jan 17 12:22:57 PM PST 24 |
| Finished | Jan 17 12:23:05 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-c7546319-d659-4b7b-8f9b-aa38f1aa37c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179353033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1179353033 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1811007893 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 121583459 ps |
| CPU time | 4.72 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:22:59 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-d35e95d9-0fe5-4b54-ba02-4141e62b9019 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1811007893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1811007893 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2694988959 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 37509162 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 12:22:46 PM PST 24 |
| Finished | Jan 17 12:22:48 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-b919fda7-e28e-4057-98c9-91a073ac18cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694988959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2694988959 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1603246908 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14367228092 ps |
| CPU time | 9.06 seconds |
| Started | Jan 17 12:22:48 PM PST 24 |
| Finished | Jan 17 12:23:02 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-69d7f99b-1b32-45c3-a5f8-9671400b9404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603246908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1603246908 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2224208146 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 815268849 ps |
| CPU time | 6.41 seconds |
| Started | Jan 17 12:22:48 PM PST 24 |
| Finished | Jan 17 12:23:00 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-8d5a1be2-ec4e-4f6b-ab54-844b109d1840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2224208146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2224208146 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.745081855 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 11136102 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 12:22:52 PM PST 24 |
| Finished | Jan 17 12:22:55 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-d40a9565-311c-4c1a-9102-26c2b2a49769 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745081855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.745081855 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3407419698 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 806777999 ps |
| CPU time | 38.81 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:23:33 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-1e8d51b9-addc-4317-92d2-efd6d450cba1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3407419698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3407419698 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2462012478 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 469589379 ps |
| CPU time | 40.49 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:23:35 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-9667d99f-7091-4579-87e6-8247790e53b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2462012478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2462012478 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1949952241 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 5783430242 ps |
| CPU time | 86.5 seconds |
| Started | Jan 17 12:22:52 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 203968 kb |
| Host | smart-034ef9a5-69d2-4bde-bd7d-0f3b50fa44a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949952241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1949952241 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2949313141 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7315132935 ps |
| CPU time | 123.91 seconds |
| Started | Jan 17 12:22:54 PM PST 24 |
| Finished | Jan 17 12:24:59 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-53e3dcf4-33e0-411f-b51c-05d5df29a994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949313141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.2949313141 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2498279857 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 89395360 ps |
| CPU time | 1.44 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:22:57 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-3cbd5474-9957-487b-a87a-b2520be42804 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2498279857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2498279857 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4063171182 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 85507130 ps |
| CPU time | 11.84 seconds |
| Started | Jan 17 12:23:12 PM PST 24 |
| Finished | Jan 17 12:23:29 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-d3945396-e3b6-413d-9929-e290f7ed8b0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063171182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4063171182 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2429862029 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 12962746377 ps |
| CPU time | 53.85 seconds |
| Started | Jan 17 12:23:11 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-02fbdf14-64c0-49ec-949d-ded451455d06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2429862029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2429862029 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1760926806 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2047189136 ps |
| CPU time | 7.91 seconds |
| Started | Jan 17 12:23:13 PM PST 24 |
| Finished | Jan 17 12:23:25 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-37513ed0-6b07-44cb-9fd3-a624db8db12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1760926806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1760926806 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2719123307 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 856965323 ps |
| CPU time | 11.67 seconds |
| Started | Jan 17 12:23:09 PM PST 24 |
| Finished | Jan 17 12:23:21 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-151d2dd8-fcda-4d87-ae6e-b36e6e8f5f50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719123307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2719123307 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3808155907 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1855250191 ps |
| CPU time | 4.43 seconds |
| Started | Jan 17 12:23:04 PM PST 24 |
| Finished | Jan 17 12:23:10 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-b93df66d-b97f-45b3-b659-d4b16593ce64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3808155907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3808155907 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.656267053 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 31284984438 ps |
| CPU time | 66.36 seconds |
| Started | Jan 17 12:23:00 PM PST 24 |
| Finished | Jan 17 12:24:07 PM PST 24 |
| Peak memory | 201980 kb |
| Host | smart-8fbcd9f4-ff20-4fb3-9200-5881b1c4bf2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=656267053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.656267053 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2966823365 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5411793068 ps |
| CPU time | 29.3 seconds |
| Started | Jan 17 12:23:10 PM PST 24 |
| Finished | Jan 17 12:23:46 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-8a0918e1-a470-45c2-8ef9-a465ad250240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2966823365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2966823365 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.591853615 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 21313947 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 12:23:01 PM PST 24 |
| Finished | Jan 17 12:23:03 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-9066da1b-5fd0-4d6e-b6d5-d5a031c76d53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591853615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.591853615 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3026866329 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 40681572 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 12:23:09 PM PST 24 |
| Finished | Jan 17 12:23:11 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-129cad66-271b-4e0f-849e-b93b2d77823f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026866329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3026866329 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.121125151 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 80060098 ps |
| CPU time | 1.68 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:22:57 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-dbcf59fd-913b-42e7-a66b-ddd79df0830d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121125151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.121125151 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.799949618 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4042272184 ps |
| CPU time | 10 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:23:05 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-54f87d34-2fc2-45eb-b809-ab7830bebd58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=799949618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.799949618 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1155109025 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 997287201 ps |
| CPU time | 7.56 seconds |
| Started | Jan 17 12:23:05 PM PST 24 |
| Finished | Jan 17 12:23:14 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-5e0b3de7-0c63-47b0-b008-5005c17385f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1155109025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1155109025 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1307343783 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 12537307 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:22:57 PM PST 24 |
| Peak memory | 201228 kb |
| Host | smart-d6629d62-b674-4012-b639-ad35a2b20b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307343783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1307343783 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1292156869 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8059858130 ps |
| CPU time | 31.47 seconds |
| Started | Jan 17 12:23:13 PM PST 24 |
| Finished | Jan 17 12:23:48 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-28d2efa8-c643-41f0-842c-ee1c23f9bafd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1292156869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1292156869 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2351091782 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 8202105852 ps |
| CPU time | 94.85 seconds |
| Started | Jan 17 12:23:08 PM PST 24 |
| Finished | Jan 17 12:24:45 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-5f5fac68-9c7b-4c79-a895-cecb2c331d3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2351091782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2351091782 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4127758655 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1488482441 ps |
| CPU time | 57.78 seconds |
| Started | Jan 17 12:23:08 PM PST 24 |
| Finished | Jan 17 12:24:07 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-97977f9a-5bdd-4e05-9588-7ba9c9d03c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127758655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.4127758655 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1517757204 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 136115073 ps |
| CPU time | 25.13 seconds |
| Started | Jan 17 12:23:19 PM PST 24 |
| Finished | Jan 17 12:23:45 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-7a6e67b6-ed60-47f1-b19f-8a28d33ca01b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1517757204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1517757204 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3237350534 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 287900204 ps |
| CPU time | 4.76 seconds |
| Started | Jan 17 12:23:10 PM PST 24 |
| Finished | Jan 17 12:23:21 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-1f2fac12-cf74-4ec1-9154-f1eac8d94629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237350534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3237350534 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1170110715 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 49247871 ps |
| CPU time | 4.84 seconds |
| Started | Jan 17 12:23:20 PM PST 24 |
| Finished | Jan 17 12:23:25 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-6e293871-ade8-444c-a99c-40beb23ce87f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170110715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1170110715 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1639171575 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 43745051091 ps |
| CPU time | 349.94 seconds |
| Started | Jan 17 12:23:20 PM PST 24 |
| Finished | Jan 17 12:29:11 PM PST 24 |
| Peak memory | 204232 kb |
| Host | smart-fcb1450e-135d-4611-95aa-f02cd9c1ca3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1639171575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.1639171575 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3175408520 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 842170951 ps |
| CPU time | 12.27 seconds |
| Started | Jan 17 12:23:57 PM PST 24 |
| Finished | Jan 17 12:24:09 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-da0abecb-bb74-48f1-8f72-5158ce5f8f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175408520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3175408520 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.4095046489 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 356126006 ps |
| CPU time | 3.92 seconds |
| Started | Jan 17 12:23:18 PM PST 24 |
| Finished | Jan 17 12:23:23 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-21ff0de5-57b4-48bf-80b9-826db07080be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4095046489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4095046489 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.2846370077 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 112741461 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 12:23:17 PM PST 24 |
| Finished | Jan 17 12:23:19 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-9c000702-23a7-4eb5-9540-de797c7062ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846370077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2846370077 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1461950644 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1323671808 ps |
| CPU time | 6.52 seconds |
| Started | Jan 17 12:23:18 PM PST 24 |
| Finished | Jan 17 12:23:25 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-85e50ce8-7661-4fe0-82cc-391abaecc4c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461950644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1461950644 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.230773769 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1232874593 ps |
| CPU time | 7.1 seconds |
| Started | Jan 17 12:23:17 PM PST 24 |
| Finished | Jan 17 12:23:25 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-b65b3f6e-7371-4fa8-b9d9-689eb70cc90e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=230773769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.230773769 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.135588701 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 57030682 ps |
| CPU time | 6.22 seconds |
| Started | Jan 17 12:23:20 PM PST 24 |
| Finished | Jan 17 12:23:27 PM PST 24 |
| Peak memory | 201684 kb |
| Host | smart-c0365ea3-fe4e-4b9f-aa1e-80f4ea006857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135588701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.135588701 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.2794674239 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 16961606 ps |
| CPU time | 1.93 seconds |
| Started | Jan 17 12:23:17 PM PST 24 |
| Finished | Jan 17 12:23:19 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-6c17729d-ccc4-4a4f-ad66-bd8408c87061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2794674239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2794674239 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.4001657310 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 177967888 ps |
| CPU time | 1.54 seconds |
| Started | Jan 17 12:23:20 PM PST 24 |
| Finished | Jan 17 12:23:23 PM PST 24 |
| Peak memory | 201672 kb |
| Host | smart-7d090467-60a9-4d10-914b-b38861a79fee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4001657310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4001657310 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1625258208 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2030199173 ps |
| CPU time | 10.22 seconds |
| Started | Jan 17 12:23:19 PM PST 24 |
| Finished | Jan 17 12:23:30 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-3370de96-a4e4-4695-a94c-b66fa98d754e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625258208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1625258208 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1100082600 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 798244981 ps |
| CPU time | 6.39 seconds |
| Started | Jan 17 12:23:17 PM PST 24 |
| Finished | Jan 17 12:23:24 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-55dcc30c-7b6b-4428-9169-d5308b0512d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1100082600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1100082600 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2691776192 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 9117570 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:23:17 PM PST 24 |
| Finished | Jan 17 12:23:19 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-b0d0b55e-5e04-4350-a536-a646dc22353f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691776192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2691776192 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3230687043 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 70252751 ps |
| CPU time | 9.32 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:24:04 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-a9739bad-179d-4ada-9102-f8f5b2fc6719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3230687043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3230687043 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.4221891624 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 887929366 ps |
| CPU time | 8.71 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:24:04 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-4d060aa1-ef49-42c4-9708-0660d0272626 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221891624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4221891624 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.670566877 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 82070944 ps |
| CPU time | 17.96 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:24:13 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-74ace614-5d14-4d44-b904-923bf874378c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670566877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.670566877 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2041914232 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2850459152 ps |
| CPU time | 21.02 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-c486f3b1-48d7-405c-ae1e-af13b9549abe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2041914232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2041914232 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3240253593 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 98810497 ps |
| CPU time | 3.24 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:23:58 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-9d5278e1-f169-4916-b08c-9ae9cb13b5e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3240253593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3240253593 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.4181084357 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 24760019 ps |
| CPU time | 2.12 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-5a8c8d11-79da-4e83-b7dd-b675bb7e12d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4181084357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.4181084357 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.679607079 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 114539343966 ps |
| CPU time | 298 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:28:59 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-c46c1007-ba3c-4b25-8188-b3db649ad7f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=679607079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.679607079 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2509662351 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 625611115 ps |
| CPU time | 10.13 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-26c3b1b6-9452-4be3-9903-3cd975b1fb81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2509662351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2509662351 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.3889130109 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 344252107 ps |
| CPU time | 3.63 seconds |
| Started | Jan 17 12:24:12 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-aead9d1f-bb8e-4469-a7c8-d9dc412ff549 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3889130109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3889130109 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3226552504 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 96250764 ps |
| CPU time | 5.38 seconds |
| Started | Jan 17 12:23:52 PM PST 24 |
| Finished | Jan 17 12:23:58 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-570bf9c6-87ce-443c-9468-b179baa55f7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3226552504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3226552504 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2266250906 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 29649765196 ps |
| CPU time | 51.41 seconds |
| Started | Jan 17 12:23:58 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-7aaa0181-3227-4bc1-af7a-6ec049badac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266250906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2266250906 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.858442854 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 21732364723 ps |
| CPU time | 46.5 seconds |
| Started | Jan 17 12:23:57 PM PST 24 |
| Finished | Jan 17 12:24:44 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-f367b108-74e4-477e-94a4-79fa721f2841 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=858442854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.858442854 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2073147031 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 289392139 ps |
| CPU time | 3.65 seconds |
| Started | Jan 17 12:23:55 PM PST 24 |
| Finished | Jan 17 12:23:59 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-de648233-d395-494a-a302-980c257598f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073147031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2073147031 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2854965738 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 16942693 ps |
| CPU time | 1.49 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:09 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-46ad6db1-e7be-4524-a0c1-ba5f682eb305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854965738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2854965738 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.4088607814 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 64427143 ps |
| CPU time | 1.4 seconds |
| Started | Jan 17 12:23:54 PM PST 24 |
| Finished | Jan 17 12:23:56 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-efc2ed9b-ee6f-4182-ab4d-839815a202e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4088607814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4088607814 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.292857811 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7124004967 ps |
| CPU time | 10.8 seconds |
| Started | Jan 17 12:23:56 PM PST 24 |
| Finished | Jan 17 12:24:07 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-78ac8219-6e87-44fc-b1a3-27010100a8c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=292857811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.292857811 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.269262077 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3667242654 ps |
| CPU time | 10.25 seconds |
| Started | Jan 17 12:23:52 PM PST 24 |
| Finished | Jan 17 12:24:03 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-5bb8ccc8-ad03-495a-84d7-2f96912406d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=269262077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.269262077 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3973935425 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 10579837 ps |
| CPU time | 1.27 seconds |
| Started | Jan 17 12:23:53 PM PST 24 |
| Finished | Jan 17 12:23:55 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-595f6777-80d1-40b8-8793-dccb38b06045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973935425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3973935425 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3021495694 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 729441508 ps |
| CPU time | 15.71 seconds |
| Started | Jan 17 12:23:57 PM PST 24 |
| Finished | Jan 17 12:24:13 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-d1d79a16-ced3-45e0-9622-1f83f9d12457 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021495694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3021495694 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1822931462 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 16924696429 ps |
| CPU time | 57.88 seconds |
| Started | Jan 17 12:24:12 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-5a439e10-889d-48f0-89b8-37274e7f8e04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822931462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1822931462 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.546604416 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 670750636 ps |
| CPU time | 82.88 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:25:31 PM PST 24 |
| Peak memory | 205344 kb |
| Host | smart-56be68c1-5c2b-4cdb-992b-a09dd3aad79a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546604416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.546604416 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.4262923288 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4146230589 ps |
| CPU time | 122.1 seconds |
| Started | Jan 17 12:24:06 PM PST 24 |
| Finished | Jan 17 12:26:08 PM PST 24 |
| Peak memory | 205540 kb |
| Host | smart-95936c68-d277-45bd-b812-75802cde7604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4262923288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.4262923288 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1302470518 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 262364810 ps |
| CPU time | 4.59 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:18 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-1e726f1d-c57d-4fa4-ab5a-a33e16498cfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302470518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1302470518 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.198075273 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 232183278 ps |
| CPU time | 10.2 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-b5040380-890f-459b-904b-86f56399a158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=198075273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.198075273 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3931942234 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 23462521560 ps |
| CPU time | 57.3 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:26:16 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-5b657563-4368-4f24-99ee-86135006f734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3931942234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3931942234 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1889938499 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 566712282 ps |
| CPU time | 2.76 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-01fe6285-0d0b-4c03-ba04-4914a7c44909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1889938499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1889938499 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3134199898 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 242506767 ps |
| CPU time | 1.42 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:03 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-1cdd49ec-9a8b-46ed-a301-ea133a2bb55e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3134199898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3134199898 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.1368599323 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5206974346 ps |
| CPU time | 10.82 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 201608 kb |
| Host | smart-175bfbaf-fd2c-4154-9dc3-acacc3a62012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1368599323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1368599323 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3652761845 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5422222046 ps |
| CPU time | 24.08 seconds |
| Started | Jan 17 12:25:01 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-0f7306b5-4d6b-4a51-9905-863ea2da538b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652761845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3652761845 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2461345362 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11633426464 ps |
| CPU time | 74.96 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201604 kb |
| Host | smart-d09d4e56-c91d-4e8b-9e8c-b44ed5cc77f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2461345362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2461345362 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2041790842 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 117843076 ps |
| CPU time | 2.9 seconds |
| Started | Jan 17 12:24:12 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-696fbc51-bf45-4241-9290-0cc64ab73972 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041790842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2041790842 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.1331242673 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3619277651 ps |
| CPU time | 6.85 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:19 PM PST 24 |
| Peak memory | 201616 kb |
| Host | smart-8337a770-1b7a-493a-adca-62ad6caece14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1331242673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1331242673 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.3788923070 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 62440312 ps |
| CPU time | 1.63 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-7ff78d98-01aa-4264-bee1-f7246a3f232f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788923070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3788923070 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3397510347 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2337183071 ps |
| CPU time | 7.44 seconds |
| Started | Jan 17 12:24:06 PM PST 24 |
| Finished | Jan 17 12:24:14 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-12450e1d-3706-4cfb-995b-3fce6f26444a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397510347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3397510347 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4078756869 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2314066068 ps |
| CPU time | 8.31 seconds |
| Started | Jan 17 12:24:12 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-7a47ecc4-4a72-4576-a7af-54a38e764625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4078756869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4078756869 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4176449690 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 10124982 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:03 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-06bc4e2b-5da0-4c48-bd55-7d2213024681 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176449690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4176449690 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.4060450980 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 722061868 ps |
| CPU time | 24.11 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 202140 kb |
| Host | smart-e0260357-5749-4ec4-b38c-c0b5e0ae7c71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060450980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.4060450980 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1083327075 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 77692579 ps |
| CPU time | 6.76 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-750a181a-a565-4fb7-8229-9043fa07b9e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1083327075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1083327075 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2141242020 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 878257247 ps |
| CPU time | 40.42 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-af60027d-ba20-43bc-8bec-dab4290746db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141242020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2141242020 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.132766956 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 5127596147 ps |
| CPU time | 85.49 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:25:47 PM PST 24 |
| Peak memory | 205152 kb |
| Host | smart-d8905a73-c2a0-43fa-9b96-42144173a24f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=132766956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.132766956 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.108253923 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 250569240 ps |
| CPU time | 4.23 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:16 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-1140c7be-81b7-4414-9c36-c4fe2e1cde34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=108253923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.108253923 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2163868341 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 916661000 ps |
| CPU time | 5.34 seconds |
| Started | Jan 17 12:24:06 PM PST 24 |
| Finished | Jan 17 12:24:12 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-684dd850-a80f-41ff-858b-07a1f316bf2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2163868341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2163868341 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2243122913 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 23886164549 ps |
| CPU time | 117.37 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:26:09 PM PST 24 |
| Peak memory | 200820 kb |
| Host | smart-61022afc-105b-4323-83e9-0662b9f8ae80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2243122913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2243122913 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1651885239 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 85906631 ps |
| CPU time | 1.31 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-4b7a2856-07ad-4b4c-a19e-fb992caf5b80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1651885239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1651885239 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3213283920 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 167413455 ps |
| CPU time | 8.2 seconds |
| Started | Jan 17 12:23:58 PM PST 24 |
| Finished | Jan 17 12:24:06 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-11db7ca6-ad7c-4385-bb1a-2d53f3699686 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3213283920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3213283920 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2368445597 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 164812662 ps |
| CPU time | 5.73 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-a7c4fb0e-12d7-462b-9057-7245c6dc17f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2368445597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2368445597 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3697857047 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 134195647434 ps |
| CPU time | 119.88 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:26:01 PM PST 24 |
| Peak memory | 201644 kb |
| Host | smart-67b1c36a-cbe8-460c-86cf-ca715374bec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697857047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3697857047 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.940581800 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 66285478104 ps |
| CPU time | 171.27 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:27:06 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-36c72240-38b5-4536-9d48-c95d324c2860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=940581800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.940581800 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1670939132 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 139731310 ps |
| CPU time | 8.01 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-e8c3a6ef-3a3f-49fc-9cc9-cea54ad97882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670939132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1670939132 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3598356995 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 27160560 ps |
| CPU time | 1.93 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-1ff26615-261b-46fd-88a9-023161502ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3598356995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3598356995 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1626431104 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 11477426 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-e8f44a9f-dc91-4640-a80c-90a0fcef2ecf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1626431104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1626431104 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1160328398 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3303302456 ps |
| CPU time | 6.86 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-d49a14b8-37c1-4dc4-a0a7-eb515a797698 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160328398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1160328398 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2965961004 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2692862584 ps |
| CPU time | 8.36 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:24 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-6867c4bb-1a5a-4290-9a02-ed5b661102b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2965961004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2965961004 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3510381422 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 11307428 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:12 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-00c6b6de-7ae9-486d-9b60-a37cd06ad2f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510381422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3510381422 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.764252179 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 3989065220 ps |
| CPU time | 47.18 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-293e3168-f8c8-44b3-8537-6c681e874a20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=764252179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.764252179 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3094849609 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 356598692 ps |
| CPU time | 17.3 seconds |
| Started | Jan 17 12:24:01 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-f20c312f-45c9-451c-980b-8c9ce7b1bb77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094849609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3094849609 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1765019291 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7961964475 ps |
| CPU time | 126.39 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:26:21 PM PST 24 |
| Peak memory | 205216 kb |
| Host | smart-73b4fc96-457a-4ae3-8a0a-d9d0dc0b7177 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1765019291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1765019291 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4090806640 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 7800880180 ps |
| CPU time | 42.25 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-d1433715-99b6-4858-8dfc-3cd7ef686214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090806640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.4090806640 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3287446544 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 186594194 ps |
| CPU time | 7.02 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:18 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-dd58be94-6bdb-463c-b8f9-ff952bb951a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3287446544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3287446544 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3520969580 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1954000814 ps |
| CPU time | 6.66 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-fa73969e-cd49-4e31-9357-c3f12e750f1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3520969580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3520969580 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.159792322 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 75978296097 ps |
| CPU time | 286.4 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:29:01 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-06d32404-506c-4074-a577-af1ba5819494 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=159792322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.159792322 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4216337201 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 78701321 ps |
| CPU time | 5.04 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-3a9dfc1e-836c-46fc-aeee-6132bb2dfed0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4216337201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4216337201 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.403838848 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 77585900 ps |
| CPU time | 5.94 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:18 PM PST 24 |
| Peak memory | 201640 kb |
| Host | smart-cf8bce19-dce4-4298-a48b-4a997b99b541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403838848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.403838848 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.4010034859 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 992855288 ps |
| CPU time | 12.4 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:24 PM PST 24 |
| Peak memory | 201676 kb |
| Host | smart-33af95ce-c35e-481e-8ccf-1dc0cc3ccf41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4010034859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4010034859 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2361929566 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 35135025742 ps |
| CPU time | 106.38 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:25:57 PM PST 24 |
| Peak memory | 201992 kb |
| Host | smart-f18531f1-a478-4ac8-abee-38f00f2c0d3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361929566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2361929566 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2616535580 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 18319155060 ps |
| CPU time | 115.4 seconds |
| Started | Jan 17 12:24:06 PM PST 24 |
| Finished | Jan 17 12:26:02 PM PST 24 |
| Peak memory | 201988 kb |
| Host | smart-4416e959-ad3a-4d55-8854-fe3b31f167d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2616535580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2616535580 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.146105026 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 58872329 ps |
| CPU time | 3.38 seconds |
| Started | Jan 17 12:24:10 PM PST 24 |
| Finished | Jan 17 12:24:14 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-8cac4cb0-a6b9-47e6-b374-9d02f17fb74a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146105026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.146105026 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.935287058 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1070915570 ps |
| CPU time | 10.69 seconds |
| Started | Jan 17 12:24:08 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-2895a935-e669-4361-ab53-87ff9e7e8c6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935287058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.935287058 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.167029897 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 83528493 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-4a3f8643-5ec7-49e4-a935-cfb7c39a2d20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=167029897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.167029897 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.147805931 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1979782409 ps |
| CPU time | 9.98 seconds |
| Started | Jan 17 12:24:49 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 200744 kb |
| Host | smart-a4315d96-e3f9-4218-9f6f-92716d32356e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=147805931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.147805931 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4284517968 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1268284317 ps |
| CPU time | 8.19 seconds |
| Started | Jan 17 12:24:06 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-9bd98b81-2edb-40bb-aab0-66e3d80c82fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4284517968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4284517968 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1952921210 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 9652446 ps |
| CPU time | 1.26 seconds |
| Started | Jan 17 12:24:11 PM PST 24 |
| Finished | Jan 17 12:24:13 PM PST 24 |
| Peak memory | 201652 kb |
| Host | smart-c29c94eb-c36a-4277-ae85-cb5d94c56295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952921210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1952921210 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.4193182284 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3899595425 ps |
| CPU time | 73.88 seconds |
| Started | Jan 17 12:24:44 PM PST 24 |
| Finished | Jan 17 12:26:01 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-643f2285-8bc9-4c91-89de-c448ee39b411 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4193182284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4193182284 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.128422065 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1169909559 ps |
| CPU time | 28.42 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-67c5f851-2b85-4851-acea-d65a8e4e809a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128422065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.128422065 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3408431879 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3731047865 ps |
| CPU time | 148.73 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:26:48 PM PST 24 |
| Peak memory | 207228 kb |
| Host | smart-c38eb33b-52a5-4298-ba1d-5b145819ecc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3408431879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.3408431879 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4050461054 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1892285962 ps |
| CPU time | 45.42 seconds |
| Started | Jan 17 12:25:25 PM PST 24 |
| Finished | Jan 17 12:26:11 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-b5b3809d-271d-4636-89b5-00ef7f96528b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4050461054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.4050461054 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1741171273 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 543600655 ps |
| CPU time | 9.13 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:28 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-0129d0bb-4964-4640-94da-6429c49d2638 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1741171273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1741171273 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.391088378 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 42597144 ps |
| CPU time | 8.91 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:28 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-dc8cabda-df3c-40e3-ad5c-a9da69a0cc7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391088378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.391088378 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3159725944 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 123642812309 ps |
| CPU time | 169.98 seconds |
| Started | Jan 17 12:24:51 PM PST 24 |
| Finished | Jan 17 12:27:43 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-823f878c-0c2e-4d9b-bfcd-236e0886fe89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3159725944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3159725944 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3857187366 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 585107535 ps |
| CPU time | 8.37 seconds |
| Started | Jan 17 12:24:02 PM PST 24 |
| Finished | Jan 17 12:24:12 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-612b4497-6a9b-41db-8a61-24fd9d9c0d2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3857187366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3857187366 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.3102418548 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 255346494 ps |
| CPU time | 6.2 seconds |
| Started | Jan 17 12:24:00 PM PST 24 |
| Finished | Jan 17 12:24:10 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-09e5a4af-12e2-4ea6-9b56-131ddb30067d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3102418548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3102418548 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.3133391096 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 579840774 ps |
| CPU time | 4.07 seconds |
| Started | Jan 17 12:24:49 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-f65d622f-8b8e-418c-a179-6c0ab1931c4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133391096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3133391096 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1919600252 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 21963017402 ps |
| CPU time | 79.32 seconds |
| Started | Jan 17 12:26:52 PM PST 24 |
| Finished | Jan 17 12:28:12 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-5fb636a5-73c3-4b01-97fb-22c68597a258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919600252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1919600252 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.186260885 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4126131713 ps |
| CPU time | 15.08 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-f61b88b1-aee0-4459-aae2-37a6e0cd9298 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=186260885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.186260885 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.673508654 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 59916561 ps |
| CPU time | 5.89 seconds |
| Started | Jan 17 12:26:53 PM PST 24 |
| Finished | Jan 17 12:26:59 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ba13baf7-c5ad-4196-a948-72a5fd89861e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673508654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.673508654 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.1751171655 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 92936958 ps |
| CPU time | 3.16 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-9ed10f6d-9779-49fb-8885-0129307fa3ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1751171655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1751171655 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3882471442 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8891325 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-fa5fc16b-801f-4d44-bd5b-08f7cd033d59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3882471442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3882471442 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.192710142 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6787094219 ps |
| CPU time | 11.89 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:31 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-b25f874f-fa29-44df-952a-1af560a0ec83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=192710142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.192710142 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1594081131 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 460443127 ps |
| CPU time | 4.27 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-584d021d-ca0c-4c19-8214-03cdfedb3a42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1594081131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1594081131 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2313746666 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 9270966 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:24:29 PM PST 24 |
| Finished | Jan 17 12:24:31 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-57433259-3ee1-4276-8596-0b6314ca6c6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313746666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2313746666 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1372010259 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5815423244 ps |
| CPU time | 34.55 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:54 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-90586bb6-1a1a-4e37-846d-da1a8609bcbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1372010259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1372010259 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3967665058 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 12174414088 ps |
| CPU time | 118.31 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:26:08 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-2f733cb4-640a-4ac4-8fd7-3ce323a4370d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967665058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3967665058 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.277335452 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1637851578 ps |
| CPU time | 178.38 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:27:18 PM PST 24 |
| Peak memory | 225760 kb |
| Host | smart-89d0d18d-7032-4d4a-bb78-230088c01c22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=277335452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.277335452 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2385535413 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 264609144 ps |
| CPU time | 6.79 seconds |
| Started | Jan 17 12:24:33 PM PST 24 |
| Finished | Jan 17 12:24:41 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-75974dd4-dc26-43ed-bb5c-fe285c11541b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385535413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2385535413 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3632182160 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1452726236 ps |
| CPU time | 17.52 seconds |
| Started | Jan 17 12:20:27 PM PST 24 |
| Finished | Jan 17 12:20:48 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-ee000025-f51b-4b97-89ab-a55c41d5686b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3632182160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3632182160 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1101837874 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 16356478424 ps |
| CPU time | 65.56 seconds |
| Started | Jan 17 12:26:42 PM PST 24 |
| Finished | Jan 17 12:27:49 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-e3d7e458-578e-4ef6-9eb0-5f7303aeb76d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1101837874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1101837874 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2173553635 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 281536578 ps |
| CPU time | 4.75 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:42 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-b4fafdde-e432-48b6-95c0-cd1570075014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2173553635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2173553635 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.4053338572 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 51757708 ps |
| CPU time | 3.57 seconds |
| Started | Jan 17 12:27:11 PM PST 24 |
| Finished | Jan 17 12:27:26 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-3cfcbfc1-17e4-44f8-9785-74cda0a04d98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4053338572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4053338572 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3750478327 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 176366046 ps |
| CPU time | 1.7 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-0ce86d17-193c-400b-8969-c069dea2f63f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750478327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3750478327 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2053301479 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 35224567344 ps |
| CPU time | 63.43 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:25:33 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-ed415c4e-b64d-4045-8397-d460d8848305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053301479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2053301479 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1493668123 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 7834980267 ps |
| CPU time | 25.51 seconds |
| Started | Jan 17 12:23:53 PM PST 24 |
| Finished | Jan 17 12:24:19 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-7c74c29e-8460-423d-9152-88f6716e6bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1493668123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1493668123 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3584470578 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 104400661 ps |
| CPU time | 2.51 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:32 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-aec97787-9f72-4df0-a919-84aae5c877ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584470578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3584470578 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3910853097 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1424057179 ps |
| CPU time | 3.48 seconds |
| Started | Jan 17 12:20:11 PM PST 24 |
| Finished | Jan 17 12:20:15 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-fef8d32c-8fdb-40a2-b1db-3f77fbc807cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3910853097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3910853097 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2369661990 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 8667444 ps |
| CPU time | 1.2 seconds |
| Started | Jan 17 12:19:40 PM PST 24 |
| Finished | Jan 17 12:19:41 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-3f4dadd5-c7a0-49da-b182-f82a9beea071 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369661990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2369661990 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.750406528 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3932298539 ps |
| CPU time | 7.38 seconds |
| Started | Jan 17 12:23:38 PM PST 24 |
| Finished | Jan 17 12:23:47 PM PST 24 |
| Peak memory | 200332 kb |
| Host | smart-5330be0f-f0ff-42db-af58-dcd21ad793fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=750406528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.750406528 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.298259442 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 3049025902 ps |
| CPU time | 6.62 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:23:02 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-00cb58a5-94ff-4c5e-9773-e1cb5f3aa348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=298259442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.298259442 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2752809303 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 16192124 ps |
| CPU time | 1.24 seconds |
| Started | Jan 17 12:23:39 PM PST 24 |
| Finished | Jan 17 12:23:43 PM PST 24 |
| Peak memory | 201164 kb |
| Host | smart-844c2146-259b-4283-b215-b1ccf1a5cc24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752809303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2752809303 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.385947183 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 20663504807 ps |
| CPU time | 101.74 seconds |
| Started | Jan 17 12:19:08 PM PST 24 |
| Finished | Jan 17 12:20:50 PM PST 24 |
| Peak memory | 202868 kb |
| Host | smart-416de988-c15a-4efa-9627-5b28ba751e67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=385947183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.385947183 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2567578871 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 238330469 ps |
| CPU time | 1.72 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 199816 kb |
| Host | smart-17f43949-775d-4caf-820f-808021941ea7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567578871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2567578871 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3288592256 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1091832875 ps |
| CPU time | 51.69 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-cab9b2b6-b09b-4635-8e86-f8435fb661b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288592256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3288592256 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3740462561 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 275512561 ps |
| CPU time | 30.96 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 200668 kb |
| Host | smart-d83a4bfd-d963-4a68-bc50-608218e79d0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740462561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.3740462561 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.588747445 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 220635923 ps |
| CPU time | 4.1 seconds |
| Started | Jan 17 12:20:30 PM PST 24 |
| Finished | Jan 17 12:20:35 PM PST 24 |
| Peak memory | 201944 kb |
| Host | smart-f0b70d0c-2eaa-4e80-aa3e-5c80df28de16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588747445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.588747445 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1301001817 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1779184947 ps |
| CPU time | 23.19 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 200720 kb |
| Host | smart-2c9b67f3-0e19-4b97-96f7-daab6267c82e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301001817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1301001817 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1717278049 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 44632710704 ps |
| CPU time | 111.79 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:26:23 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-560679eb-a99b-469a-89d6-474cd6bd6082 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1717278049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.1717278049 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4206171785 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 873782565 ps |
| CPU time | 9.95 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-eafbfc80-4369-4c15-8426-159bbdcea93d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4206171785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4206171785 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3841264466 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 41246958 ps |
| CPU time | 3.93 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-f347a6ab-caed-473c-bd1e-8d8281ec7072 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3841264466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3841264466 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.4000645721 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 711063893 ps |
| CPU time | 7.96 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-d01b7209-9bc2-4983-8521-b48ec387d3ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000645721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.4000645721 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3535764522 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 47985069986 ps |
| CPU time | 142.66 seconds |
| Started | Jan 17 12:24:50 PM PST 24 |
| Finished | Jan 17 12:27:15 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-8ee78e4a-c516-43b2-9c73-e91caebc02ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535764522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3535764522 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2406797234 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 34108042160 ps |
| CPU time | 62.07 seconds |
| Started | Jan 17 12:24:50 PM PST 24 |
| Finished | Jan 17 12:25:54 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-87d17216-2959-4d32-98f0-84e0bdc6c5e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2406797234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2406797234 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.765862878 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 119559707 ps |
| CPU time | 6.72 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:24:28 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-0bc64249-43ac-418e-be99-7b4085bcaa94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765862878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.765862878 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1401860171 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 702922812 ps |
| CPU time | 9.57 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:29 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-cbe8f20d-3942-421d-9aa8-8ce38580e795 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1401860171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1401860171 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.4256008470 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8725350 ps |
| CPU time | 1.24 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-17fe9d7a-f103-4ad1-b486-9585fb7b4db7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4256008470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4256008470 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3888645586 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 14342792598 ps |
| CPU time | 11.17 seconds |
| Started | Jan 17 12:24:16 PM PST 24 |
| Finished | Jan 17 12:24:31 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-566424fb-8152-4832-aec2-aa37c8af4729 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888645586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3888645586 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.690295634 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1150567677 ps |
| CPU time | 7.6 seconds |
| Started | Jan 17 12:24:13 PM PST 24 |
| Finished | Jan 17 12:24:21 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-e27d9bad-2d23-431a-97c0-5604ec31c33d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=690295634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.690295634 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.492807714 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 10982565 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:24:55 PM PST 24 |
| Peak memory | 201940 kb |
| Host | smart-9f9b680a-a5e3-4460-b83e-356c1d651c34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492807714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.492807714 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2174682397 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 12048502887 ps |
| CPU time | 59.31 seconds |
| Started | Jan 17 12:26:53 PM PST 24 |
| Finished | Jan 17 12:27:53 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-1798e195-1038-4c15-88e5-703f858d20c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174682397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2174682397 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2458030139 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1786397916 ps |
| CPU time | 24.49 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-b6879aa4-8550-4f2d-9475-1db0692e07ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2458030139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2458030139 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2145856060 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 12609932213 ps |
| CPU time | 203.58 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:28:17 PM PST 24 |
| Peak memory | 207392 kb |
| Host | smart-a61a9acb-eb1d-43f8-9914-1dbd86b79111 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2145856060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2145856060 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1141264590 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4713070175 ps |
| CPU time | 77.26 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:26:11 PM PST 24 |
| Peak memory | 205644 kb |
| Host | smart-b867d3d0-ec63-4661-a88b-c74d46f82e57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1141264590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1141264590 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2656294626 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 430371868 ps |
| CPU time | 6.5 seconds |
| Started | Jan 17 12:26:53 PM PST 24 |
| Finished | Jan 17 12:27:00 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ae16f51a-43c7-46a1-ab98-1af76208f5e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2656294626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2656294626 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.739752652 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 734800613 ps |
| CPU time | 15.26 seconds |
| Started | Jan 17 12:24:21 PM PST 24 |
| Finished | Jan 17 12:24:43 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-f0661900-b98c-4376-bf3d-ca1973869937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739752652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.739752652 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2889741825 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 5145276379 ps |
| CPU time | 13.89 seconds |
| Started | Jan 17 12:24:21 PM PST 24 |
| Finished | Jan 17 12:24:41 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-b53caa35-01c5-4b20-99b4-a86bd6696444 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2889741825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2889741825 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2164992268 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 349665659 ps |
| CPU time | 4.26 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-312901bd-cdd7-41c4-93e2-b505709f1c1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2164992268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2164992268 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.312891710 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1808976431 ps |
| CPU time | 7.36 seconds |
| Started | Jan 17 12:24:18 PM PST 24 |
| Finished | Jan 17 12:24:28 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-05e4151b-9f96-4b43-9dbb-bf641522c789 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312891710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.312891710 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.789451012 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 769282936 ps |
| CPU time | 14.74 seconds |
| Started | Jan 17 12:24:15 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-d439dbeb-1c60-407c-b584-345e4e5bc0aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=789451012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.789451012 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1292007242 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 3583890684 ps |
| CPU time | 26.26 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:42 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-be8ded32-8e8e-4374-9071-27bf60d2febf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1292007242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1292007242 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3025788788 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 76795824 ps |
| CPU time | 3.75 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-3b58f157-3718-474e-90f2-1f1208073dbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025788788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3025788788 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.2606530555 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 902628893 ps |
| CPU time | 11.57 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:24:33 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-06a121b4-4d7a-4afe-92a6-27bf245d8bec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2606530555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2606530555 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.1925472376 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 94800279 ps |
| CPU time | 1.7 seconds |
| Started | Jan 17 12:24:17 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-ae6ee8d7-35e8-4d9d-8c02-059abe405eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925472376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1925472376 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.631486978 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3213641912 ps |
| CPU time | 8.2 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:22 PM PST 24 |
| Peak memory | 201740 kb |
| Host | smart-8748e3c8-a0b8-400c-8559-fb9aa7c1c14c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=631486978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.631486978 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2480430121 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1349895187 ps |
| CPU time | 4.53 seconds |
| Started | Jan 17 12:24:14 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-395a08fb-8df4-4f1e-8250-836ae7f6e341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2480430121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2480430121 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3441035861 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 9962062 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-2a711420-a406-4f96-84c3-94a15e24c9b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441035861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3441035861 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3472634515 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2058404335 ps |
| CPU time | 43.13 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:25:13 PM PST 24 |
| Peak memory | 204144 kb |
| Host | smart-0bfb2868-ad73-4ae3-960d-1d70e73b3b4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472634515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3472634515 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.883976172 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5679442826 ps |
| CPU time | 71.77 seconds |
| Started | Jan 17 12:24:29 PM PST 24 |
| Finished | Jan 17 12:25:42 PM PST 24 |
| Peak memory | 203008 kb |
| Host | smart-29152854-b550-4647-bebe-06b5f820fb20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883976172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.883976172 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3606067603 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3363680594 ps |
| CPU time | 102.02 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:26:03 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-53d731fe-4755-41d1-94c3-f6fa7b65da3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3606067603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3606067603 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4919667 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 369239033 ps |
| CPU time | 40.42 seconds |
| Started | Jan 17 12:24:24 PM PST 24 |
| Finished | Jan 17 12:25:10 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-ef66c082-d550-46a8-8a56-e670400c2bfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4919667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset _error.4919667 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3155130316 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 635818243 ps |
| CPU time | 8.11 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:24:41 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-dc5c40b8-7ec2-4d04-8428-e4c49cbba26b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3155130316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3155130316 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2418651705 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 177718244 ps |
| CPU time | 4.22 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-357221e3-3062-48f8-a056-4dc8c1424c48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418651705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2418651705 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2194261184 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 25708057694 ps |
| CPU time | 181.15 seconds |
| Started | Jan 17 12:24:19 PM PST 24 |
| Finished | Jan 17 12:27:22 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-d6d8df4a-b9fb-4fbc-8873-e448fc2f5682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2194261184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2194261184 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.125013212 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 442702444 ps |
| CPU time | 6.25 seconds |
| Started | Jan 17 12:24:24 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-c619d473-61e4-4aaa-9050-250075dab200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=125013212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.125013212 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.600522614 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 62122252 ps |
| CPU time | 5.44 seconds |
| Started | Jan 17 12:24:21 PM PST 24 |
| Finished | Jan 17 12:24:27 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-988f03d0-3308-4b93-aa49-e75418f556e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=600522614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.600522614 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.3215400567 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 29021130 ps |
| CPU time | 2.72 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-0496c996-9b25-4193-964a-41b38fd5fce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215400567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3215400567 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.861787942 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 7739909218 ps |
| CPU time | 19.12 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:49 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-69383fde-bcfc-4666-86ec-91bddb440add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=861787942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.861787942 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.423976136 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 13264396460 ps |
| CPU time | 86.26 seconds |
| Started | Jan 17 12:24:33 PM PST 24 |
| Finished | Jan 17 12:26:00 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-bbea0ff7-70a4-44c6-83de-4d09e431ea16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=423976136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.423976136 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2280299643 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 263844638 ps |
| CPU time | 4.63 seconds |
| Started | Jan 17 12:24:35 PM PST 24 |
| Finished | Jan 17 12:24:41 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-3d575e89-5d06-417a-b7b0-56ca6bea38d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280299643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2280299643 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.3623203825 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1651987696 ps |
| CPU time | 3.11 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:24:36 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-bc3108f3-42df-44ed-98bb-be697737273f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3623203825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3623203825 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2813133867 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 12380918 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 12:24:32 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-697c2576-3312-4fd2-bba9-aba910e11bde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2813133867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2813133867 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4144418576 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 9051760176 ps |
| CPU time | 7.43 seconds |
| Started | Jan 17 12:24:29 PM PST 24 |
| Finished | Jan 17 12:24:37 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-a84266a2-f64b-4d9c-bc7b-dbf601c8223e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144418576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4144418576 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1139272153 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1298898283 ps |
| CPU time | 9.66 seconds |
| Started | Jan 17 12:24:33 PM PST 24 |
| Finished | Jan 17 12:24:43 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-3725c37a-aed9-4536-90d6-d25884da2f89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1139272153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1139272153 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2181073171 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9052528 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:24:21 PM PST 24 |
| Finished | Jan 17 12:24:23 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-511fd222-bcaa-4298-b2f0-730ce7707b54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181073171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2181073171 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1001998542 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 11435071185 ps |
| CPU time | 109.49 seconds |
| Started | Jan 17 12:24:38 PM PST 24 |
| Finished | Jan 17 12:26:28 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-371dab53-0fee-431a-a8ac-d44d7815d1e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1001998542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1001998542 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3846270634 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3573176837 ps |
| CPU time | 22.09 seconds |
| Started | Jan 17 12:24:27 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-ef8dcbf1-205f-4737-936c-9e282368d374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3846270634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3846270634 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3607315521 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 374553422 ps |
| CPU time | 47.52 seconds |
| Started | Jan 17 12:24:26 PM PST 24 |
| Finished | Jan 17 12:25:17 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-134a54c9-b1f9-47d8-821d-de5d8a0c3508 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607315521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3607315521 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.930607342 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 739596478 ps |
| CPU time | 7.42 seconds |
| Started | Jan 17 12:26:29 PM PST 24 |
| Finished | Jan 17 12:26:37 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-e02eef8c-624e-45e8-9743-31a8c2585361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930607342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.930607342 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3191486704 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3031127818 ps |
| CPU time | 14.47 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:45 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-2f68f1e1-8678-411e-8443-409ec45307d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191486704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3191486704 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.386150912 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 71161285520 ps |
| CPU time | 318.64 seconds |
| Started | Jan 17 12:24:36 PM PST 24 |
| Finished | Jan 17 12:29:55 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-f881d6a6-032f-45ed-91b7-0317cdaf0ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=386150912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo w_rsp.386150912 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.291075511 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 32594830 ps |
| CPU time | 3.97 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:51 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-e86f2228-c845-45ed-a899-31eae63ef3db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291075511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.291075511 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.4245148336 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1636747669 ps |
| CPU time | 5.89 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-35d7b7d2-8454-4fb9-bbc5-91502cf0cc66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4245148336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4245148336 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3062112853 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5428127885 ps |
| CPU time | 19.31 seconds |
| Started | Jan 17 12:24:36 PM PST 24 |
| Finished | Jan 17 12:24:55 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-7b51fd11-af2f-4078-a322-fa9bcc389118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062112853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3062112853 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1586891176 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1903039575 ps |
| CPU time | 10.57 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:25:05 PM PST 24 |
| Peak memory | 201256 kb |
| Host | smart-061748cc-b61c-4bfc-aeb7-281710141db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1586891176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1586891176 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1520740605 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 104583224 ps |
| CPU time | 6.03 seconds |
| Started | Jan 17 12:24:49 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-7487d6a6-bec4-45ae-9164-3b56805ff37d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520740605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1520740605 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.803744076 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 10287015 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-db178759-6b30-4d93-8a57-7679baae43a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=803744076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.803744076 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1202483139 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 17332039 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:24:44 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-1093daa9-7e95-466b-9d4e-340ac7b508bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202483139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1202483139 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4075950292 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4613885570 ps |
| CPU time | 10.53 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:57 PM PST 24 |
| Peak memory | 200608 kb |
| Host | smart-88d7fa34-4286-4e12-8f6e-8556735e2615 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075950292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4075950292 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2171661062 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1541153269 ps |
| CPU time | 7.59 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:24:54 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-cb4a9f5b-311b-422e-a2c1-d7bb61bedaa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2171661062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2171661062 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.99967844 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 11104967 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 12:24:31 PM PST 24 |
| Finished | Jan 17 12:24:33 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-e8d019c2-65f9-4e7f-80bb-ea63515ec607 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99967844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.99967844 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.273174160 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5606255368 ps |
| CPU time | 47.69 seconds |
| Started | Jan 17 12:24:39 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-04eccdba-1816-4d69-95fb-b620ecb9f36d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273174160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.273174160 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.409616924 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 762502265 ps |
| CPU time | 28.36 seconds |
| Started | Jan 17 12:24:36 PM PST 24 |
| Finished | Jan 17 12:25:05 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-b1d06a39-4df8-401d-a795-662fa85aa3a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409616924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.409616924 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1995184955 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3004386884 ps |
| CPU time | 59.45 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:25:46 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-6079bd69-8013-47ab-bc24-aba971e1a319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1995184955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1995184955 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2885551762 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 872600519 ps |
| CPU time | 9.39 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-c3a6c520-0941-4cea-b5e2-0a68af76baea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885551762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2885551762 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3202428200 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 11377340 ps |
| CPU time | 2.21 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-96353cfe-c96b-417b-8057-303fef85fb66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3202428200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3202428200 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1512190135 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 11824375367 ps |
| CPU time | 87.44 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:26:16 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-e0aadc61-c732-4486-bfdd-80f17b96db93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1512190135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1512190135 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.141396546 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 17736909 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 12:24:46 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-737c0633-0afc-4f45-920e-7b06701eaae3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=141396546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.141396546 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2918895726 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 265022558 ps |
| CPU time | 4.31 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:51 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-ed541538-f665-43ff-b211-37661c90e28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2918895726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2918895726 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3344887699 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 812368031 ps |
| CPU time | 13.71 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:51 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-b6f59ed0-7cf1-4630-a5cf-d49f5c95b2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3344887699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3344887699 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3549149888 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 228343235444 ps |
| CPU time | 122.16 seconds |
| Started | Jan 17 12:24:28 PM PST 24 |
| Finished | Jan 17 12:26:32 PM PST 24 |
| Peak memory | 201648 kb |
| Host | smart-6ec34a80-29b8-4c66-9172-fc5c8b777a02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549149888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3549149888 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1519971406 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 10715672803 ps |
| CPU time | 69.69 seconds |
| Started | Jan 17 12:24:40 PM PST 24 |
| Finished | Jan 17 12:25:54 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-d6bdf2e9-2eb9-48b3-ad43-a8d78e7b739c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1519971406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1519971406 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.673959951 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 11755897 ps |
| CPU time | 1.27 seconds |
| Started | Jan 17 12:24:28 PM PST 24 |
| Finished | Jan 17 12:24:31 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-3151136f-f566-4f83-9a26-e224df4b5f5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673959951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.673959951 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.4211392458 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1639519044 ps |
| CPU time | 10.03 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:24:59 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-e29b9cfb-3fa8-49e0-a579-4c3aca0c3e5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4211392458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4211392458 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1548050097 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 79553189 ps |
| CPU time | 1.5 seconds |
| Started | Jan 17 12:24:49 PM PST 24 |
| Finished | Jan 17 12:24:54 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-6785279c-f8a2-4b16-800e-2781c8d52710 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1548050097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1548050097 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.729595496 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2810732411 ps |
| CPU time | 8.34 seconds |
| Started | Jan 17 12:24:38 PM PST 24 |
| Finished | Jan 17 12:24:47 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-5ccd5193-4be1-427a-b381-43c801e831b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=729595496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.729595496 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1106391030 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1633701015 ps |
| CPU time | 10.8 seconds |
| Started | Jan 17 12:24:38 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-a150177f-16f3-4f5d-8c74-9b2f225d1e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1106391030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1106391030 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2044989706 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 11500392 ps |
| CPU time | 1.26 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-e0a37797-a6b7-4b51-b9b7-8bfcf15af090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044989706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2044989706 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.870608003 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 174446620 ps |
| CPU time | 8.03 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:45 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-a7aa6c6d-1962-4e9c-ac16-52af161f47cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=870608003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.870608003 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2073748759 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 290647016 ps |
| CPU time | 30.03 seconds |
| Started | Jan 17 12:24:38 PM PST 24 |
| Finished | Jan 17 12:25:08 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-b6a957d8-d9da-4596-a9eb-0c714279c815 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073748759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2073748759 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1108149337 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 401504151 ps |
| CPU time | 64.88 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:25:42 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-0da7ed9f-fbab-43cd-be96-4324c7408f65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108149337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1108149337 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1078164576 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 10689854941 ps |
| CPU time | 95.02 seconds |
| Started | Jan 17 12:24:46 PM PST 24 |
| Finished | Jan 17 12:26:24 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-af558aa6-dace-4824-8e6d-9faef96a3876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1078164576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1078164576 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1799495823 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 206372717 ps |
| CPU time | 3.66 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-40e9d299-4fca-487c-ac06-0b1fdd413cb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799495823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1799495823 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1168904202 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1450422853 ps |
| CPU time | 23.76 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:25:14 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-3f89386a-0a19-4107-8b41-2eb6b691f57e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168904202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1168904202 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.310543455 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 204111860 ps |
| CPU time | 3.97 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-90464110-4c36-475e-bd5e-51764b7ecbd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=310543455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.310543455 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1498595792 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 805875986 ps |
| CPU time | 12.11 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:25:00 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-bd94662b-5d32-4e19-aea2-c6d2856bab3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498595792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1498595792 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.1678832473 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 285074570 ps |
| CPU time | 4.73 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:24:54 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-695d87f3-ae14-4987-8451-4122612fb29f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1678832473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1678832473 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.595355043 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5810526218 ps |
| CPU time | 22.07 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:25:12 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-65a67b32-efa4-4c0d-8b7c-9410f76e795b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=595355043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.595355043 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.476012811 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3881183548 ps |
| CPU time | 27.41 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:25:14 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-9cbd3834-2a6d-42fe-9cd8-5008dfbddc6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=476012811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.476012811 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2762077628 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 47455095 ps |
| CPU time | 4.82 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-c6027748-1ea7-4981-981e-b406250f8570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762077628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2762077628 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.5111110 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 223150522 ps |
| CPU time | 1.44 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-0b610734-5167-4088-b680-c7ed6b249bee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5111110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.5111110 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1122043252 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 88209284 ps |
| CPU time | 1.25 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-803d5824-2541-48d6-8d0c-2cd98b5b984c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1122043252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1122043252 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.979687463 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2391759097 ps |
| CPU time | 11.21 seconds |
| Started | Jan 17 12:24:39 PM PST 24 |
| Finished | Jan 17 12:24:51 PM PST 24 |
| Peak memory | 201632 kb |
| Host | smart-0bf7d599-44d3-4bf1-984f-ec10ae501633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=979687463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.979687463 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2904124686 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3919290256 ps |
| CPU time | 8.46 seconds |
| Started | Jan 17 12:24:41 PM PST 24 |
| Finished | Jan 17 12:24:55 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-03719e3d-1a87-43c3-a9b7-a6c6e41acdb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2904124686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2904124686 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3028073421 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 9406995 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:39 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-5c1f3d3c-b171-4c37-a590-744c5a495832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028073421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3028073421 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.550571251 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 270571897 ps |
| CPU time | 16.74 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-8f921174-f4c4-4341-9caf-5fb514a18ce9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=550571251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.550571251 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2404956140 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 649397117 ps |
| CPU time | 7.18 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-befa0bc1-cfea-4d4d-816f-aea443e70b0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404956140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2404956140 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.943785424 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5244430842 ps |
| CPU time | 143.64 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:27:19 PM PST 24 |
| Peak memory | 204416 kb |
| Host | smart-03606f05-723e-4504-86a2-d1f661a8d498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=943785424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.943785424 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2234028949 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 5352406894 ps |
| CPU time | 174.84 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:27:32 PM PST 24 |
| Peak memory | 209688 kb |
| Host | smart-5dbaef4e-f24e-4afb-8aec-faa4cf29ee94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2234028949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2234028949 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3892572421 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 62241366 ps |
| CPU time | 1.32 seconds |
| Started | Jan 17 12:24:55 PM PST 24 |
| Finished | Jan 17 12:24:57 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-71c0ce1d-5a4d-4220-8076-0ffae6764664 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3892572421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3892572421 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1227399061 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 110217765 ps |
| CPU time | 5.35 seconds |
| Started | Jan 17 12:24:55 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a000aa1a-dc37-487c-8c5f-de34899a17c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1227399061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1227399061 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2434204498 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5452948390 ps |
| CPU time | 18.89 seconds |
| Started | Jan 17 12:24:55 PM PST 24 |
| Finished | Jan 17 12:25:15 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-8598ec3a-8754-4303-b5f8-b89adf4e67ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2434204498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2434204498 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1077611737 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 298856484 ps |
| CPU time | 3.25 seconds |
| Started | Jan 17 12:24:47 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 201684 kb |
| Host | smart-aa81a50f-22b4-41c5-8fce-32d1f5cc32f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077611737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1077611737 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.796897383 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 648862939 ps |
| CPU time | 7.3 seconds |
| Started | Jan 17 12:24:39 PM PST 24 |
| Finished | Jan 17 12:24:47 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-3948f941-0ada-4cb9-9f6d-fd404d18143a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796897383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.796897383 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.1046813718 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3376078203 ps |
| CPU time | 7.01 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:57 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-d0ad49b1-2de5-4276-8da7-6bb72c23fe81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046813718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1046813718 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1812510423 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 15004464542 ps |
| CPU time | 63.49 seconds |
| Started | Jan 17 12:24:45 PM PST 24 |
| Finished | Jan 17 12:25:52 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-67bed710-a985-4623-b310-e5de322cdf99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812510423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1812510423 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3490109022 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 48252013293 ps |
| CPU time | 74.51 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:26:01 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-422bd0b8-ec6a-4e97-99bc-5925584f5c6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3490109022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3490109022 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3443789867 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 82902232 ps |
| CPU time | 8.29 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-818b478c-4231-4af6-9ffb-e3d6cb5a9356 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443789867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3443789867 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3383191389 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1526230063 ps |
| CPU time | 5.96 seconds |
| Started | Jan 17 12:24:44 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-7b58e34b-f1b0-49ae-b93c-e3c0b87dafdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3383191389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3383191389 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1449980640 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 11240096 ps |
| CPU time | 1.2 seconds |
| Started | Jan 17 12:24:46 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-5756d621-4e0d-48b3-9017-ab4e7ee1761a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1449980640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1449980640 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3132218940 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4597578925 ps |
| CPU time | 9.21 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:25:00 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-a403cccd-8cf8-4391-ae55-e176a653d578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132218940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3132218940 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1381619595 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 971677647 ps |
| CPU time | 6.48 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:57 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-3f6b712f-7732-443d-8f61-a50032e0a61f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1381619595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1381619595 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.105935069 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 10362937 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:52 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-aff55be7-f7cf-49e4-a164-d2db6f40a8c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105935069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.105935069 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.4269607518 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 162327419 ps |
| CPU time | 18.8 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-c7a55013-99a0-4d88-ba5b-14c4bda87c29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4269607518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4269607518 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.359362492 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5262639274 ps |
| CPU time | 44.65 seconds |
| Started | Jan 17 12:24:46 PM PST 24 |
| Finished | Jan 17 12:25:33 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-47d6c625-6688-4a56-9ccd-df5cfb5e622d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=359362492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.359362492 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3898659650 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 303310923 ps |
| CPU time | 40.59 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:46 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-95219239-1fa3-45a9-a7c5-64a6d3925f9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3898659650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3898659650 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1214916818 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 6668046197 ps |
| CPU time | 113.36 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:26:45 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-0222ffaa-8f3b-401a-bf46-f8a18ebcd79b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1214916818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1214916818 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3662262575 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 729421308 ps |
| CPU time | 11.46 seconds |
| Started | Jan 17 12:24:49 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ba77d891-d666-465e-ae40-40e5db45923b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3662262575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3662262575 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1990384649 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 45812423 ps |
| CPU time | 9.2 seconds |
| Started | Jan 17 12:24:50 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 200712 kb |
| Host | smart-0602603a-7565-44d8-bb4a-50c2043f29e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990384649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1990384649 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2667894205 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 114033100876 ps |
| CPU time | 235.94 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:29:02 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-0ad3c5ff-44cb-48c9-a509-eaaf1d12dba7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2667894205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.2667894205 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2816407974 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 220018206 ps |
| CPU time | 4.49 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:09 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-a6d5f231-10ea-498c-b995-dcd0e31b697b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2816407974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2816407974 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.2890887368 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 309237906 ps |
| CPU time | 5.36 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-8ca9d502-857e-4d63-8672-5f673b890e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2890887368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2890887368 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2611165958 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 53261720 ps |
| CPU time | 4.73 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:24:59 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-69b45b2d-1fc8-4387-9a79-2e9fe49c5af0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2611165958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2611165958 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2829343757 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 21055750203 ps |
| CPU time | 98.1 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:26:33 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-0637b6f9-7079-498d-9246-d1ca2582b1d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829343757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2829343757 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2784822875 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 45061111795 ps |
| CPU time | 186.11 seconds |
| Started | Jan 17 12:24:44 PM PST 24 |
| Finished | Jan 17 12:27:53 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-8c657556-2fba-4b76-a767-41a2437081b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2784822875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2784822875 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2413175808 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 85953200 ps |
| CPU time | 4.84 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:55 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-4f72e8b1-b980-4d34-90b1-fe6a324adb16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413175808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2413175808 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.148396352 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1236094214 ps |
| CPU time | 10.51 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:16 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-0eb24a0d-61b0-4431-aa6f-9663964c2544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=148396352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.148396352 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1032250668 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 50708615 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:24:46 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-1d357290-3c8c-4f45-b364-af91822c4b1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032250668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1032250668 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.9908719 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 6821220287 ps |
| CPU time | 7.18 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-3f913941-2e37-4d20-bce8-1a3ebf004d07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=9908719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.9908719 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.597740507 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1459605281 ps |
| CPU time | 9.45 seconds |
| Started | Jan 17 12:24:42 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-df1bbb46-84ca-4279-85f3-3318fa0fb32f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=597740507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.597740507 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3196828724 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 10755780 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:24:50 PM PST 24 |
| Finished | Jan 17 12:24:53 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-57eedadc-2084-4876-ab34-43697475dad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196828724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3196828724 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3572009828 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4422551415 ps |
| CPU time | 82.61 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:26:28 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-69da63d9-2c8d-4b02-9aac-c7416af33ede |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3572009828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3572009828 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3376459439 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1175267160 ps |
| CPU time | 34.67 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:40 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-e49d1ad2-8444-41f4-a70c-23036db01359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376459439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3376459439 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.109765754 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 263900169 ps |
| CPU time | 48.04 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:25:39 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-04ab6481-2ae4-4a8a-884b-23b73a8f276f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=109765754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.109765754 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2111970632 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 490351084 ps |
| CPU time | 87.75 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:26:33 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-4840f2a8-558c-4203-8109-9ea6fdf441fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111970632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.2111970632 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.949335314 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 16796325 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:51 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-43d3d041-fdc8-4829-8b33-b800c1b54eae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=949335314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.949335314 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2306495433 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 38588549 ps |
| CPU time | 5.33 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-39895477-9a5c-4920-919b-24b6ffc98855 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2306495433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2306495433 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2955797293 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 17035006378 ps |
| CPU time | 116.55 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:26:44 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-2935b19e-a195-472f-b19f-9518d3568f6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2955797293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2955797293 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.178595974 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 558560154 ps |
| CPU time | 10.05 seconds |
| Started | Jan 17 12:26:29 PM PST 24 |
| Finished | Jan 17 12:26:40 PM PST 24 |
| Peak memory | 199172 kb |
| Host | smart-c5736449-2698-4b50-afb4-a55aa2324016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178595974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.178595974 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1907757894 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 51102048 ps |
| CPU time | 4.67 seconds |
| Started | Jan 17 12:26:29 PM PST 24 |
| Finished | Jan 17 12:26:34 PM PST 24 |
| Peak memory | 199180 kb |
| Host | smart-2396b4ff-4f0f-4c0c-94a3-8a7643e94420 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1907757894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1907757894 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3697416490 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 665536116 ps |
| CPU time | 6.69 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-a6c19a91-fdc3-4dd2-8962-f47c1aaf5a28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697416490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3697416490 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1604750718 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 27946395477 ps |
| CPU time | 122.28 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:26:53 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-fd6acb51-905a-4cfe-8b17-1c7cf33deeaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604750718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1604750718 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.361780710 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 43919199535 ps |
| CPU time | 159.79 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:27:34 PM PST 24 |
| Peak memory | 200808 kb |
| Host | smart-77e9fa70-e892-4da0-b185-911590d2c498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=361780710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.361780710 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.4179849275 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 55962762 ps |
| CPU time | 6.79 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:24:57 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-f8722d67-db38-4167-b71c-aecc6f4262bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179849275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.4179849275 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.838712065 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 33687748 ps |
| CPU time | 2.91 seconds |
| Started | Jan 17 12:24:44 PM PST 24 |
| Finished | Jan 17 12:24:50 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-4220b05b-1a15-46b1-a870-2874596dd58a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=838712065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.838712065 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2575497321 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 99179060 ps |
| CPU time | 1.37 seconds |
| Started | Jan 17 12:24:43 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-eb90654c-2ffd-42f5-9233-4ad7cafd0453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2575497321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2575497321 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1158376531 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2388767872 ps |
| CPU time | 8.69 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:14 PM PST 24 |
| Peak memory | 201096 kb |
| Host | smart-00249c53-7c19-497e-9960-98915aa6a88e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158376531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1158376531 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2463757073 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1175204996 ps |
| CPU time | 9.28 seconds |
| Started | Jan 17 12:24:48 PM PST 24 |
| Finished | Jan 17 12:25:00 PM PST 24 |
| Peak memory | 200312 kb |
| Host | smart-57292705-5a30-484d-be83-e827e665f3f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2463757073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2463757073 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.522348523 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 9270621 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-7a62e09a-25c5-4f4d-8898-29aaefe84c86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522348523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.522348523 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3746038653 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4563233053 ps |
| CPU time | 56.77 seconds |
| Started | Jan 17 12:26:53 PM PST 24 |
| Finished | Jan 17 12:27:50 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-7e4ed4e1-bc3e-47e5-8f55-1fcd0a1b6d95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3746038653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3746038653 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3873904826 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 185197956 ps |
| CPU time | 4.55 seconds |
| Started | Jan 17 12:24:57 PM PST 24 |
| Finished | Jan 17 12:25:02 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-0956c477-aa57-4cbd-96be-8c731949e56c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3873904826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3873904826 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2694729687 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1883254101 ps |
| CPU time | 244.38 seconds |
| Started | Jan 17 12:24:56 PM PST 24 |
| Finished | Jan 17 12:29:01 PM PST 24 |
| Peak memory | 209388 kb |
| Host | smart-a777bee2-2f5f-4660-97cf-aa073c2cf1ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694729687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2694729687 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1779753198 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 137312902 ps |
| CPU time | 14.41 seconds |
| Started | Jan 17 12:25:15 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-c3de336e-77c2-4ab3-a902-20c5858382f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1779753198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1779753198 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1393010724 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 489569037 ps |
| CPU time | 5.41 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:25:00 PM PST 24 |
| Peak memory | 201928 kb |
| Host | smart-71823bc2-3a23-4e32-bb2f-beb4e0687bfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393010724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1393010724 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.4104143842 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 537668392 ps |
| CPU time | 7.43 seconds |
| Started | Jan 17 12:26:29 PM PST 24 |
| Finished | Jan 17 12:26:37 PM PST 24 |
| Peak memory | 199204 kb |
| Host | smart-a061e9ea-d284-43f0-af27-62077deab01b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104143842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.4104143842 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3667767790 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 622450227 ps |
| CPU time | 8.99 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-15c7323d-69ec-4f6b-aaec-f32f12fe7a02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667767790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3667767790 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.1372086910 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 11867800 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-a1e2fab7-1fc0-4b96-8301-b5c2d72d7d8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1372086910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1372086910 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3020236485 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 111386496 ps |
| CPU time | 4.82 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-9cfa2075-56a9-4ee1-9728-c2982cc4e518 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020236485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3020236485 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3173792486 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 26478960864 ps |
| CPU time | 102.19 seconds |
| Started | Jan 17 12:24:56 PM PST 24 |
| Finished | Jan 17 12:26:39 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-2603fe03-d6c8-45e1-a7c8-6d4552c05e04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173792486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3173792486 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4215740022 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 33339196138 ps |
| CPU time | 93.59 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:26:28 PM PST 24 |
| Peak memory | 201628 kb |
| Host | smart-786df9db-3776-4f47-8fe2-a72b96c688c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4215740022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4215740022 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2443669163 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 28687002 ps |
| CPU time | 2.92 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-158814a9-5787-4496-81f6-2a7c0d61f45f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443669163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2443669163 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1541752110 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 817004555 ps |
| CPU time | 9.58 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:25:03 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-8a4fd364-1f14-46e6-91eb-565770cb607f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1541752110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1541752110 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.4213371832 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 8296006 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:24:56 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-d5ee47d9-698c-4e5f-811f-ab0379712492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213371832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4213371832 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3379518521 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 3503031525 ps |
| CPU time | 7.59 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:16 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-ece3415e-0971-4453-be97-f96fa7cac340 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379518521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3379518521 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1318537372 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 952888445 ps |
| CPU time | 7.56 seconds |
| Started | Jan 17 12:24:58 PM PST 24 |
| Finished | Jan 17 12:25:06 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-09238e63-079a-411c-8a4f-4d9517026edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1318537372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1318537372 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2219949672 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 13062234 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-933127f8-afa6-4ecd-bcc2-3842c4b08d83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219949672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2219949672 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.277419783 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 8271005230 ps |
| CPU time | 61.53 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:26:03 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-428d68ac-161a-4809-a6dc-a5317ec9959d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=277419783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.277419783 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2205592259 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 7741815901 ps |
| CPU time | 15.93 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-fc4a2c58-2b5e-4d94-a6ca-fd53da3eced7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205592259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2205592259 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1101232200 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8798229957 ps |
| CPU time | 95.07 seconds |
| Started | Jan 17 12:24:54 PM PST 24 |
| Finished | Jan 17 12:26:31 PM PST 24 |
| Peak memory | 203976 kb |
| Host | smart-ba059aae-9eb1-4585-bf0b-a40e8096f1eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1101232200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1101232200 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1198142262 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 47495891 ps |
| CPU time | 5.37 seconds |
| Started | Jan 17 12:26:53 PM PST 24 |
| Finished | Jan 17 12:26:59 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-c8e272aa-01e9-4d8f-b315-94d831aa966c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198142262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1198142262 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3380895219 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 71060885 ps |
| CPU time | 8.18 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:10 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-a9e95ee8-3a73-4501-8748-70882612ae96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380895219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3380895219 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.719392588 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1943377166 ps |
| CPU time | 14.36 seconds |
| Started | Jan 17 12:23:58 PM PST 24 |
| Finished | Jan 17 12:24:15 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-3bea4a21-924f-4f03-aed0-107d483d8578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=719392588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.719392588 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.526830794 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 636202798 ps |
| CPU time | 7.65 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:50 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-9d9a600e-5ffa-4aa3-8f23-03b11b88b9fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=526830794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.526830794 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.4262872691 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 177877861 ps |
| CPU time | 6.17 seconds |
| Started | Jan 17 12:20:06 PM PST 24 |
| Finished | Jan 17 12:20:13 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-8e05d8af-d633-4543-90cf-ff8ed8c1a5aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4262872691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4262872691 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3269911862 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 47805444 ps |
| CPU time | 5.79 seconds |
| Started | Jan 17 12:20:36 PM PST 24 |
| Finished | Jan 17 12:20:42 PM PST 24 |
| Peak memory | 201672 kb |
| Host | smart-09c6751d-6fc3-4485-8cdb-64a808e854dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269911862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3269911862 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2179703028 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 20323447644 ps |
| CPU time | 63.61 seconds |
| Started | Jan 17 12:23:43 PM PST 24 |
| Finished | Jan 17 12:24:47 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-83137d11-7a15-46ec-aa8e-40523dfc3014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179703028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2179703028 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4145763836 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2407479939 ps |
| CPU time | 9.47 seconds |
| Started | Jan 17 12:19:44 PM PST 24 |
| Finished | Jan 17 12:19:56 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-4ea5d539-dad3-47a2-b3cb-bba87f8dca71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4145763836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4145763836 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.450418025 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 92634171 ps |
| CPU time | 5.02 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:43 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-395b305c-4a31-47fd-9f96-9a852723be87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450418025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.450418025 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.679082386 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 661231548 ps |
| CPU time | 2.35 seconds |
| Started | Jan 17 12:20:06 PM PST 24 |
| Finished | Jan 17 12:20:09 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-64e9e0ae-1c01-4980-b35e-955f0f84a7aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=679082386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.679082386 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2434318431 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 240358765 ps |
| CPU time | 1.66 seconds |
| Started | Jan 17 12:20:04 PM PST 24 |
| Finished | Jan 17 12:20:07 PM PST 24 |
| Peak memory | 199220 kb |
| Host | smart-77a7714c-16ef-49fe-a7f0-bced5a40ad3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2434318431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2434318431 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1903360920 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10296682773 ps |
| CPU time | 10.22 seconds |
| Started | Jan 17 12:19:07 PM PST 24 |
| Finished | Jan 17 12:19:18 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-1ba2d572-36f8-42ad-81e2-a58784f0c0b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903360920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1903360920 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.446001786 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3173693211 ps |
| CPU time | 6.99 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:24:14 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-61a95446-daf8-41bc-b9b1-b9e97ccca516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=446001786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.446001786 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1114034721 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 11113863 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 12:20:01 PM PST 24 |
| Finished | Jan 17 12:20:04 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-31672411-4d55-48ee-bab6-8cae025d9cc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114034721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1114034721 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.383411112 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 23013422581 ps |
| CPU time | 121.86 seconds |
| Started | Jan 17 12:23:53 PM PST 24 |
| Finished | Jan 17 12:25:56 PM PST 24 |
| Peak memory | 203280 kb |
| Host | smart-f73e2f76-6605-4a35-b500-9928632903a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=383411112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.383411112 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1223722015 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 342517553 ps |
| CPU time | 38.64 seconds |
| Started | Jan 17 12:18:21 PM PST 24 |
| Finished | Jan 17 12:19:00 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-5e59609c-a7c3-4d8d-a188-abf29bae2a1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223722015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1223722015 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.674317096 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1924075105 ps |
| CPU time | 133.1 seconds |
| Started | Jan 17 12:24:24 PM PST 24 |
| Finished | Jan 17 12:26:43 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-8c63cd32-432f-4329-ba8d-58734587e5d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674317096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.674317096 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3808487195 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1262785517 ps |
| CPU time | 11.17 seconds |
| Started | Jan 17 12:20:41 PM PST 24 |
| Finished | Jan 17 12:20:54 PM PST 24 |
| Peak memory | 201688 kb |
| Host | smart-8546b46d-4d0c-4a78-a237-dcbe1687c500 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3808487195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3808487195 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1075693154 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 929758292 ps |
| CPU time | 23.69 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-4adc2dd5-04f7-48ae-adf3-7b2122b2a2f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075693154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1075693154 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3386037546 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 101598714573 ps |
| CPU time | 181.76 seconds |
| Started | Jan 17 12:24:56 PM PST 24 |
| Finished | Jan 17 12:27:59 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-920dc653-c48a-4c15-86c0-ff3005716ede |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3386037546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3386037546 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1419978344 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 139802091 ps |
| CPU time | 1.56 seconds |
| Started | Jan 17 12:24:55 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-870ee812-2f95-4f0d-8f38-6b70080e7187 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1419978344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1419978344 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.1922015206 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 130560913 ps |
| CPU time | 2.79 seconds |
| Started | Jan 17 12:25:00 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-0184e8b5-49c4-45aa-8042-935005033b96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1922015206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1922015206 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.702119955 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 223031640 ps |
| CPU time | 3.33 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:24:58 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-33619330-0dee-4994-b95b-ab1920580c39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702119955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.702119955 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.4059799760 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 37355589788 ps |
| CPU time | 96.62 seconds |
| Started | Jan 17 12:24:58 PM PST 24 |
| Finished | Jan 17 12:26:36 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-269748de-b5c0-469d-a3cd-d01463a5fc4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059799760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4059799760 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2247011393 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 932900018 ps |
| CPU time | 7.29 seconds |
| Started | Jan 17 12:24:58 PM PST 24 |
| Finished | Jan 17 12:25:06 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-f5fd8eaf-c490-42e0-8053-b6d62f687bc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2247011393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2247011393 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1032686375 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 87916449 ps |
| CPU time | 6.68 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:25 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-be5363b5-d1cf-43ca-b2e4-bf19ee0937e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032686375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1032686375 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.1974153210 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1180236043 ps |
| CPU time | 3.8 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-7350455a-88dd-48c3-af4b-e36823b38e7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1974153210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1974153210 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.4270466155 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 11343861 ps |
| CPU time | 1.3 seconds |
| Started | Jan 17 12:24:57 PM PST 24 |
| Finished | Jan 17 12:24:59 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-b0bce4d5-3eac-48d7-9a53-10a08ae170ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4270466155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.4270466155 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1959218365 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8300369420 ps |
| CPU time | 13.77 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:17 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-72f23c9e-1b5d-4676-9f74-55f93465d318 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959218365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1959218365 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3584243134 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6916773681 ps |
| CPU time | 9.62 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-01a56019-6575-49db-9d70-f215e68445bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3584243134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3584243134 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2832094436 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 11197523 ps |
| CPU time | 1.35 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-a8085a10-3b0a-42a8-a7ba-c4fd68f5397d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832094436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2832094436 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2800381135 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 11679720383 ps |
| CPU time | 79.78 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:26:28 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-7daaaa85-9b4c-4985-884c-8cee5e539468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2800381135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2800381135 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1045900435 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5088456620 ps |
| CPU time | 48.1 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:26:06 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-6044f164-aa43-40c1-b38c-53e5ddba9cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1045900435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1045900435 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1398356239 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 89224782 ps |
| CPU time | 5.98 seconds |
| Started | Jan 17 12:24:58 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-87dc706f-7be9-450a-b901-97a399d86b41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1398356239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1398356239 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1460701988 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 55501168 ps |
| CPU time | 5.38 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:05 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-8e10dcd7-880b-407c-8e96-277a4bcc7162 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460701988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1460701988 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2713331742 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1991592531 ps |
| CPU time | 17.07 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-2ef9ab8a-73e5-454d-89ee-f3f9a71092fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2713331742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2713331742 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.501837537 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 40303891291 ps |
| CPU time | 220.02 seconds |
| Started | Jan 17 12:25:03 PM PST 24 |
| Finished | Jan 17 12:28:46 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-96a630a5-a8be-45a8-aebf-bed5dba4446b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=501837537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo w_rsp.501837537 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3210626501 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 521560694 ps |
| CPU time | 8.88 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:25:18 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-b0801e29-c1a3-4ae3-abb2-6c86f9b8549e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3210626501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3210626501 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.784344151 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 875709701 ps |
| CPU time | 9.33 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:15 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-ae83c44f-3522-4638-988d-4856aaf8ba99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784344151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.784344151 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.554082917 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 8441589 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:25:10 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-54ce54ca-828d-43e9-a0ef-d88d8d377a78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=554082917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.554082917 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.747854983 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 10445654650 ps |
| CPU time | 49.02 seconds |
| Started | Jan 17 12:25:01 PM PST 24 |
| Finished | Jan 17 12:25:52 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-e8b65191-7116-420f-8204-81227658bfd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=747854983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.747854983 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1908998246 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 21927490455 ps |
| CPU time | 36.09 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:35 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-63f063bb-8c65-4490-883b-72dd952625bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1908998246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1908998246 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.115453753 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 42389372 ps |
| CPU time | 4.01 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:25:12 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-195b4f65-efa5-413d-89b5-36d6bbd26229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115453753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.115453753 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.3658087968 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 148685092 ps |
| CPU time | 5.18 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-3bb31508-128b-44a6-b5bc-a177c99ce3b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3658087968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3658087968 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.1694179986 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 36034545 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 12:24:52 PM PST 24 |
| Finished | Jan 17 12:24:55 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-7f61799a-9d64-4593-a566-4d6bfb1cb07c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1694179986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1694179986 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.722825114 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6997253825 ps |
| CPU time | 10.27 seconds |
| Started | Jan 17 12:25:03 PM PST 24 |
| Finished | Jan 17 12:25:16 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-0f936a03-35b8-4a4e-95fb-0c475534b822 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=722825114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.722825114 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1076881785 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1405238950 ps |
| CPU time | 7.53 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:25:17 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-b4d242fd-d667-40e0-bbce-481ab186f00c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1076881785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1076881785 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.220625407 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10070604 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-ff36a7cf-b299-426e-b080-c426dd452ce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220625407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.220625407 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.4246225329 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 7245266168 ps |
| CPU time | 54.71 seconds |
| Started | Jan 17 12:25:03 PM PST 24 |
| Finished | Jan 17 12:26:01 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-13b03b1c-d4eb-4ac3-8bff-1dd0ebda1dab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4246225329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4246225329 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2103204173 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1738833078 ps |
| CPU time | 31.68 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:40 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-3fb03325-c2be-43a7-b36e-c12828c43125 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103204173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2103204173 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.260328530 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 6749798243 ps |
| CPU time | 101.76 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:27:00 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-03d3aa59-67d0-4440-8acc-ad3696c4cafb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=260328530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.260328530 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4278859588 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2472121670 ps |
| CPU time | 77.49 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:26:22 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-55d371a9-32a3-47e4-81db-ae92af21ffdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4278859588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.4278859588 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3107797897 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 361023276 ps |
| CPU time | 7.86 seconds |
| Started | Jan 17 12:25:03 PM PST 24 |
| Finished | Jan 17 12:25:13 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-db6a1cd5-564e-455e-a0d5-bdb314e44950 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107797897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3107797897 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.599163257 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 891021018 ps |
| CPU time | 15.13 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-78bb6aea-5410-42c4-9e22-7cf60f48bf2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599163257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.599163257 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1188058505 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 19208189725 ps |
| CPU time | 135.93 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:27:24 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-743395ac-7bdc-4bec-8d0d-2c3c9bd4c4fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1188058505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.1188058505 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3108460995 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2067431040 ps |
| CPU time | 10.4 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-0b03d32f-4781-47f7-8f86-74e1aa59e860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3108460995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3108460995 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.1165472116 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1992100098 ps |
| CPU time | 11.41 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 200856 kb |
| Host | smart-fa1af62d-a783-4103-9ef7-852d473bc9ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1165472116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1165472116 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.2336354792 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 45998327 ps |
| CPU time | 6.81 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-2b48a9bb-8314-4b08-9328-2d3389b8833a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336354792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2336354792 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1718123117 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 25902014094 ps |
| CPU time | 56.88 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:26:05 PM PST 24 |
| Peak memory | 200316 kb |
| Host | smart-dc062cd3-ba38-4975-b6a0-50bba099ede0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718123117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1718123117 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1855203041 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 14821850901 ps |
| CPU time | 90.92 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:26:38 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-16549b87-18e1-4f88-8ece-09ddb19825df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1855203041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1855203041 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2471093905 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 16695663 ps |
| CPU time | 1.45 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:25:09 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-5ebf298d-3236-4b12-aad7-b214a4b4cbf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471093905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2471093905 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3298783791 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 775875934 ps |
| CPU time | 9.46 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-6664ca7a-d9a7-467e-8138-694d6f481dab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3298783791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3298783791 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.1854893034 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 98182801 ps |
| CPU time | 1.39 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:10 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5c3ec401-0e58-439f-aeb2-af7d59dee451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854893034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1854893034 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1528281482 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3939133483 ps |
| CPU time | 8.03 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-75cd0b2d-7b91-4402-bbe4-8e4feb052c2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528281482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1528281482 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3352864958 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3259809358 ps |
| CPU time | 12.79 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-f940819c-3f95-451a-a6db-2c4ab75f5d29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3352864958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3352864958 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1172814424 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 9836808 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-9ee52655-3eda-4af4-97e8-55923372c07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172814424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1172814424 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2975855160 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 91120488 ps |
| CPU time | 4.03 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:21 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-de6effe7-de70-408c-82b6-c79732e4b857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2975855160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2975855160 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.670524924 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 15374667788 ps |
| CPU time | 46.33 seconds |
| Started | Jan 17 12:25:03 PM PST 24 |
| Finished | Jan 17 12:25:52 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-4d488fcc-9866-478b-aa85-b59dd9904805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670524924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.670524924 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1023240555 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3268605415 ps |
| CPU time | 99.08 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:26:48 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-5d79e813-4649-45a2-9dff-3d6b38d6b3b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1023240555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1023240555 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.85958438 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2095137447 ps |
| CPU time | 116 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:27:05 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-9e6bce51-9964-4839-81b0-c4cc9eb9d605 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85958438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rese t_error.85958438 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.130426097 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 227757275 ps |
| CPU time | 2.24 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:06 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-dbe918c4-f0b5-4a30-a712-994dac62de52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=130426097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.130426097 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1334299353 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 366079162 ps |
| CPU time | 8.29 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-f364126c-0989-45f0-84c2-bb765b85754d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1334299353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1334299353 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1075285101 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 26113581427 ps |
| CPU time | 88.56 seconds |
| Started | Jan 17 12:25:07 PM PST 24 |
| Finished | Jan 17 12:26:38 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-4d5e2b47-bba4-44e8-8a66-0bce44e33d31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1075285101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1075285101 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1657863693 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2249007018 ps |
| CPU time | 10.96 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-0a8538ba-63ca-43c7-98e9-8c97312ef285 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1657863693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1657863693 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.953725023 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 195302774 ps |
| CPU time | 2.68 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:25:21 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-821d83fe-89f9-43fb-819d-652e6c87afdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=953725023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.953725023 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3186502654 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1051130618 ps |
| CPU time | 8.12 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-9c2e1b22-db64-4d1a-9a8b-5371793601ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186502654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3186502654 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2175100323 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 35865802598 ps |
| CPU time | 131.63 seconds |
| Started | Jan 17 12:25:01 PM PST 24 |
| Finished | Jan 17 12:27:14 PM PST 24 |
| Peak memory | 200808 kb |
| Host | smart-0da82192-bfab-4e86-8d5b-16a84c323d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175100323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2175100323 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1763653424 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 33862236470 ps |
| CPU time | 189.3 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:28:17 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-419f611a-c9b3-4739-9072-76875bc8ef11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1763653424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1763653424 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.30721932 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 43875865 ps |
| CPU time | 3.94 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-9c185b72-4088-4e39-98ee-adefb991aee1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.30721932 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1322793925 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 671624684 ps |
| CPU time | 7.42 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:17 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-955e64fa-0309-4eee-9d75-d1b81a67e041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322793925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1322793925 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.4213357267 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 9835150 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:09 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-3c8f6355-6458-45bc-b76b-2976e4992801 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213357267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.4213357267 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3138469981 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1536469567 ps |
| CPU time | 6.96 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-fb689dbf-a599-4f37-b3a8-74c37f9f405b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138469981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3138469981 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.711548322 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4991186325 ps |
| CPU time | 7.01 seconds |
| Started | Jan 17 12:25:04 PM PST 24 |
| Finished | Jan 17 12:25:15 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-4ab00fbb-cd3c-4be1-95e8-61fde4ee062d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=711548322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.711548322 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.674796755 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 8621761 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 12:25:16 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-36a81966-257a-410d-910d-836dc179f5af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674796755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.674796755 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3687018399 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1501038405 ps |
| CPU time | 29.24 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-b1ec835b-06b3-4a6f-9f29-3cd688fe5987 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3687018399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3687018399 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.4202139946 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 137301397 ps |
| CPU time | 9.63 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-66c0bb15-c629-4e6c-bb5c-2a2e4d15975f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4202139946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.4202139946 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2769040147 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 8724147363 ps |
| CPU time | 110.4 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:26:59 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-a416f296-7485-4b02-9a22-447bdef7a541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769040147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2769040147 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2028153801 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 131556348 ps |
| CPU time | 2.33 seconds |
| Started | Jan 17 12:25:01 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-81078f8e-0268-43a4-87a2-77268ca576b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028153801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2028153801 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.398247021 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 817126339 ps |
| CPU time | 16.55 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-8889f5ec-a8fb-462d-9818-fa62f7f7ed47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398247021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.398247021 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2649197391 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 36382702766 ps |
| CPU time | 257.41 seconds |
| Started | Jan 17 12:25:10 PM PST 24 |
| Finished | Jan 17 12:29:35 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-7a90e234-f315-42fd-ad44-f46001f958b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2649197391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2649197391 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.295331481 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2243787497 ps |
| CPU time | 8.88 seconds |
| Started | Jan 17 12:25:07 PM PST 24 |
| Finished | Jan 17 12:25:18 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-209f22cf-6426-41ab-999b-968e51a2ed8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=295331481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.295331481 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1260249336 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 27072477 ps |
| CPU time | 1.57 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-aa7dfde1-e3be-49fc-8760-20a12356005f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1260249336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1260249336 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.67902119 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 43108813436 ps |
| CPU time | 164.24 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:27:54 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-41b9d442-6f7b-409a-b832-9373b8a3e40d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=67902119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.67902119 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3971233550 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 27290284705 ps |
| CPU time | 162.89 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:27:52 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-9675fdd2-0156-4351-b1ec-ea54de2d64dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3971233550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3971233550 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1045878973 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 36101929 ps |
| CPU time | 3.93 seconds |
| Started | Jan 17 12:25:02 PM PST 24 |
| Finished | Jan 17 12:25:07 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-66b69df2-fd64-4e13-b165-3e443e15c623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045878973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1045878973 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3354617511 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 839438207 ps |
| CPU time | 11.03 seconds |
| Started | Jan 17 12:25:22 PM PST 24 |
| Finished | Jan 17 12:25:34 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-83bb7097-5973-43bf-9c48-c3bc72994ef2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354617511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3354617511 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1477012477 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 9180576 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 12:25:05 PM PST 24 |
| Finished | Jan 17 12:25:10 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-43a57f73-0401-4384-99f6-6639f4b46faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1477012477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1477012477 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1041394958 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1839832023 ps |
| CPU time | 7.09 seconds |
| Started | Jan 17 12:25:10 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-1dd8f728-2a55-443f-b089-c8bd1e163fcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041394958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1041394958 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3801856219 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3082489982 ps |
| CPU time | 12.7 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201624 kb |
| Host | smart-876c004a-220b-414c-93cb-8e92874bc39d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3801856219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3801856219 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1081272197 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12199701 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:11 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-da5ab2be-11d6-45d2-b698-4bdb84d81884 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081272197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1081272197 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4011862274 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 6312196073 ps |
| CPU time | 96.21 seconds |
| Started | Jan 17 12:25:06 PM PST 24 |
| Finished | Jan 17 12:26:45 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-d2da88d9-6fe8-406e-8a56-ecb926d44dd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011862274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4011862274 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3023669556 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1772836710 ps |
| CPU time | 11.13 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-0e91ac80-3b3e-4a96-ae53-9baed0ad0fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3023669556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3023669556 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1462608336 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 570078276 ps |
| CPU time | 35.54 seconds |
| Started | Jan 17 12:25:07 PM PST 24 |
| Finished | Jan 17 12:25:45 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-7b11339d-6d7a-4aeb-a6dc-c87d466b1022 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1462608336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.1462608336 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3751715184 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 59253259 ps |
| CPU time | 3.69 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-8668e2e7-f0c9-4b53-b564-1c3458f0ef65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3751715184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3751715184 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2489276466 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 51280582 ps |
| CPU time | 7.1 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:25 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-301a36ea-81a9-458e-ac62-792975e519ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2489276466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2489276466 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.734220388 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 30913062421 ps |
| CPU time | 199.08 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:28:36 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-dbe72b4d-fd58-4bfe-86b4-6fd5e8b2d555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=734220388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.734220388 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.791416921 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 685702675 ps |
| CPU time | 2 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:20 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-3782fa67-ab92-4975-a8f9-5f38cb2c091e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791416921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.791416921 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2032232215 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1041710387 ps |
| CPU time | 14.62 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:35 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-81e662db-9d24-4743-9e9f-0c3d17422388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2032232215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2032232215 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3166522723 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9176065 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:21 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-3123bf83-92ab-43e2-a68f-85787e3c0eda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3166522723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3166522723 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3076830483 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3321432015 ps |
| CPU time | 15.87 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-492c065a-1d24-4e7f-a6f0-d52f28ed5ed8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076830483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3076830483 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1026703896 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 19466715289 ps |
| CPU time | 83.42 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:26:48 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-7ef64642-061c-4d6e-b2bb-5740adc4a0bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1026703896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1026703896 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3070717758 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 49337557 ps |
| CPU time | 6.33 seconds |
| Started | Jan 17 12:25:08 PM PST 24 |
| Finished | Jan 17 12:25:16 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-76f3d8c3-12f2-48e9-9f03-8ddd8e15c70b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070717758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3070717758 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1403397874 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4029645602 ps |
| CPU time | 9.06 seconds |
| Started | Jan 17 12:25:31 PM PST 24 |
| Finished | Jan 17 12:25:42 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-dab8158a-84b3-4248-be0f-dde07dc5ae4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403397874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1403397874 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.774827493 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 171427992 ps |
| CPU time | 1.56 seconds |
| Started | Jan 17 12:25:10 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-ba181f9f-ebee-4ea4-bd4d-5b847c3e8ab7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=774827493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.774827493 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2816379266 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6358565981 ps |
| CPU time | 7.76 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-7aebbf9c-e97f-4ed1-9009-25f7ac117363 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816379266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2816379266 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1762792739 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2934204928 ps |
| CPU time | 11.76 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-68ac66a6-0734-40b9-83f9-cb9cfb2d8a93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1762792739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1762792739 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3181387077 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 23930025 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-d6b8be36-1905-47fc-838e-d5837c07baf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181387077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3181387077 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1057787447 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1881131155 ps |
| CPU time | 38.88 seconds |
| Started | Jan 17 12:25:29 PM PST 24 |
| Finished | Jan 17 12:26:11 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-e9aa30a9-4a03-41bc-b754-828e4694f87c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1057787447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1057787447 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3530636954 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 211532991 ps |
| CPU time | 19.95 seconds |
| Started | Jan 17 12:25:10 PM PST 24 |
| Finished | Jan 17 12:25:37 PM PST 24 |
| Peak memory | 201680 kb |
| Host | smart-9ddd2ad3-4c17-4f20-8911-d847c656526f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3530636954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3530636954 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1130930923 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 886997890 ps |
| CPU time | 41.32 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:26:04 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-bb20b867-2872-4828-8be8-4e9bf14f9c87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1130930923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1130930923 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2952736331 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 38732993 ps |
| CPU time | 11.38 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-ee528881-2dc4-4c67-b6d8-7d83293c031b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2952736331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2952736331 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1689594321 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 59440635 ps |
| CPU time | 4.95 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-65b12665-70cc-41c4-b358-28189be68c3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1689594321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1689594321 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2531795085 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2392213538 ps |
| CPU time | 14.07 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-960965f8-41dc-4191-af5a-7d5e7922a23c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2531795085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2531795085 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.149507139 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 7302854116 ps |
| CPU time | 21.76 seconds |
| Started | Jan 17 12:25:30 PM PST 24 |
| Finished | Jan 17 12:25:54 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-c8640dc8-3462-46d8-b10a-f61cd765d6bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=149507139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.149507139 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3080665123 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 246584176 ps |
| CPU time | 3.43 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-0bb45ee9-a53e-4b1a-9dd5-24f872b2d1cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080665123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3080665123 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.406055165 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 472079902 ps |
| CPU time | 7.31 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:25 PM PST 24 |
| Peak memory | 201132 kb |
| Host | smart-4e3525b9-4524-4e33-b92c-ac7f10955149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406055165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.406055165 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3066424276 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 859024249 ps |
| CPU time | 14.05 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 200416 kb |
| Host | smart-317502e6-9b57-4020-bc3b-8593cefd57ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3066424276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3066424276 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3445314790 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 31583621020 ps |
| CPU time | 110.13 seconds |
| Started | Jan 17 12:25:30 PM PST 24 |
| Finished | Jan 17 12:27:23 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-959cf1fe-92bf-4874-a9a3-3a2954ceb621 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445314790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3445314790 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.897380308 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 48437005510 ps |
| CPU time | 165.66 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:28:04 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ee5369ca-3997-4bba-ad83-55232d9bbc7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=897380308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.897380308 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3845147394 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 193539395 ps |
| CPU time | 7.5 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-ea713785-ce21-4774-9e71-d491ef792374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845147394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3845147394 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2122884907 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 111741951 ps |
| CPU time | 6.33 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-b6938f49-0987-42ff-a43e-91d6b7f59f9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2122884907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2122884907 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.662709622 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 36476217 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-69b9e1b2-21b6-4bcc-ab4f-eeb0ca3adc3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=662709622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.662709622 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3286787731 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2597971056 ps |
| CPU time | 9.73 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:31 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-ce99e65c-f118-40cd-becf-17c5ed88f145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286787731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3286787731 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3043918312 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1355671465 ps |
| CPU time | 7.82 seconds |
| Started | Jan 17 12:25:31 PM PST 24 |
| Finished | Jan 17 12:25:40 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-46c962c7-ebec-4409-aab9-1f9920e7acc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3043918312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3043918312 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3331566603 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 10426947 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-4f2f2f8b-0330-44f2-9e80-3af1d6fbd501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331566603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3331566603 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.4048137579 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3859874231 ps |
| CPU time | 46.27 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:26:09 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-c916a4b8-a570-4d7c-bacb-8f54d1552be0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4048137579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4048137579 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1037932437 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8758595531 ps |
| CPU time | 78.65 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:26:41 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-aa65a0b1-1f3e-44f0-b0a0-564ae525b6e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037932437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1037932437 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4262961243 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 52090543 ps |
| CPU time | 9.12 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-b8916dad-7eeb-4dce-87e6-9e45468b501b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4262961243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.4262961243 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2441669999 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 118599720 ps |
| CPU time | 8.82 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:25:33 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-7411d23f-fb29-49dc-a83e-5100f97b1ca6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2441669999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2441669999 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2879545082 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 51488552 ps |
| CPU time | 1.66 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-d4db564e-74f4-4716-88d4-3d546c424e8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879545082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2879545082 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1149418131 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 984326662 ps |
| CPU time | 19.99 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:44 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a4a0c2c2-f9ad-4d63-841f-a9a79552b75a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149418131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1149418131 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3304305491 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3471920129 ps |
| CPU time | 15.2 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-d3565646-4dc0-48fb-a27d-9001d48af17f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3304305491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3304305491 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3205797280 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1985486449 ps |
| CPU time | 10.71 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-526424b7-5b12-40c1-a40c-338df4e51466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3205797280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3205797280 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2408604927 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 74766856 ps |
| CPU time | 4.6 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-5c10a0ff-ff05-42ee-996d-485c99bf4c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408604927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2408604927 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2393257517 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 83772198 ps |
| CPU time | 3.39 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-33210e8e-3072-459c-941f-b74900c5374b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2393257517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2393257517 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3507384458 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2253742001 ps |
| CPU time | 11.52 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:36 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-856785e9-5102-4be3-af08-421a8770e893 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507384458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3507384458 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2043074930 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 15963801918 ps |
| CPU time | 78.19 seconds |
| Started | Jan 17 12:25:12 PM PST 24 |
| Finished | Jan 17 12:26:36 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-0f9e4dcc-1041-4a6a-9d7f-41b8aba9f604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2043074930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2043074930 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2327621351 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 57582631 ps |
| CPU time | 3.72 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-82c15169-6dc4-40cd-8316-1a41cf6a1900 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327621351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2327621351 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.1767796873 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 89450607 ps |
| CPU time | 5.25 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:23 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-02ea002e-a312-40b8-86ca-43d89ac054e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1767796873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1767796873 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3905954255 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 80386659 ps |
| CPU time | 1.54 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-489e063d-6360-4460-8468-c2152ddd17f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3905954255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3905954255 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3637050187 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2712717095 ps |
| CPU time | 12.89 seconds |
| Started | Jan 17 12:25:09 PM PST 24 |
| Finished | Jan 17 12:25:30 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-6788a05d-2963-47de-af5f-b37c850fa25b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637050187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3637050187 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.298448958 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 6054701371 ps |
| CPU time | 13.17 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:31 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-88a7fd6a-0a25-4d3c-a081-7315ecfea41f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=298448958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.298448958 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.828390650 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 22352677 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ffb41c37-ec7e-4222-9cf5-779d3562ed08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828390650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.828390650 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2377322258 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8761510152 ps |
| CPU time | 102.1 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:27:02 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-503d57cf-b5cc-42b3-ae22-6a98c3b5767a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377322258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2377322258 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3475078735 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2009718500 ps |
| CPU time | 35.61 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:55 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-454f8806-ea92-41ca-8e8a-8202a9bbad8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3475078735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3475078735 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1735811918 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 330865386 ps |
| CPU time | 37.02 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:57 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-6f6b5e42-39c8-45a6-a179-8d1a0db1b246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1735811918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1735811918 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1498979206 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 124655017 ps |
| CPU time | 13.8 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:34 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-22566b2d-6a49-4259-a4a7-160fdc574194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498979206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1498979206 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.801484814 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 28102892 ps |
| CPU time | 3.11 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:21 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-f16f68b7-9eb7-4f2e-b470-5c6a4b49dd12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=801484814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.801484814 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1749691649 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1780336994 ps |
| CPU time | 23.13 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:25:42 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-27be1d1c-9882-4ead-9145-4a896b5aad83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1749691649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1749691649 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.972044226 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 26826898357 ps |
| CPU time | 197.75 seconds |
| Started | Jan 17 12:25:28 PM PST 24 |
| Finished | Jan 17 12:28:48 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-b3d2762b-fb55-43b4-9dd9-2d21d27db3c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=972044226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.972044226 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2456530514 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 19128024 ps |
| CPU time | 1.25 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-07d95e66-3dc5-42bc-9c50-89b3bf91bfa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2456530514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2456530514 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3662672127 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 44648994 ps |
| CPU time | 3.47 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:25 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-860e5aac-b021-48ad-83b7-2f3e8432720c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3662672127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3662672127 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1272965185 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 327746590 ps |
| CPU time | 3.57 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:24 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-d585d040-cd69-4c3a-b58e-431d3782eb5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1272965185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1272965185 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2569900597 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 23647139920 ps |
| CPU time | 102.58 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:27:07 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-01e1b94a-aa42-4616-90f4-5dc8d764a4c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569900597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2569900597 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.219460317 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 33727291484 ps |
| CPU time | 208.26 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:28:52 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-d2cef0fa-9a07-4d4c-bd49-79208ca0dcd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=219460317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.219460317 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3209898203 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 66013207 ps |
| CPU time | 4.24 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-ac7b6ce5-3db7-495c-8809-0eef8700bba6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209898203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3209898203 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3760869886 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 280836683 ps |
| CPU time | 3.29 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:22 PM PST 24 |
| Peak memory | 201692 kb |
| Host | smart-109ae310-fe58-407b-a422-10a56296fd03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3760869886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3760869886 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.1967357718 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 72158087 ps |
| CPU time | 1.5 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-691fc230-377a-4686-a432-db8759d788ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1967357718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1967357718 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1395294154 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2785673271 ps |
| CPU time | 9.84 seconds |
| Started | Jan 17 12:25:28 PM PST 24 |
| Finished | Jan 17 12:25:40 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-d378055d-2e53-4b67-9a08-a1bfd16dcb90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395294154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1395294154 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3060152025 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2213453031 ps |
| CPU time | 10.47 seconds |
| Started | Jan 17 12:25:17 PM PST 24 |
| Finished | Jan 17 12:25:29 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-b485071b-ecf8-4754-86b3-e41456da0e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3060152025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3060152025 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4241542977 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 10148193 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 12:25:13 PM PST 24 |
| Finished | Jan 17 12:25:19 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-e2e9de65-141a-42bb-aecd-06b76b965034 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241542977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.4241542977 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2925602368 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3682543505 ps |
| CPU time | 24.81 seconds |
| Started | Jan 17 12:25:18 PM PST 24 |
| Finished | Jan 17 12:25:44 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-97b4435e-f57a-417d-9f04-954807c1defb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925602368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2925602368 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1270796386 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2222556785 ps |
| CPU time | 29.81 seconds |
| Started | Jan 17 12:25:29 PM PST 24 |
| Finished | Jan 17 12:26:02 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-8a880280-fbbf-407d-afc0-b74e414b2208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1270796386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1270796386 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3406042639 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2949106271 ps |
| CPU time | 194.46 seconds |
| Started | Jan 17 12:25:33 PM PST 24 |
| Finished | Jan 17 12:28:48 PM PST 24 |
| Peak memory | 208280 kb |
| Host | smart-0a5a38b5-378c-462c-80cc-7b5dc46b6b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406042639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3406042639 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3416831002 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 985955559 ps |
| CPU time | 11.79 seconds |
| Started | Jan 17 12:25:25 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-6498951d-a6ae-4b37-bace-acf47b85bad7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3416831002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3416831002 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2027515806 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 31658671 ps |
| CPU time | 2.74 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201676 kb |
| Host | smart-fd45b451-7ad0-4634-a875-c97770e15137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2027515806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2027515806 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2022287702 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2029699004 ps |
| CPU time | 15.04 seconds |
| Started | Jan 17 12:25:24 PM PST 24 |
| Finished | Jan 17 12:25:40 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-d00cde16-3274-4605-a537-decdb4ef0270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2022287702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2022287702 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2982668666 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 59168637 ps |
| CPU time | 6.39 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-5c4a0178-3da2-481b-a42d-ff65996a6864 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2982668666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2982668666 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.436835585 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 181674412 ps |
| CPU time | 3.43 seconds |
| Started | Jan 17 12:25:33 PM PST 24 |
| Finished | Jan 17 12:25:37 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-38618c18-f92d-44e5-8ff3-bcdf525905a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=436835585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.436835585 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1298353366 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 228895342 ps |
| CPU time | 3.41 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-2fc5fb98-1153-4d97-a17e-03d574b5c261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1298353366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1298353366 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.4077870526 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 106861031046 ps |
| CPU time | 112.54 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:27:13 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-96dbd1af-18e4-4065-a709-c793e3029e4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077870526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4077870526 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4200517010 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2745443432 ps |
| CPU time | 16.16 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:37 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-e8483cfc-5a35-4d2f-a43c-65f658f4ced5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4200517010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4200517010 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1241641354 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 61013751 ps |
| CPU time | 6.43 seconds |
| Started | Jan 17 12:25:28 PM PST 24 |
| Finished | Jan 17 12:25:37 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-e923791a-059d-4042-b87d-b18536ee3fd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241641354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1241641354 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.3013002763 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 47106959 ps |
| CPU time | 2.14 seconds |
| Started | Jan 17 12:25:25 PM PST 24 |
| Finished | Jan 17 12:25:28 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-fc1d0e9a-bd85-444a-a351-d5ca1d874346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013002763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3013002763 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.2960404505 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 94292233 ps |
| CPU time | 1.67 seconds |
| Started | Jan 17 12:25:23 PM PST 24 |
| Finished | Jan 17 12:25:26 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-086eb108-723a-4888-ba2a-04a954b92c94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2960404505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2960404505 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2587342691 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4344585242 ps |
| CPU time | 11.45 seconds |
| Started | Jan 17 12:25:20 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-a4a59143-e547-4d8e-a9c6-01fc757b9788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587342691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2587342691 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.342965887 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 6809423065 ps |
| CPU time | 7.33 seconds |
| Started | Jan 17 12:25:29 PM PST 24 |
| Finished | Jan 17 12:25:38 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-0bcf19b1-3a05-4599-91eb-6298ce769679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=342965887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.342965887 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3828117636 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 10381102 ps |
| CPU time | 1.39 seconds |
| Started | Jan 17 12:25:25 PM PST 24 |
| Finished | Jan 17 12:25:27 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-8c9414e9-c92b-40f3-b436-3db379ca2650 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828117636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3828117636 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3355898226 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1924670013 ps |
| CPU time | 15.36 seconds |
| Started | Jan 17 12:25:33 PM PST 24 |
| Finished | Jan 17 12:25:49 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-578ea9ce-f8a8-497b-86a6-b12aa3ad2520 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3355898226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3355898226 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1063450363 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 813899652 ps |
| CPU time | 11.2 seconds |
| Started | Jan 17 12:25:19 PM PST 24 |
| Finished | Jan 17 12:25:32 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-5157cbcb-2531-4acf-a4a9-35ad79194931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1063450363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1063450363 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4127416821 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1802441486 ps |
| CPU time | 59.12 seconds |
| Started | Jan 17 12:25:33 PM PST 24 |
| Finished | Jan 17 12:26:33 PM PST 24 |
| Peak memory | 204008 kb |
| Host | smart-fa654321-4170-4aa3-8b92-0f3fbe42205f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127416821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.4127416821 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3802840624 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 306602279 ps |
| CPU time | 44.68 seconds |
| Started | Jan 17 12:25:21 PM PST 24 |
| Finished | Jan 17 12:26:07 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-a4083f3f-eed6-4c89-a70f-39c00334c4c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3802840624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3802840624 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1951993281 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 44836888 ps |
| CPU time | 5.76 seconds |
| Started | Jan 17 12:20:13 PM PST 24 |
| Finished | Jan 17 12:20:20 PM PST 24 |
| Peak memory | 200720 kb |
| Host | smart-a9654bc3-e594-4350-9abb-016a91408060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951993281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1951993281 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.672145774 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 13712024175 ps |
| CPU time | 105.5 seconds |
| Started | Jan 17 12:20:27 PM PST 24 |
| Finished | Jan 17 12:22:16 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-79bbde51-7606-4ff4-98db-40db016032e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=672145774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.672145774 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.808941230 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 189137636 ps |
| CPU time | 2.96 seconds |
| Started | Jan 17 12:19:08 PM PST 24 |
| Finished | Jan 17 12:19:11 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-59fd104b-402d-435d-af8f-7b7b37e5f8c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808941230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.808941230 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.150755610 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8606989 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:20:27 PM PST 24 |
| Finished | Jan 17 12:20:32 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-2f60b11a-cdb3-492c-b2e1-eb3ec94b0c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=150755610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.150755610 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.797278007 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 44222684 ps |
| CPU time | 2.83 seconds |
| Started | Jan 17 12:24:37 PM PST 24 |
| Finished | Jan 17 12:24:40 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-a04a7219-0c39-41ca-84dd-6aee8dc9015a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797278007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.797278007 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3757036794 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 18277716899 ps |
| CPU time | 55.76 seconds |
| Started | Jan 17 12:20:04 PM PST 24 |
| Finished | Jan 17 12:21:01 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-2e30306e-628f-4789-8e30-e96839bf2360 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757036794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3757036794 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.686758841 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 29256282272 ps |
| CPU time | 104.03 seconds |
| Started | Jan 17 12:23:03 PM PST 24 |
| Finished | Jan 17 12:24:48 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-17d86f35-510d-4eaa-8779-7cafde8c5a9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=686758841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.686758841 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3459446078 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 24863606 ps |
| CPU time | 2.77 seconds |
| Started | Jan 17 12:24:30 PM PST 24 |
| Finished | Jan 17 12:24:34 PM PST 24 |
| Peak memory | 199420 kb |
| Host | smart-db9dc717-be10-4bd0-ba14-5b56dd0054b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459446078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3459446078 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2749473444 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 135144166 ps |
| CPU time | 1.62 seconds |
| Started | Jan 17 12:21:33 PM PST 24 |
| Finished | Jan 17 12:21:35 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-490a4c18-921a-43b4-8f4e-36f7d50232c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749473444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2749473444 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.3389345375 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 12880287 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 12:20:04 PM PST 24 |
| Finished | Jan 17 12:20:06 PM PST 24 |
| Peak memory | 199392 kb |
| Host | smart-ff51d2bf-95e9-4d00-b301-2724f1f55140 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3389345375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3389345375 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.306732041 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1902095206 ps |
| CPU time | 9.8 seconds |
| Started | Jan 17 12:19:30 PM PST 24 |
| Finished | Jan 17 12:19:40 PM PST 24 |
| Peak memory | 201668 kb |
| Host | smart-9e95a338-5724-4d33-b9b5-8313ed75d081 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=306732041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.306732041 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1513574572 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 948390993 ps |
| CPU time | 7.43 seconds |
| Started | Jan 17 12:20:27 PM PST 24 |
| Finished | Jan 17 12:20:38 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-77b93632-020d-4600-9f33-dd23436f05be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1513574572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1513574572 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3250713518 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 8214753 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:21:05 PM PST 24 |
| Finished | Jan 17 12:21:07 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-16ed2bd4-3cf8-409b-b243-984cbe7f0f41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250713518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3250713518 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2485936564 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3167501123 ps |
| CPU time | 25.77 seconds |
| Started | Jan 17 12:25:14 PM PST 24 |
| Finished | Jan 17 12:25:44 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-60ba1187-0a70-4b0d-9b0b-3fa9b2b63857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2485936564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2485936564 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3770871613 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 186026140 ps |
| CPU time | 11.51 seconds |
| Started | Jan 17 12:23:38 PM PST 24 |
| Finished | Jan 17 12:23:51 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-3656872e-ac27-4bda-8eff-4eb3a1f15e95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770871613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3770871613 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3237266157 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 6467850244 ps |
| CPU time | 173.69 seconds |
| Started | Jan 17 12:23:58 PM PST 24 |
| Finished | Jan 17 12:26:54 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-af5be7fb-a53e-4bae-94ff-501a9654a7fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237266157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3237266157 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1261622471 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 153898878 ps |
| CPU time | 8.04 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:10 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-7ca09deb-108a-463c-8205-6f33c1dc82e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261622471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1261622471 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.523473879 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 703097916 ps |
| CPU time | 10.02 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:20 PM PST 24 |
| Peak memory | 199284 kb |
| Host | smart-8690fd2d-a7b9-48f4-8457-b0684ec2d274 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=523473879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.523473879 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1269385139 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1014477344 ps |
| CPU time | 3.74 seconds |
| Started | Jan 17 12:26:16 PM PST 24 |
| Finished | Jan 17 12:26:22 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-cb7bcf94-315e-4fb9-b01d-f0ab6f82f012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1269385139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1269385139 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2477420695 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 21148727281 ps |
| CPU time | 100.36 seconds |
| Started | Jan 17 12:19:44 PM PST 24 |
| Finished | Jan 17 12:21:27 PM PST 24 |
| Peak memory | 199384 kb |
| Host | smart-ae17ce9d-b9d1-44a5-840a-4c53fac28cad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2477420695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.2477420695 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3056971031 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 262168305 ps |
| CPU time | 3.88 seconds |
| Started | Jan 17 12:19:32 PM PST 24 |
| Finished | Jan 17 12:19:37 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-bf1cd9e0-45db-4812-8a24-666dc46af3c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056971031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3056971031 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.696237823 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 85307173 ps |
| CPU time | 5.56 seconds |
| Started | Jan 17 12:27:09 PM PST 24 |
| Finished | Jan 17 12:27:28 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-63683831-7e28-402d-9176-26ae98f1b623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=696237823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.696237823 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.994428621 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 173104473 ps |
| CPU time | 2.9 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:22:58 PM PST 24 |
| Peak memory | 198380 kb |
| Host | smart-c2de6832-6221-4448-a215-e2552479ef63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=994428621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.994428621 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1743411022 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6401026076 ps |
| CPU time | 26.55 seconds |
| Started | Jan 17 12:23:48 PM PST 24 |
| Finished | Jan 17 12:24:17 PM PST 24 |
| Peak memory | 200756 kb |
| Host | smart-2b23f610-3643-4302-a75f-62912ffbc730 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743411022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1743411022 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1982029114 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2622917191 ps |
| CPU time | 12.13 seconds |
| Started | Jan 17 12:23:12 PM PST 24 |
| Finished | Jan 17 12:23:29 PM PST 24 |
| Peak memory | 200788 kb |
| Host | smart-27fd7cd5-dbf8-457d-81a1-792fb81d3de5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1982029114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1982029114 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.225007965 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 149034022 ps |
| CPU time | 6.06 seconds |
| Started | Jan 17 12:23:53 PM PST 24 |
| Finished | Jan 17 12:24:00 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-73b39194-4c70-4476-8cdf-7cfab9dc9e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225007965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.225007965 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.528232087 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 54320665 ps |
| CPU time | 5.11 seconds |
| Started | Jan 17 12:19:43 PM PST 24 |
| Finished | Jan 17 12:19:49 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-c0b36bb9-4de3-40bc-9b87-16da167ca742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=528232087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.528232087 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.361982820 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 38668572 ps |
| CPU time | 1.42 seconds |
| Started | Jan 17 12:22:55 PM PST 24 |
| Finished | Jan 17 12:22:57 PM PST 24 |
| Peak memory | 198652 kb |
| Host | smart-23adbce1-1e20-4c44-8d1c-cf849695c8e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=361982820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.361982820 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2255840212 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2107677873 ps |
| CPU time | 8.73 seconds |
| Started | Jan 17 12:23:38 PM PST 24 |
| Finished | Jan 17 12:23:48 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-c9061e90-7af3-40b5-a638-670a92930de6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255840212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2255840212 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.285006326 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 855912659 ps |
| CPU time | 5.47 seconds |
| Started | Jan 17 12:18:20 PM PST 24 |
| Finished | Jan 17 12:18:27 PM PST 24 |
| Peak memory | 200768 kb |
| Host | smart-baa96a99-93dc-4061-b26d-f7c5d7cdfa9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=285006326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.285006326 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2893345378 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8442779 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 12:20:07 PM PST 24 |
| Finished | Jan 17 12:20:08 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-43f5cc06-8d34-4b4c-832c-0081fce988ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893345378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2893345378 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4081886978 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 18648559493 ps |
| CPU time | 55.43 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:23:36 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-351895b2-b889-4582-b217-4457295ef0da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4081886978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4081886978 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2187745313 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 241426485 ps |
| CPU time | 7.03 seconds |
| Started | Jan 17 12:19:42 PM PST 24 |
| Finished | Jan 17 12:19:51 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-dcea612c-9380-4d76-b78f-5d45024e0021 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187745313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2187745313 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1323968817 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 577732593 ps |
| CPU time | 96.37 seconds |
| Started | Jan 17 12:20:30 PM PST 24 |
| Finished | Jan 17 12:22:07 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-e3ec0b4d-cfb4-40a1-a762-424f44bcbce4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323968817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1323968817 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3726373751 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 367865025 ps |
| CPU time | 38.71 seconds |
| Started | Jan 17 12:24:53 PM PST 24 |
| Finished | Jan 17 12:25:33 PM PST 24 |
| Peak memory | 201600 kb |
| Host | smart-6c7e7e65-4342-466b-9dfc-52b581524d9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3726373751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.3726373751 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1332247486 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 519977468 ps |
| CPU time | 10.24 seconds |
| Started | Jan 17 12:19:42 PM PST 24 |
| Finished | Jan 17 12:19:54 PM PST 24 |
| Peak memory | 201600 kb |
| Host | smart-67b0e1ee-7808-494b-a2dc-ee109a2613a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1332247486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1332247486 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.547748752 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1022148501 ps |
| CPU time | 5.42 seconds |
| Started | Jan 17 12:26:43 PM PST 24 |
| Finished | Jan 17 12:26:49 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-286e4046-9d2a-44b2-aab2-4f025995e1c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=547748752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.547748752 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2206307177 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 68395076069 ps |
| CPU time | 255.35 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:28:17 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-98e7c6ed-4b38-499a-83b6-d6536b3ce6a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2206307177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2206307177 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2818396973 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 580314569 ps |
| CPU time | 6.7 seconds |
| Started | Jan 17 12:20:13 PM PST 24 |
| Finished | Jan 17 12:20:20 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-af28fbe1-8bae-4c37-9231-1aa66715db0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2818396973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2818396973 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.3746312018 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 712716445 ps |
| CPU time | 11.76 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:42 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-849eba3e-fb5a-4093-953a-34c2ac25fc68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3746312018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3746312018 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.3384796217 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1718363667 ps |
| CPU time | 6.27 seconds |
| Started | Jan 17 12:19:33 PM PST 24 |
| Finished | Jan 17 12:19:39 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-506f9b49-9810-4b9f-9c44-58ff2f19c6ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384796217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3384796217 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1468097169 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 23964356643 ps |
| CPU time | 34.55 seconds |
| Started | Jan 17 12:23:43 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 200812 kb |
| Host | smart-5611c107-5083-4337-8fff-8727f3227d30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468097169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1468097169 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3807513444 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3272266366 ps |
| CPU time | 23.82 seconds |
| Started | Jan 17 12:19:43 PM PST 24 |
| Finished | Jan 17 12:20:08 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-b4a6c1ea-7ddb-4518-8ef4-17f4b6b9ae0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3807513444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3807513444 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.598811078 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 47374861 ps |
| CPU time | 6.63 seconds |
| Started | Jan 17 12:22:40 PM PST 24 |
| Finished | Jan 17 12:22:47 PM PST 24 |
| Peak memory | 199012 kb |
| Host | smart-eddb1684-f6f9-44e8-a58c-874789c1fd7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598811078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.598811078 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1422582572 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 361669524 ps |
| CPU time | 4.97 seconds |
| Started | Jan 17 12:19:44 PM PST 24 |
| Finished | Jan 17 12:19:52 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-50d396f9-e420-4904-840c-6153cca714ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1422582572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1422582572 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.196716095 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 163202858 ps |
| CPU time | 1.48 seconds |
| Started | Jan 17 12:23:02 PM PST 24 |
| Finished | Jan 17 12:23:05 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-e179cd3f-1509-44bb-981d-1a5f5acc2763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196716095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.196716095 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3015363565 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 6416271944 ps |
| CPU time | 9.66 seconds |
| Started | Jan 17 12:19:42 PM PST 24 |
| Finished | Jan 17 12:19:53 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-274c4338-f6a0-4615-a04e-d03dc570f389 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015363565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3015363565 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1247006705 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4139494369 ps |
| CPU time | 7.1 seconds |
| Started | Jan 17 12:23:59 PM PST 24 |
| Finished | Jan 17 12:24:09 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-ff6f66f9-a465-4ad4-8ef5-9ae1a535922b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1247006705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1247006705 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3155228689 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 8971598 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 12:19:42 PM PST 24 |
| Finished | Jan 17 12:19:45 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-a4349114-490e-4eb7-8200-fe1ff0bc2d2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155228689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3155228689 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.148304726 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 615378618 ps |
| CPU time | 29.31 seconds |
| Started | Jan 17 12:20:02 PM PST 24 |
| Finished | Jan 17 12:20:34 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-7d81919e-8e12-423e-a10c-f4e5b0aa3d49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=148304726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.148304726 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2171829769 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8034828362 ps |
| CPU time | 35.59 seconds |
| Started | Jan 17 12:20:02 PM PST 24 |
| Finished | Jan 17 12:20:40 PM PST 24 |
| Peak memory | 201980 kb |
| Host | smart-9eee52b3-3b16-4ae1-9b61-7c0ad0074b82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2171829769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2171829769 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1183873505 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9173602448 ps |
| CPU time | 142.09 seconds |
| Started | Jan 17 12:20:34 PM PST 24 |
| Finished | Jan 17 12:22:57 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-25ef9aa8-e1ac-4ab8-b675-bf9db7faa569 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1183873505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1183873505 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3611302607 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 242790134 ps |
| CPU time | 41.67 seconds |
| Started | Jan 17 12:20:13 PM PST 24 |
| Finished | Jan 17 12:20:55 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-faf414e2-fcb3-492e-9c86-18c088d53128 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3611302607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3611302607 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2559866262 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 49455005 ps |
| CPU time | 4.52 seconds |
| Started | Jan 17 12:26:43 PM PST 24 |
| Finished | Jan 17 12:26:48 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-9793333d-0457-442a-9662-b536daf08977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559866262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2559866262 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4288901177 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1018892845 ps |
| CPU time | 8.47 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:38 PM PST 24 |
| Peak memory | 200244 kb |
| Host | smart-c4d3c938-4342-40fc-84b4-11363b17169d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4288901177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4288901177 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.3018465910 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 72383955 ps |
| CPU time | 6.49 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:49 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-6b65b861-3e27-4c5b-a92d-053239277611 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018465910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3018465910 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.203283408 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 136014736 ps |
| CPU time | 2.58 seconds |
| Started | Jan 17 12:21:10 PM PST 24 |
| Finished | Jan 17 12:21:13 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-b5bd720f-848b-4cdc-a734-4cc7dce7b44e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=203283408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.203283408 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3653027861 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 22169251731 ps |
| CPU time | 77.12 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:25:47 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-f3493418-28bb-4ee3-921f-6e50c8505eae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653027861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3653027861 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1601298278 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 8575173356 ps |
| CPU time | 32.7 seconds |
| Started | Jan 17 12:24:21 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-51a9f62b-c086-401a-818b-8b29a7f8756b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1601298278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1601298278 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1198218645 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 41229582 ps |
| CPU time | 3.59 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:46 PM PST 24 |
| Peak memory | 200860 kb |
| Host | smart-20f032f0-cdd8-4deb-9109-67cde45f2a27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198218645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1198218645 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1857123819 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 54476378 ps |
| CPU time | 4.95 seconds |
| Started | Jan 17 12:20:07 PM PST 24 |
| Finished | Jan 17 12:20:12 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-bf9896fa-ba41-410f-ab4e-1396c73aafbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1857123819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1857123819 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.2477118906 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 21045452 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 12:20:03 PM PST 24 |
| Finished | Jan 17 12:20:06 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-e4f59208-2c02-498d-9c62-5a7720feabd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2477118906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2477118906 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3303149611 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3646455979 ps |
| CPU time | 11.31 seconds |
| Started | Jan 17 12:20:10 PM PST 24 |
| Finished | Jan 17 12:20:22 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-d4ec129e-6b9d-4114-a943-e73036a0fbbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303149611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3303149611 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1830539099 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1839869329 ps |
| CPU time | 11.65 seconds |
| Started | Jan 17 12:20:13 PM PST 24 |
| Finished | Jan 17 12:20:25 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-e443cda6-520f-4a67-9425-559e6f89a4a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1830539099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1830539099 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3527029477 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 10933130 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 12:24:09 PM PST 24 |
| Finished | Jan 17 12:24:11 PM PST 24 |
| Peak memory | 199456 kb |
| Host | smart-bc72e6aa-57b9-4f22-a6bc-f80da6ef8fd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527029477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3527029477 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2754486467 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1350385131 ps |
| CPU time | 34.57 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:25:04 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-ff8c5944-099e-4901-ad57-fd1b825ec872 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2754486467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2754486467 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.837820115 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 366474261 ps |
| CPU time | 30.09 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:25:00 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-f11d8e04-2ca5-4b1a-91c8-b9d6ceb37867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837820115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.837820115 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.627476912 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3435520125 ps |
| CPU time | 86.96 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:25:09 PM PST 24 |
| Peak memory | 202944 kb |
| Host | smart-3e30c245-aa7f-45dd-95f8-d22596213b55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=627476912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.627476912 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.883729202 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 965719539 ps |
| CPU time | 124.79 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:25:47 PM PST 24 |
| Peak memory | 206128 kb |
| Host | smart-ca19dc57-cb3d-4bc7-9600-ae94c3509711 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883729202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese t_error.883729202 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1491655368 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 21032754 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-fc5f9f07-ee45-448b-9284-caf2db536974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1491655368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1491655368 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2373969196 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 92764844 ps |
| CPU time | 4.86 seconds |
| Started | Jan 17 12:24:22 PM PST 24 |
| Finished | Jan 17 12:24:35 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-668a7099-960f-4845-8023-5d7418ca677e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2373969196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2373969196 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2712745785 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 63359407 ps |
| CPU time | 6.55 seconds |
| Started | Jan 17 12:23:45 PM PST 24 |
| Finished | Jan 17 12:23:57 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-ba20faf1-3424-46fa-9330-d35467a1dee9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2712745785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2712745785 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.3153237084 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2449617101 ps |
| CPU time | 14.56 seconds |
| Started | Jan 17 12:21:02 PM PST 24 |
| Finished | Jan 17 12:21:17 PM PST 24 |
| Peak memory | 201740 kb |
| Host | smart-77419527-b46c-43c7-aa14-e09397332cca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3153237084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3153237084 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3603394708 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 72304482 ps |
| CPU time | 4.1 seconds |
| Started | Jan 17 12:23:14 PM PST 24 |
| Finished | Jan 17 12:23:21 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-41bdb66d-b515-4690-b7f5-b04a434161fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3603394708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3603394708 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3672213103 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4438234808 ps |
| CPU time | 16.21 seconds |
| Started | Jan 17 12:21:10 PM PST 24 |
| Finished | Jan 17 12:21:27 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-51164d72-f659-4857-8980-54870fa2f46a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672213103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3672213103 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1404627409 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 23148164488 ps |
| CPU time | 48.35 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:24:31 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-803d8fd7-1cc3-46a8-83bf-d7948a692099 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1404627409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1404627409 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.376209956 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 32032594 ps |
| CPU time | 1.49 seconds |
| Started | Jan 17 12:23:57 PM PST 24 |
| Finished | Jan 17 12:23:59 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-816a9db1-c90b-4f69-94de-131083156ec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376209956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.376209956 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1207109597 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 64650976 ps |
| CPU time | 1.48 seconds |
| Started | Jan 17 12:24:59 PM PST 24 |
| Finished | Jan 17 12:25:01 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-4fce932d-6040-48c9-b23c-20c63509af83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1207109597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1207109597 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3706038105 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 18599543 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:23:40 PM PST 24 |
| Finished | Jan 17 12:23:44 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-da354333-f45b-4cc8-a742-1a580122cc6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706038105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3706038105 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3830095721 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 17946167615 ps |
| CPU time | 10.63 seconds |
| Started | Jan 17 12:20:59 PM PST 24 |
| Finished | Jan 17 12:21:11 PM PST 24 |
| Peak memory | 201604 kb |
| Host | smart-0c5d7e06-3fea-4c00-9f7e-2159e332dd1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830095721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3830095721 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2255040411 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 844452941 ps |
| CPU time | 4.79 seconds |
| Started | Jan 17 12:24:20 PM PST 24 |
| Finished | Jan 17 12:24:26 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-b1465714-abea-48d1-9a6f-e60b1ed267d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2255040411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2255040411 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3213051127 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 8477693 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 12:23:12 PM PST 24 |
| Finished | Jan 17 12:23:18 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-4f27b53d-b85f-4158-be1a-377cf5b7b973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213051127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3213051127 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2673050213 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 591585481 ps |
| CPU time | 20.25 seconds |
| Started | Jan 17 12:21:02 PM PST 24 |
| Finished | Jan 17 12:21:23 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-5dc21609-1b6a-46fb-a6ed-4795d1cd1883 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673050213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2673050213 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1474657896 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2841976589 ps |
| CPU time | 33.77 seconds |
| Started | Jan 17 12:20:47 PM PST 24 |
| Finished | Jan 17 12:21:26 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-58ff18f7-201a-4f5d-b0c1-e8f9ee6e91af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1474657896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1474657896 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1757351846 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 43221756 ps |
| CPU time | 6.35 seconds |
| Started | Jan 17 12:20:33 PM PST 24 |
| Finished | Jan 17 12:20:40 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-bb691c76-cddc-4b3f-8aa6-7cd5062eed70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1757351846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1757351846 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2328704373 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3947686044 ps |
| CPU time | 131.6 seconds |
| Started | Jan 17 12:24:07 PM PST 24 |
| Finished | Jan 17 12:26:19 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-2ea6352d-9a51-4112-94b6-889431e2e79b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2328704373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2328704373 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4178626563 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 79043439 ps |
| CPU time | 1.4 seconds |
| Started | Jan 17 12:23:03 PM PST 24 |
| Finished | Jan 17 12:23:04 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-5d4a1722-6071-4bd1-8341-6002246c345a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4178626563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4178626563 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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