| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.32 | 100.00 | 95.90 | 100.00 | 100.00 | 100.00 | 100.00 |
| T762 | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2374627175 | Jan 21 09:45:10 PM PST 24 | Jan 21 09:45:20 PM PST 24 | 190352329 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2094163628 | Jan 21 09:50:15 PM PST 24 | Jan 21 09:50:33 PM PST 24 | 57997536 ps | ||
| T188 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3914895161 | Jan 21 09:40:56 PM PST 24 | Jan 21 09:42:56 PM PST 24 | 4827618330 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2371447945 | Jan 21 10:11:10 PM PST 24 | Jan 21 10:11:20 PM PST 24 | 62041275 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1909321179 | Jan 21 09:46:18 PM PST 24 | Jan 21 09:46:41 PM PST 24 | 6477632944 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3085921457 | Jan 21 09:41:38 PM PST 24 | Jan 21 09:42:41 PM PST 24 | 10720213534 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.560676534 | Jan 21 09:45:26 PM PST 24 | Jan 21 09:46:55 PM PST 24 | 63850017025 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/7.xbar_random.642152374 | Jan 21 09:42:24 PM PST 24 | Jan 21 09:42:30 PM PST 24 | 1597147326 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.267706208 | Jan 21 09:38:54 PM PST 24 | Jan 21 09:39:05 PM PST 24 | 2200956307 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.373075370 | Jan 21 09:41:16 PM PST 24 | Jan 21 09:41:30 PM PST 24 | 471638329 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1624552344 | Jan 21 09:48:58 PM PST 24 | Jan 21 09:49:01 PM PST 24 | 28005924 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3188478045 | Jan 21 09:40:08 PM PST 24 | Jan 21 09:40:27 PM PST 24 | 1387722831 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1085929670 | Jan 21 09:53:41 PM PST 24 | Jan 21 09:53:44 PM PST 24 | 34325396 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3919028708 | Jan 21 09:39:24 PM PST 24 | Jan 21 09:39:39 PM PST 24 | 6256557026 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.896561703 | Jan 21 09:49:55 PM PST 24 | Jan 21 09:50:34 PM PST 24 | 474773066 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2670097210 | Jan 21 09:49:35 PM PST 24 | Jan 21 09:51:55 PM PST 24 | 24498122449 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4023226800 | Jan 21 09:52:33 PM PST 24 | Jan 21 09:53:26 PM PST 24 | 8502342394 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3490630804 | Jan 21 09:53:27 PM PST 24 | Jan 21 09:53:30 PM PST 24 | 229672252 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1687566663 | Jan 21 09:53:06 PM PST 24 | Jan 21 09:53:16 PM PST 24 | 5794528415 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2576627348 | Jan 21 09:50:54 PM PST 24 | Jan 21 09:52:11 PM PST 24 | 30517479757 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/13.xbar_random.4276881344 | Jan 21 09:44:36 PM PST 24 | Jan 21 09:44:47 PM PST 24 | 645297950 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.886122504 | Jan 21 10:30:18 PM PST 24 | Jan 21 10:30:39 PM PST 24 | 320568312 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2023354543 | Jan 21 09:43:47 PM PST 24 | Jan 21 09:44:11 PM PST 24 | 1636089453 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.36727064 | Jan 21 09:53:11 PM PST 24 | Jan 21 09:53:32 PM PST 24 | 95429065 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2834245664 | Jan 21 09:42:31 PM PST 24 | Jan 21 09:42:37 PM PST 24 | 209436117 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3580963693 | Jan 21 09:39:24 PM PST 24 | Jan 21 09:39:42 PM PST 24 | 2360358119 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.951778669 | Jan 21 09:39:03 PM PST 24 | Jan 21 09:39:19 PM PST 24 | 1880158838 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3932827330 | Jan 21 09:53:45 PM PST 24 | Jan 21 09:56:53 PM PST 24 | 24206148348 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.971610894 | Jan 21 09:51:24 PM PST 24 | Jan 21 09:52:14 PM PST 24 | 375501337 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4100511997 | Jan 21 09:47:40 PM PST 24 | Jan 21 09:50:08 PM PST 24 | 67826912861 ps | ||
| T119 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3019268385 | Jan 21 09:54:57 PM PST 24 | Jan 21 09:59:39 PM PST 24 | 63318822334 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3697744699 | Jan 21 09:43:18 PM PST 24 | Jan 21 09:44:58 PM PST 24 | 42202827730 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3350136614 | Jan 21 10:15:48 PM PST 24 | Jan 21 10:16:08 PM PST 24 | 3439439872 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1403022238 | Jan 21 09:43:40 PM PST 24 | Jan 21 09:43:48 PM PST 24 | 64226616 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/37.xbar_same_source.1729497730 | Jan 21 09:51:24 PM PST 24 | Jan 21 09:51:34 PM PST 24 | 371611812 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1687987825 | Jan 21 09:44:11 PM PST 24 | Jan 21 09:44:23 PM PST 24 | 295281683 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3585259001 | Jan 21 09:53:47 PM PST 24 | Jan 21 09:53:59 PM PST 24 | 1332181753 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2859488641 | Jan 21 09:50:51 PM PST 24 | Jan 21 09:50:59 PM PST 24 | 156941857 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/36.xbar_same_source.458238254 | Jan 21 10:16:08 PM PST 24 | Jan 21 10:16:32 PM PST 24 | 1142884468 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2845834192 | Jan 21 09:54:13 PM PST 24 | Jan 21 09:55:25 PM PST 24 | 3847439324 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.360575583 | Jan 21 09:43:59 PM PST 24 | Jan 21 09:44:11 PM PST 24 | 1773522964 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1539346022 | Jan 21 09:53:07 PM PST 24 | Jan 21 09:53:09 PM PST 24 | 14141892 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2503520024 | Jan 21 09:50:13 PM PST 24 | Jan 21 09:50:24 PM PST 24 | 264049998 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3432460823 | Jan 21 09:43:02 PM PST 24 | Jan 21 09:45:47 PM PST 24 | 26810666899 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3475566513 | Jan 21 09:44:44 PM PST 24 | Jan 21 09:46:18 PM PST 24 | 14490409395 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1543159794 | Jan 21 09:48:56 PM PST 24 | Jan 21 09:49:37 PM PST 24 | 412923774 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1555913440 | Jan 21 09:45:43 PM PST 24 | Jan 21 09:45:50 PM PST 24 | 12094820 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/24.xbar_random.1689072235 | Jan 21 09:47:58 PM PST 24 | Jan 21 09:48:07 PM PST 24 | 81504921 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.534126635 | Jan 21 10:51:09 PM PST 24 | Jan 21 10:51:50 PM PST 24 | 4725847740 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2247274528 | Jan 21 09:50:50 PM PST 24 | Jan 21 09:50:57 PM PST 24 | 73020229 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/32.xbar_random.2111970141 | Jan 21 09:50:04 PM PST 24 | Jan 21 09:50:19 PM PST 24 | 200678295 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4054358300 | Jan 21 09:52:55 PM PST 24 | Jan 21 09:53:03 PM PST 24 | 1686140396 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3010567653 | Jan 21 09:41:37 PM PST 24 | Jan 21 09:41:45 PM PST 24 | 572259721 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3361342057 | Jan 21 09:48:51 PM PST 24 | Jan 21 09:48:57 PM PST 24 | 28117367 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2095741668 | Jan 21 09:53:26 PM PST 24 | Jan 21 09:53:33 PM PST 24 | 53350351 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.53211122 | Jan 21 09:40:16 PM PST 24 | Jan 21 09:40:30 PM PST 24 | 62764119 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2963358007 | Jan 21 09:48:20 PM PST 24 | Jan 21 09:51:09 PM PST 24 | 34675759702 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3337725635 | Jan 21 09:52:32 PM PST 24 | Jan 21 09:52:45 PM PST 24 | 20033748 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1692748349 | Jan 21 09:42:54 PM PST 24 | Jan 21 09:43:35 PM PST 24 | 5917994975 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.4097102749 | Jan 21 09:51:57 PM PST 24 | Jan 21 09:52:04 PM PST 24 | 48440166 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3788802899 | Jan 21 09:43:02 PM PST 24 | Jan 21 09:45:07 PM PST 24 | 1314609632 ps | ||
| T120 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2722022439 | Jan 21 09:53:56 PM PST 24 | Jan 21 09:59:40 PM PST 24 | 50254236574 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2240631314 | Jan 21 09:51:03 PM PST 24 | Jan 21 09:51:06 PM PST 24 | 10835389 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.191769225 | Jan 21 09:58:34 PM PST 24 | Jan 21 09:59:25 PM PST 24 | 7660462052 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2739340139 | Jan 21 09:49:55 PM PST 24 | Jan 21 09:51:26 PM PST 24 | 10788518341 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1108955119 | Jan 21 09:52:54 PM PST 24 | Jan 21 09:53:56 PM PST 24 | 34920686666 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1407004943 | Jan 21 09:51:59 PM PST 24 | Jan 21 09:52:01 PM PST 24 | 9304395 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2364912033 | Jan 21 09:52:55 PM PST 24 | Jan 21 09:53:01 PM PST 24 | 31529640 ps | ||
| T10 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.833636690 | Jan 21 09:43:13 PM PST 24 | Jan 21 09:44:46 PM PST 24 | 11203830050 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1968960610 | Jan 21 09:39:53 PM PST 24 | Jan 21 09:40:29 PM PST 24 | 652617093 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2461836312 | Jan 21 09:46:20 PM PST 24 | Jan 21 09:46:32 PM PST 24 | 8537862 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.2641414922 | Jan 21 09:42:21 PM PST 24 | Jan 21 09:42:30 PM PST 24 | 73970949 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3148500620 | Jan 21 09:48:56 PM PST 24 | Jan 21 09:49:08 PM PST 24 | 2999045410 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3886385041 | Jan 21 09:50:16 PM PST 24 | Jan 21 09:50:31 PM PST 24 | 132120007 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1282760963 | Jan 21 09:56:19 PM PST 24 | Jan 21 09:56:45 PM PST 24 | 1099685170 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.4073369713 | Jan 21 09:49:28 PM PST 24 | Jan 21 09:49:36 PM PST 24 | 41795679 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2496747902 | Jan 21 09:46:59 PM PST 24 | Jan 21 09:47:02 PM PST 24 | 9566138 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4026682621 | Jan 21 10:55:54 PM PST 24 | Jan 21 10:56:11 PM PST 24 | 207185613 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/31.xbar_smoke.690932659 | Jan 21 09:49:41 PM PST 24 | Jan 21 09:49:44 PM PST 24 | 72526263 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2373047140 | Jan 21 09:52:30 PM PST 24 | Jan 21 09:52:45 PM PST 24 | 1331259012 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1354291129 | Jan 21 09:47:17 PM PST 24 | Jan 21 09:49:28 PM PST 24 | 1589846365 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.752150921 | Jan 21 09:50:13 PM PST 24 | Jan 21 09:52:46 PM PST 24 | 52866677415 ps | ||
| T178 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1650748844 | Jan 22 12:13:36 AM PST 24 | Jan 22 12:14:45 AM PST 24 | 7899046565 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/14.xbar_random.1897672415 | Jan 21 09:45:03 PM PST 24 | Jan 21 09:45:16 PM PST 24 | 317313240 ps | ||
| T250 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.925936429 | Jan 21 09:44:26 PM PST 24 | Jan 21 09:46:51 PM PST 24 | 55362799841 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2346602104 | Jan 21 09:54:49 PM PST 24 | Jan 21 09:54:56 PM PST 24 | 32964326 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.154519210 | Jan 21 09:47:20 PM PST 24 | Jan 21 09:47:33 PM PST 24 | 220730493 ps | ||
| T206 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.117377282 | Jan 21 09:42:18 PM PST 24 | Jan 21 09:44:51 PM PST 24 | 6894305241 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.465292465 | Jan 21 09:52:11 PM PST 24 | Jan 21 09:52:22 PM PST 24 | 1643417290 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.615252767 | Jan 21 09:52:38 PM PST 24 | Jan 21 09:53:07 PM PST 24 | 1335648856 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4261188348 | Jan 21 09:48:30 PM PST 24 | Jan 21 09:49:39 PM PST 24 | 291236136 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.500121998 | Jan 21 09:52:12 PM PST 24 | Jan 21 09:52:21 PM PST 24 | 3766153730 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3267370613 | Jan 21 09:47:38 PM PST 24 | Jan 21 09:47:50 PM PST 24 | 12342740416 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1117916776 | Jan 21 09:45:40 PM PST 24 | Jan 21 09:45:46 PM PST 24 | 19457607 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.313067931 | Jan 21 09:47:56 PM PST 24 | Jan 21 09:47:58 PM PST 24 | 15835729 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1602663597 | Jan 21 09:53:06 PM PST 24 | Jan 21 09:53:34 PM PST 24 | 217379571 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1083796853 | Jan 21 09:44:37 PM PST 24 | Jan 21 09:44:41 PM PST 24 | 40403086 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3004269379 | Jan 21 09:42:31 PM PST 24 | Jan 21 09:43:57 PM PST 24 | 32692993437 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.773155919 | Jan 21 09:44:00 PM PST 24 | Jan 21 09:44:14 PM PST 24 | 4006851529 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1834111677 | Jan 21 09:43:13 PM PST 24 | Jan 21 09:43:26 PM PST 24 | 2993431485 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1866017131 | Jan 21 09:51:35 PM PST 24 | Jan 21 09:51:52 PM PST 24 | 10441267016 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.68891070 | Jan 21 11:10:00 PM PST 24 | Jan 21 11:10:58 PM PST 24 | 7238215913 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1370429675 | Jan 21 09:53:56 PM PST 24 | Jan 21 09:54:21 PM PST 24 | 85112120 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4254768559 | Jan 21 09:50:14 PM PST 24 | Jan 21 09:52:21 PM PST 24 | 31122095806 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3824291809 | Jan 21 09:52:10 PM PST 24 | Jan 21 09:52:12 PM PST 24 | 9761634 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2867660117 | Jan 21 09:51:26 PM PST 24 | Jan 21 09:51:36 PM PST 24 | 689746774 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3450596807 | Jan 21 09:40:00 PM PST 24 | Jan 21 09:40:11 PM PST 24 | 5256359043 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3673741596 | Jan 21 09:52:39 PM PST 24 | Jan 21 09:52:51 PM PST 24 | 9464842 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4262050912 | Jan 21 09:48:54 PM PST 24 | Jan 21 09:49:07 PM PST 24 | 93486352 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.4049530702 | Jan 21 10:32:59 PM PST 24 | Jan 21 10:33:07 PM PST 24 | 225384537 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2531096285 | Jan 21 09:53:48 PM PST 24 | Jan 21 09:54:09 PM PST 24 | 1324317739 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/8.xbar_smoke.2459493609 | Jan 21 09:42:42 PM PST 24 | Jan 21 09:42:44 PM PST 24 | 268451945 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2737007996 | Jan 21 10:10:21 PM PST 24 | Jan 21 10:13:09 PM PST 24 | 36253641561 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4021832587 | Jan 21 09:54:05 PM PST 24 | Jan 21 09:55:29 PM PST 24 | 2290223908 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2512931392 | Jan 21 09:44:08 PM PST 24 | Jan 21 09:44:19 PM PST 24 | 65214921 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.4234912257 | Jan 21 09:41:15 PM PST 24 | Jan 21 09:41:19 PM PST 24 | 160573452 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1625394345 | Jan 21 09:55:51 PM PST 24 | Jan 21 09:55:58 PM PST 24 | 23182556 ps | ||
| T36 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.711425091 | Jan 21 09:50:05 PM PST 24 | Jan 21 09:50:15 PM PST 24 | 1633076072 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/20.xbar_random.3539871622 | Jan 21 09:46:59 PM PST 24 | Jan 21 09:47:06 PM PST 24 | 905189453 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/0.xbar_random.1854062504 | Jan 21 09:39:03 PM PST 24 | Jan 21 09:39:20 PM PST 24 | 303427748 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2347578029 | Jan 21 09:51:35 PM PST 24 | Jan 21 09:52:04 PM PST 24 | 509685715 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3519443165 | Jan 21 09:47:35 PM PST 24 | Jan 21 09:47:49 PM PST 24 | 723464862 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2954101547 | Jan 21 09:43:03 PM PST 24 | Jan 21 09:43:11 PM PST 24 | 1676324794 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4218727406 | Jan 21 09:45:43 PM PST 24 | Jan 21 09:45:57 PM PST 24 | 531841787 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/10.xbar_error_random.3073985829 | Jan 21 09:43:44 PM PST 24 | Jan 21 09:43:56 PM PST 24 | 1202279061 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.456384596 | Jan 21 09:51:26 PM PST 24 | Jan 21 09:51:36 PM PST 24 | 1832930868 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1431791734 | Jan 21 10:04:01 PM PST 24 | Jan 21 10:04:09 PM PST 24 | 1041717725 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3656406571 | Jan 21 09:53:11 PM PST 24 | Jan 21 09:54:54 PM PST 24 | 13367418482 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.867957337 | Jan 21 09:50:38 PM PST 24 | Jan 21 09:50:52 PM PST 24 | 769135312 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2509775907 | Jan 21 09:52:39 PM PST 24 | Jan 21 09:52:56 PM PST 24 | 2234748739 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3968385004 | Jan 21 09:42:19 PM PST 24 | Jan 21 09:42:25 PM PST 24 | 508850255 ps | ||
| T121 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3170613425 | Jan 21 09:50:59 PM PST 24 | Jan 21 09:53:16 PM PST 24 | 7760603481 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1335477306 | Jan 21 09:48:08 PM PST 24 | Jan 21 09:48:14 PM PST 24 | 122635257 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1125957311 | Jan 21 09:51:21 PM PST 24 | Jan 21 09:51:30 PM PST 24 | 151465613 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2036129099 | Jan 21 10:44:21 PM PST 24 | Jan 21 10:44:35 PM PST 24 | 343632659 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.940816752 | Jan 21 09:47:57 PM PST 24 | Jan 21 09:48:00 PM PST 24 | 66300156 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/19.xbar_random.2513251418 | Jan 21 10:19:43 PM PST 24 | Jan 21 10:19:50 PM PST 24 | 132703350 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3291705221 | Jan 21 09:49:02 PM PST 24 | Jan 21 09:49:08 PM PST 24 | 569725944 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3440227279 | Jan 21 09:49:40 PM PST 24 | Jan 21 09:50:59 PM PST 24 | 602066200 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.765796686 | Jan 21 10:45:15 PM PST 24 | Jan 21 10:45:22 PM PST 24 | 177355288 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3135943634 | Jan 21 09:48:36 PM PST 24 | Jan 21 09:48:43 PM PST 24 | 183974120 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/1.xbar_random.2333473250 | Jan 21 10:02:42 PM PST 24 | Jan 21 10:02:55 PM PST 24 | 1776022818 ps | ||
| T198 | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2537634783 | Jan 21 09:53:54 PM PST 24 | Jan 21 09:56:33 PM PST 24 | 36164443082 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2514557640 | Jan 21 09:42:08 PM PST 24 | Jan 21 09:44:43 PM PST 24 | 32777099969 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.2866787084 | Jan 21 09:53:38 PM PST 24 | Jan 21 09:53:41 PM PST 24 | 78247722 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1959135526 | Jan 21 09:43:40 PM PST 24 | Jan 21 09:45:04 PM PST 24 | 18695211274 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1252364148 | Jan 21 09:41:01 PM PST 24 | Jan 21 09:41:28 PM PST 24 | 702141019 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3060042898 | Jan 21 09:44:45 PM PST 24 | Jan 21 09:44:58 PM PST 24 | 2423290671 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1349912451 | Jan 21 09:41:02 PM PST 24 | Jan 21 09:41:14 PM PST 24 | 12441163 ps | ||
| T122 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3944634484 | Jan 21 09:39:09 PM PST 24 | Jan 21 09:42:53 PM PST 24 | 115265703484 ps |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1472572683 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5418435032 ps |
| CPU time | 81.85 seconds |
| Started | Jan 21 09:50:17 PM PST 24 |
| Finished | Jan 21 09:51:51 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-cec869d2-0b3a-4b17-b386-9035267853eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1472572683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1472572683 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2574217777 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 114904193309 ps |
| CPU time | 313.95 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:55:41 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-6e372e49-8c1a-4183-a4b5-f6384735c02e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2574217777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2574217777 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.233824839 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 232668496843 ps |
| CPU time | 300.68 seconds |
| Started | Jan 21 10:28:54 PM PST 24 |
| Finished | Jan 21 10:33:59 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-10a85dd7-d3d1-4495-9b70-9823b3b203f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=233824839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.233824839 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1419648081 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 101833809034 ps |
| CPU time | 276.84 seconds |
| Started | Jan 21 09:52:12 PM PST 24 |
| Finished | Jan 21 09:56:49 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-74f79d78-5025-43f5-bddb-199707b633af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1419648081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1419648081 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2839171662 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1099268883 ps |
| CPU time | 240.23 seconds |
| Started | Jan 21 09:50:55 PM PST 24 |
| Finished | Jan 21 09:55:01 PM PST 24 |
| Peak memory | 209840 kb |
| Host | smart-9f636a25-5e9e-4b5c-89fd-41ac691c447e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2839171662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.2839171662 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.435268494 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 42657777537 ps |
| CPU time | 253.91 seconds |
| Started | Jan 21 09:43:21 PM PST 24 |
| Finished | Jan 21 09:47:43 PM PST 24 |
| Peak memory | 202880 kb |
| Host | smart-be2b62ac-6856-4e0e-96bc-d9ad75f696f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=435268494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow _rsp.435268494 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2873602085 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 84455166997 ps |
| CPU time | 228.5 seconds |
| Started | Jan 21 09:43:59 PM PST 24 |
| Finished | Jan 21 09:47:50 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-5b571597-ee9e-4e16-a2ec-56e947726ab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2873602085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.2873602085 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3021811166 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 73184110018 ps |
| CPU time | 151.78 seconds |
| Started | Jan 21 09:53:41 PM PST 24 |
| Finished | Jan 21 09:56:16 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-f813955d-fcdd-4554-9b5c-7a202e99de79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021811166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3021811166 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2519000227 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 21629822570 ps |
| CPU time | 163.91 seconds |
| Started | Jan 21 09:51:02 PM PST 24 |
| Finished | Jan 21 09:53:48 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-6207c764-d961-4934-87f7-ea9061dde5d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2519000227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2519000227 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.951461931 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 22118559415 ps |
| CPU time | 221.79 seconds |
| Started | Jan 21 09:49:55 PM PST 24 |
| Finished | Jan 21 09:53:45 PM PST 24 |
| Peak memory | 206044 kb |
| Host | smart-4a9b1a2d-2362-460a-b499-df7207733009 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=951461931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.951461931 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3500325555 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 51483041613 ps |
| CPU time | 337.72 seconds |
| Started | Jan 21 09:49:06 PM PST 24 |
| Finished | Jan 21 09:54:45 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-c6e528fd-6687-4134-bd22-05db563d514a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3500325555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3500325555 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3916748858 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 58325740762 ps |
| CPU time | 115.56 seconds |
| Started | Jan 21 09:45:25 PM PST 24 |
| Finished | Jan 21 09:47:22 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-ec3c3786-6c7b-4b06-be1d-615347fd486c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3916748858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3916748858 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4036603179 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 27129691837 ps |
| CPU time | 123.79 seconds |
| Started | Jan 21 09:42:17 PM PST 24 |
| Finished | Jan 21 09:44:24 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-3c20cec7-d526-48e6-a114-d3b73cd61b4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036603179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4036603179 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1441835353 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 871109194 ps |
| CPU time | 190.03 seconds |
| Started | Jan 21 09:43:28 PM PST 24 |
| Finished | Jan 21 09:46:44 PM PST 24 |
| Peak memory | 209136 kb |
| Host | smart-c9d0ecc8-9525-4f84-a0d6-0c905d16d7c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1441835353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1441835353 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.513958806 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1881355444 ps |
| CPU time | 177.15 seconds |
| Started | Jan 21 09:51:37 PM PST 24 |
| Finished | Jan 21 09:54:42 PM PST 24 |
| Peak memory | 206224 kb |
| Host | smart-f9640970-7e4a-45c3-890e-68572e8b78d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513958806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.513958806 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.833636690 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11203830050 ps |
| CPU time | 91.74 seconds |
| Started | Jan 21 09:43:13 PM PST 24 |
| Finished | Jan 21 09:44:46 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-dcdeb237-e47c-4603-8220-2a77423020a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833636690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.833636690 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1441646079 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 65454457295 ps |
| CPU time | 384.6 seconds |
| Started | Jan 21 09:47:33 PM PST 24 |
| Finished | Jan 21 09:54:00 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-d8e5f1eb-d0a0-4945-ac0b-f90830693949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1441646079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1441646079 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2120572588 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4248005964 ps |
| CPU time | 70 seconds |
| Started | Jan 21 09:53:06 PM PST 24 |
| Finished | Jan 21 09:54:17 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-ba062539-8f43-4a7b-824f-86f5b17cfa7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2120572588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2120572588 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3902956762 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 9665921507 ps |
| CPU time | 89.69 seconds |
| Started | Jan 21 09:45:49 PM PST 24 |
| Finished | Jan 21 09:47:32 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-918d87c2-240e-4e11-a6c2-9dc4866cdce5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3902956762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3902956762 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1215903056 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 45501924302 ps |
| CPU time | 225.58 seconds |
| Started | Jan 21 11:09:01 PM PST 24 |
| Finished | Jan 21 11:12:47 PM PST 24 |
| Peak memory | 203008 kb |
| Host | smart-cc15458e-2ed2-4fc5-a088-957fda6f288f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1215903056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1215903056 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3494895420 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3957045559 ps |
| CPU time | 118.25 seconds |
| Started | Jan 21 10:23:06 PM PST 24 |
| Finished | Jan 21 10:25:09 PM PST 24 |
| Peak memory | 207016 kb |
| Host | smart-c1ce4555-2fc9-442d-ab27-4bd00c7182de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3494895420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3494895420 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3189760801 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 10644606183 ps |
| CPU time | 91.87 seconds |
| Started | Jan 21 09:49:11 PM PST 24 |
| Finished | Jan 21 09:50:45 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-518e3556-3839-47d9-af18-8fceafa1d68f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3189760801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.3189760801 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1379303127 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4132486580 ps |
| CPU time | 14.93 seconds |
| Started | Jan 21 09:43:58 PM PST 24 |
| Finished | Jan 21 09:44:16 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-2056bd54-dd19-44f8-9b26-3a8521704c6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1379303127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1379303127 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2068145706 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1877147977 ps |
| CPU time | 22.43 seconds |
| Started | Jan 21 10:12:01 PM PST 24 |
| Finished | Jan 21 10:12:26 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-4cd12d0a-6ef5-47ae-b333-8909b466a4b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068145706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2068145706 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3671520374 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 13982532 ps |
| CPU time | 1.42 seconds |
| Started | Jan 21 09:39:07 PM PST 24 |
| Finished | Jan 21 09:39:16 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-01c732f2-36f7-40ad-ab4f-7232b3cde430 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3671520374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3671520374 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3944634484 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 115265703484 ps |
| CPU time | 215.19 seconds |
| Started | Jan 21 09:39:09 PM PST 24 |
| Finished | Jan 21 09:42:53 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-e98ed69d-66bd-40cf-b142-809e15fb3d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3944634484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3944634484 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3635395811 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 79624839 ps |
| CPU time | 6.63 seconds |
| Started | Jan 21 09:39:20 PM PST 24 |
| Finished | Jan 21 09:39:34 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-58eb6f1f-c8ec-4ad6-8736-810fc28cb2b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635395811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3635395811 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.3124413429 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 630788777 ps |
| CPU time | 8.43 seconds |
| Started | Jan 21 10:56:30 PM PST 24 |
| Finished | Jan 21 10:56:39 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-c2353b41-d292-45d2-a444-cbe0462be645 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3124413429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3124413429 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.1854062504 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 303427748 ps |
| CPU time | 7.26 seconds |
| Started | Jan 21 09:39:03 PM PST 24 |
| Finished | Jan 21 09:39:20 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-2f45ad4d-6c71-4766-a668-c9d9cc97c815 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854062504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1854062504 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.951778669 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1880158838 ps |
| CPU time | 5.6 seconds |
| Started | Jan 21 09:39:03 PM PST 24 |
| Finished | Jan 21 09:39:19 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-957d557a-8269-4abb-8078-1431f7a46523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=951778669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.951778669 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3675870992 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 8744310706 ps |
| CPU time | 64.49 seconds |
| Started | Jan 21 09:39:09 PM PST 24 |
| Finished | Jan 21 09:40:23 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-c7cca8c1-4e5c-4c3a-ba87-b224bf89ad3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3675870992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3675870992 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1865914149 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 108944945 ps |
| CPU time | 7.52 seconds |
| Started | Jan 21 09:39:02 PM PST 24 |
| Finished | Jan 21 09:39:19 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-a5fd2367-c476-470c-a74a-2fd431ca33c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865914149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1865914149 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3661044006 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1005014629 ps |
| CPU time | 7.74 seconds |
| Started | Jan 21 09:39:09 PM PST 24 |
| Finished | Jan 21 09:39:27 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-3ca9b29f-7eac-4ae1-8aa1-5e8c9813ad6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661044006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3661044006 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3122195346 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 8493657 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 10:05:38 PM PST 24 |
| Finished | Jan 21 10:05:44 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-a91d35a4-1b5b-4336-8417-33d4642b1194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3122195346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3122195346 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.267706208 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2200956307 ps |
| CPU time | 9.86 seconds |
| Started | Jan 21 09:38:54 PM PST 24 |
| Finished | Jan 21 09:39:05 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-61d945b8-db52-4fd0-aa9a-1f3bb7c05542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=267706208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.267706208 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1538633426 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 3311160331 ps |
| CPU time | 6.97 seconds |
| Started | Jan 21 09:39:03 PM PST 24 |
| Finished | Jan 21 09:39:20 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-7678d022-38d8-4161-a763-8c1f43ccf2d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1538633426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1538633426 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.218780960 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 9723674 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 09:38:55 PM PST 24 |
| Finished | Jan 21 09:38:57 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-55ab4451-73b4-46f7-a62c-0185fb0ee41e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218780960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.218780960 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3366618347 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 191032042 ps |
| CPU time | 6.73 seconds |
| Started | Jan 21 09:39:21 PM PST 24 |
| Finished | Jan 21 09:39:34 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-859df9f5-2ca2-4fc4-8a68-a337abd18824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3366618347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3366618347 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.15432861 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1104121561 ps |
| CPU time | 27.38 seconds |
| Started | Jan 21 10:10:50 PM PST 24 |
| Finished | Jan 21 10:11:19 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-5f9f7174-9c36-4f4b-8881-91a57fd7d156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=15432861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.15432861 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.800909981 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 117274171 ps |
| CPU time | 32.46 seconds |
| Started | Jan 21 09:39:22 PM PST 24 |
| Finished | Jan 21 09:40:01 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-da2bed7b-e592-4712-ba87-d75bff2f5699 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=800909981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.800909981 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1703970844 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 30243805 ps |
| CPU time | 15.14 seconds |
| Started | Jan 21 10:30:26 PM PST 24 |
| Finished | Jan 21 10:30:55 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-08a5511b-7923-4090-a9a8-053cc80991d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1703970844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.1703970844 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.599388876 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 122663834 ps |
| CPU time | 7.83 seconds |
| Started | Jan 21 09:39:17 PM PST 24 |
| Finished | Jan 21 09:39:34 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-345e2ac6-b1ab-4a59-bb4b-46240110bc78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599388876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.599388876 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.841738042 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 470919814 ps |
| CPU time | 9.59 seconds |
| Started | Jan 21 09:39:47 PM PST 24 |
| Finished | Jan 21 09:39:59 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-9643d861-6f60-49a6-a85f-d33bbbc300f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841738042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.841738042 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1706457915 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 30269043449 ps |
| CPU time | 92.45 seconds |
| Started | Jan 21 09:39:47 PM PST 24 |
| Finished | Jan 21 09:41:21 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-a91872bd-e39b-42d2-9b70-9d4f33c95da0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1706457915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1706457915 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3046412604 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1814663546 ps |
| CPU time | 7.67 seconds |
| Started | Jan 21 09:39:52 PM PST 24 |
| Finished | Jan 21 09:40:02 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-92be35ea-05f7-4e29-9956-191bda5efb99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3046412604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3046412604 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.1576678695 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 21004896 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 09:39:46 PM PST 24 |
| Finished | Jan 21 09:39:50 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-2f082218-6543-4c3c-bb25-347bc31f131e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1576678695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1576678695 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2333473250 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1776022818 ps |
| CPU time | 8.03 seconds |
| Started | Jan 21 10:02:42 PM PST 24 |
| Finished | Jan 21 10:02:55 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-8e16a2b4-9b91-49e7-bcdb-450a707833bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2333473250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2333473250 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3671027473 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 39798352481 ps |
| CPU time | 131.87 seconds |
| Started | Jan 21 09:39:39 PM PST 24 |
| Finished | Jan 21 09:41:54 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-a73e1488-cf5c-4d11-aefa-e4fdf5ad4a8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671027473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3671027473 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3953270522 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 9541766573 ps |
| CPU time | 68.86 seconds |
| Started | Jan 21 09:39:38 PM PST 24 |
| Finished | Jan 21 09:40:49 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-ad44e02a-04dc-4e2b-8344-b09c37a352fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3953270522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3953270522 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3352139769 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 56111595 ps |
| CPU time | 7.5 seconds |
| Started | Jan 21 09:39:40 PM PST 24 |
| Finished | Jan 21 09:39:50 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-1e95f637-187f-4a8a-b20e-18ca5715aea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352139769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3352139769 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2892732102 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 134685143 ps |
| CPU time | 5.65 seconds |
| Started | Jan 21 09:39:50 PM PST 24 |
| Finished | Jan 21 09:39:58 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-b8fcc15e-e07e-4ddf-8db4-fcb5932b8097 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2892732102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2892732102 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1993776458 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 28942010 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 09:39:24 PM PST 24 |
| Finished | Jan 21 09:39:32 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-fc05be75-7e8b-4816-ab0f-68cb7e472130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1993776458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1993776458 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3919028708 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6256557026 ps |
| CPU time | 9.55 seconds |
| Started | Jan 21 09:39:24 PM PST 24 |
| Finished | Jan 21 09:39:39 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-0fd41cba-07ff-4f88-bfa9-a29ecd5f5516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919028708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3919028708 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3580963693 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2360358119 ps |
| CPU time | 12.62 seconds |
| Started | Jan 21 09:39:24 PM PST 24 |
| Finished | Jan 21 09:39:42 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-44f5249b-b499-4f4b-9031-a81811f8a07f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3580963693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3580963693 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1631608420 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13001554 ps |
| CPU time | 1.22 seconds |
| Started | Jan 21 09:39:24 PM PST 24 |
| Finished | Jan 21 09:39:31 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-80d6c72f-522a-4edc-a663-6d1c99a78984 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631608420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1631608420 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3497692981 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 7442530057 ps |
| CPU time | 70.54 seconds |
| Started | Jan 21 09:39:57 PM PST 24 |
| Finished | Jan 21 09:41:12 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-419efea5-7183-4938-b57c-d72e8524ae51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497692981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3497692981 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1106573706 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4508325359 ps |
| CPU time | 58.45 seconds |
| Started | Jan 21 09:39:53 PM PST 24 |
| Finished | Jan 21 09:40:54 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-781d2816-a288-46dd-a145-a5d6db749205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1106573706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1106573706 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.406056831 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 425549633 ps |
| CPU time | 30.88 seconds |
| Started | Jan 21 11:30:01 PM PST 24 |
| Finished | Jan 21 11:30:38 PM PST 24 |
| Peak memory | 203972 kb |
| Host | smart-94603f2e-ce3b-46ff-a2ad-585f0ba58a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406056831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.406056831 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1968960610 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 652617093 ps |
| CPU time | 34.09 seconds |
| Started | Jan 21 09:39:53 PM PST 24 |
| Finished | Jan 21 09:40:29 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-da8556bc-e7de-402f-bb94-0456a67811de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1968960610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1968960610 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3823485405 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 10520578 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 09:39:46 PM PST 24 |
| Finished | Jan 21 09:39:49 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-990f04c5-bf71-4a11-a8c5-036248615ea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3823485405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3823485405 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2023354543 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1636089453 ps |
| CPU time | 22.54 seconds |
| Started | Jan 21 09:43:47 PM PST 24 |
| Finished | Jan 21 09:44:11 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-7e934fd8-bc41-47e7-bfec-583eb534f6d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2023354543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2023354543 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3054408113 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 31597648718 ps |
| CPU time | 241.75 seconds |
| Started | Jan 21 09:43:44 PM PST 24 |
| Finished | Jan 21 09:47:47 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-591c7511-642b-4647-9c1e-832444e9392f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3054408113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.3054408113 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.106782324 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 394626597 ps |
| CPU time | 4.71 seconds |
| Started | Jan 21 09:58:27 PM PST 24 |
| Finished | Jan 21 09:58:34 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-167196f5-e044-4140-b279-5ba148046a55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=106782324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.106782324 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.3073985829 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1202279061 ps |
| CPU time | 11.22 seconds |
| Started | Jan 21 09:43:44 PM PST 24 |
| Finished | Jan 21 09:43:56 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-2fa2d4c0-20d0-4501-bb76-f0f327d14ed9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3073985829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3073985829 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.464468263 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 383201907 ps |
| CPU time | 4.47 seconds |
| Started | Jan 21 09:43:41 PM PST 24 |
| Finished | Jan 21 09:43:48 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-1931ec7a-4629-4d4e-bc6c-ae978edce6b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464468263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.464468263 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1959135526 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 18695211274 ps |
| CPU time | 80.61 seconds |
| Started | Jan 21 09:43:40 PM PST 24 |
| Finished | Jan 21 09:45:04 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-257286b7-ac6d-4f05-8720-a78be1bb19a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959135526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1959135526 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1332512020 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 42236354636 ps |
| CPU time | 99.28 seconds |
| Started | Jan 21 09:43:40 PM PST 24 |
| Finished | Jan 21 09:45:22 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-8aace26b-dd65-488f-bd7c-d8ca645094ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1332512020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1332512020 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1403022238 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 64226616 ps |
| CPU time | 5.28 seconds |
| Started | Jan 21 09:43:40 PM PST 24 |
| Finished | Jan 21 09:43:48 PM PST 24 |
| Peak memory | 201704 kb |
| Host | smart-655e82ba-0c59-4baa-bbf8-a2e2d79b7e0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403022238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1403022238 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3183618327 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1126551630 ps |
| CPU time | 13.61 seconds |
| Started | Jan 21 09:43:45 PM PST 24 |
| Finished | Jan 21 09:43:59 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-d9d92eac-f83b-4e48-9258-2fed03c0ab32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3183618327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3183618327 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.3066567638 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 14452460 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 09:43:29 PM PST 24 |
| Finished | Jan 21 09:43:35 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-3ff7e0f9-254c-4ec9-9b3b-52c3e98c72a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3066567638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3066567638 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3003363566 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5791022320 ps |
| CPU time | 7.13 seconds |
| Started | Jan 21 09:43:28 PM PST 24 |
| Finished | Jan 21 09:43:41 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-9fb6a660-c571-4d2b-8d8b-6512b5a14bb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003363566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3003363566 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.600714051 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1651858363 ps |
| CPU time | 6.28 seconds |
| Started | Jan 21 09:43:42 PM PST 24 |
| Finished | Jan 21 09:43:50 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-90aa451c-dd75-43f7-9672-c0176e302d33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=600714051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.600714051 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3000318653 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 27207962 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 09:43:28 PM PST 24 |
| Finished | Jan 21 09:43:35 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-2976b22c-286d-4d49-808e-5f23c8165a5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000318653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3000318653 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1424977701 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 385288418 ps |
| CPU time | 43.11 seconds |
| Started | Jan 21 09:43:42 PM PST 24 |
| Finished | Jan 21 09:44:27 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-0a532d02-7213-4959-8386-08c0914bc6eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1424977701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1424977701 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2028393586 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 25992253997 ps |
| CPU time | 92.56 seconds |
| Started | Jan 21 09:43:46 PM PST 24 |
| Finished | Jan 21 09:45:20 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-79fb196f-85a1-4b5b-ae5c-db96b618c714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028393586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2028393586 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.791167779 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 178983705 ps |
| CPU time | 9.31 seconds |
| Started | Jan 21 10:06:45 PM PST 24 |
| Finished | Jan 21 10:07:11 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-41df1ac6-4d88-4ee8-852e-7d9770c7e10e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791167779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.791167779 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2879466401 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 294209318 ps |
| CPU time | 42.5 seconds |
| Started | Jan 21 09:43:43 PM PST 24 |
| Finished | Jan 21 09:44:27 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-4c1cb177-faae-47e3-9ff2-59288e3fcf90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879466401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2879466401 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1102828213 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 112383971 ps |
| CPU time | 9.01 seconds |
| Started | Jan 21 09:43:43 PM PST 24 |
| Finished | Jan 21 09:43:54 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-71ae89bb-8d5b-47a0-8418-54c04ef236a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102828213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1102828213 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.4065322208 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2339336518 ps |
| CPU time | 18.69 seconds |
| Started | Jan 21 09:43:59 PM PST 24 |
| Finished | Jan 21 09:44:20 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-90ffe552-ba98-406a-8df0-5d60669fadf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4065322208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4065322208 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.885780308 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 165293993 ps |
| CPU time | 2.15 seconds |
| Started | Jan 21 09:44:05 PM PST 24 |
| Finished | Jan 21 09:44:13 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-1095bfed-be2b-41e8-83b9-bf2cfd4cf464 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=885780308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.885780308 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1687987825 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 295281683 ps |
| CPU time | 5.99 seconds |
| Started | Jan 21 09:44:11 PM PST 24 |
| Finished | Jan 21 09:44:23 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-06182d6c-ed5c-4628-a1d9-1955bb7fb2d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1687987825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1687987825 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.2246177834 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 561272489 ps |
| CPU time | 8.31 seconds |
| Started | Jan 21 09:44:01 PM PST 24 |
| Finished | Jan 21 09:44:15 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-630ea7a5-6c51-49ef-9712-0894d3b53fc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2246177834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2246177834 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2351260236 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 27003573286 ps |
| CPU time | 41.55 seconds |
| Started | Jan 21 09:43:59 PM PST 24 |
| Finished | Jan 21 09:44:43 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-c18ca536-e199-4baa-8867-4a6cc8a121da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351260236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2351260236 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1765078842 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 97105817 ps |
| CPU time | 6.73 seconds |
| Started | Jan 21 09:43:57 PM PST 24 |
| Finished | Jan 21 09:44:06 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-214f29a0-6875-4e7f-b831-1b326549bd74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765078842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1765078842 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2840252852 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1223003271 ps |
| CPU time | 10.67 seconds |
| Started | Jan 21 09:43:58 PM PST 24 |
| Finished | Jan 21 09:44:11 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-0c3400c5-4048-4e3b-b7d8-26b540b20e41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840252852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2840252852 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.52780651 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 35161556 ps |
| CPU time | 1.29 seconds |
| Started | Jan 21 09:43:51 PM PST 24 |
| Finished | Jan 21 09:43:53 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-41a5154d-4aa4-4958-9e3f-5bc383d3a861 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52780651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.52780651 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.773155919 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4006851529 ps |
| CPU time | 11.98 seconds |
| Started | Jan 21 09:44:00 PM PST 24 |
| Finished | Jan 21 09:44:14 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-dc99789f-602f-46f3-8f7e-add96614e6d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=773155919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.773155919 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.360575583 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1773522964 ps |
| CPU time | 10.16 seconds |
| Started | Jan 21 09:43:59 PM PST 24 |
| Finished | Jan 21 09:44:11 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-53f33b2b-34cf-47fc-bd88-ca9ebaedcf03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=360575583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.360575583 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1752965910 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 10076355 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 09:43:53 PM PST 24 |
| Finished | Jan 21 09:43:55 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-d2ca63af-3bbe-4711-bafb-8fa06eab6dad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752965910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1752965910 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1654498396 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4677556550 ps |
| CPU time | 72.23 seconds |
| Started | Jan 21 09:44:05 PM PST 24 |
| Finished | Jan 21 09:45:23 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-565c0c61-b02a-4b10-b5aa-8ca9558785c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1654498396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1654498396 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1569487997 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 331789953 ps |
| CPU time | 18.72 seconds |
| Started | Jan 21 09:44:15 PM PST 24 |
| Finished | Jan 21 09:44:37 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-e88fa92a-6409-4d85-a9fe-1cb4b3d608bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569487997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1569487997 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1868391858 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1865585713 ps |
| CPU time | 127.62 seconds |
| Started | Jan 21 09:44:22 PM PST 24 |
| Finished | Jan 21 09:46:32 PM PST 24 |
| Peak memory | 206556 kb |
| Host | smart-a04aa28d-c41c-4074-a77a-867f62caeee6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868391858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1868391858 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2685755169 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 512871653 ps |
| CPU time | 32.21 seconds |
| Started | Jan 21 09:44:17 PM PST 24 |
| Finished | Jan 21 09:44:52 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-9e2f0d09-185e-4143-9d48-7cf380dde74c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2685755169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2685755169 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2512931392 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 65214921 ps |
| CPU time | 5.04 seconds |
| Started | Jan 21 09:44:08 PM PST 24 |
| Finished | Jan 21 09:44:19 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-e41094ff-27a3-48c1-aa6c-3f0b9840ce40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2512931392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2512931392 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2424468625 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1569933689 ps |
| CPU time | 13.21 seconds |
| Started | Jan 21 09:44:26 PM PST 24 |
| Finished | Jan 21 09:44:41 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-f42428e5-bb29-45bf-b132-7e5a7fe9bc1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2424468625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2424468625 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3394689870 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 191503829425 ps |
| CPU time | 285.68 seconds |
| Started | Jan 21 09:44:30 PM PST 24 |
| Finished | Jan 21 09:49:20 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-bc212b68-ddfd-45b1-9d5b-34b6878b1490 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3394689870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.3394689870 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4281088188 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 166947242 ps |
| CPU time | 5.69 seconds |
| Started | Jan 21 10:14:09 PM PST 24 |
| Finished | Jan 21 10:14:19 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-4ac4123e-3122-4b2f-8a68-f6b61f392ad4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4281088188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4281088188 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1625394345 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 23182556 ps |
| CPU time | 1.73 seconds |
| Started | Jan 21 09:55:51 PM PST 24 |
| Finished | Jan 21 09:55:58 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-40a19cbd-6b5b-4346-a204-c7da90e03506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1625394345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1625394345 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3602392822 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 34737839 ps |
| CPU time | 2.71 seconds |
| Started | Jan 21 09:44:27 PM PST 24 |
| Finished | Jan 21 09:44:31 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-fc7edbbd-740b-46a2-91f6-3f9dc613b7a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3602392822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3602392822 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.925936429 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 55362799841 ps |
| CPU time | 143.93 seconds |
| Started | Jan 21 09:44:26 PM PST 24 |
| Finished | Jan 21 09:46:51 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-912bf688-7d40-43c9-8cb1-6fbf102b8258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=925936429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.925936429 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2184062747 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 9292910242 ps |
| CPU time | 59.55 seconds |
| Started | Jan 21 09:44:27 PM PST 24 |
| Finished | Jan 21 09:45:31 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-799a5c42-e396-4b10-b419-50e4add64e17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2184062747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2184062747 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2799919927 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 219790931 ps |
| CPU time | 5.3 seconds |
| Started | Jan 21 09:44:29 PM PST 24 |
| Finished | Jan 21 09:44:38 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-b5f8af0f-185c-4281-8603-69096b37abe7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799919927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2799919927 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.1985245476 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 760812287 ps |
| CPU time | 5.04 seconds |
| Started | Jan 21 10:57:18 PM PST 24 |
| Finished | Jan 21 10:57:24 PM PST 24 |
| Peak memory | 201724 kb |
| Host | smart-3389052a-1848-4918-aaff-d84c5ab335e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1985245476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1985245476 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1822296019 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 315384329 ps |
| CPU time | 1.8 seconds |
| Started | Jan 21 09:44:17 PM PST 24 |
| Finished | Jan 21 09:44:22 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-fdeb1dac-55d7-4c8d-a68b-b2813ca8f915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822296019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1822296019 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.233598843 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3802655750 ps |
| CPU time | 14.22 seconds |
| Started | Jan 21 09:55:39 PM PST 24 |
| Finished | Jan 21 09:56:01 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-05f430c5-95ca-45b9-bfce-c6b78347866f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=233598843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.233598843 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1588917753 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 14061906624 ps |
| CPU time | 11.17 seconds |
| Started | Jan 21 09:44:32 PM PST 24 |
| Finished | Jan 21 09:44:46 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-a5598c3c-975d-4341-baa5-16287e53bcd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1588917753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1588917753 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.341167077 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 9806082 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 09:44:23 PM PST 24 |
| Finished | Jan 21 09:44:26 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-839ab03d-9b0f-438d-b3ee-c66788b12b5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341167077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.341167077 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.4085713541 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1701801027 ps |
| CPU time | 21.65 seconds |
| Started | Jan 21 09:44:33 PM PST 24 |
| Finished | Jan 21 09:44:58 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-aa8a0b80-5bca-46b3-adb8-adcad0c14021 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4085713541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.4085713541 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.191769225 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 7660462052 ps |
| CPU time | 48.05 seconds |
| Started | Jan 21 09:58:34 PM PST 24 |
| Finished | Jan 21 09:59:25 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-94bb813b-e777-4c15-8570-96eb62dd8f4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=191769225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.191769225 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2620702753 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 287794035 ps |
| CPU time | 37.98 seconds |
| Started | Jan 21 09:44:34 PM PST 24 |
| Finished | Jan 21 09:45:16 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-e1920a0a-f189-4b12-a619-7a7e638a7617 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2620702753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2620702753 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.4221840123 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7128099805 ps |
| CPU time | 132.48 seconds |
| Started | Jan 21 09:44:36 PM PST 24 |
| Finished | Jan 21 09:46:51 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-f17fd694-f2f9-4cb3-ae0f-b715dbd2b69f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221840123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.4221840123 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1801352453 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 38469590 ps |
| CPU time | 3.88 seconds |
| Started | Jan 21 09:44:31 PM PST 24 |
| Finished | Jan 21 09:44:38 PM PST 24 |
| Peak memory | 201712 kb |
| Host | smart-38508719-f425-4d95-b1c1-47475d6a2277 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801352453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1801352453 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1171523800 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 736539476 ps |
| CPU time | 9.71 seconds |
| Started | Jan 21 09:44:45 PM PST 24 |
| Finished | Jan 21 09:45:00 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-76b92193-5bc9-4ffe-a2fa-75c13c1537dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171523800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1171523800 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3475566513 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 14490409395 ps |
| CPU time | 89.88 seconds |
| Started | Jan 21 09:44:44 PM PST 24 |
| Finished | Jan 21 09:46:18 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-5e823a71-f5ec-4404-8c80-2c7c8186b659 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3475566513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3475566513 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1171347544 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 73521474 ps |
| CPU time | 4.81 seconds |
| Started | Jan 21 09:44:55 PM PST 24 |
| Finished | Jan 21 09:45:02 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-716fee2c-03fe-4fd8-9918-c328803ec42f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171347544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1171347544 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3060042898 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2423290671 ps |
| CPU time | 8.84 seconds |
| Started | Jan 21 09:44:45 PM PST 24 |
| Finished | Jan 21 09:44:58 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-1ae54736-1ad1-44d3-a998-16f92cbaf793 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3060042898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3060042898 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.4276881344 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 645297950 ps |
| CPU time | 8.19 seconds |
| Started | Jan 21 09:44:36 PM PST 24 |
| Finished | Jan 21 09:44:47 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-bc59ceee-9524-42da-90df-0c5783080d0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4276881344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.4276881344 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3001268495 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 30534971692 ps |
| CPU time | 116.79 seconds |
| Started | Jan 21 10:29:02 PM PST 24 |
| Finished | Jan 21 10:31:12 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-6761d19a-e1d7-4455-bdbb-505cf0f91d9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001268495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3001268495 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3350136614 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3439439872 ps |
| CPU time | 13.76 seconds |
| Started | Jan 21 10:15:48 PM PST 24 |
| Finished | Jan 21 10:16:08 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-43b7eb44-7bfd-4190-a571-a54dba930953 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3350136614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3350136614 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2854060752 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 32327336 ps |
| CPU time | 5.26 seconds |
| Started | Jan 21 09:44:37 PM PST 24 |
| Finished | Jan 21 09:44:45 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-993cef09-89b1-4690-aee5-cc9b40d1ae19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854060752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2854060752 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2972267828 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 115846127 ps |
| CPU time | 4.97 seconds |
| Started | Jan 21 09:44:45 PM PST 24 |
| Finished | Jan 21 09:44:55 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-3762ec97-1de7-44c7-8045-2dd61e4c6015 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2972267828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2972267828 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1083796853 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 40403086 ps |
| CPU time | 1.42 seconds |
| Started | Jan 21 09:44:37 PM PST 24 |
| Finished | Jan 21 09:44:41 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-9b000de3-c085-429a-b4a5-ac5f678243f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1083796853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1083796853 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3042334203 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12294859332 ps |
| CPU time | 11.98 seconds |
| Started | Jan 21 09:44:35 PM PST 24 |
| Finished | Jan 21 09:44:50 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-16f67185-c0a9-4d82-9d5f-d87777701443 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042334203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3042334203 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.583277594 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 801415336 ps |
| CPU time | 6.08 seconds |
| Started | Jan 21 09:44:36 PM PST 24 |
| Finished | Jan 21 09:44:45 PM PST 24 |
| Peak memory | 201720 kb |
| Host | smart-17f2bc4c-c3e2-4d69-a59b-95efcdedbb32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=583277594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.583277594 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3440729756 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8528990 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 09:44:37 PM PST 24 |
| Finished | Jan 21 09:44:40 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-211b4e0b-2fd4-4b5f-aaac-0e7d5ee743e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440729756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3440729756 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.491885110 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 177824392 ps |
| CPU time | 29.92 seconds |
| Started | Jan 21 09:44:52 PM PST 24 |
| Finished | Jan 21 09:45:26 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-ab2d0816-4c6d-4eb0-8928-195ebc116ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=491885110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.491885110 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2214203215 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 87000863 ps |
| CPU time | 6 seconds |
| Started | Jan 21 09:45:04 PM PST 24 |
| Finished | Jan 21 09:45:17 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-c8a43d82-d625-42a2-89a9-ce424e02985b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2214203215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2214203215 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1091555355 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 391414505 ps |
| CPU time | 59.04 seconds |
| Started | Jan 21 09:44:51 PM PST 24 |
| Finished | Jan 21 09:45:55 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-292f8af3-0c97-49a1-b429-3a3e872fe133 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1091555355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1091555355 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.365275900 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6056334370 ps |
| CPU time | 54.82 seconds |
| Started | Jan 21 09:45:01 PM PST 24 |
| Finished | Jan 21 09:45:57 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-60ae2d64-915e-4de2-9ae2-3b1482dbac6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=365275900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.365275900 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.596838047 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 50654424 ps |
| CPU time | 6.2 seconds |
| Started | Jan 21 09:44:44 PM PST 24 |
| Finished | Jan 21 09:44:55 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-01b9fa1b-cd93-476d-af7a-338b3229c889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=596838047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.596838047 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1905303121 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1623532033 ps |
| CPU time | 21.93 seconds |
| Started | Jan 21 09:45:12 PM PST 24 |
| Finished | Jan 21 09:45:40 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-a338ff12-c27c-446e-88ae-10f477aaecb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1905303121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1905303121 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1159688180 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 34985260962 ps |
| CPU time | 207.16 seconds |
| Started | Jan 21 09:45:13 PM PST 24 |
| Finished | Jan 21 09:48:47 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-ee00760c-9193-4e85-88fe-ea59b67bd837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1159688180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1159688180 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4004228532 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 596560007 ps |
| CPU time | 10.28 seconds |
| Started | Jan 21 09:45:11 PM PST 24 |
| Finished | Jan 21 09:45:25 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-73a63d13-2f53-4361-ba28-7fd99582242d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4004228532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4004228532 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.1783769459 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 123204809 ps |
| CPU time | 10.86 seconds |
| Started | Jan 21 09:45:11 PM PST 24 |
| Finished | Jan 21 09:45:25 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-c0927b01-b155-4b14-aa77-7a881fd8a4bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1783769459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1783769459 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1897672415 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 317313240 ps |
| CPU time | 10.79 seconds |
| Started | Jan 21 09:45:03 PM PST 24 |
| Finished | Jan 21 09:45:16 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-53aabbf4-2dad-49bf-96a6-afb67e1e4ab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897672415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1897672415 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.4060027077 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 13907506425 ps |
| CPU time | 66.6 seconds |
| Started | Jan 21 09:45:03 PM PST 24 |
| Finished | Jan 21 09:46:12 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-c53deab8-06c8-45ae-a518-e033af6d0341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060027077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.4060027077 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.637035791 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 44040157392 ps |
| CPU time | 83.48 seconds |
| Started | Jan 21 09:45:01 PM PST 24 |
| Finished | Jan 21 09:46:27 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-ebe1981f-73a4-4b93-92e7-d3c6dcccb606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=637035791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.637035791 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3396260869 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 107834491 ps |
| CPU time | 7.08 seconds |
| Started | Jan 21 09:45:04 PM PST 24 |
| Finished | Jan 21 09:45:18 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-7c0047ce-4ad0-46b1-bb8d-7f138c497c67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396260869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3396260869 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.631405192 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 33803763 ps |
| CPU time | 1.27 seconds |
| Started | Jan 21 09:45:08 PM PST 24 |
| Finished | Jan 21 09:45:15 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-13a82ad8-993c-46b6-a9a2-f045eaa1f0ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=631405192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.631405192 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.1382579899 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 82284410 ps |
| CPU time | 1.41 seconds |
| Started | Jan 21 09:45:01 PM PST 24 |
| Finished | Jan 21 09:45:04 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-59c86f15-dd82-4130-a61c-b53dc659d6e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382579899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1382579899 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2517137914 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1315442896 ps |
| CPU time | 5.57 seconds |
| Started | Jan 21 09:45:02 PM PST 24 |
| Finished | Jan 21 09:45:10 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-3ef6a215-4ae3-422c-ada8-f51044bc3fef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517137914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2517137914 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.857026698 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 765661415 ps |
| CPU time | 6.63 seconds |
| Started | Jan 21 09:45:05 PM PST 24 |
| Finished | Jan 21 09:45:19 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-167c7482-067b-42aa-98a5-ecdbbfa70004 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=857026698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.857026698 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2160371535 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 12517753 ps |
| CPU time | 1.22 seconds |
| Started | Jan 21 09:45:04 PM PST 24 |
| Finished | Jan 21 09:45:12 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-76ad9c91-4427-4586-8fd8-16b4ff33fe58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160371535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2160371535 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.4213110318 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1497703295 ps |
| CPU time | 18.85 seconds |
| Started | Jan 21 09:45:13 PM PST 24 |
| Finished | Jan 21 09:45:38 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-5313e4bf-c968-4fad-ae9f-f949f1782cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213110318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4213110318 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.360320944 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 7932893500 ps |
| CPU time | 30.49 seconds |
| Started | Jan 21 09:45:12 PM PST 24 |
| Finished | Jan 21 09:45:47 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-53f274a0-82a3-46d6-8935-dbdf11d5484b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360320944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.360320944 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3129779569 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 7396653 ps |
| CPU time | 5.41 seconds |
| Started | Jan 21 09:45:09 PM PST 24 |
| Finished | Jan 21 09:45:20 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-7855bedb-cbc2-4262-ba7c-39df3f0dfc1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3129779569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3129779569 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1668361787 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3904570332 ps |
| CPU time | 50.73 seconds |
| Started | Jan 21 10:30:22 PM PST 24 |
| Finished | Jan 21 10:31:27 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-e1b22e87-ddce-49d2-bcad-2f28c0301c61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668361787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1668361787 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2374627175 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 190352329 ps |
| CPU time | 5.4 seconds |
| Started | Jan 21 09:45:10 PM PST 24 |
| Finished | Jan 21 09:45:20 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-46f77d0b-c490-431f-9d5b-09460773ec90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2374627175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2374627175 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.788559555 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 54994380 ps |
| CPU time | 7.72 seconds |
| Started | Jan 21 09:45:26 PM PST 24 |
| Finished | Jan 21 09:45:35 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-7cea58bd-8639-4dfc-954d-4e305998b262 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788559555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.788559555 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2478020139 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 13524539282 ps |
| CPU time | 99.19 seconds |
| Started | Jan 21 09:45:27 PM PST 24 |
| Finished | Jan 21 09:47:08 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-9e85835d-891c-4609-a036-d38780718d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2478020139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2478020139 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4218727406 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 531841787 ps |
| CPU time | 8.25 seconds |
| Started | Jan 21 09:45:43 PM PST 24 |
| Finished | Jan 21 09:45:57 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-f2de4ad2-e2ee-4ba9-a1e9-f6db4d09bab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4218727406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4218727406 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.3744407345 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 929979731 ps |
| CPU time | 8.52 seconds |
| Started | Jan 21 09:45:26 PM PST 24 |
| Finished | Jan 21 09:45:36 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-61ab8b5e-3bd2-4197-86f3-e5765b8eb6a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3744407345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3744407345 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2999125528 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 12241537 ps |
| CPU time | 1.69 seconds |
| Started | Jan 21 09:45:25 PM PST 24 |
| Finished | Jan 21 09:45:29 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-447c92ad-d982-45b0-aec5-9a6275750f23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2999125528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2999125528 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.560676534 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 63850017025 ps |
| CPU time | 87.09 seconds |
| Started | Jan 21 09:45:26 PM PST 24 |
| Finished | Jan 21 09:46:55 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-57ed2be8-f586-4210-8cb3-6e5dfb46777e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=560676534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.560676534 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.605217652 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 11685896 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 09:45:32 PM PST 24 |
| Finished | Jan 21 09:45:34 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-9a0ad0c0-b3a0-45aa-80d9-34af2f732b79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605217652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.605217652 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3585259001 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1332181753 ps |
| CPU time | 9.9 seconds |
| Started | Jan 21 09:53:47 PM PST 24 |
| Finished | Jan 21 09:53:59 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-9f35572b-a134-4bb2-a7a9-aa7b6719c492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3585259001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3585259001 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.192287639 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 8118394 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 09:45:20 PM PST 24 |
| Finished | Jan 21 09:45:25 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-b431959f-6f81-496d-9121-97dde96dc86a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=192287639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.192287639 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3154819467 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2865672875 ps |
| CPU time | 12.51 seconds |
| Started | Jan 21 09:45:19 PM PST 24 |
| Finished | Jan 21 09:45:36 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-3e383488-698e-4440-befd-0397eaae6189 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154819467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3154819467 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1137731396 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 593419317 ps |
| CPU time | 5.17 seconds |
| Started | Jan 21 09:45:20 PM PST 24 |
| Finished | Jan 21 09:45:29 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-d49b12c1-96c7-4cbc-ae9c-7c6168d0d0f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1137731396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1137731396 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.314361452 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 22838860 ps |
| CPU time | 1.23 seconds |
| Started | Jan 21 09:45:16 PM PST 24 |
| Finished | Jan 21 09:45:24 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-79430cd0-95ac-4eaa-9200-0bf09bd393ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314361452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.314361452 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1248935717 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4317487758 ps |
| CPU time | 44.92 seconds |
| Started | Jan 21 09:45:40 PM PST 24 |
| Finished | Jan 21 09:46:29 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-94df358d-5d23-4e37-8e65-07b4dcafa829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1248935717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1248935717 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2721487785 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3327535040 ps |
| CPU time | 31.06 seconds |
| Started | Jan 21 09:57:19 PM PST 24 |
| Finished | Jan 21 09:57:53 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-d445c932-3eef-4210-8ab6-bb24f133393a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2721487785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2721487785 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3657673257 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1348564529 ps |
| CPU time | 180.89 seconds |
| Started | Jan 21 09:45:37 PM PST 24 |
| Finished | Jan 21 09:48:41 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-d6ae01c9-a918-4381-82f6-f1cb000e06b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3657673257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3657673257 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.104322674 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 288840112 ps |
| CPU time | 29.42 seconds |
| Started | Jan 21 09:45:36 PM PST 24 |
| Finished | Jan 21 09:46:09 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-57deb17c-d6a3-4fcc-8f9b-306413e28c0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=104322674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.104322674 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3189264650 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 65579507 ps |
| CPU time | 6.85 seconds |
| Started | Jan 21 09:56:25 PM PST 24 |
| Finished | Jan 21 09:56:36 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-54df96b8-bcf9-47a1-b71c-f837647e7727 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3189264650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3189264650 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1835403824 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 57247936 ps |
| CPU time | 7 seconds |
| Started | Jan 21 09:45:45 PM PST 24 |
| Finished | Jan 21 09:46:00 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-1d3a9c32-1d6c-445b-b566-d87d6dbe9bc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1835403824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1835403824 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3019268385 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 63318822334 ps |
| CPU time | 280.39 seconds |
| Started | Jan 21 09:54:57 PM PST 24 |
| Finished | Jan 21 09:59:39 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-a9a8b51a-aba4-4b48-a055-d386a949cb2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3019268385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3019268385 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1840518178 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2105569203 ps |
| CPU time | 6.37 seconds |
| Started | Jan 21 09:45:49 PM PST 24 |
| Finished | Jan 21 09:46:08 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-f54888ec-42d4-462d-90e6-64810e8b15f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840518178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1840518178 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.553045097 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 58932419 ps |
| CPU time | 7.25 seconds |
| Started | Jan 21 09:45:52 PM PST 24 |
| Finished | Jan 21 09:46:15 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-a02acd38-09a7-4b8c-a958-0a597f6faa08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=553045097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.553045097 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.893642641 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 213544334 ps |
| CPU time | 6.55 seconds |
| Started | Jan 21 09:45:40 PM PST 24 |
| Finished | Jan 21 09:45:51 PM PST 24 |
| Peak memory | 201744 kb |
| Host | smart-4cca1287-f51f-4973-874d-425f11f5829e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893642641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.893642641 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1142578960 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 18822479866 ps |
| CPU time | 73.32 seconds |
| Started | Jan 21 10:11:25 PM PST 24 |
| Finished | Jan 21 10:12:44 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-a4fd78a4-8a6f-4696-986f-c3653527f5a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142578960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1142578960 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.4101575763 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 12144778582 ps |
| CPU time | 95.21 seconds |
| Started | Jan 21 10:37:26 PM PST 24 |
| Finished | Jan 21 10:39:13 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-2674040c-1608-4901-9771-7c4a01185c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4101575763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4101575763 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2288166657 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 75761912 ps |
| CPU time | 8.71 seconds |
| Started | Jan 21 09:56:42 PM PST 24 |
| Finished | Jan 21 09:56:55 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-4327f21c-70cd-4dca-a92b-086319d2b3e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288166657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2288166657 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2123925789 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 71017124 ps |
| CPU time | 5.99 seconds |
| Started | Jan 21 09:45:45 PM PST 24 |
| Finished | Jan 21 09:45:58 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-96a18d33-1c8b-4b14-95ef-f47ef42f4f88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123925789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2123925789 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1555913440 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 12094820 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 09:45:43 PM PST 24 |
| Finished | Jan 21 09:45:50 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-29b2bc67-b1cd-4e20-9f81-3f4c89eb23f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555913440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1555913440 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1046259643 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4555374181 ps |
| CPU time | 9.65 seconds |
| Started | Jan 21 09:45:36 PM PST 24 |
| Finished | Jan 21 09:45:49 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-75289d5c-2c13-4ac2-aad3-cc233b58bc65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046259643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1046259643 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.42275833 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1111134598 ps |
| CPU time | 7.58 seconds |
| Started | Jan 21 09:55:43 PM PST 24 |
| Finished | Jan 21 09:55:58 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-58fe3d5c-20d5-44b8-82ad-0efbe3334c59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=42275833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.42275833 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1117916776 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 19457607 ps |
| CPU time | 1.32 seconds |
| Started | Jan 21 09:45:40 PM PST 24 |
| Finished | Jan 21 09:45:46 PM PST 24 |
| Peak memory | 201716 kb |
| Host | smart-e8cf90aa-686f-491e-baa8-64f2c6ea3b5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117916776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1117916776 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3234233473 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 472813227 ps |
| CPU time | 30.36 seconds |
| Started | Jan 21 09:45:57 PM PST 24 |
| Finished | Jan 21 09:46:42 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-e2cfc3ac-ef9b-47cc-85a9-8a3e57f727df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3234233473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3234233473 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4077147294 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 178743041 ps |
| CPU time | 44.53 seconds |
| Started | Jan 21 09:45:49 PM PST 24 |
| Finished | Jan 21 09:46:48 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-3fa11738-3fc3-43f5-84f8-77d20999d352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4077147294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.4077147294 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1915790835 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 581711410 ps |
| CPU time | 50.09 seconds |
| Started | Jan 21 09:45:57 PM PST 24 |
| Finished | Jan 21 09:47:01 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-b5fd3db3-ed2d-4079-804a-d7f747cbb68d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915790835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1915790835 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.961015198 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1172506107 ps |
| CPU time | 8.04 seconds |
| Started | Jan 21 09:45:57 PM PST 24 |
| Finished | Jan 21 09:46:19 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-93b60676-709d-4fd6-ad57-6d93fd1d1ec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=961015198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.961015198 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2938121447 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 132489843 ps |
| CPU time | 12.94 seconds |
| Started | Jan 21 10:52:15 PM PST 24 |
| Finished | Jan 21 10:52:30 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-ad5ef6a1-289c-4dff-9296-8a650e2d754b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2938121447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2938121447 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2048708981 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 19124811108 ps |
| CPU time | 63.83 seconds |
| Started | Jan 21 09:46:05 PM PST 24 |
| Finished | Jan 21 09:47:22 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-ab94b3d6-af26-48da-9d9d-423e92d8d7f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2048708981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2048708981 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3901684698 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 189509971 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 09:46:06 PM PST 24 |
| Finished | Jan 21 09:46:22 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-e5a22a20-8cad-4307-9549-9e0b8604b637 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3901684698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3901684698 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2264284170 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 603602035 ps |
| CPU time | 8.44 seconds |
| Started | Jan 21 09:46:05 PM PST 24 |
| Finished | Jan 21 09:46:27 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-3007f2c6-6059-484c-8c4f-bf481f810fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2264284170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2264284170 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3406464380 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 269542122 ps |
| CPU time | 4.17 seconds |
| Started | Jan 21 09:45:57 PM PST 24 |
| Finished | Jan 21 09:46:15 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-7b7a5085-f302-48f7-9f45-46b865c86d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406464380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3406464380 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3334965720 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 127226948865 ps |
| CPU time | 144.14 seconds |
| Started | Jan 21 09:45:57 PM PST 24 |
| Finished | Jan 21 09:48:35 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-fb2ed234-dfc3-4869-b107-83e7132bf187 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334965720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3334965720 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2737007996 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 36253641561 ps |
| CPU time | 164.26 seconds |
| Started | Jan 21 10:10:21 PM PST 24 |
| Finished | Jan 21 10:13:09 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-bf8b6b17-61f5-44f0-9a3d-3cf43c59583c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2737007996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2737007996 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1384838957 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 604529166 ps |
| CPU time | 11.32 seconds |
| Started | Jan 21 09:45:58 PM PST 24 |
| Finished | Jan 21 09:46:23 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-02021037-da9f-4ddd-b98c-d65a4a7acdb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384838957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1384838957 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.3945490340 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 105495696 ps |
| CPU time | 5.7 seconds |
| Started | Jan 21 09:46:06 PM PST 24 |
| Finished | Jan 21 09:46:25 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-8e158ace-1e1d-4213-b4c0-9e3070a1cc3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3945490340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3945490340 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.2872591196 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 60403043 ps |
| CPU time | 1.61 seconds |
| Started | Jan 21 10:12:42 PM PST 24 |
| Finished | Jan 21 10:12:47 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-04f9af0e-38a6-4905-b772-c3587b56be2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872591196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2872591196 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1431791734 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1041717725 ps |
| CPU time | 6.05 seconds |
| Started | Jan 21 10:04:01 PM PST 24 |
| Finished | Jan 21 10:04:09 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-9abeef41-69f0-47e3-b260-1c670f9d3beb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431791734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1431791734 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1319992217 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2814117441 ps |
| CPU time | 6.4 seconds |
| Started | Jan 21 10:52:36 PM PST 24 |
| Finished | Jan 21 10:52:46 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-a0d982f3-846f-40c0-afa3-f1124d77651d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1319992217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1319992217 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2397885364 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 10602732 ps |
| CPU time | 1.29 seconds |
| Started | Jan 21 09:45:49 PM PST 24 |
| Finished | Jan 21 09:46:04 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-a2484b48-d665-4af7-ac2c-33730d75a47a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397885364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2397885364 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.4096248576 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 180795662 ps |
| CPU time | 22.86 seconds |
| Started | Jan 21 09:46:08 PM PST 24 |
| Finished | Jan 21 09:46:46 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-3902abaa-60d4-4803-ae0e-419df95ee764 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096248576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4096248576 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3238028138 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 7040571143 ps |
| CPU time | 49.4 seconds |
| Started | Jan 21 09:46:07 PM PST 24 |
| Finished | Jan 21 09:47:11 PM PST 24 |
| Peak memory | 201884 kb |
| Host | smart-6eac9c1a-2342-4eab-be83-6c2f5e5c1b74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3238028138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3238028138 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1313328474 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 825273407 ps |
| CPU time | 69.62 seconds |
| Started | Jan 21 09:46:06 PM PST 24 |
| Finished | Jan 21 09:47:30 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-0df5b6d3-1c5c-4463-917d-55a645bc3eda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1313328474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1313328474 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.264962561 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 271975737 ps |
| CPU time | 9.15 seconds |
| Started | Jan 21 09:46:07 PM PST 24 |
| Finished | Jan 21 09:46:30 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-7af6a629-93b9-4a73-8e1b-69eacb40a240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=264962561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.264962561 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2813621349 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 20779766 ps |
| CPU time | 2.42 seconds |
| Started | Jan 21 09:46:05 PM PST 24 |
| Finished | Jan 21 09:46:21 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-f5fffd69-07ea-4013-a7e4-14167f5757b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2813621349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2813621349 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2731838952 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 164903997 ps |
| CPU time | 5.59 seconds |
| Started | Jan 21 09:46:30 PM PST 24 |
| Finished | Jan 21 09:46:42 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-4334b75e-d213-403f-9246-777a098cb934 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2731838952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2731838952 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3466920839 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 227570602152 ps |
| CPU time | 189.35 seconds |
| Started | Jan 21 09:46:22 PM PST 24 |
| Finished | Jan 21 09:49:42 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-65a6539b-ad38-4421-8d9d-1fcf1a392501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3466920839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3466920839 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3175751478 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 26502649 ps |
| CPU time | 2.88 seconds |
| Started | Jan 21 09:46:18 PM PST 24 |
| Finished | Jan 21 09:46:33 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-0ccce349-c90b-42e3-bbe8-22f2fddaa487 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175751478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3175751478 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.4272950521 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 556063259 ps |
| CPU time | 7.06 seconds |
| Started | Jan 21 09:46:20 PM PST 24 |
| Finished | Jan 21 09:46:38 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-f5785e23-be46-4bf6-8f3c-347942154fb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272950521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4272950521 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2545929013 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 59039610 ps |
| CPU time | 1.3 seconds |
| Started | Jan 21 09:46:30 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-028d16e9-8079-44bb-a10e-0aa0978f042d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545929013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2545929013 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1909321179 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 6477632944 ps |
| CPU time | 11.35 seconds |
| Started | Jan 21 09:46:18 PM PST 24 |
| Finished | Jan 21 09:46:41 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-65bf5543-c339-4bfc-85db-4c4b5e6aa44f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909321179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1909321179 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1772573351 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 31168525979 ps |
| CPU time | 169.52 seconds |
| Started | Jan 21 09:46:19 PM PST 24 |
| Finished | Jan 21 09:49:20 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-dcbf1d37-3a96-4ba1-a4a0-acc2efffe4bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1772573351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1772573351 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3811759516 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 62505275 ps |
| CPU time | 7.68 seconds |
| Started | Jan 21 09:46:17 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-440931f6-1f90-40f8-9529-a5413de70354 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811759516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3811759516 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.3460941619 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 153250562 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 09:46:17 PM PST 24 |
| Finished | Jan 21 09:46:31 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-4d4399da-efa8-4aec-9410-ef2c5858a055 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3460941619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3460941619 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.3369321963 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 58965986 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 09:46:08 PM PST 24 |
| Finished | Jan 21 09:46:24 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-ceebcf22-3fe4-4077-a889-b76a74f1da8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3369321963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3369321963 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1100764744 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2486833493 ps |
| CPU time | 7.57 seconds |
| Started | Jan 21 09:46:17 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-2e36175f-14c6-48c9-ae6d-4d22ec6fc64a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100764744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1100764744 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2235987719 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1004986404 ps |
| CPU time | 7.46 seconds |
| Started | Jan 21 09:46:17 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-8b27390a-5990-4d25-b9b8-c1de8519a585 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2235987719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2235987719 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1053571884 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11734383 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 09:46:09 PM PST 24 |
| Finished | Jan 21 09:46:25 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-a0d9eda6-ecfc-484a-acba-0577d4f30946 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053571884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1053571884 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4171949198 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 8190706946 ps |
| CPU time | 95.6 seconds |
| Started | Jan 21 09:46:21 PM PST 24 |
| Finished | Jan 21 09:48:07 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-037c67cf-7b21-4e1b-ab43-c52d3dfc81f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4171949198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4171949198 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.68891070 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 7238215913 ps |
| CPU time | 56.65 seconds |
| Started | Jan 21 11:10:00 PM PST 24 |
| Finished | Jan 21 11:10:58 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-b35c4b57-d948-42c3-b22c-c8c2bb8db832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=68891070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.68891070 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.86916380 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5519938173 ps |
| CPU time | 140.59 seconds |
| Started | Jan 21 09:46:19 PM PST 24 |
| Finished | Jan 21 09:48:51 PM PST 24 |
| Peak memory | 206900 kb |
| Host | smart-9d9edfab-2719-4770-91a8-b3c44746a620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86916380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_ reset.86916380 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3907371086 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2294341041 ps |
| CPU time | 33.29 seconds |
| Started | Jan 21 09:46:21 PM PST 24 |
| Finished | Jan 21 09:47:05 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-6f8b8ef8-8650-42b9-aad5-aba068641f29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3907371086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3907371086 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1351471273 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 165917490 ps |
| CPU time | 3.59 seconds |
| Started | Jan 21 09:46:28 PM PST 24 |
| Finished | Jan 21 09:46:39 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-fd865186-4aee-444a-8c14-0bca3a124af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351471273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1351471273 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.833289530 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 394876380 ps |
| CPU time | 5.79 seconds |
| Started | Jan 21 09:46:41 PM PST 24 |
| Finished | Jan 21 09:46:52 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-4f79edef-957a-4f2e-8e15-ac77eb41a864 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833289530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.833289530 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3833065971 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 38243770816 ps |
| CPU time | 131.87 seconds |
| Started | Jan 21 09:46:36 PM PST 24 |
| Finished | Jan 21 09:48:54 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-c6ec6550-4407-46b5-a5da-ebff4aaa1473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3833065971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3833065971 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3333065921 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 54741443 ps |
| CPU time | 3.83 seconds |
| Started | Jan 21 09:46:38 PM PST 24 |
| Finished | Jan 21 09:46:48 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-5e075839-a446-4115-bdff-92fcd3ebada3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333065921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3333065921 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.3770788884 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 136184756 ps |
| CPU time | 4.68 seconds |
| Started | Jan 21 09:46:41 PM PST 24 |
| Finished | Jan 21 09:46:51 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-3940eb26-67b9-4929-89a4-0ba8754fd144 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770788884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3770788884 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2513251418 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 132703350 ps |
| CPU time | 3.11 seconds |
| Started | Jan 21 10:19:43 PM PST 24 |
| Finished | Jan 21 10:19:50 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-68359544-3380-4ae1-b263-360ff6994cd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2513251418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2513251418 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2821492496 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 34950458688 ps |
| CPU time | 96.31 seconds |
| Started | Jan 21 09:46:35 PM PST 24 |
| Finished | Jan 21 09:48:17 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-2341f6f4-2a1f-458d-a276-0e2336f27d01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821492496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2821492496 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1222728461 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 17880971092 ps |
| CPU time | 108.15 seconds |
| Started | Jan 21 09:56:41 PM PST 24 |
| Finished | Jan 21 09:58:34 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-289a3ca8-fce7-45c6-a3ea-2ea6bb2d5add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1222728461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1222728461 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2428481240 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 63090303 ps |
| CPU time | 4.86 seconds |
| Started | Jan 21 09:46:26 PM PST 24 |
| Finished | Jan 21 09:46:39 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-56788faf-b00c-496e-b587-93763742b4b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428481240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2428481240 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3768710406 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 17975577 ps |
| CPU time | 2.16 seconds |
| Started | Jan 21 09:46:38 PM PST 24 |
| Finished | Jan 21 09:46:46 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-3dda915d-c978-4b8f-a946-1878947f9a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3768710406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3768710406 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3075079496 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 77593369 ps |
| CPU time | 1.52 seconds |
| Started | Jan 21 09:46:28 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-0af38aa6-a48b-4a66-8136-313c824424a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075079496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3075079496 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2847643418 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1313109306 ps |
| CPU time | 5.87 seconds |
| Started | Jan 21 09:46:20 PM PST 24 |
| Finished | Jan 21 09:46:37 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-f56fa73a-835f-4469-ba57-f165e2f31cb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847643418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2847643418 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2517784136 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3388709698 ps |
| CPU time | 11.87 seconds |
| Started | Jan 21 09:46:30 PM PST 24 |
| Finished | Jan 21 09:46:48 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-6cc8e635-9a95-4338-93b7-73639a05f288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2517784136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2517784136 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2461836312 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 8537862 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 09:46:20 PM PST 24 |
| Finished | Jan 21 09:46:32 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-03369c1d-b186-4784-90d8-6e2d0c9daa67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461836312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2461836312 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3192738021 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 153124196 ps |
| CPU time | 17.98 seconds |
| Started | Jan 21 09:46:43 PM PST 24 |
| Finished | Jan 21 09:47:06 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-5d11f092-c23f-4148-ac59-9fb7350e1e22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3192738021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3192738021 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.522844250 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 33322331765 ps |
| CPU time | 90.76 seconds |
| Started | Jan 21 09:47:02 PM PST 24 |
| Finished | Jan 21 09:48:34 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-6d1d19c7-0559-491e-9e72-0845c50635a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=522844250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.522844250 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2702497984 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3073526268 ps |
| CPU time | 111.4 seconds |
| Started | Jan 21 10:41:22 PM PST 24 |
| Finished | Jan 21 10:43:15 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-1448c186-27d7-40cb-9707-204369fe7b1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702497984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2702497984 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1460866588 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3947892419 ps |
| CPU time | 73.78 seconds |
| Started | Jan 21 09:47:00 PM PST 24 |
| Finished | Jan 21 09:48:15 PM PST 24 |
| Peak memory | 205664 kb |
| Host | smart-c1037763-4ada-44dc-95be-2869e3f6bb2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460866588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1460866588 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3565419807 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 244183206 ps |
| CPU time | 4.61 seconds |
| Started | Jan 21 09:46:41 PM PST 24 |
| Finished | Jan 21 09:46:51 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-080894b3-0b76-47fd-96ff-44384f67d7a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3565419807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3565419807 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3684649493 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 147898124720 ps |
| CPU time | 263.53 seconds |
| Started | Jan 21 09:40:07 PM PST 24 |
| Finished | Jan 21 09:44:40 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-23a77d0b-3b62-47d0-bae1-28439d0bf4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3684649493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3684649493 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1882127578 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 237631559 ps |
| CPU time | 3.82 seconds |
| Started | Jan 21 10:09:38 PM PST 24 |
| Finished | Jan 21 10:09:45 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-59a4bc9e-5a50-4407-8305-7e1014120c53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1882127578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1882127578 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1294982100 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1576786666 ps |
| CPU time | 12.5 seconds |
| Started | Jan 21 09:40:13 PM PST 24 |
| Finished | Jan 21 09:40:36 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-d50a91fd-7103-4364-a1f0-affe1814b908 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1294982100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1294982100 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.4104335900 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 67546309 ps |
| CPU time | 7.08 seconds |
| Started | Jan 21 09:40:14 PM PST 24 |
| Finished | Jan 21 09:40:31 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-66e69838-0f5a-4d97-bd67-31755716e816 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104335900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4104335900 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2273550015 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 26272395646 ps |
| CPU time | 28.49 seconds |
| Started | Jan 21 09:40:07 PM PST 24 |
| Finished | Jan 21 09:40:45 PM PST 24 |
| Peak memory | 201884 kb |
| Host | smart-e272b890-56bf-4276-ae45-76abbb7dc226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273550015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2273550015 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3587421598 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 70685298499 ps |
| CPU time | 86.53 seconds |
| Started | Jan 21 09:40:06 PM PST 24 |
| Finished | Jan 21 09:41:43 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-e89321ee-52e1-4340-a6fa-b336bcfeadc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3587421598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3587421598 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3606009563 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 104564751 ps |
| CPU time | 4.45 seconds |
| Started | Jan 21 09:40:09 PM PST 24 |
| Finished | Jan 21 09:40:21 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-4d20880b-8327-4acc-889f-ecd90d1de0ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606009563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3606009563 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3188478045 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1387722831 ps |
| CPU time | 10.57 seconds |
| Started | Jan 21 09:40:08 PM PST 24 |
| Finished | Jan 21 09:40:27 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-c06d82ba-8101-41cc-a2c7-861e4c2b284f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3188478045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3188478045 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3199040545 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 209041305 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 10:32:59 PM PST 24 |
| Finished | Jan 21 10:33:05 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-59a08ab0-9b18-45a1-8dba-9e38e6a1f892 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3199040545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3199040545 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3450596807 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5256359043 ps |
| CPU time | 6 seconds |
| Started | Jan 21 09:40:00 PM PST 24 |
| Finished | Jan 21 09:40:11 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-9d0163d8-59ed-4bf4-8061-1330ce81275a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450596807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3450596807 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.291287567 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1628502798 ps |
| CPU time | 12.5 seconds |
| Started | Jan 21 09:40:06 PM PST 24 |
| Finished | Jan 21 09:40:29 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-68278c8a-9ca3-4208-8d36-ca8af67d6988 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=291287567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.291287567 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.399631375 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 31796301 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 09:40:03 PM PST 24 |
| Finished | Jan 21 09:40:13 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-61bf16de-2239-45a3-b738-acfa0785b4bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399631375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.399631375 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1278358464 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3093681760 ps |
| CPU time | 19.51 seconds |
| Started | Jan 21 09:40:12 PM PST 24 |
| Finished | Jan 21 09:40:41 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-7ae6dd29-8c8e-478a-b7b8-c6f1a6deaf0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1278358464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1278358464 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3020170601 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 15099769987 ps |
| CPU time | 64.94 seconds |
| Started | Jan 21 09:40:19 PM PST 24 |
| Finished | Jan 21 09:41:30 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-e89c7b2c-8ffd-4006-b59e-ae3a43037d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020170601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3020170601 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3210774756 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 422163400 ps |
| CPU time | 77.64 seconds |
| Started | Jan 21 09:40:13 PM PST 24 |
| Finished | Jan 21 09:41:41 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-30eddcc9-234f-48ae-a54e-1473f3329f87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3210774756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3210774756 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4026682621 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 207185613 ps |
| CPU time | 15.32 seconds |
| Started | Jan 21 10:55:54 PM PST 24 |
| Finished | Jan 21 10:56:11 PM PST 24 |
| Peak memory | 202916 kb |
| Host | smart-9fbc40be-8707-4be1-9d72-2876741a84aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4026682621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.4026682621 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.53211122 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 62764119 ps |
| CPU time | 5.47 seconds |
| Started | Jan 21 09:40:16 PM PST 24 |
| Finished | Jan 21 09:40:30 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-191af755-9758-4732-a36e-89f7d07e2132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=53211122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.53211122 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1282760963 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1099685170 ps |
| CPU time | 21.4 seconds |
| Started | Jan 21 09:56:19 PM PST 24 |
| Finished | Jan 21 09:56:45 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-d6bff9ca-c3a2-44d8-86ac-76903198491d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1282760963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1282760963 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.882216632 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 62970845651 ps |
| CPU time | 188.28 seconds |
| Started | Jan 21 09:46:59 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-8d61ff1b-2d86-4238-a035-8cc7efb76166 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=882216632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.882216632 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.985193022 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 343056594 ps |
| CPU time | 6.21 seconds |
| Started | Jan 21 10:12:32 PM PST 24 |
| Finished | Jan 21 10:12:40 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-bf27b4d2-e8af-42ee-9e4b-cf888be4043a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=985193022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.985193022 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.722708776 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 207050567 ps |
| CPU time | 6.56 seconds |
| Started | Jan 21 09:47:04 PM PST 24 |
| Finished | Jan 21 09:47:12 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-1e65896e-c5c2-4695-a2a6-0412b0e9e80b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722708776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.722708776 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3539871622 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 905189453 ps |
| CPU time | 5.87 seconds |
| Started | Jan 21 09:46:59 PM PST 24 |
| Finished | Jan 21 09:47:06 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-333c4bac-c6be-4adc-89e5-9b76218f8b19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539871622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3539871622 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3344636278 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 115788625654 ps |
| CPU time | 98.71 seconds |
| Started | Jan 21 09:47:01 PM PST 24 |
| Finished | Jan 21 09:48:42 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-02ce47c2-6317-431f-b502-dbd1143bf83b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344636278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3344636278 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2875804548 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 26374506882 ps |
| CPU time | 108.92 seconds |
| Started | Jan 21 10:45:33 PM PST 24 |
| Finished | Jan 21 10:47:24 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-cd6fcfd6-11dc-4ee3-972a-1d7608fee135 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2875804548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2875804548 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.395864437 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 109206377 ps |
| CPU time | 6.31 seconds |
| Started | Jan 21 10:57:48 PM PST 24 |
| Finished | Jan 21 10:58:01 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-45df7130-aea2-4d98-8c3e-2ec889c16583 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395864437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.395864437 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.313259020 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 14248779 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 10:59:09 PM PST 24 |
| Finished | Jan 21 10:59:11 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-32b85ba6-3bed-4b6e-a881-5bc5b0696703 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313259020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.313259020 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.1561745688 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 36957192 ps |
| CPU time | 1.3 seconds |
| Started | Jan 21 10:22:07 PM PST 24 |
| Finished | Jan 21 10:22:14 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-af10c380-e022-4995-9853-05366dd4827d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1561745688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1561745688 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2445681119 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1480189416 ps |
| CPU time | 6.92 seconds |
| Started | Jan 21 09:46:55 PM PST 24 |
| Finished | Jan 21 09:47:03 PM PST 24 |
| Peak memory | 202012 kb |
| Host | smart-15c9407f-f8ea-4625-821e-22418a676633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445681119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2445681119 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1225644176 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1286285361 ps |
| CPU time | 9.13 seconds |
| Started | Jan 21 10:08:38 PM PST 24 |
| Finished | Jan 21 10:08:47 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-cbab348d-3b17-4e61-b6db-35b5ba82b2f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1225644176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1225644176 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2496747902 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 9566138 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 09:46:59 PM PST 24 |
| Finished | Jan 21 09:47:02 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-5d4b1cd3-25fd-4493-9213-1bde87eb0d4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496747902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2496747902 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2747692836 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4756557719 ps |
| CPU time | 43.81 seconds |
| Started | Jan 21 10:36:08 PM PST 24 |
| Finished | Jan 21 10:36:55 PM PST 24 |
| Peak memory | 203968 kb |
| Host | smart-175f1277-ebf3-4144-91c1-71c5a6d5dc83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747692836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2747692836 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3119964505 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 27182424458 ps |
| CPU time | 66.77 seconds |
| Started | Jan 21 09:47:06 PM PST 24 |
| Finished | Jan 21 09:48:14 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-4287e962-4b32-4b14-88d0-2955c7ca634c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119964505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3119964505 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2444018169 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 843115206 ps |
| CPU time | 131.5 seconds |
| Started | Jan 21 09:47:05 PM PST 24 |
| Finished | Jan 21 09:49:18 PM PST 24 |
| Peak memory | 206092 kb |
| Host | smart-76d31ba9-a562-47b7-88fd-aabb801257bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2444018169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2444018169 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1354291129 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1589846365 ps |
| CPU time | 122.55 seconds |
| Started | Jan 21 09:47:17 PM PST 24 |
| Finished | Jan 21 09:49:28 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-60e41463-4ecf-45c5-b317-cd063e8c6b2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1354291129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1354291129 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1642015410 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 168167310 ps |
| CPU time | 6.48 seconds |
| Started | Jan 21 09:47:07 PM PST 24 |
| Finished | Jan 21 09:47:16 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-9088070a-7e80-4a76-a957-0b480fc4cfbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642015410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1642015410 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.272765357 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1136748695 ps |
| CPU time | 14.04 seconds |
| Started | Jan 21 09:47:18 PM PST 24 |
| Finished | Jan 21 09:47:42 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-a967043a-f28c-4849-add9-0fe74a7423c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=272765357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.272765357 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.154519210 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 220730493 ps |
| CPU time | 2.92 seconds |
| Started | Jan 21 09:47:20 PM PST 24 |
| Finished | Jan 21 09:47:33 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-79fe87c9-66ff-4128-95b3-13a65b3d73a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=154519210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.154519210 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1606686988 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 138155692 ps |
| CPU time | 2.93 seconds |
| Started | Jan 21 09:47:23 PM PST 24 |
| Finished | Jan 21 09:47:35 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-8483f3ce-a079-41e3-aa2c-e4843408693c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1606686988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1606686988 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.2545828966 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 556891669 ps |
| CPU time | 6.15 seconds |
| Started | Jan 21 09:47:14 PM PST 24 |
| Finished | Jan 21 09:47:26 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-1d6a7393-6d63-4d85-b28c-5e8ac5a6c64a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545828966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2545828966 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3982620575 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 97576355642 ps |
| CPU time | 129.29 seconds |
| Started | Jan 21 09:47:16 PM PST 24 |
| Finished | Jan 21 09:49:32 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-20ea29f3-0119-4dd7-a19e-906ae0575d1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982620575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3982620575 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1702257331 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 16243997111 ps |
| CPU time | 61.29 seconds |
| Started | Jan 21 09:47:15 PM PST 24 |
| Finished | Jan 21 09:48:23 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-902d2d98-807d-4eb6-9921-e70a3c492efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1702257331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1702257331 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.229191591 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 41220027 ps |
| CPU time | 4.24 seconds |
| Started | Jan 21 09:47:13 PM PST 24 |
| Finished | Jan 21 09:47:22 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-d7832f18-9839-4d78-97c0-e5432a1b2bfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229191591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.229191591 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2085905662 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 21832487 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 10:25:49 PM PST 24 |
| Finished | Jan 21 10:26:07 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-4c31c036-a299-4b15-aff8-9f4ee8895163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2085905662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2085905662 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2309663231 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 11744584 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 09:47:17 PM PST 24 |
| Finished | Jan 21 09:47:27 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-c5532f41-928b-4965-a20d-cb9adadbd8b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2309663231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2309663231 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.758646224 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2626946891 ps |
| CPU time | 10.72 seconds |
| Started | Jan 21 09:47:16 PM PST 24 |
| Finished | Jan 21 09:47:35 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-3cb5af61-ba61-4cd4-b482-a8c219a24d52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=758646224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.758646224 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.110018125 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1322158667 ps |
| CPU time | 6.35 seconds |
| Started | Jan 21 09:47:18 PM PST 24 |
| Finished | Jan 21 09:47:34 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-704a5412-9aca-4285-8098-8fdc39b4b145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=110018125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.110018125 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1928849861 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 10147721 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 09:47:14 PM PST 24 |
| Finished | Jan 21 09:47:22 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-e04e8d41-61ad-4afa-838b-2537a24f454c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928849861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1928849861 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.768374973 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 53914945333 ps |
| CPU time | 101.33 seconds |
| Started | Jan 21 09:55:26 PM PST 24 |
| Finished | Jan 21 09:57:19 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-ca4078fb-3ea7-4f4c-9fc7-ef44dcf2e531 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=768374973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.768374973 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3891391414 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 491479455 ps |
| CPU time | 21.99 seconds |
| Started | Jan 21 10:00:18 PM PST 24 |
| Finished | Jan 21 10:00:50 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-8e74c103-6788-4fb0-a1ad-1613bbea488b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3891391414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3891391414 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1891619263 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 7163217242 ps |
| CPU time | 135.49 seconds |
| Started | Jan 21 09:47:21 PM PST 24 |
| Finished | Jan 21 09:49:47 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-5e09afa2-d668-445a-bdef-187972e13937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891619263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.1891619263 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1929368391 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 14761725 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 10:55:50 PM PST 24 |
| Finished | Jan 21 10:55:52 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-408ffcc0-942c-4b65-abde-95808ce17df9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1929368391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1929368391 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3513162017 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 91728297 ps |
| CPU time | 6.3 seconds |
| Started | Jan 21 09:47:35 PM PST 24 |
| Finished | Jan 21 09:47:42 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-9180576d-80f6-4ac2-9b62-ef7a88ccf2b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3513162017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3513162017 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1013421991 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 646076616 ps |
| CPU time | 5.96 seconds |
| Started | Jan 21 09:47:41 PM PST 24 |
| Finished | Jan 21 09:47:48 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-511f9b76-8993-48c3-b2e6-3af621dfeeaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013421991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1013421991 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3519443165 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 723464862 ps |
| CPU time | 13.71 seconds |
| Started | Jan 21 09:47:35 PM PST 24 |
| Finished | Jan 21 09:47:49 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-3d6c14fd-9520-4c03-b6ff-42c980dbd769 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519443165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3519443165 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.716488834 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1201554720 ps |
| CPU time | 16.19 seconds |
| Started | Jan 21 10:18:52 PM PST 24 |
| Finished | Jan 21 10:19:13 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-3d629118-b14f-48f5-a9b3-683d1556fd71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=716488834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.716488834 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.4049000481 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 53242151852 ps |
| CPU time | 48.06 seconds |
| Started | Jan 21 09:47:31 PM PST 24 |
| Finished | Jan 21 09:48:22 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-be71bdc3-8475-4221-a884-875a083f2815 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049000481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.4049000481 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3411463039 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 7195376623 ps |
| CPU time | 26.52 seconds |
| Started | Jan 21 09:47:34 PM PST 24 |
| Finished | Jan 21 09:48:02 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-45c1ec29-be66-4c43-949f-7b3a5f4fa2c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3411463039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3411463039 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.4041960897 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 37238319 ps |
| CPU time | 5.92 seconds |
| Started | Jan 21 09:47:32 PM PST 24 |
| Finished | Jan 21 09:47:40 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-b2765c71-eded-4611-bfc1-562e22cae006 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041960897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.4041960897 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2347218237 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 863159486 ps |
| CPU time | 8.7 seconds |
| Started | Jan 21 09:47:33 PM PST 24 |
| Finished | Jan 21 09:47:44 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-92b454e0-45dc-4f65-bbb5-5a4eaf9c4d14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347218237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2347218237 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.4231023555 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 10762985 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 10:56:06 PM PST 24 |
| Finished | Jan 21 10:56:08 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-662eaaa9-d290-4dd0-81d7-47f0e68bd4ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4231023555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.4231023555 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.146887737 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3036080537 ps |
| CPU time | 8.01 seconds |
| Started | Jan 21 09:47:22 PM PST 24 |
| Finished | Jan 21 09:47:40 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-94f76905-ad34-4ccd-97a6-b470486fa1f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=146887737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.146887737 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2166279478 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1669945740 ps |
| CPU time | 5.4 seconds |
| Started | Jan 21 10:24:40 PM PST 24 |
| Finished | Jan 21 10:24:53 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-38b7af4c-2160-457b-be0c-47b1f4874301 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2166279478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2166279478 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1255210370 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8965511 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 10:24:13 PM PST 24 |
| Finished | Jan 21 10:24:17 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-e57159fa-c190-4077-9b04-6cafa351ba1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255210370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1255210370 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3690465932 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 457156049 ps |
| CPU time | 46.68 seconds |
| Started | Jan 21 09:47:42 PM PST 24 |
| Finished | Jan 21 09:48:30 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-5ef2bbf6-f6dc-4949-b3b7-653692a0b8ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3690465932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3690465932 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3527725226 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 19484437 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 09:47:42 PM PST 24 |
| Finished | Jan 21 09:47:44 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-5ca78aff-f51d-4f18-a593-4d2334c132c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527725226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3527725226 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3195292222 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1580965188 ps |
| CPU time | 158.34 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:50:19 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-5b469c95-3982-4c7d-8445-aa42c8d08a36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3195292222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3195292222 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3039600803 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 741523499 ps |
| CPU time | 107.71 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:49:28 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-c207c1ee-dbc2-4b8f-a7d1-db12287fd602 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039600803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3039600803 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1230161094 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 475918357 ps |
| CPU time | 11.22 seconds |
| Started | Jan 21 09:47:34 PM PST 24 |
| Finished | Jan 21 09:47:47 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-6d7bae03-5b66-485b-ae60-911b37b28ac3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1230161094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1230161094 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1317497351 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 142742876 ps |
| CPU time | 5.49 seconds |
| Started | Jan 21 09:47:43 PM PST 24 |
| Finished | Jan 21 09:47:50 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-8e3665e1-444f-4632-b7a5-01d4de2bdcdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1317497351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1317497351 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4100511997 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 67826912861 ps |
| CPU time | 146.84 seconds |
| Started | Jan 21 09:47:40 PM PST 24 |
| Finished | Jan 21 09:50:08 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-e95064ac-142a-4537-8073-be0a8f31b738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4100511997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.4100511997 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1452559069 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 247812421 ps |
| CPU time | 5.43 seconds |
| Started | Jan 21 09:47:53 PM PST 24 |
| Finished | Jan 21 09:47:59 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-769c14fe-9564-4dc1-bb1d-b7b8db24b9b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452559069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1452559069 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3961879011 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1364734999 ps |
| CPU time | 4.98 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:47:45 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-222b25ae-31a1-4fd2-9ed5-2b468b4f7cb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961879011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3961879011 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3932877422 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 90841104 ps |
| CPU time | 6.03 seconds |
| Started | Jan 21 09:47:41 PM PST 24 |
| Finished | Jan 21 09:47:48 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-01785c1d-dca4-43ac-aa4d-9db0dbc07a12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3932877422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3932877422 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3073246505 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4252907559 ps |
| CPU time | 17.41 seconds |
| Started | Jan 21 09:47:42 PM PST 24 |
| Finished | Jan 21 09:48:00 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-08b04aeb-2577-4c08-a574-01684795836e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073246505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3073246505 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3707585771 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 22380944450 ps |
| CPU time | 51.77 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:48:32 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-bdfaaf37-fa01-4b1c-8318-bb84103e403f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3707585771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3707585771 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3658790450 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 175370262 ps |
| CPU time | 5.03 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:47:45 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-adb73b96-2df3-4c1b-bc31-edfc5756b853 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658790450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3658790450 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2769824114 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 966192652 ps |
| CPU time | 10.19 seconds |
| Started | Jan 21 09:47:38 PM PST 24 |
| Finished | Jan 21 09:47:49 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-7e5b54da-eefd-4587-88ed-b2ddc6ac8528 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769824114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2769824114 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.792376960 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 42542121 ps |
| CPU time | 1.45 seconds |
| Started | Jan 21 09:47:39 PM PST 24 |
| Finished | Jan 21 09:47:41 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-ffe9cd6e-42e7-4ee4-a175-391bf1e7db85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=792376960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.792376960 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3267370613 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 12342740416 ps |
| CPU time | 11 seconds |
| Started | Jan 21 09:47:38 PM PST 24 |
| Finished | Jan 21 09:47:50 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-2a496572-026b-45a0-933f-ffc7ef36305f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267370613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3267370613 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2708012890 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3107870883 ps |
| CPU time | 8.48 seconds |
| Started | Jan 21 09:47:37 PM PST 24 |
| Finished | Jan 21 09:47:46 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-32a11d1a-595b-4b7a-b047-2c65d44afe44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2708012890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2708012890 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2530807035 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 13738111 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 09:47:40 PM PST 24 |
| Finished | Jan 21 09:47:42 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-74d22774-faed-4385-b1d7-f675b6704e6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530807035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2530807035 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2334336453 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3538720452 ps |
| CPU time | 33.88 seconds |
| Started | Jan 21 09:47:44 PM PST 24 |
| Finished | Jan 21 09:48:19 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-146f187c-3c72-4eef-8ac0-18dd6859ac01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334336453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2334336453 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3346363548 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 789956920 ps |
| CPU time | 10.4 seconds |
| Started | Jan 21 09:47:53 PM PST 24 |
| Finished | Jan 21 09:48:05 PM PST 24 |
| Peak memory | 200928 kb |
| Host | smart-f8c73732-6588-403e-b243-a2bd3f718b41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3346363548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3346363548 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.131331845 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 516684923 ps |
| CPU time | 92.33 seconds |
| Started | Jan 21 09:47:53 PM PST 24 |
| Finished | Jan 21 09:49:27 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-b28dbbde-0809-4f7f-b9cc-4e73f8409300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131331845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.131331845 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1564796936 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 477177925 ps |
| CPU time | 84.68 seconds |
| Started | Jan 21 09:47:55 PM PST 24 |
| Finished | Jan 21 09:49:20 PM PST 24 |
| Peak memory | 205600 kb |
| Host | smart-39bfe860-8cdd-4df3-ab08-617a2ddb089c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1564796936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1564796936 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3421304824 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 32588540 ps |
| CPU time | 4.04 seconds |
| Started | Jan 21 09:47:53 PM PST 24 |
| Finished | Jan 21 09:47:58 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-7783aa63-3d44-4235-8e07-4d31c4027179 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3421304824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3421304824 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1942000191 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 183053501 ps |
| CPU time | 4.72 seconds |
| Started | Jan 21 09:48:02 PM PST 24 |
| Finished | Jan 21 09:48:07 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-97a8ecf7-c420-4520-9668-d508efaab4b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942000191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1942000191 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2781613478 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 35534838279 ps |
| CPU time | 155.85 seconds |
| Started | Jan 21 09:48:01 PM PST 24 |
| Finished | Jan 21 09:50:38 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e66a4ff2-52a8-42d9-8010-8afc9774e008 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2781613478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2781613478 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1335477306 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 122635257 ps |
| CPU time | 5.48 seconds |
| Started | Jan 21 09:48:08 PM PST 24 |
| Finished | Jan 21 09:48:14 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-d6a1b0e6-c3fb-4fc0-a72e-f2e5c576dac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1335477306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1335477306 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.872478257 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 35016839 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 09:48:08 PM PST 24 |
| Finished | Jan 21 09:48:11 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-8da8b842-9238-4093-9d08-bd51af686a7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872478257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.872478257 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1689072235 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 81504921 ps |
| CPU time | 8.13 seconds |
| Started | Jan 21 09:47:58 PM PST 24 |
| Finished | Jan 21 09:48:07 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-1eebdae5-d8f0-45b6-ada2-9dd6255c7f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1689072235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1689072235 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1610490923 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 38891054739 ps |
| CPU time | 135.96 seconds |
| Started | Jan 21 09:48:02 PM PST 24 |
| Finished | Jan 21 09:50:19 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-72385700-b6ba-4bf5-b642-1c30490f6496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610490923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1610490923 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.852384739 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 15047646493 ps |
| CPU time | 88.04 seconds |
| Started | Jan 21 09:48:02 PM PST 24 |
| Finished | Jan 21 09:49:32 PM PST 24 |
| Peak memory | 202072 kb |
| Host | smart-80b7ceb3-2044-4741-89ac-171fdcaaff29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=852384739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.852384739 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.940816752 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 66300156 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 09:47:57 PM PST 24 |
| Finished | Jan 21 09:48:00 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-2755121d-da12-4462-85ba-ac3e136244a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940816752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.940816752 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1249914163 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1527021923 ps |
| CPU time | 9.05 seconds |
| Started | Jan 21 09:48:13 PM PST 24 |
| Finished | Jan 21 09:48:24 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-5f517671-b093-46f2-a573-69bc29b58cb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1249914163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1249914163 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.313067931 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 15835729 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 09:47:56 PM PST 24 |
| Finished | Jan 21 09:47:58 PM PST 24 |
| Peak memory | 201740 kb |
| Host | smart-1a21e5a6-0009-406c-ba2c-82fb74d0d951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313067931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.313067931 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2206720513 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 9225717352 ps |
| CPU time | 12.15 seconds |
| Started | Jan 21 09:47:56 PM PST 24 |
| Finished | Jan 21 09:48:09 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-d51c941f-b9ba-424d-868b-9e3ee42c019c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206720513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2206720513 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2168393619 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2948034044 ps |
| CPU time | 14.49 seconds |
| Started | Jan 21 09:47:56 PM PST 24 |
| Finished | Jan 21 09:48:11 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-3a686b7b-bc42-4317-acc5-7bba3af4edbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2168393619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2168393619 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1824483773 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 17755141 ps |
| CPU time | 1.35 seconds |
| Started | Jan 21 09:47:56 PM PST 24 |
| Finished | Jan 21 09:47:58 PM PST 24 |
| Peak memory | 201716 kb |
| Host | smart-5511eb0f-586e-4149-a54e-5158e3770f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824483773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1824483773 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2654073842 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 714668911 ps |
| CPU time | 53.77 seconds |
| Started | Jan 21 09:48:15 PM PST 24 |
| Finished | Jan 21 09:49:10 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-9a3cc1fd-8fcf-4b58-bbfe-634aba5ebafb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2654073842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2654073842 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2337880533 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 23743515971 ps |
| CPU time | 84.39 seconds |
| Started | Jan 21 09:48:19 PM PST 24 |
| Finished | Jan 21 09:49:44 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-fa41bad8-4b3f-49bc-b3ae-9c451e48f8a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337880533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2337880533 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1341034297 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 518445657 ps |
| CPU time | 67.55 seconds |
| Started | Jan 21 10:01:10 PM PST 24 |
| Finished | Jan 21 10:02:24 PM PST 24 |
| Peak memory | 203916 kb |
| Host | smart-266e5a8a-5773-405a-b620-df576b2b3b42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1341034297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.1341034297 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2402123592 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 12868890848 ps |
| CPU time | 141.31 seconds |
| Started | Jan 21 09:48:13 PM PST 24 |
| Finished | Jan 21 09:50:36 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-94dd7709-caf6-4335-8b92-8a505fc73f59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2402123592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2402123592 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.325532599 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 79780933 ps |
| CPU time | 5.28 seconds |
| Started | Jan 21 09:48:14 PM PST 24 |
| Finished | Jan 21 09:48:20 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-edec1e03-976f-4dd0-a598-276bb480c3fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325532599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.325532599 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.4294497181 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 80074098 ps |
| CPU time | 5.31 seconds |
| Started | Jan 21 09:48:20 PM PST 24 |
| Finished | Jan 21 09:48:26 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-43a5ac8d-224d-4cc9-ab71-60b6346824e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4294497181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.4294497181 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2963358007 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 34675759702 ps |
| CPU time | 168.1 seconds |
| Started | Jan 21 09:48:20 PM PST 24 |
| Finished | Jan 21 09:51:09 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-2dc040ff-15bb-4fa3-bf5a-7957bb025378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2963358007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2963358007 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1784545404 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 167927290 ps |
| CPU time | 3.46 seconds |
| Started | Jan 21 09:48:28 PM PST 24 |
| Finished | Jan 21 09:48:34 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-f67c215b-bf17-44d5-95d4-38ffbaf0547a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784545404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1784545404 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2745915276 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 738083668 ps |
| CPU time | 7.96 seconds |
| Started | Jan 21 09:48:27 PM PST 24 |
| Finished | Jan 21 09:48:38 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-18bb9b7e-5f89-47f8-bf4b-296e986ede06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2745915276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2745915276 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3222323150 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 17037494 ps |
| CPU time | 1.75 seconds |
| Started | Jan 21 09:48:19 PM PST 24 |
| Finished | Jan 21 09:48:22 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-595311d3-4b6b-4a18-9cf6-c3393274e3d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222323150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3222323150 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1531100314 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 15750763932 ps |
| CPU time | 43.8 seconds |
| Started | Jan 21 09:48:21 PM PST 24 |
| Finished | Jan 21 09:49:06 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-22cc56f9-794f-43d0-9bba-35cc0815bb45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531100314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1531100314 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3828008266 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3166214553 ps |
| CPU time | 12.34 seconds |
| Started | Jan 21 09:48:21 PM PST 24 |
| Finished | Jan 21 09:48:34 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-a0647105-0de7-4571-9970-2012b17787f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3828008266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3828008266 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2550921314 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 20126665 ps |
| CPU time | 1.23 seconds |
| Started | Jan 21 09:48:21 PM PST 24 |
| Finished | Jan 21 09:48:23 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-ac851254-72ca-4f10-8b60-59efefb077da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550921314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2550921314 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.765796686 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 177355288 ps |
| CPU time | 2.94 seconds |
| Started | Jan 21 10:45:15 PM PST 24 |
| Finished | Jan 21 10:45:22 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-52313c0e-bcce-4f8a-b7e9-bbd85b055482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=765796686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.765796686 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.4107983554 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 125492718 ps |
| CPU time | 1.67 seconds |
| Started | Jan 21 09:48:14 PM PST 24 |
| Finished | Jan 21 09:48:17 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-39ba0b42-81ea-4692-8ddc-ba9dfc4c884c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4107983554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4107983554 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3024423043 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2329452071 ps |
| CPU time | 9.79 seconds |
| Started | Jan 21 10:27:20 PM PST 24 |
| Finished | Jan 21 10:27:49 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-03ad6c1a-e8d3-48e5-8e05-5f2aee57cc7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024423043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3024423043 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2673477553 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 7340846494 ps |
| CPU time | 6.84 seconds |
| Started | Jan 21 09:48:21 PM PST 24 |
| Finished | Jan 21 09:48:29 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-a56351b8-7075-4811-a41c-91bf69a3ac20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2673477553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2673477553 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3075069326 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 10350133 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 10:39:55 PM PST 24 |
| Finished | Jan 21 10:39:57 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-20abf312-2b20-47e1-84b1-a7b371bfe94e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075069326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3075069326 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3372447966 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5838481979 ps |
| CPU time | 98.84 seconds |
| Started | Jan 21 09:48:27 PM PST 24 |
| Finished | Jan 21 09:50:08 PM PST 24 |
| Peak memory | 205528 kb |
| Host | smart-63ba5fa1-0f90-48d0-8e24-f9d7df6e266d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372447966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3372447966 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2201833746 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1572608103 ps |
| CPU time | 16.87 seconds |
| Started | Jan 21 09:48:30 PM PST 24 |
| Finished | Jan 21 09:48:50 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-90979e5d-3ba4-4bd2-9073-1c5e44ba329c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2201833746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2201833746 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4261188348 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 291236136 ps |
| CPU time | 65.96 seconds |
| Started | Jan 21 09:48:30 PM PST 24 |
| Finished | Jan 21 09:49:39 PM PST 24 |
| Peak memory | 204140 kb |
| Host | smart-124a07d3-3dec-47b9-ba51-ed5a31abeefd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4261188348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.4261188348 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1449535267 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4706235623 ps |
| CPU time | 55.65 seconds |
| Started | Jan 21 09:48:27 PM PST 24 |
| Finished | Jan 21 09:49:24 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-9187038f-ffaa-43ca-9dc0-fab65fc22b22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1449535267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1449535267 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.4049530702 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 225384537 ps |
| CPU time | 4.03 seconds |
| Started | Jan 21 10:32:59 PM PST 24 |
| Finished | Jan 21 10:33:07 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-ede974a4-4b42-4eb3-a47f-a7b63823d38a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049530702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4049530702 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2585274451 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 20515756 ps |
| CPU time | 4.24 seconds |
| Started | Jan 21 09:48:35 PM PST 24 |
| Finished | Jan 21 09:48:42 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-aff64027-58d3-4905-8652-b82da8684f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2585274451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2585274451 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3266516958 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 33037954877 ps |
| CPU time | 235.68 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:52:34 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-5380ec4c-ee46-4942-8af3-b5e5eb24472e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3266516958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3266516958 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3135943634 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 183974120 ps |
| CPU time | 3.97 seconds |
| Started | Jan 21 09:48:36 PM PST 24 |
| Finished | Jan 21 09:48:43 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-b0581c76-01a1-4753-9961-9cab869c3692 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3135943634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3135943634 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2987579783 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 60505238 ps |
| CPU time | 7.68 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:48:45 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-808fa508-2ad4-4f0d-b22e-318a1fb6e96d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2987579783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2987579783 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3161844185 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 78270889 ps |
| CPU time | 4.42 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:48:42 PM PST 24 |
| Peak memory | 201744 kb |
| Host | smart-2eb34473-8fec-4188-b22f-265ff837adf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161844185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3161844185 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3436655433 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 13073097734 ps |
| CPU time | 44.4 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:49:22 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-07191438-443d-4934-9e07-164c9012bd39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436655433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3436655433 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3224267863 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 20762037489 ps |
| CPU time | 133.22 seconds |
| Started | Jan 21 09:48:35 PM PST 24 |
| Finished | Jan 21 09:50:51 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-99918c1e-00e1-47d5-a39d-00f236d6f142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3224267863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3224267863 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3320460256 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 44365814 ps |
| CPU time | 4.76 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:48:42 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-0c056a75-3a2c-474d-9624-b14af81e0cbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320460256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3320460256 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3278605961 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1475718912 ps |
| CPU time | 13.74 seconds |
| Started | Jan 21 09:48:35 PM PST 24 |
| Finished | Jan 21 09:48:52 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-7b9ec19a-8afc-41ce-8269-ef2cd4d63406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3278605961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3278605961 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2378816125 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 112201664 ps |
| CPU time | 1.4 seconds |
| Started | Jan 21 09:48:29 PM PST 24 |
| Finished | Jan 21 09:48:33 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-bbffa475-f9cb-4db3-994a-132d1eb582fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2378816125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2378816125 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1813367007 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1970465038 ps |
| CPU time | 8.37 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:48:46 PM PST 24 |
| Peak memory | 202008 kb |
| Host | smart-ea906bc8-572d-4385-947e-580ce8e90e65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813367007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1813367007 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.443978077 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1557569314 ps |
| CPU time | 8.19 seconds |
| Started | Jan 21 09:48:34 PM PST 24 |
| Finished | Jan 21 09:48:46 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-c926acb9-0ee5-4655-80c7-bcdf21527ee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=443978077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.443978077 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2723406595 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 10348967 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 09:48:36 PM PST 24 |
| Finished | Jan 21 09:48:40 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-959cbe90-63e4-4daa-b9d4-9a097a67dbe9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723406595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2723406595 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.535948653 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1010805025 ps |
| CPU time | 33.67 seconds |
| Started | Jan 21 09:48:36 PM PST 24 |
| Finished | Jan 21 09:49:12 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-1e440db3-a39e-4d24-bd42-57d697d3aff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=535948653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.535948653 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4173018295 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4673149957 ps |
| CPU time | 60.07 seconds |
| Started | Jan 21 09:48:49 PM PST 24 |
| Finished | Jan 21 09:49:52 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-cb45d9ff-89b2-4655-b0c7-0176c1a99e48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4173018295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4173018295 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.785424781 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 654478256 ps |
| CPU time | 45.87 seconds |
| Started | Jan 21 09:48:35 PM PST 24 |
| Finished | Jan 21 09:49:24 PM PST 24 |
| Peak memory | 203840 kb |
| Host | smart-aee88238-8749-4361-b88c-cb69dec8f9bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785424781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.785424781 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2438343488 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6239556535 ps |
| CPU time | 82.3 seconds |
| Started | Jan 21 09:48:43 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 203160 kb |
| Host | smart-59032bf1-4459-49a6-a844-7a3d8d95b4d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2438343488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.2438343488 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2024764402 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1818100261 ps |
| CPU time | 7.5 seconds |
| Started | Jan 21 09:48:35 PM PST 24 |
| Finished | Jan 21 09:48:46 PM PST 24 |
| Peak memory | 201704 kb |
| Host | smart-0ba0f93c-2313-42fa-9c00-f9b3364f1f3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2024764402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2024764402 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2920510539 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 380857670 ps |
| CPU time | 3.41 seconds |
| Started | Jan 21 09:48:53 PM PST 24 |
| Finished | Jan 21 09:49:00 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-b8138187-7449-4e7f-8a96-c89e7905ce16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920510539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2920510539 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3202467883 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 103280098065 ps |
| CPU time | 183.62 seconds |
| Started | Jan 21 09:48:50 PM PST 24 |
| Finished | Jan 21 09:51:56 PM PST 24 |
| Peak memory | 201968 kb |
| Host | smart-c5f02f98-8aa0-468a-92a5-8c619e989e1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3202467883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3202467883 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3503801783 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 316318433 ps |
| CPU time | 4.98 seconds |
| Started | Jan 21 09:48:57 PM PST 24 |
| Finished | Jan 21 09:49:04 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-ab28dbef-0b5f-4f92-a7be-ec3a094e0eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503801783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3503801783 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3361342057 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 28117367 ps |
| CPU time | 2.77 seconds |
| Started | Jan 21 09:48:51 PM PST 24 |
| Finished | Jan 21 09:48:57 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-fbf7e1eb-0c08-4358-bacb-2d6489554ee5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3361342057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3361342057 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2195124867 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 111551702 ps |
| CPU time | 1.6 seconds |
| Started | Jan 21 09:48:51 PM PST 24 |
| Finished | Jan 21 09:48:56 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-fecf7034-18e1-4446-a900-81eb0669b387 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2195124867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2195124867 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3659431775 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 30253388292 ps |
| CPU time | 84.02 seconds |
| Started | Jan 21 09:48:52 PM PST 24 |
| Finished | Jan 21 09:50:19 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-39a3b901-ae28-437b-8447-e6506d04b1fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659431775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3659431775 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2642799562 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 25631620286 ps |
| CPU time | 56.91 seconds |
| Started | Jan 21 09:48:49 PM PST 24 |
| Finished | Jan 21 09:49:49 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-b2a3cce0-cc55-4f02-9152-7068e67c0bc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2642799562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2642799562 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1190194032 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 96134972 ps |
| CPU time | 9.02 seconds |
| Started | Jan 21 09:48:51 PM PST 24 |
| Finished | Jan 21 09:49:03 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-de4f52dc-b9cd-4886-a6c9-9a5337bb8691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190194032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1190194032 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1211919438 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 51899464 ps |
| CPU time | 5.53 seconds |
| Started | Jan 21 09:48:53 PM PST 24 |
| Finished | Jan 21 09:49:02 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-c98cf5c0-149b-4028-8b7c-7c2863400fa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1211919438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1211919438 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.2693463860 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8566462 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 09:48:43 PM PST 24 |
| Finished | Jan 21 09:48:47 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-856173e8-3352-460e-a376-5ef70a71ed1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693463860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2693463860 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.152596340 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2060322006 ps |
| CPU time | 9.88 seconds |
| Started | Jan 21 09:48:49 PM PST 24 |
| Finished | Jan 21 09:49:02 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-d06b82d6-b98f-4230-a338-1aeb303dac30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=152596340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.152596340 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3559150251 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2831410188 ps |
| CPU time | 9.74 seconds |
| Started | Jan 21 09:48:52 PM PST 24 |
| Finished | Jan 21 09:49:05 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-2a77e10e-16ab-408f-8b37-95d61bb282f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3559150251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3559150251 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.718155031 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 9804866 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 09:48:45 PM PST 24 |
| Finished | Jan 21 09:48:49 PM PST 24 |
| Peak memory | 201744 kb |
| Host | smart-94725f05-56c1-45ff-a0d7-f76a9f5d0af4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718155031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.718155031 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4262050912 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 93486352 ps |
| CPU time | 9.14 seconds |
| Started | Jan 21 09:48:54 PM PST 24 |
| Finished | Jan 21 09:49:07 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-b3a9281e-dbbc-4a86-baa1-901219f52376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4262050912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4262050912 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1543159794 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 412923774 ps |
| CPU time | 38.63 seconds |
| Started | Jan 21 09:48:56 PM PST 24 |
| Finished | Jan 21 09:49:37 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-915d4cd0-2a94-4147-91b1-95cb0844da9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543159794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1543159794 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.566778573 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 106733763 ps |
| CPU time | 12.46 seconds |
| Started | Jan 21 09:48:56 PM PST 24 |
| Finished | Jan 21 09:49:10 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-7b4ad309-8315-4306-ae4a-9e08d5721570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=566778573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.566778573 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.695872045 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 20438805 ps |
| CPU time | 7.59 seconds |
| Started | Jan 21 09:48:56 PM PST 24 |
| Finished | Jan 21 09:49:06 PM PST 24 |
| Peak memory | 201704 kb |
| Host | smart-7b5c1697-67ce-4ae7-b1d0-ddf4d8107afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695872045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.695872045 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3665208655 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 41540263 ps |
| CPU time | 4.02 seconds |
| Started | Jan 21 09:48:57 PM PST 24 |
| Finished | Jan 21 09:49:03 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-dccca4ce-77cf-416c-852f-bbb99d720e1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665208655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3665208655 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2234748668 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 984824389 ps |
| CPU time | 21.55 seconds |
| Started | Jan 21 09:49:04 PM PST 24 |
| Finished | Jan 21 09:49:26 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-c29f8f4b-7a20-4298-9d77-b933537c1dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2234748668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2234748668 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.799030958 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 579261056 ps |
| CPU time | 7.54 seconds |
| Started | Jan 21 09:49:09 PM PST 24 |
| Finished | Jan 21 09:49:18 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-012a3ec2-71a0-4f5b-b2ed-c94d4dddd898 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=799030958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.799030958 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3852976004 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 610877028 ps |
| CPU time | 3.55 seconds |
| Started | Jan 21 09:49:12 PM PST 24 |
| Finished | Jan 21 09:49:19 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-e3a821b4-f303-4fc7-a8fa-533b58e6266a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3852976004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3852976004 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3019683516 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 457970025 ps |
| CPU time | 8.59 seconds |
| Started | Jan 21 09:49:05 PM PST 24 |
| Finished | Jan 21 09:49:15 PM PST 24 |
| Peak memory | 201716 kb |
| Host | smart-b8a3948a-54e2-4862-9ad2-e3048c8ddfd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3019683516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3019683516 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.852310859 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 22508974440 ps |
| CPU time | 25.46 seconds |
| Started | Jan 21 09:49:01 PM PST 24 |
| Finished | Jan 21 09:49:28 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-25f28a22-5f82-40e8-9bb4-0fb6fef82765 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=852310859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.852310859 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3658657571 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 30657112339 ps |
| CPU time | 133.63 seconds |
| Started | Jan 21 09:49:04 PM PST 24 |
| Finished | Jan 21 09:51:18 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-948f8c16-fb81-4c67-bceb-7b3174530628 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3658657571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3658657571 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1091408308 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 219297404 ps |
| CPU time | 7.31 seconds |
| Started | Jan 21 09:49:02 PM PST 24 |
| Finished | Jan 21 09:49:10 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-16514794-bda3-47de-9f22-07bdd71b964c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091408308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1091408308 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.2019838828 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 546005330 ps |
| CPU time | 6.75 seconds |
| Started | Jan 21 09:49:04 PM PST 24 |
| Finished | Jan 21 09:49:11 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-04616f75-fe0a-4ff1-af52-1c180bde9fac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2019838828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2019838828 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3666914403 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 221807497 ps |
| CPU time | 1.46 seconds |
| Started | Jan 21 09:56:27 PM PST 24 |
| Finished | Jan 21 09:56:31 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-70cd401d-354e-48d7-8c28-d5831cb86867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3666914403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3666914403 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3148500620 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2999045410 ps |
| CPU time | 9.98 seconds |
| Started | Jan 21 09:48:56 PM PST 24 |
| Finished | Jan 21 09:49:08 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-07dc0b90-94ef-41d7-b020-7552bbd7e9b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148500620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3148500620 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3291705221 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 569725944 ps |
| CPU time | 4.74 seconds |
| Started | Jan 21 09:49:02 PM PST 24 |
| Finished | Jan 21 09:49:08 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-ae632aff-8966-4cc5-8464-afa507e80c0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3291705221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3291705221 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1624552344 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 28005924 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 09:48:58 PM PST 24 |
| Finished | Jan 21 09:49:01 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-bfb83c6e-9834-4345-a145-9bb63f9dacec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624552344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1624552344 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1028871232 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4384814524 ps |
| CPU time | 81.94 seconds |
| Started | Jan 21 09:49:15 PM PST 24 |
| Finished | Jan 21 09:50:43 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-4f4a72d5-6202-461b-b41a-ea59804318c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028871232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1028871232 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3850153127 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 94390006 ps |
| CPU time | 9.68 seconds |
| Started | Jan 21 09:49:10 PM PST 24 |
| Finished | Jan 21 09:49:22 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-259c98df-6544-486d-b854-970b4b5cde71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3850153127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3850153127 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.791342354 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4679112616 ps |
| CPU time | 67.57 seconds |
| Started | Jan 21 09:49:11 PM PST 24 |
| Finished | Jan 21 09:50:21 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-0d6758fc-0ee1-4148-b31b-928b55aa4174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791342354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.791342354 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1027007853 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1098070790 ps |
| CPU time | 8.45 seconds |
| Started | Jan 21 09:49:09 PM PST 24 |
| Finished | Jan 21 09:49:20 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-eb09d6a4-8502-424b-ac11-f44bc486add0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1027007853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1027007853 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.4073369713 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 41795679 ps |
| CPU time | 3.95 seconds |
| Started | Jan 21 09:49:28 PM PST 24 |
| Finished | Jan 21 09:49:36 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-c8b41de2-74f3-4bb6-9fb7-16577bc08a8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073369713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.4073369713 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2583285216 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 22060859597 ps |
| CPU time | 107.22 seconds |
| Started | Jan 21 09:49:34 PM PST 24 |
| Finished | Jan 21 09:51:25 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-77c9ed20-5249-466b-98df-f679aae77a70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2583285216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2583285216 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.701103309 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10218508 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 09:49:26 PM PST 24 |
| Finished | Jan 21 09:49:31 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-23b822ca-d12f-46ae-b462-51af332d3233 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=701103309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.701103309 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.3859109502 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 58317190 ps |
| CPU time | 3.48 seconds |
| Started | Jan 21 09:49:27 PM PST 24 |
| Finished | Jan 21 09:49:34 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-eaba999d-452d-41ea-94ef-8f2874a0760f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859109502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3859109502 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2084733684 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 44646520 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 09:49:18 PM PST 24 |
| Finished | Jan 21 09:49:27 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-daf0ab93-7572-4486-b615-477c9ffef404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2084733684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2084733684 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2109253239 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 16337881105 ps |
| CPU time | 69.75 seconds |
| Started | Jan 21 09:49:18 PM PST 24 |
| Finished | Jan 21 09:50:34 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-46f793aa-0a73-4a8b-b142-653ff944895f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109253239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2109253239 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2602017868 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2378750458 ps |
| CPU time | 11.05 seconds |
| Started | Jan 21 09:49:26 PM PST 24 |
| Finished | Jan 21 09:49:41 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-014c8c9a-aab3-411c-b3ca-8b8406103f91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2602017868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2602017868 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3128701556 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 68429473 ps |
| CPU time | 7.94 seconds |
| Started | Jan 21 09:49:24 PM PST 24 |
| Finished | Jan 21 09:49:36 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-65b43877-b95e-41f6-91fc-dfd97632af68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128701556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3128701556 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.1890097284 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 161272261 ps |
| CPU time | 6.33 seconds |
| Started | Jan 21 09:49:29 PM PST 24 |
| Finished | Jan 21 09:49:39 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-c2149d10-5715-40aa-80c8-2a65454d8fe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890097284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1890097284 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2977340353 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 8215032 ps |
| CPU time | 1.29 seconds |
| Started | Jan 21 09:49:11 PM PST 24 |
| Finished | Jan 21 09:49:14 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-fc7c4af9-b8d2-4474-bdb3-c02941878e16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2977340353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2977340353 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.525219082 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1988053104 ps |
| CPU time | 9.13 seconds |
| Started | Jan 21 09:49:20 PM PST 24 |
| Finished | Jan 21 09:49:34 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-f04d14f8-c762-4807-96da-abfddc971a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=525219082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.525219082 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1154021182 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1149136709 ps |
| CPU time | 6.43 seconds |
| Started | Jan 21 09:49:19 PM PST 24 |
| Finished | Jan 21 09:49:30 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-59457370-ef84-49ed-b284-adf5d2c29f77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1154021182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1154021182 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.4178450653 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 14270026 ps |
| CPU time | 1.23 seconds |
| Started | Jan 21 09:49:19 PM PST 24 |
| Finished | Jan 21 09:49:25 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-56cc596e-0b97-4fd0-a254-c585d08c55b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178450653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.4178450653 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2369541736 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 10727809482 ps |
| CPU time | 116.79 seconds |
| Started | Jan 21 09:49:28 PM PST 24 |
| Finished | Jan 21 09:51:28 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-5c381680-aead-4c6d-8f9d-ae42e2ebc249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369541736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2369541736 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.129080881 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 357051682 ps |
| CPU time | 16.9 seconds |
| Started | Jan 21 09:49:45 PM PST 24 |
| Finished | Jan 21 09:50:03 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-97360687-d853-4b1f-a87f-b4ddf59d359c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=129080881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.129080881 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2732404988 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1501167490 ps |
| CPU time | 208.1 seconds |
| Started | Jan 21 09:49:26 PM PST 24 |
| Finished | Jan 21 09:52:58 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-69016882-12ab-4b98-b62b-17150c595974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2732404988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2732404988 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1394947879 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4832540342 ps |
| CPU time | 81.91 seconds |
| Started | Jan 21 09:49:45 PM PST 24 |
| Finished | Jan 21 09:51:08 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-a5be568f-0b8d-4d0c-8e49-240ee5f5eaa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1394947879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.1394947879 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.274232761 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 301391874 ps |
| CPU time | 4.67 seconds |
| Started | Jan 21 09:49:30 PM PST 24 |
| Finished | Jan 21 09:49:38 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-219e1e4f-9af1-4312-a146-8d4e7691c037 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274232761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.274232761 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2036129099 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 343632659 ps |
| CPU time | 7.03 seconds |
| Started | Jan 21 10:44:21 PM PST 24 |
| Finished | Jan 21 10:44:35 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-d05e358c-c1bd-44e4-9c9a-9bd901c123a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2036129099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2036129099 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1748583389 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 20876241881 ps |
| CPU time | 90.83 seconds |
| Started | Jan 21 09:40:42 PM PST 24 |
| Finished | Jan 21 09:42:15 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-d4895c99-fa68-4f3d-b710-25e59a94faca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1748583389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1748583389 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2679793601 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 57243725 ps |
| CPU time | 6.71 seconds |
| Started | Jan 21 09:40:55 PM PST 24 |
| Finished | Jan 21 09:41:08 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-a830767f-c259-45d5-9caa-c776dac79ea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2679793601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2679793601 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.273945770 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 80016215 ps |
| CPU time | 8.36 seconds |
| Started | Jan 21 09:40:49 PM PST 24 |
| Finished | Jan 21 09:41:08 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-6707e853-b465-4180-92b2-0b4a6a420030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273945770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.273945770 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.1420145519 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4763242917 ps |
| CPU time | 17.4 seconds |
| Started | Jan 21 09:55:53 PM PST 24 |
| Finished | Jan 21 09:56:15 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-a53fda81-e80e-4a47-a71f-f127fc00be3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420145519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1420145519 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2758745925 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 51396724617 ps |
| CPU time | 80.58 seconds |
| Started | Jan 21 09:40:31 PM PST 24 |
| Finished | Jan 21 09:41:53 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-2453ca62-6c81-4bcb-bea6-6b47730e5ffb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758745925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2758745925 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4181217457 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 4562349464 ps |
| CPU time | 27.67 seconds |
| Started | Jan 21 11:29:51 PM PST 24 |
| Finished | Jan 21 11:30:25 PM PST 24 |
| Peak memory | 201964 kb |
| Host | smart-a7ad56b0-4433-496f-922c-3d62984a2b38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4181217457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4181217457 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3865336392 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 22010334 ps |
| CPU time | 2.47 seconds |
| Started | Jan 21 09:40:21 PM PST 24 |
| Finished | Jan 21 09:40:28 PM PST 24 |
| Peak memory | 201712 kb |
| Host | smart-6019f4d2-b562-4279-a5e6-302e2ccd1571 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865336392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3865336392 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3981253576 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 296576748 ps |
| CPU time | 6.23 seconds |
| Started | Jan 21 09:40:42 PM PST 24 |
| Finished | Jan 21 09:40:52 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-1d26b650-44d6-47a4-83f9-2f34bc9119f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981253576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3981253576 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.746766844 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 82216295 ps |
| CPU time | 1.51 seconds |
| Started | Jan 21 09:40:21 PM PST 24 |
| Finished | Jan 21 09:40:27 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-c2924b6e-c026-4e42-ad47-a840c7ea2b5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=746766844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.746766844 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.21574163 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1506621768 ps |
| CPU time | 7.96 seconds |
| Started | Jan 21 10:26:18 PM PST 24 |
| Finished | Jan 21 10:26:43 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-6c1f37b7-5d61-48ac-a6fb-405a550a4c66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=21574163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.21574163 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4261086702 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5508091234 ps |
| CPU time | 8.92 seconds |
| Started | Jan 21 10:15:06 PM PST 24 |
| Finished | Jan 21 10:15:33 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-9f272454-8540-440d-865a-fb3f064bc623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4261086702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4261086702 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2346602104 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 32964326 ps |
| CPU time | 1.38 seconds |
| Started | Jan 21 09:54:49 PM PST 24 |
| Finished | Jan 21 09:54:56 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-98adcf2c-dab3-4130-bda5-55818f2f4557 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346602104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2346602104 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3275930938 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 18156959350 ps |
| CPU time | 47.64 seconds |
| Started | Jan 21 09:40:55 PM PST 24 |
| Finished | Jan 21 09:41:49 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-1e58f853-6087-41c6-a8df-1634692f6674 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3275930938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3275930938 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3643776861 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 393761403 ps |
| CPU time | 12.66 seconds |
| Started | Jan 21 09:40:54 PM PST 24 |
| Finished | Jan 21 09:41:13 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-a10ce890-fa56-4bfb-a36c-bcc349805c43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3643776861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3643776861 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3914895161 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4827618330 ps |
| CPU time | 109.86 seconds |
| Started | Jan 21 09:40:56 PM PST 24 |
| Finished | Jan 21 09:42:56 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-20d36176-a44a-4385-bc9c-60e1183a2f66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3914895161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3914895161 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1252364148 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 702141019 ps |
| CPU time | 15.96 seconds |
| Started | Jan 21 09:41:01 PM PST 24 |
| Finished | Jan 21 09:41:28 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-af6e1e6a-f7f5-4880-9579-6a848908dfa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252364148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1252364148 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2371447945 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 62041275 ps |
| CPU time | 8.11 seconds |
| Started | Jan 21 10:11:10 PM PST 24 |
| Finished | Jan 21 10:11:20 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-ecc0ed0d-2773-4c2c-aa5d-525ca3bf8aa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2371447945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2371447945 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.263415554 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 170688207 ps |
| CPU time | 4.59 seconds |
| Started | Jan 21 09:49:43 PM PST 24 |
| Finished | Jan 21 09:49:49 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-09a98758-19e6-48a8-b656-49f0bb4da6cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=263415554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.263415554 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2063288033 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 330709926022 ps |
| CPU time | 407.77 seconds |
| Started | Jan 21 09:49:36 PM PST 24 |
| Finished | Jan 21 09:56:26 PM PST 24 |
| Peak memory | 204328 kb |
| Host | smart-200c72e5-d3af-49a0-b8c8-6b0ad6701850 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2063288033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2063288033 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4152160340 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 428922133 ps |
| CPU time | 5.25 seconds |
| Started | Jan 21 09:49:40 PM PST 24 |
| Finished | Jan 21 09:49:47 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-5e84cf69-ef7c-4c18-9e1a-8376ab672bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4152160340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4152160340 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2279261240 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 329754318 ps |
| CPU time | 6.04 seconds |
| Started | Jan 21 09:49:41 PM PST 24 |
| Finished | Jan 21 09:49:49 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-4cfa86de-9674-42e0-abdd-c01f2e6330fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2279261240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2279261240 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.3754090408 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 964585383 ps |
| CPU time | 12.4 seconds |
| Started | Jan 21 09:49:34 PM PST 24 |
| Finished | Jan 21 09:49:50 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-60905d47-ee01-4524-8fb5-88a4f5dafda2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754090408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3754090408 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.115871826 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 70557203861 ps |
| CPU time | 65 seconds |
| Started | Jan 21 09:49:35 PM PST 24 |
| Finished | Jan 21 09:50:43 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-346bf92b-b2c3-4e39-94a1-fc0594aae29c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=115871826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.115871826 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2670097210 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 24498122449 ps |
| CPU time | 137.38 seconds |
| Started | Jan 21 09:49:35 PM PST 24 |
| Finished | Jan 21 09:51:55 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-989a8a92-c9d0-49f3-8da5-7ef417823567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2670097210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2670097210 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1907548105 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 22929313 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 09:49:36 PM PST 24 |
| Finished | Jan 21 09:49:40 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-387e28a0-fd4d-4b1d-a3e7-76461d3946a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907548105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1907548105 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.379602963 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1865551433 ps |
| CPU time | 12.42 seconds |
| Started | Jan 21 09:49:43 PM PST 24 |
| Finished | Jan 21 09:49:57 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-fd33ebf8-b810-4bd3-97a4-767ce9e2ad67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379602963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.379602963 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.992283445 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 190322698 ps |
| CPU time | 1.76 seconds |
| Started | Jan 21 09:49:34 PM PST 24 |
| Finished | Jan 21 09:49:39 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-a89163c2-6577-4795-8299-1ce5585d96bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992283445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.992283445 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1433095526 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2832836598 ps |
| CPU time | 9.83 seconds |
| Started | Jan 21 09:49:34 PM PST 24 |
| Finished | Jan 21 09:49:47 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-5ea2c882-aa15-4ed7-aa7f-ea3401ef537c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433095526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1433095526 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.500770478 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3838691338 ps |
| CPU time | 8.26 seconds |
| Started | Jan 21 09:49:35 PM PST 24 |
| Finished | Jan 21 09:49:46 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-9b648de9-ec32-4438-82e8-6b971321d93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=500770478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.500770478 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1349594464 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9457813 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 09:49:35 PM PST 24 |
| Finished | Jan 21 09:49:39 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-1e378067-6420-4a6a-a277-a92a38e0e817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349594464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1349594464 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.534126635 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4725847740 ps |
| CPU time | 40.22 seconds |
| Started | Jan 21 10:51:09 PM PST 24 |
| Finished | Jan 21 10:51:50 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-cac08b7e-c0a8-4c57-b2a8-f4658e73032b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534126635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.534126635 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3421743444 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 405084364 ps |
| CPU time | 8.39 seconds |
| Started | Jan 21 10:28:46 PM PST 24 |
| Finished | Jan 21 10:29:02 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-ccf061c5-86d3-48df-9d3d-a4b0df85bc96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3421743444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3421743444 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3440227279 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 602066200 ps |
| CPU time | 77.5 seconds |
| Started | Jan 21 09:49:40 PM PST 24 |
| Finished | Jan 21 09:50:59 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-3a0849c3-4cdc-4233-b69e-36aab9339091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440227279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.3440227279 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1402492197 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2510452051 ps |
| CPU time | 63.63 seconds |
| Started | Jan 21 09:56:48 PM PST 24 |
| Finished | Jan 21 09:57:59 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-ddbb417d-8f4e-4fca-ad85-b226b706da43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402492197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1402492197 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1224371363 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 289765644 ps |
| CPU time | 5.68 seconds |
| Started | Jan 21 10:59:18 PM PST 24 |
| Finished | Jan 21 10:59:25 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-3d9e1f47-792a-4672-a0fb-0f41bdbad335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1224371363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1224371363 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1593643293 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 22668981 ps |
| CPU time | 4.22 seconds |
| Started | Jan 21 09:49:56 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-db1b4d78-c549-4eac-b9cf-e2bd24c0500c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593643293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1593643293 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3147398745 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1298804050 ps |
| CPU time | 6.34 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-fbd1c52f-0db1-452b-8e88-eee8633208fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147398745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3147398745 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.110276674 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1333763155 ps |
| CPU time | 13.13 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:15 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-1b63b858-4cb0-4f3a-afe9-09bd065a2fd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=110276674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.110276674 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2878612449 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 266499660 ps |
| CPU time | 5.31 seconds |
| Started | Jan 21 09:49:56 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-6db761cd-b0c3-4a08-88fc-aab802113d2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878612449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2878612449 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3380277387 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 13241677311 ps |
| CPU time | 31.78 seconds |
| Started | Jan 21 09:49:53 PM PST 24 |
| Finished | Jan 21 09:50:33 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-f69bd393-3156-48c4-a861-a1af619ac169 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380277387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3380277387 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2282620764 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 24699083818 ps |
| CPU time | 106.8 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:51:49 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-4dbe3024-f59a-495d-bbb3-108b5bb85144 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2282620764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2282620764 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1273617192 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 24298194 ps |
| CPU time | 2.54 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:05 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-ca05b002-6350-4003-80be-6593482ef666 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273617192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1273617192 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1683570185 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 29000284 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 09:49:57 PM PST 24 |
| Finished | Jan 21 09:50:08 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-76846c08-08b5-4339-9804-b189a82c8ed1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683570185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1683570185 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.690932659 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 72526263 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 09:49:41 PM PST 24 |
| Finished | Jan 21 09:49:44 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-4449ada8-fb39-4179-b910-afb1a12ed012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690932659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.690932659 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.450922656 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4397848868 ps |
| CPU time | 11.87 seconds |
| Started | Jan 21 09:49:53 PM PST 24 |
| Finished | Jan 21 09:50:14 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-f3a88968-40e6-487d-bfae-94b9aa7e8643 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=450922656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.450922656 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2740333496 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 743806933 ps |
| CPU time | 6.33 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:08 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-594025e3-54dd-423e-9698-9130b7b1275c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2740333496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2740333496 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.246074603 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 13211841 ps |
| CPU time | 1.34 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:04 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-60d5977d-af7a-45c0-af8f-d84c69e70434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246074603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.246074603 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2739340139 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 10788518341 ps |
| CPU time | 82.69 seconds |
| Started | Jan 21 09:49:55 PM PST 24 |
| Finished | Jan 21 09:51:26 PM PST 24 |
| Peak memory | 203308 kb |
| Host | smart-2ef0becb-0779-4dea-820d-1930c89392f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2739340139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2739340139 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.896561703 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 474773066 ps |
| CPU time | 30.72 seconds |
| Started | Jan 21 09:49:55 PM PST 24 |
| Finished | Jan 21 09:50:34 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-a0fd812e-6739-4308-bf78-31b7d4d5d9b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=896561703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.896561703 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1492753085 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 885464761 ps |
| CPU time | 137.28 seconds |
| Started | Jan 21 10:14:33 PM PST 24 |
| Finished | Jan 21 10:16:53 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-de267ff7-a27b-4cba-a74a-1032479ef963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492753085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1492753085 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2921792057 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 61920803 ps |
| CPU time | 8.12 seconds |
| Started | Jan 21 09:49:54 PM PST 24 |
| Finished | Jan 21 09:50:10 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-927002e7-57c4-41e7-9c19-8a3230bbf7bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2921792057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2921792057 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2800668928 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 44816114 ps |
| CPU time | 7.89 seconds |
| Started | Jan 21 10:14:49 PM PST 24 |
| Finished | Jan 21 10:15:06 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-a684e6e8-8888-4409-b2f5-dbf42ca76d35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2800668928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2800668928 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3886385041 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 132120007 ps |
| CPU time | 2.72 seconds |
| Started | Jan 21 09:50:16 PM PST 24 |
| Finished | Jan 21 09:50:31 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-ec959dd7-4624-4c73-ae1c-78caa021039c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3886385041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3886385041 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.4020400660 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1413883222 ps |
| CPU time | 8.08 seconds |
| Started | Jan 21 09:50:12 PM PST 24 |
| Finished | Jan 21 09:50:26 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-43140575-e76b-42d4-9164-90cfe1b09460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4020400660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4020400660 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2111970141 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 200678295 ps |
| CPU time | 10.8 seconds |
| Started | Jan 21 09:50:04 PM PST 24 |
| Finished | Jan 21 09:50:19 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-9dd83655-39d8-410e-95e7-7a3fdb1811a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111970141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2111970141 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.752150921 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 52866677415 ps |
| CPU time | 147.48 seconds |
| Started | Jan 21 09:50:13 PM PST 24 |
| Finished | Jan 21 09:52:46 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-5e81ded6-033c-4e7e-a540-4870f38b2db6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=752150921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.752150921 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3479545681 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 11695322904 ps |
| CPU time | 64.74 seconds |
| Started | Jan 21 09:50:13 PM PST 24 |
| Finished | Jan 21 09:51:24 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-bf79ea3c-18f1-4f89-a432-ad62ee04faa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3479545681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3479545681 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4288700643 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 29090793 ps |
| CPU time | 2.59 seconds |
| Started | Jan 21 09:50:10 PM PST 24 |
| Finished | Jan 21 09:50:16 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-d904565c-a730-4f64-9889-eb2645a27f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288700643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4288700643 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2503520024 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 264049998 ps |
| CPU time | 5.33 seconds |
| Started | Jan 21 09:50:13 PM PST 24 |
| Finished | Jan 21 09:50:24 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-c5f934e1-6bbc-4a7c-90ce-44101d2cd6e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2503520024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2503520024 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2850524229 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 9394012 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 09:49:55 PM PST 24 |
| Finished | Jan 21 09:50:05 PM PST 24 |
| Peak memory | 201692 kb |
| Host | smart-ebb5506e-7c36-46b8-8889-94c1ced8c443 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850524229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2850524229 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.711425091 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1633076072 ps |
| CPU time | 6.73 seconds |
| Started | Jan 21 09:50:05 PM PST 24 |
| Finished | Jan 21 09:50:15 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-098d0eb6-19a3-49be-a03d-b4b1f4b7a0b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=711425091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.711425091 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2656482787 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1140249843 ps |
| CPU time | 7.72 seconds |
| Started | Jan 21 09:50:08 PM PST 24 |
| Finished | Jan 21 09:50:18 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-31bb5d9f-5b8d-44a7-a95a-fb8a738cc8c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2656482787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2656482787 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2814078706 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8828725 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 09:50:03 PM PST 24 |
| Finished | Jan 21 09:50:09 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-e39fa27c-575f-4cc6-9f05-f7ade13967ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814078706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2814078706 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.164553957 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1654435860 ps |
| CPU time | 33.39 seconds |
| Started | Jan 21 10:29:44 PM PST 24 |
| Finished | Jan 21 10:30:21 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-51f20f93-57f3-4d9f-9f00-df25bc7b678c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=164553957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.164553957 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2094163628 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 57997536 ps |
| CPU time | 6.55 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:50:33 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-ee19f449-a3d0-4e6b-8fce-911b9e13c665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2094163628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2094163628 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3009696260 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1342589499 ps |
| CPU time | 145.78 seconds |
| Started | Jan 21 10:04:01 PM PST 24 |
| Finished | Jan 21 10:06:28 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-f6b0d2db-21d6-45bb-bf3a-a44e6e1463df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3009696260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3009696260 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.830091950 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 318173296 ps |
| CPU time | 5.38 seconds |
| Started | Jan 21 09:50:14 PM PST 24 |
| Finished | Jan 21 09:50:26 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-84156d82-aed8-473d-8714-0cf11677f786 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830091950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.830091950 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3769468884 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 68514045 ps |
| CPU time | 13.57 seconds |
| Started | Jan 21 09:50:19 PM PST 24 |
| Finished | Jan 21 09:50:44 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-da6136af-5e15-4bf9-a428-d26cc75e5d34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769468884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3769468884 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3102547046 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 78250947557 ps |
| CPU time | 245.26 seconds |
| Started | Jan 21 09:50:20 PM PST 24 |
| Finished | Jan 21 09:54:36 PM PST 24 |
| Peak memory | 203896 kb |
| Host | smart-5db19a1d-bae2-4a70-8c9f-012315dd5ed0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3102547046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3102547046 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.630670778 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 656863474 ps |
| CPU time | 5.67 seconds |
| Started | Jan 21 09:50:18 PM PST 24 |
| Finished | Jan 21 09:50:35 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-ac9168b5-1b01-4204-9113-81ea63d2b63f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630670778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.630670778 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.3954640180 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 69944354 ps |
| CPU time | 1.57 seconds |
| Started | Jan 21 09:50:18 PM PST 24 |
| Finished | Jan 21 09:50:31 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-0dfd4258-bd66-4dd3-90c1-64d5d4af3b34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3954640180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3954640180 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.3406087160 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 129908359 ps |
| CPU time | 2.99 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:50:30 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-15ba95dc-e0e9-4667-9f39-b0b903a1f734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406087160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3406087160 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4254768559 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 31122095806 ps |
| CPU time | 114.65 seconds |
| Started | Jan 21 09:50:14 PM PST 24 |
| Finished | Jan 21 09:52:21 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-ab17e0d7-51c5-4d25-a81a-8a76614dbcb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254768559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4254768559 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1437259872 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1544795991 ps |
| CPU time | 10.55 seconds |
| Started | Jan 21 09:50:19 PM PST 24 |
| Finished | Jan 21 09:50:41 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-c8ae017b-cc40-4de7-baa9-fd548ae30165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1437259872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1437259872 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2925984880 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 93292018 ps |
| CPU time | 4.75 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:50:31 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-c75b1edb-5e76-448b-a539-336745093a77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925984880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2925984880 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2970680058 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 376186397 ps |
| CPU time | 5.49 seconds |
| Started | Jan 21 09:50:20 PM PST 24 |
| Finished | Jan 21 09:50:36 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-59a1c738-d248-4740-aedc-e646897e2b4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970680058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2970680058 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.456934779 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9974282 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 09:50:16 PM PST 24 |
| Finished | Jan 21 09:50:29 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-7dc6d8b5-5898-4c29-8fda-5e0005218590 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456934779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.456934779 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1289652044 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4940673768 ps |
| CPU time | 11.28 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:50:38 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-f5771e8f-6efb-47b8-8012-a9457022f6a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289652044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1289652044 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3461597362 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 982329073 ps |
| CPU time | 7.73 seconds |
| Started | Jan 21 10:13:26 PM PST 24 |
| Finished | Jan 21 10:13:37 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-d311823f-ff8c-431d-8226-8b9cc56a9f48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3461597362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3461597362 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.365237861 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 16893355 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 09:50:15 PM PST 24 |
| Finished | Jan 21 09:50:28 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-c5a0ebb9-ddff-4718-8602-65b7d15fae62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365237861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.365237861 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2044000510 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3548131203 ps |
| CPU time | 45.67 seconds |
| Started | Jan 21 09:50:20 PM PST 24 |
| Finished | Jan 21 09:51:17 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-8b72cbb5-9278-4af8-b8a9-23e8d47788dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2044000510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2044000510 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.900221636 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5436704311 ps |
| CPU time | 23.42 seconds |
| Started | Jan 21 09:50:33 PM PST 24 |
| Finished | Jan 21 09:51:03 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-b6812308-0583-460b-a393-09dfe9b53028 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900221636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.900221636 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1444984076 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 230253505 ps |
| CPU time | 33.91 seconds |
| Started | Jan 21 09:50:30 PM PST 24 |
| Finished | Jan 21 09:51:12 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-2244f24f-8198-4316-bd44-c336d49e62bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1444984076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1444984076 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3173296752 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 9731878649 ps |
| CPU time | 105.49 seconds |
| Started | Jan 21 09:50:34 PM PST 24 |
| Finished | Jan 21 09:52:26 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-7030407b-ada2-446a-a09f-5326c3fc999b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3173296752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3173296752 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2076278906 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 85733632 ps |
| CPU time | 6.67 seconds |
| Started | Jan 21 09:50:20 PM PST 24 |
| Finished | Jan 21 09:50:38 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-2c287eba-15c7-4923-80fd-8aaadc2957c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2076278906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2076278906 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.847546657 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 72776562 ps |
| CPU time | 13.42 seconds |
| Started | Jan 21 09:50:34 PM PST 24 |
| Finished | Jan 21 09:50:54 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-135c5145-6d70-42da-8246-bcce1c0148f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=847546657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.847546657 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1326404134 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 27429124331 ps |
| CPU time | 70.64 seconds |
| Started | Jan 21 09:50:35 PM PST 24 |
| Finished | Jan 21 09:51:51 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-a68c4a43-dd1a-4d3a-8bd9-abcb8de1d65c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1326404134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1326404134 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1057562056 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 510621404 ps |
| CPU time | 2.78 seconds |
| Started | Jan 21 09:50:39 PM PST 24 |
| Finished | Jan 21 09:50:46 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-bfb5966c-bdb0-46fb-91ea-1aa826e22bc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1057562056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1057562056 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.703067507 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 671152900 ps |
| CPU time | 12.63 seconds |
| Started | Jan 21 09:50:30 PM PST 24 |
| Finished | Jan 21 09:50:51 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-e76493ef-0532-48ba-96f3-362dcb170ea4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=703067507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.703067507 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.1251097331 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1336344292 ps |
| CPU time | 13.6 seconds |
| Started | Jan 21 09:50:30 PM PST 24 |
| Finished | Jan 21 09:50:52 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-b0218f9b-b792-41e3-a4de-af89a4144d52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251097331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1251097331 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.664563023 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 54100073489 ps |
| CPU time | 156.26 seconds |
| Started | Jan 21 09:50:29 PM PST 24 |
| Finished | Jan 21 09:53:14 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-ae5b3616-7073-42f9-a46d-65a0371a1a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=664563023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.664563023 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3295557584 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 8039818814 ps |
| CPU time | 55.6 seconds |
| Started | Jan 21 09:50:36 PM PST 24 |
| Finished | Jan 21 09:51:37 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-90268281-d617-4ea0-9d5f-791d41c53498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3295557584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3295557584 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2335441037 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 8841044 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 09:50:35 PM PST 24 |
| Finished | Jan 21 09:50:42 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-6938addc-e37b-41ac-90bf-65801ec7bc36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335441037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2335441037 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.426873804 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2640937882 ps |
| CPU time | 13.26 seconds |
| Started | Jan 21 09:50:34 PM PST 24 |
| Finished | Jan 21 09:50:54 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-7b152ac0-c318-4f0d-a49c-cd874f9fbeaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=426873804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.426873804 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1228574132 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 77148612 ps |
| CPU time | 1.45 seconds |
| Started | Jan 21 09:50:29 PM PST 24 |
| Finished | Jan 21 09:50:39 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-30aecc14-c8e4-43f4-9485-5c06e86e6575 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228574132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1228574132 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.491566042 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1485274076 ps |
| CPU time | 6.8 seconds |
| Started | Jan 21 09:50:30 PM PST 24 |
| Finished | Jan 21 09:50:45 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-8c7c01c1-4bc8-44c2-8e09-cebd5bc0e534 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=491566042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.491566042 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1207271914 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 676095494 ps |
| CPU time | 5.78 seconds |
| Started | Jan 21 09:50:33 PM PST 24 |
| Finished | Jan 21 09:50:45 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-5579a7f9-19fb-4c24-a246-47273d0a4dc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1207271914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1207271914 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.843588166 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 9647682 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 09:50:35 PM PST 24 |
| Finished | Jan 21 09:50:42 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-69004201-92f3-49fd-98cd-04674c277049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843588166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.843588166 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1660153189 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 444913627 ps |
| CPU time | 34.26 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:51:17 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-8d456379-7dee-4fda-8490-75fe31687bd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660153189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1660153189 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.867957337 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 769135312 ps |
| CPU time | 8.85 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:50:52 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-53caad52-f5a1-4cb6-938c-4f6edd7f4251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=867957337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.867957337 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3417240503 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 614122188 ps |
| CPU time | 135.15 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:52:58 PM PST 24 |
| Peak memory | 206404 kb |
| Host | smart-593e55c4-38a7-48cb-be0c-3560b3c03fd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417240503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3417240503 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1390138757 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3873641155 ps |
| CPU time | 126.24 seconds |
| Started | Jan 21 09:50:39 PM PST 24 |
| Finished | Jan 21 09:52:50 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-d300ba8f-e1f0-4a9a-aa37-3dc91c071cc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1390138757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1390138757 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3694953194 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 33594802 ps |
| CPU time | 3.65 seconds |
| Started | Jan 21 09:50:31 PM PST 24 |
| Finished | Jan 21 09:50:42 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-756ea0e0-195e-48fd-97bc-260fa3f90824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3694953194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3694953194 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2632484400 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 124980306 ps |
| CPU time | 10.7 seconds |
| Started | Jan 21 09:50:58 PM PST 24 |
| Finished | Jan 21 09:51:13 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-098edc0d-3e7a-4fef-9c68-71ec6f30a4ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2632484400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2632484400 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2576627348 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 30517479757 ps |
| CPU time | 72.61 seconds |
| Started | Jan 21 09:50:54 PM PST 24 |
| Finished | Jan 21 09:52:11 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-1235615e-376a-424c-9edc-01f07739e120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2576627348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2576627348 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3571673470 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 102536798 ps |
| CPU time | 4.36 seconds |
| Started | Jan 21 09:50:53 PM PST 24 |
| Finished | Jan 21 09:51:02 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-f43415cf-ff0c-4a2f-98f2-bb72b390eb93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3571673470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3571673470 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.3586201507 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1602681776 ps |
| CPU time | 16.28 seconds |
| Started | Jan 21 09:50:55 PM PST 24 |
| Finished | Jan 21 09:51:16 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-6392ebde-ac2c-4e13-8ba4-8d17c84f373b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3586201507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3586201507 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.1492380088 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 315272116 ps |
| CPU time | 9.43 seconds |
| Started | Jan 21 09:50:51 PM PST 24 |
| Finished | Jan 21 09:51:04 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-db636b12-8efe-443a-8c77-d2130c357a7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492380088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1492380088 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.4057291686 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 39466616765 ps |
| CPU time | 79.25 seconds |
| Started | Jan 21 09:50:59 PM PST 24 |
| Finished | Jan 21 09:52:23 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-b7e5779b-336a-41b0-b230-a6f3df93c275 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057291686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.4057291686 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2008374331 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 26864320706 ps |
| CPU time | 53.34 seconds |
| Started | Jan 21 09:50:57 PM PST 24 |
| Finished | Jan 21 09:51:55 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-424dbd26-d7e6-4f67-af6e-4b4921ddc323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2008374331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2008374331 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2247274528 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 73020229 ps |
| CPU time | 4.31 seconds |
| Started | Jan 21 09:50:50 PM PST 24 |
| Finished | Jan 21 09:50:57 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-ef581bd7-958e-43d9-9614-88855e6490ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247274528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2247274528 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.2168433579 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1248594197 ps |
| CPU time | 11.86 seconds |
| Started | Jan 21 09:50:52 PM PST 24 |
| Finished | Jan 21 09:51:08 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-d1eab048-ecce-4853-b250-55c854c51ac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168433579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2168433579 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.62092002 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 175988227 ps |
| CPU time | 1.44 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:50:44 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-cd64a292-2afa-4e39-99c8-daefe99da8db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=62092002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.62092002 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.318794418 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2812287601 ps |
| CPU time | 9.99 seconds |
| Started | Jan 21 09:50:39 PM PST 24 |
| Finished | Jan 21 09:50:53 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-486bb995-7efa-43e3-a507-ebf4eb85dd43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=318794418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.318794418 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2098407809 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2016709885 ps |
| CPU time | 8.19 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:50:51 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-5810bd9e-c81c-4684-bd44-73cba13e96d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2098407809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2098407809 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1410879525 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 11182254 ps |
| CPU time | 1.42 seconds |
| Started | Jan 21 09:50:38 PM PST 24 |
| Finished | Jan 21 09:50:44 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-15a53728-f3eb-4714-ade5-c8c1df86307d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410879525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1410879525 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3170613425 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 7760603481 ps |
| CPU time | 132.86 seconds |
| Started | Jan 21 09:50:59 PM PST 24 |
| Finished | Jan 21 09:53:16 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-cef96f8c-a0dc-4f32-ad02-e422ce19aade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3170613425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3170613425 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1299738865 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 431269854 ps |
| CPU time | 10.45 seconds |
| Started | Jan 21 09:50:59 PM PST 24 |
| Finished | Jan 21 09:51:14 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-55f56ffb-7e25-48f3-97d3-2583fbee2634 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1299738865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1299738865 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3463380170 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 75069565 ps |
| CPU time | 8.65 seconds |
| Started | Jan 21 09:50:54 PM PST 24 |
| Finished | Jan 21 09:51:07 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-2af603a0-b7c7-40bf-95c0-3cc6c62372b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463380170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3463380170 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2859488641 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 156941857 ps |
| CPU time | 4.51 seconds |
| Started | Jan 21 09:50:51 PM PST 24 |
| Finished | Jan 21 09:50:59 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-d04c86c8-ad1a-4444-aa8d-947918b04fdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2859488641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2859488641 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1727798542 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 465516444 ps |
| CPU time | 5.05 seconds |
| Started | Jan 21 09:51:05 PM PST 24 |
| Finished | Jan 21 09:51:11 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-20e75ecf-400f-4d5b-9df9-585528009054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1727798542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1727798542 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1941804940 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 22937203 ps |
| CPU time | 1.56 seconds |
| Started | Jan 21 10:02:40 PM PST 24 |
| Finished | Jan 21 10:02:48 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-111e925d-dcbf-475a-89ef-616b14f58a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941804940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1941804940 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.2656780917 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 613507440 ps |
| CPU time | 8.21 seconds |
| Started | Jan 21 09:51:03 PM PST 24 |
| Finished | Jan 21 09:51:13 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-ef8fb416-f909-4395-bc66-e02dabce6716 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2656780917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2656780917 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.1636925729 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 44022857 ps |
| CPU time | 1.35 seconds |
| Started | Jan 21 09:50:53 PM PST 24 |
| Finished | Jan 21 09:50:59 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-9edf5b8c-e23b-42d3-b92e-989d351fa5bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636925729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1636925729 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1883761815 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 47310502945 ps |
| CPU time | 82.77 seconds |
| Started | Jan 21 09:51:05 PM PST 24 |
| Finished | Jan 21 09:52:29 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-fdc7d6de-86cf-472d-a80d-3c697c96d59c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883761815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1883761815 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.713111846 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 46591971020 ps |
| CPU time | 168.94 seconds |
| Started | Jan 21 09:51:02 PM PST 24 |
| Finished | Jan 21 09:53:53 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-e8ef7297-5c96-44f0-be14-5da029eadd99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=713111846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.713111846 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.181607632 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 74301948 ps |
| CPU time | 7.28 seconds |
| Started | Jan 21 09:51:06 PM PST 24 |
| Finished | Jan 21 09:51:15 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-b490b4ef-f019-4345-bbb5-d5a72148c6c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181607632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.181607632 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.458238254 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1142884468 ps |
| CPU time | 13.53 seconds |
| Started | Jan 21 10:16:08 PM PST 24 |
| Finished | Jan 21 10:16:32 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-46329381-d6c1-487e-97c8-f5d57f510525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=458238254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.458238254 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2240631314 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 10835389 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 09:51:03 PM PST 24 |
| Finished | Jan 21 09:51:06 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-ea50bea0-df4e-40e5-8e9a-3c20485a3119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2240631314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2240631314 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2790000385 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 9213379565 ps |
| CPU time | 10.55 seconds |
| Started | Jan 21 09:50:55 PM PST 24 |
| Finished | Jan 21 09:51:11 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-85119be3-545b-4359-a3fb-150fce14bc4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790000385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2790000385 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.367936245 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2067358437 ps |
| CPU time | 10.65 seconds |
| Started | Jan 21 09:51:03 PM PST 24 |
| Finished | Jan 21 09:51:15 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-3e2a59b9-d131-481f-94c7-579fcce6a977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=367936245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.367936245 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.754005702 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 19603742 ps |
| CPU time | 1.29 seconds |
| Started | Jan 21 09:50:54 PM PST 24 |
| Finished | Jan 21 09:51:00 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-0b3e24e1-9c8f-4aad-860c-33f12c3c3723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754005702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.754005702 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.919842681 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5749479897 ps |
| CPU time | 32.39 seconds |
| Started | Jan 21 09:51:13 PM PST 24 |
| Finished | Jan 21 09:51:52 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-31c29d09-d3bb-4675-abc2-532b3f305c34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919842681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.919842681 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.766908642 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 10961599459 ps |
| CPU time | 34.24 seconds |
| Started | Jan 21 09:56:53 PM PST 24 |
| Finished | Jan 21 09:57:33 PM PST 24 |
| Peak memory | 201884 kb |
| Host | smart-bc0b9992-006a-4c1b-8d73-4d9ad3566c06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=766908642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.766908642 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2600970270 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 932397003 ps |
| CPU time | 154.47 seconds |
| Started | Jan 21 09:51:14 PM PST 24 |
| Finished | Jan 21 09:53:54 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-8124bfd3-fccb-4011-aad9-6170f73fd406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2600970270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2600970270 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4054451098 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1841165469 ps |
| CPU time | 168.98 seconds |
| Started | Jan 21 09:51:11 PM PST 24 |
| Finished | Jan 21 09:54:08 PM PST 24 |
| Peak memory | 205780 kb |
| Host | smart-3b07f79f-6358-4e6c-9a15-03892a4c5a89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054451098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.4054451098 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2030058488 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 105263584 ps |
| CPU time | 5.69 seconds |
| Started | Jan 21 09:51:01 PM PST 24 |
| Finished | Jan 21 09:51:10 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-4bc02e24-ec4e-46b1-8c0b-b75dea4f3792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2030058488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2030058488 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.886122504 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 320568312 ps |
| CPU time | 8.61 seconds |
| Started | Jan 21 10:30:18 PM PST 24 |
| Finished | Jan 21 10:30:39 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-8324d1cc-b54d-48eb-a606-90038d3c8206 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=886122504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.886122504 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4204436727 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 288423913306 ps |
| CPU time | 307 seconds |
| Started | Jan 21 09:51:22 PM PST 24 |
| Finished | Jan 21 09:56:34 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-06ae6fd3-295d-47bc-83e0-dec505541547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4204436727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.4204436727 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3636619356 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 832047874 ps |
| CPU time | 11.44 seconds |
| Started | Jan 21 09:51:28 PM PST 24 |
| Finished | Jan 21 09:51:45 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-daf86033-6c34-462f-90d6-44bd7c834b81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3636619356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3636619356 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.845858273 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12023034 ps |
| CPU time | 1.57 seconds |
| Started | Jan 21 09:51:25 PM PST 24 |
| Finished | Jan 21 09:51:30 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-2cae4e5b-c461-4814-96c8-da809be5a1ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=845858273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.845858273 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.3432494947 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1134461661 ps |
| CPU time | 13.84 seconds |
| Started | Jan 21 10:04:15 PM PST 24 |
| Finished | Jan 21 10:04:30 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-63565929-2fae-4c9a-906e-b38ecd8d0f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432494947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3432494947 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.235389320 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 66676027501 ps |
| CPU time | 83.05 seconds |
| Started | Jan 21 09:51:21 PM PST 24 |
| Finished | Jan 21 09:52:50 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-480a50b8-e85f-465c-b642-677fe2cfe359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=235389320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.235389320 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.4139920997 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 11254857248 ps |
| CPU time | 47.27 seconds |
| Started | Jan 21 09:51:21 PM PST 24 |
| Finished | Jan 21 09:52:14 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-dbf1277d-2964-44c2-839e-fe79b1eeb8a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4139920997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.4139920997 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1125957311 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 151465613 ps |
| CPU time | 3.45 seconds |
| Started | Jan 21 09:51:21 PM PST 24 |
| Finished | Jan 21 09:51:30 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-e76fb2ff-ba58-4acc-9bd2-d889b6755cb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125957311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1125957311 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.1729497730 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 371611812 ps |
| CPU time | 5.61 seconds |
| Started | Jan 21 09:51:24 PM PST 24 |
| Finished | Jan 21 09:51:34 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-8a6e5f9d-77f5-46ac-a755-2fc5752fb4d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729497730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1729497730 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2301166599 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8202997 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 10:26:46 PM PST 24 |
| Finished | Jan 21 10:27:04 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-5590a219-8ef9-4710-8b42-d00ef4fbcd54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301166599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2301166599 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1049928363 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4664626783 ps |
| CPU time | 9.02 seconds |
| Started | Jan 21 09:51:11 PM PST 24 |
| Finished | Jan 21 09:51:28 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-f29290aa-b99a-4729-b7ef-33c88de69226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049928363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1049928363 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1202140855 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7261327110 ps |
| CPU time | 6.77 seconds |
| Started | Jan 21 09:51:20 PM PST 24 |
| Finished | Jan 21 09:51:33 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-fed7d9ea-ad8f-4fc2-bf8c-86b4df42d345 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1202140855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1202140855 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3233065838 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 16043251 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 09:51:11 PM PST 24 |
| Finished | Jan 21 09:51:20 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-c25e767c-f63d-4b48-90dd-e025d003ebde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233065838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3233065838 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3827025997 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 423294431 ps |
| CPU time | 43.99 seconds |
| Started | Jan 21 09:51:25 PM PST 24 |
| Finished | Jan 21 09:52:12 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-07bcbd5d-869f-4fc9-ba74-268faf99e649 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3827025997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3827025997 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.971610894 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 375501337 ps |
| CPU time | 46 seconds |
| Started | Jan 21 09:51:24 PM PST 24 |
| Finished | Jan 21 09:52:14 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-a1f04b43-b8a8-4858-a7a7-6f58d073ef5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=971610894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.971610894 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.782830564 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3953216261 ps |
| CPU time | 115.15 seconds |
| Started | Jan 21 09:51:27 PM PST 24 |
| Finished | Jan 21 09:53:27 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-440be63a-a5c1-46af-aed3-b0cd362c6bfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=782830564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.782830564 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3112973799 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7315792062 ps |
| CPU time | 124.49 seconds |
| Started | Jan 21 09:51:29 PM PST 24 |
| Finished | Jan 21 09:53:38 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-89304bf3-89e9-48e9-8331-1ad27737effc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3112973799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3112973799 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2618891140 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 276717410 ps |
| CPU time | 4.34 seconds |
| Started | Jan 21 11:21:11 PM PST 24 |
| Finished | Jan 21 11:21:16 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-40f3622f-cb25-4755-bc7d-5f9d6cc1b2fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2618891140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2618891140 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2867660117 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 689746774 ps |
| CPU time | 7.14 seconds |
| Started | Jan 21 09:51:26 PM PST 24 |
| Finished | Jan 21 09:51:36 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-e4604ff7-2766-40fe-a683-1c84add29500 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2867660117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2867660117 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3961481883 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 16429190988 ps |
| CPU time | 91.27 seconds |
| Started | Jan 22 12:03:25 AM PST 24 |
| Finished | Jan 22 12:05:09 AM PST 24 |
| Peak memory | 201976 kb |
| Host | smart-22425d44-c303-4657-b82b-23568d143ac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3961481883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3961481883 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3622107339 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 483952354 ps |
| CPU time | 7.79 seconds |
| Started | Jan 21 09:51:35 PM PST 24 |
| Finished | Jan 21 09:51:50 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-091aeb6c-2d01-4acb-b445-05dd03e077fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3622107339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3622107339 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1871362643 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 85964203 ps |
| CPU time | 7.21 seconds |
| Started | Jan 21 09:51:38 PM PST 24 |
| Finished | Jan 21 09:51:53 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-b706efcb-c1ac-4f8a-833b-5b31995f7071 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871362643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1871362643 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2476763722 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1537394202 ps |
| CPU time | 8.94 seconds |
| Started | Jan 21 09:51:28 PM PST 24 |
| Finished | Jan 21 09:51:42 PM PST 24 |
| Peak memory | 202008 kb |
| Host | smart-2e37094b-3453-4c79-8b5c-7046be9f045b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2476763722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2476763722 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3462631555 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5467427434 ps |
| CPU time | 21.67 seconds |
| Started | Jan 21 10:12:10 PM PST 24 |
| Finished | Jan 21 10:12:34 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-8c90f00e-cbd8-4ada-907c-65f3f1512ebd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462631555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3462631555 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1535601568 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5791132492 ps |
| CPU time | 45.1 seconds |
| Started | Jan 21 09:51:26 PM PST 24 |
| Finished | Jan 21 09:52:14 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-af1bf908-5432-4e93-975b-a5e479ae09e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1535601568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1535601568 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.274075596 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 23404550 ps |
| CPU time | 3.25 seconds |
| Started | Jan 21 10:36:07 PM PST 24 |
| Finished | Jan 21 10:36:14 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-d67d80b9-4849-4838-ba39-df1b1dbe0c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274075596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.274075596 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.953398383 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 393040588 ps |
| CPU time | 5.88 seconds |
| Started | Jan 21 10:22:14 PM PST 24 |
| Finished | Jan 21 10:22:25 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-00837921-7ccc-4525-b841-5693dc2f4b7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=953398383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.953398383 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1628834759 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 8729005 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 09:51:25 PM PST 24 |
| Finished | Jan 21 09:51:29 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-dce5a14d-fcb0-40ac-ba4c-414828b1019d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628834759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1628834759 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.456384596 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1832930868 ps |
| CPU time | 7.12 seconds |
| Started | Jan 21 09:51:26 PM PST 24 |
| Finished | Jan 21 09:51:36 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-e8624d9c-b02b-48a8-9eef-b6b0c0ba3e3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=456384596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.456384596 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2709136814 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1089017202 ps |
| CPU time | 5.9 seconds |
| Started | Jan 21 10:35:02 PM PST 24 |
| Finished | Jan 21 10:35:12 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-e77ec218-862f-4a01-b12b-d9556a66bd18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2709136814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2709136814 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1360151951 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 10670209 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 09:51:25 PM PST 24 |
| Finished | Jan 21 09:51:30 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-08b9364a-aa82-4606-a506-c6cb2a1ad6f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360151951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1360151951 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1013662062 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 516812953 ps |
| CPU time | 62.13 seconds |
| Started | Jan 21 09:51:39 PM PST 24 |
| Finished | Jan 21 09:52:49 PM PST 24 |
| Peak memory | 201712 kb |
| Host | smart-3ec729c8-f7c0-4c13-949b-fece1a78130a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013662062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1013662062 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2347578029 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 509685715 ps |
| CPU time | 21.32 seconds |
| Started | Jan 21 09:51:35 PM PST 24 |
| Finished | Jan 21 09:52:04 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-e1eedf5e-6a5e-4a78-b3b8-0b646e63d759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347578029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2347578029 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3914761297 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2684072356 ps |
| CPU time | 50.13 seconds |
| Started | Jan 21 09:51:36 PM PST 24 |
| Finished | Jan 21 09:52:34 PM PST 24 |
| Peak memory | 203268 kb |
| Host | smart-7b19142e-ef83-4732-8039-afcd20300526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3914761297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3914761297 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2062335789 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 56656887 ps |
| CPU time | 1.96 seconds |
| Started | Jan 21 10:07:10 PM PST 24 |
| Finished | Jan 21 10:07:17 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-c3fbb40a-79a6-44d2-ab9c-bffc2f4c1653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2062335789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2062335789 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1825750861 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 279266296 ps |
| CPU time | 5.27 seconds |
| Started | Jan 21 09:51:47 PM PST 24 |
| Finished | Jan 21 09:51:55 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-7e5db953-ea8c-4b35-a009-092f0b83dfd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825750861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1825750861 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.153654423 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 14803989864 ps |
| CPU time | 114.75 seconds |
| Started | Jan 21 09:51:46 PM PST 24 |
| Finished | Jan 21 09:53:44 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-8366e7bf-5bd5-4042-9427-846c1eaf7fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=153654423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.153654423 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2498147215 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 58195112 ps |
| CPU time | 5.62 seconds |
| Started | Jan 21 09:51:46 PM PST 24 |
| Finished | Jan 21 09:51:55 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-3a705ddb-1c22-4761-a4a2-17a3f5ba692a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2498147215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2498147215 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.4109368608 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1163644051 ps |
| CPU time | 12.02 seconds |
| Started | Jan 21 09:51:47 PM PST 24 |
| Finished | Jan 21 09:52:01 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-d2c652df-94ef-4518-8b0f-2396919c9bb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4109368608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4109368608 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3654574026 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 94062470 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 09:51:36 PM PST 24 |
| Finished | Jan 21 09:51:51 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-0f96241b-b514-41c6-8f6e-d546f1845c2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3654574026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3654574026 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1909614961 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 45806573184 ps |
| CPU time | 135.27 seconds |
| Started | Jan 21 09:51:50 PM PST 24 |
| Finished | Jan 21 09:54:07 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-deb3c89a-54e0-42cc-89fe-5757a9be32f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909614961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1909614961 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.429870900 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 33239949937 ps |
| CPU time | 166.16 seconds |
| Started | Jan 21 09:51:48 PM PST 24 |
| Finished | Jan 21 09:54:36 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-9ffc8ac6-6dbd-4c4e-8887-dab78958ffbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=429870900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.429870900 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3825806665 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 75448662 ps |
| CPU time | 8.38 seconds |
| Started | Jan 21 09:51:48 PM PST 24 |
| Finished | Jan 21 09:51:58 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-e2f97318-ee7e-46c7-bbe3-6df1ace6b489 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825806665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3825806665 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.930339631 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 25549944 ps |
| CPU time | 2.53 seconds |
| Started | Jan 21 09:51:47 PM PST 24 |
| Finished | Jan 21 09:51:52 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-6f990808-907e-46b5-8eb3-1a92411dabc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930339631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.930339631 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3649556044 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 51007727 ps |
| CPU time | 1.55 seconds |
| Started | Jan 21 09:51:39 PM PST 24 |
| Finished | Jan 21 09:51:48 PM PST 24 |
| Peak memory | 201696 kb |
| Host | smart-e7487b3c-a9cf-4cbf-90e4-fa00f7d38b07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3649556044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3649556044 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1866017131 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 10441267016 ps |
| CPU time | 9.75 seconds |
| Started | Jan 21 09:51:35 PM PST 24 |
| Finished | Jan 21 09:51:52 PM PST 24 |
| Peak memory | 201904 kb |
| Host | smart-ef0ede18-0f2f-4ecd-8d3a-acf447a5d119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866017131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1866017131 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3513029824 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1993407433 ps |
| CPU time | 6.44 seconds |
| Started | Jan 21 09:51:36 PM PST 24 |
| Finished | Jan 21 09:51:52 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-5bc65c8d-30ea-4e36-9484-42045533d477 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3513029824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3513029824 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1376811713 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 11798933 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 09:51:34 PM PST 24 |
| Finished | Jan 21 09:51:42 PM PST 24 |
| Peak memory | 202004 kb |
| Host | smart-3923632c-d4fc-4799-8648-7c58564bc2d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376811713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1376811713 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3596694360 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3499115922 ps |
| CPU time | 39.71 seconds |
| Started | Jan 21 09:51:50 PM PST 24 |
| Finished | Jan 21 09:52:31 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-09424391-1947-4346-a3eb-a345074561ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3596694360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3596694360 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2559945388 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 512550702 ps |
| CPU time | 16.73 seconds |
| Started | Jan 21 09:51:46 PM PST 24 |
| Finished | Jan 21 09:52:06 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-42a3be23-81a6-4a87-ba05-1746b1de7ae1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559945388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2559945388 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3528610477 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 568261441 ps |
| CPU time | 74.57 seconds |
| Started | Jan 21 09:51:50 PM PST 24 |
| Finished | Jan 21 09:53:05 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-fbcdf3ed-53d3-4a68-a85d-3412c1a51fde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3528610477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3528610477 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1348660002 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5931980203 ps |
| CPU time | 59.5 seconds |
| Started | Jan 21 09:51:50 PM PST 24 |
| Finished | Jan 21 09:52:51 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-6af9c6f8-e87e-4bb8-b7e5-ef9aa6574c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1348660002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1348660002 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3343267 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 580952446 ps |
| CPU time | 4.62 seconds |
| Started | Jan 21 09:51:46 PM PST 24 |
| Finished | Jan 21 09:51:53 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-e95aacb2-e438-43d8-b762-dad0eb9f75b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3343267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3343267 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1825324023 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 48696116 ps |
| CPU time | 7.67 seconds |
| Started | Jan 21 09:41:10 PM PST 24 |
| Finished | Jan 21 09:41:22 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-6be99b8e-9d2d-4588-a544-26b606526ce0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825324023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1825324023 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.667549413 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6744152197 ps |
| CPU time | 43.72 seconds |
| Started | Jan 21 09:41:16 PM PST 24 |
| Finished | Jan 21 09:42:02 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-58ca9551-08dc-41f8-ad0f-8609011aabf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=667549413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.667549413 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.4234912257 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 160573452 ps |
| CPU time | 2.09 seconds |
| Started | Jan 21 09:41:15 PM PST 24 |
| Finished | Jan 21 09:41:19 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-468ccec6-3e97-41b5-ab5d-c1a9de62b952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234912257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.4234912257 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.373075370 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 471638329 ps |
| CPU time | 11.1 seconds |
| Started | Jan 21 09:41:16 PM PST 24 |
| Finished | Jan 21 09:41:30 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-8759b1d3-14b1-4e9b-9167-5fe4eaf62b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=373075370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.373075370 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1535547849 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4320203057 ps |
| CPU time | 16.86 seconds |
| Started | Jan 21 09:41:11 PM PST 24 |
| Finished | Jan 21 09:41:32 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-1c438821-e73e-4914-bd24-b2b80225e896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1535547849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1535547849 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1100276784 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 43685560046 ps |
| CPU time | 154.88 seconds |
| Started | Jan 21 09:41:12 PM PST 24 |
| Finished | Jan 21 09:43:50 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-c5843184-b78a-4615-a242-0700539bc0e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100276784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1100276784 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1893567728 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 17373674549 ps |
| CPU time | 102.96 seconds |
| Started | Jan 21 10:02:38 PM PST 24 |
| Finished | Jan 21 10:04:28 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-359e9c54-cc6d-4083-9474-bfd260a901d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1893567728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1893567728 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1195107683 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 98157292 ps |
| CPU time | 10.24 seconds |
| Started | Jan 21 09:41:09 PM PST 24 |
| Finished | Jan 21 09:41:25 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-20dff228-04eb-4641-a541-712dc11b080a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195107683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1195107683 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.678058416 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 25296910 ps |
| CPU time | 3.05 seconds |
| Started | Jan 21 09:41:16 PM PST 24 |
| Finished | Jan 21 09:41:22 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-31809043-123a-47a4-a689-bd10296fc19e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=678058416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.678058416 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3994509135 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 90848020 ps |
| CPU time | 1.76 seconds |
| Started | Jan 21 10:40:16 PM PST 24 |
| Finished | Jan 21 10:40:20 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-53a936ed-3dde-4da7-b308-43e0fd49202b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994509135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3994509135 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2280272167 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 6567298946 ps |
| CPU time | 12.11 seconds |
| Started | Jan 21 10:53:25 PM PST 24 |
| Finished | Jan 21 10:53:37 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-ce35124d-40ba-4b5b-93b9-0d6725d16c32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280272167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2280272167 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2487011672 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 10669454562 ps |
| CPU time | 9.6 seconds |
| Started | Jan 21 09:41:13 PM PST 24 |
| Finished | Jan 21 09:41:25 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-d231c2d4-bf6a-4400-85f2-db9cabb35b45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2487011672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2487011672 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1349912451 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 12441163 ps |
| CPU time | 1.6 seconds |
| Started | Jan 21 09:41:02 PM PST 24 |
| Finished | Jan 21 09:41:14 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-c11a4cec-1507-4280-85f2-62211c947c0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349912451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1349912451 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.4182914490 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2948176017 ps |
| CPU time | 22.25 seconds |
| Started | Jan 21 09:41:16 PM PST 24 |
| Finished | Jan 21 09:41:40 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-74514bac-f939-4ba3-8d35-5720a9b107a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182914490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4182914490 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2129390572 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 12726000787 ps |
| CPU time | 26.26 seconds |
| Started | Jan 21 09:41:16 PM PST 24 |
| Finished | Jan 21 09:41:44 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-2c7f61fe-ebae-4fc5-b84d-e33ebcecf8fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2129390572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2129390572 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4050417146 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 10526057630 ps |
| CPU time | 323.61 seconds |
| Started | Jan 21 09:41:15 PM PST 24 |
| Finished | Jan 21 09:46:41 PM PST 24 |
| Peak memory | 209348 kb |
| Host | smart-5f2bd5ac-dade-479d-b41e-7acdcf47624a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4050417146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.4050417146 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.170234440 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4876542797 ps |
| CPU time | 87.33 seconds |
| Started | Jan 21 10:53:57 PM PST 24 |
| Finished | Jan 21 10:55:26 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-50d33425-5233-4ea6-8ee0-a749a89c8825 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=170234440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.170234440 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.4247205814 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 221272775 ps |
| CPU time | 3.35 seconds |
| Started | Jan 21 09:41:20 PM PST 24 |
| Finished | Jan 21 09:41:25 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-b49f7ee9-e89d-4963-ab89-98723d8b8724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247205814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4247205814 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1957198809 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 106119574 ps |
| CPU time | 8.11 seconds |
| Started | Jan 21 09:52:07 PM PST 24 |
| Finished | Jan 21 09:52:16 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-fb9f0440-7f80-4121-b11a-8de3e0977530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1957198809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1957198809 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.465292465 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1643417290 ps |
| CPU time | 9.49 seconds |
| Started | Jan 21 09:52:11 PM PST 24 |
| Finished | Jan 21 09:52:22 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-496198cd-ba2c-4eed-ad23-47ed7522ebb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465292465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.465292465 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.1953320060 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 526322592 ps |
| CPU time | 5.45 seconds |
| Started | Jan 21 09:52:08 PM PST 24 |
| Finished | Jan 21 09:52:14 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-ceea3329-e704-44ee-b148-bd821541382e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1953320060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1953320060 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.4090795109 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 938055325 ps |
| CPU time | 17.53 seconds |
| Started | Jan 21 09:51:58 PM PST 24 |
| Finished | Jan 21 09:52:17 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-3b04d390-b60d-4658-9595-1a3ac4bd804b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090795109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4090795109 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3631925452 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 77613744562 ps |
| CPU time | 108.41 seconds |
| Started | Jan 21 09:52:03 PM PST 24 |
| Finished | Jan 21 09:53:53 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-9b0dbf91-00b1-4a0b-a565-76bdd075e80c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631925452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3631925452 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1115248608 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1547053315 ps |
| CPU time | 9.42 seconds |
| Started | Jan 21 10:48:36 PM PST 24 |
| Finished | Jan 21 10:48:47 PM PST 24 |
| Peak memory | 201712 kb |
| Host | smart-6f116b47-d2c5-4404-85a5-1f8d1168c74b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1115248608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1115248608 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.4097102749 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 48440166 ps |
| CPU time | 5.27 seconds |
| Started | Jan 21 09:51:57 PM PST 24 |
| Finished | Jan 21 09:52:04 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-6447aeae-423c-49e2-b565-508471e2b7d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097102749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.4097102749 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2941465438 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 37310145 ps |
| CPU time | 2.82 seconds |
| Started | Jan 21 09:52:07 PM PST 24 |
| Finished | Jan 21 09:52:10 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-4123dc5c-121c-494b-9b6f-673436ea1b06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2941465438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2941465438 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.454654876 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 9519359 ps |
| CPU time | 1.38 seconds |
| Started | Jan 21 09:52:00 PM PST 24 |
| Finished | Jan 21 09:52:02 PM PST 24 |
| Peak memory | 201696 kb |
| Host | smart-84070563-898b-4564-b276-a6f30b4fa83b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454654876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.454654876 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.394966648 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 12257873379 ps |
| CPU time | 7.71 seconds |
| Started | Jan 21 09:51:57 PM PST 24 |
| Finished | Jan 21 09:52:07 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-12d0e49a-e314-4db4-bf34-fda61375d032 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=394966648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.394966648 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1570767958 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1225041298 ps |
| CPU time | 5.57 seconds |
| Started | Jan 21 09:51:58 PM PST 24 |
| Finished | Jan 21 09:52:05 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-c99479ee-8bc3-461f-9655-6766fcbf453f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1570767958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1570767958 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1407004943 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 9304395 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 09:51:59 PM PST 24 |
| Finished | Jan 21 09:52:01 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-222da14f-4efe-4a33-b7a8-c6d096915b6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407004943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1407004943 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3502794070 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 7067688004 ps |
| CPU time | 86.75 seconds |
| Started | Jan 21 09:52:06 PM PST 24 |
| Finished | Jan 21 09:53:34 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-a8c08bb0-f852-4708-b31a-f1f94212ff2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3502794070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3502794070 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2462889177 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1197526944 ps |
| CPU time | 18.3 seconds |
| Started | Jan 21 09:52:07 PM PST 24 |
| Finished | Jan 21 09:52:26 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-b1383a5a-c881-449a-b4ce-ac7f2f6a1456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2462889177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2462889177 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1384201941 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 13877497 ps |
| CPU time | 3.7 seconds |
| Started | Jan 21 09:52:09 PM PST 24 |
| Finished | Jan 21 09:52:14 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-9ec7bed2-62ec-4ea6-931a-0369a0b73e42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1384201941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1384201941 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3448085279 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2027303926 ps |
| CPU time | 52.85 seconds |
| Started | Jan 21 09:52:11 PM PST 24 |
| Finished | Jan 21 09:53:05 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-e4bd2e73-74e0-4aa9-886e-e91238a07787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3448085279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3448085279 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3943440132 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 51689776 ps |
| CPU time | 5.3 seconds |
| Started | Jan 21 09:52:08 PM PST 24 |
| Finished | Jan 21 09:52:15 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-17d00f49-454c-4508-979a-20fb4273663d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3943440132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3943440132 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3706572764 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 80216575 ps |
| CPU time | 8.7 seconds |
| Started | Jan 21 09:52:16 PM PST 24 |
| Finished | Jan 21 09:52:25 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-1911c9e7-ecdb-468c-a377-5650a8b9aac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706572764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3706572764 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1073748161 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 28066421131 ps |
| CPU time | 173.16 seconds |
| Started | Jan 21 09:52:16 PM PST 24 |
| Finished | Jan 21 09:55:10 PM PST 24 |
| Peak memory | 202916 kb |
| Host | smart-f0d549c2-9985-49b9-909c-8e5c9c4c5d04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1073748161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1073748161 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3337725635 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 20033748 ps |
| CPU time | 2.09 seconds |
| Started | Jan 21 09:52:32 PM PST 24 |
| Finished | Jan 21 09:52:45 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-6e7b72cc-9484-4313-a87f-04cde27fc39c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3337725635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3337725635 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.951390365 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1153154431 ps |
| CPU time | 13.56 seconds |
| Started | Jan 21 09:52:16 PM PST 24 |
| Finished | Jan 21 09:52:30 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-b2b62b94-9cb9-4254-b6be-45fe950a98fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=951390365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.951390365 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.3948708410 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 58401963 ps |
| CPU time | 4.34 seconds |
| Started | Jan 21 09:52:14 PM PST 24 |
| Finished | Jan 21 09:52:19 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-d91a8ea2-17f1-4067-b3ab-2f067f120405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3948708410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3948708410 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.546735280 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 33698462780 ps |
| CPU time | 117.09 seconds |
| Started | Jan 21 09:52:13 PM PST 24 |
| Finished | Jan 21 09:54:12 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-96608fa6-f67a-424d-b081-bf32a4626876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=546735280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.546735280 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.866227085 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8557238383 ps |
| CPU time | 38.04 seconds |
| Started | Jan 21 09:52:15 PM PST 24 |
| Finished | Jan 21 09:52:54 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-8e88de86-f0de-4078-a85f-2843a79141f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=866227085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.866227085 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.4093083690 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23634633 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 09:52:13 PM PST 24 |
| Finished | Jan 21 09:52:16 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-ae6e4fdb-d8ba-4cc6-bc45-0a12637d164f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093083690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.4093083690 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.123461809 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 33343602 ps |
| CPU time | 3.75 seconds |
| Started | Jan 21 09:52:15 PM PST 24 |
| Finished | Jan 21 09:52:20 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-f80b2d50-3848-44a3-b03a-911a6fcf993e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=123461809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.123461809 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3660749377 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 28531932 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 09:52:06 PM PST 24 |
| Finished | Jan 21 09:52:08 PM PST 24 |
| Peak memory | 201740 kb |
| Host | smart-62c42bea-203e-41af-9c32-68ae6a0072a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3660749377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3660749377 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.500121998 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3766153730 ps |
| CPU time | 7.53 seconds |
| Started | Jan 21 09:52:12 PM PST 24 |
| Finished | Jan 21 09:52:21 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-3087a66c-2b63-4510-a977-4d0752e7201a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=500121998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.500121998 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.369633396 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 975408952 ps |
| CPU time | 8.54 seconds |
| Started | Jan 21 09:52:14 PM PST 24 |
| Finished | Jan 21 09:52:24 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-1e046ad8-9756-4c1a-899c-dbdd40d6e93a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=369633396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.369633396 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3824291809 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 9761634 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 09:52:10 PM PST 24 |
| Finished | Jan 21 09:52:12 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-bf6a7afb-4ef6-4271-90f5-351136a416e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824291809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3824291809 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1645241433 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 334854391 ps |
| CPU time | 27.27 seconds |
| Started | Jan 21 09:52:18 PM PST 24 |
| Finished | Jan 21 09:52:47 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-3e41e691-ef22-4a80-8aee-2dadf72c9dc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1645241433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1645241433 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1173059826 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 583174476 ps |
| CPU time | 37.92 seconds |
| Started | Jan 21 09:52:15 PM PST 24 |
| Finished | Jan 21 09:52:54 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-c2cd738e-0efc-42c6-ae89-4151e472259a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173059826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1173059826 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.961399727 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 470004310 ps |
| CPU time | 60.02 seconds |
| Started | Jan 21 09:52:22 PM PST 24 |
| Finished | Jan 21 09:53:24 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-37d4e7b0-5ebf-4ad7-988d-c5329382e39e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=961399727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.961399727 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1565750916 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 6932877230 ps |
| CPU time | 115.38 seconds |
| Started | Jan 21 09:52:19 PM PST 24 |
| Finished | Jan 21 09:54:17 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-e7d66f6c-c87d-4461-8feb-fc573ef10b01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1565750916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1565750916 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2373047140 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1331259012 ps |
| CPU time | 6.15 seconds |
| Started | Jan 21 09:52:30 PM PST 24 |
| Finished | Jan 21 09:52:45 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-62fbc27d-0633-4180-b142-a8d28d15365f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2373047140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2373047140 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.280099980 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 91541015 ps |
| CPU time | 12.16 seconds |
| Started | Jan 21 09:52:23 PM PST 24 |
| Finished | Jan 21 09:52:38 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-b1982606-f55d-4c31-9bd8-11b9e1f7588d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=280099980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.280099980 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.601720318 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 16120121887 ps |
| CPU time | 93 seconds |
| Started | Jan 21 09:52:24 PM PST 24 |
| Finished | Jan 21 09:54:01 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-8d5c99c9-7e59-49d4-a6fe-7e6e5b9a9928 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=601720318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.601720318 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2872544985 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2854892207 ps |
| CPU time | 9.8 seconds |
| Started | Jan 21 09:52:31 PM PST 24 |
| Finished | Jan 21 09:52:50 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-8ee83a00-5fd2-4013-a382-fd9af3cf656c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872544985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2872544985 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.407726368 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 65731761 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 09:52:23 PM PST 24 |
| Finished | Jan 21 09:52:28 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-4b0838cc-d6f8-43a7-b0d5-e864c1cdedab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407726368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.407726368 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.2353545776 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 819497281 ps |
| CPU time | 7.55 seconds |
| Started | Jan 21 09:52:32 PM PST 24 |
| Finished | Jan 21 09:52:50 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-dae941b9-60b8-4fcd-a04c-11b8e1d9a6d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2353545776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2353545776 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2137586590 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 38070972243 ps |
| CPU time | 143 seconds |
| Started | Jan 21 09:52:23 PM PST 24 |
| Finished | Jan 21 09:54:49 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-9a5a9b2d-6c9e-4301-a7ff-27a4921fbf4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137586590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2137586590 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3707890545 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4615577867 ps |
| CPU time | 31.03 seconds |
| Started | Jan 21 09:52:22 PM PST 24 |
| Finished | Jan 21 09:52:55 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-7b42365a-58e2-4435-9944-ef1505cbb481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3707890545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3707890545 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1674057187 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 168226763 ps |
| CPU time | 5.11 seconds |
| Started | Jan 21 09:52:27 PM PST 24 |
| Finished | Jan 21 09:52:37 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-8e2faa3b-99a2-4f22-86dd-eeac41af04f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674057187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1674057187 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.704034060 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 117204376 ps |
| CPU time | 2.34 seconds |
| Started | Jan 21 09:52:27 PM PST 24 |
| Finished | Jan 21 09:52:35 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-7b4a8548-5205-4f00-b3b8-36f8247c7f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=704034060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.704034060 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.3674816499 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 10388119 ps |
| CPU time | 1.32 seconds |
| Started | Jan 21 09:52:32 PM PST 24 |
| Finished | Jan 21 09:52:44 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-43ca111d-6081-4f8a-ad54-a7ed1ef0c35b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674816499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3674816499 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1017376918 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2985336669 ps |
| CPU time | 12.93 seconds |
| Started | Jan 21 09:52:15 PM PST 24 |
| Finished | Jan 21 09:52:28 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-5ee219e7-31bd-403b-bb2c-42baf40fa123 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017376918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1017376918 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3452266235 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 950531090 ps |
| CPU time | 6.29 seconds |
| Started | Jan 21 09:52:27 PM PST 24 |
| Finished | Jan 21 09:52:38 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-c8d06b5e-9576-4c41-a6e5-d2df868958b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3452266235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3452266235 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4166948430 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 11389197 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 09:52:32 PM PST 24 |
| Finished | Jan 21 09:52:44 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-2e1a0d47-3694-444c-9504-ee650f5ca15c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166948430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4166948430 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.3902632636 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10214891688 ps |
| CPU time | 50.2 seconds |
| Started | Jan 21 09:52:30 PM PST 24 |
| Finished | Jan 21 09:53:29 PM PST 24 |
| Peak memory | 202876 kb |
| Host | smart-bb11100e-c766-4664-a588-19e1e6b7374e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3902632636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3902632636 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4023226800 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 8502342394 ps |
| CPU time | 41.95 seconds |
| Started | Jan 21 09:52:33 PM PST 24 |
| Finished | Jan 21 09:53:26 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-5c40a9df-034e-4f2d-aedc-de28ef2d5671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4023226800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4023226800 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2086803468 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 152449998 ps |
| CPU time | 23.06 seconds |
| Started | Jan 21 09:52:33 PM PST 24 |
| Finished | Jan 21 09:53:07 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-09a858fb-ae77-457d-aceb-37c1a3cf931f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086803468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.2086803468 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3305930904 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 445137059 ps |
| CPU time | 45.12 seconds |
| Started | Jan 21 09:52:39 PM PST 24 |
| Finished | Jan 21 09:53:35 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-ea40fc87-bafd-426b-a3e1-62c5a1447060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305930904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3305930904 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1792710869 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 372949681 ps |
| CPU time | 6.37 seconds |
| Started | Jan 21 09:52:33 PM PST 24 |
| Finished | Jan 21 09:52:49 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-60f3b9e2-f7eb-4865-b785-7105be0f183e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792710869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1792710869 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.615252767 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1335648856 ps |
| CPU time | 17.69 seconds |
| Started | Jan 21 09:52:38 PM PST 24 |
| Finished | Jan 21 09:53:07 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-5a5a264d-7ec1-4f21-b39b-acc1a61fd591 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=615252767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.615252767 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3797819999 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 5315709855 ps |
| CPU time | 33.14 seconds |
| Started | Jan 21 09:52:40 PM PST 24 |
| Finished | Jan 21 09:53:24 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-8212ac8e-41b3-45ac-b39c-0d2740b8ce9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3797819999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3797819999 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1113954739 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 876940267 ps |
| CPU time | 4.04 seconds |
| Started | Jan 21 09:52:46 PM PST 24 |
| Finished | Jan 21 09:52:57 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-55d69fc3-dc37-4e2a-9e39-20f255347f88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1113954739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1113954739 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.470777708 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 22165433 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 09:52:39 PM PST 24 |
| Finished | Jan 21 09:52:52 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-2ac45d15-38c9-4e11-9f75-6780e89ae656 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=470777708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.470777708 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3604453291 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 880496526 ps |
| CPU time | 8.7 seconds |
| Started | Jan 21 09:52:42 PM PST 24 |
| Finished | Jan 21 09:53:00 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-850790c6-1354-453d-af96-1abe5c8ff41b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3604453291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3604453291 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2513040725 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 80125832159 ps |
| CPU time | 148.23 seconds |
| Started | Jan 21 09:52:38 PM PST 24 |
| Finished | Jan 21 09:55:17 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-fb2af643-6735-4d95-a158-25eff8b02017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513040725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2513040725 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3034104354 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 9831884135 ps |
| CPU time | 47.57 seconds |
| Started | Jan 21 09:52:44 PM PST 24 |
| Finished | Jan 21 09:53:40 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-f13d36d8-776c-48db-b69e-fc46a0eea651 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3034104354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3034104354 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3673741596 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9464842 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 09:52:39 PM PST 24 |
| Finished | Jan 21 09:52:51 PM PST 24 |
| Peak memory | 201700 kb |
| Host | smart-992d9d96-8b97-4657-8364-13fe595550b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673741596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3673741596 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.4172510198 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 82429871 ps |
| CPU time | 2.94 seconds |
| Started | Jan 21 09:52:41 PM PST 24 |
| Finished | Jan 21 09:52:54 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-319efe67-fd4b-49af-ab58-4fa404681c65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172510198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4172510198 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.2761735573 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 15184592 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 09:52:41 PM PST 24 |
| Finished | Jan 21 09:52:52 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-eb086af2-9d9e-4926-bb83-df59e66bfe48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761735573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2761735573 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3063360452 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7406450623 ps |
| CPU time | 11.93 seconds |
| Started | Jan 21 09:52:41 PM PST 24 |
| Finished | Jan 21 09:53:03 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-f67617ea-cefd-4f12-81b4-8f7275bbe825 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063360452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3063360452 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2509775907 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2234748739 ps |
| CPU time | 6.22 seconds |
| Started | Jan 21 09:52:39 PM PST 24 |
| Finished | Jan 21 09:52:56 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-effe3568-2b1f-486a-8561-e4147bcc71f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2509775907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2509775907 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3610802532 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 8483448 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 09:52:37 PM PST 24 |
| Finished | Jan 21 09:52:50 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-7fd07d59-1737-4ced-ba73-bfdb4bd3d079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610802532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3610802532 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3149586487 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 24185608676 ps |
| CPU time | 51.09 seconds |
| Started | Jan 21 09:52:56 PM PST 24 |
| Finished | Jan 21 09:53:49 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-15f271da-aa63-4740-b30c-702726be059c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3149586487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3149586487 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1854972630 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5677258578 ps |
| CPU time | 13.74 seconds |
| Started | Jan 21 09:52:48 PM PST 24 |
| Finished | Jan 21 09:53:08 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-c09289bb-4b91-42a5-ab87-5a1124b9403d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854972630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1854972630 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2949483521 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 654515841 ps |
| CPU time | 148.94 seconds |
| Started | Jan 21 09:52:48 PM PST 24 |
| Finished | Jan 21 09:55:24 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-12dc6565-d462-4437-a15f-b0b71c007767 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949483521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2949483521 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3120344559 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 276075503 ps |
| CPU time | 25.02 seconds |
| Started | Jan 21 09:52:47 PM PST 24 |
| Finished | Jan 21 09:53:19 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-ee9b85cd-2648-4231-bbb3-f066d1fca776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3120344559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3120344559 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3977762868 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 436569232 ps |
| CPU time | 7.7 seconds |
| Started | Jan 21 09:52:40 PM PST 24 |
| Finished | Jan 21 09:52:58 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-8a83f0d2-61a7-4bc4-839b-9823c5c47682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3977762868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3977762868 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3967533820 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 78575970 ps |
| CPU time | 8.65 seconds |
| Started | Jan 21 09:52:56 PM PST 24 |
| Finished | Jan 21 09:53:06 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-f45a0112-c55b-49e8-bf8c-bc7f8af3b42b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967533820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3967533820 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2361098443 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 45345182852 ps |
| CPU time | 38.52 seconds |
| Started | Jan 21 09:53:08 PM PST 24 |
| Finished | Jan 21 09:53:48 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-a313b038-85a3-4d89-86c7-9536d745898c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2361098443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2361098443 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3705734534 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1539869891 ps |
| CPU time | 8.21 seconds |
| Started | Jan 21 09:53:03 PM PST 24 |
| Finished | Jan 21 09:53:12 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-8355432a-96bf-45a6-9184-d5663e11b038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705734534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3705734534 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.3376333905 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1159013550 ps |
| CPU time | 12.8 seconds |
| Started | Jan 21 09:53:03 PM PST 24 |
| Finished | Jan 21 09:53:17 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-8c0e55e1-0483-470c-bd74-2537a0f37f22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376333905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3376333905 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2761230471 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 70469774 ps |
| CPU time | 4.47 seconds |
| Started | Jan 21 09:52:54 PM PST 24 |
| Finished | Jan 21 09:53:01 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-011c4eb4-c8ee-4ab7-b027-452425d924da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761230471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2761230471 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1108955119 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 34920686666 ps |
| CPU time | 60.13 seconds |
| Started | Jan 21 09:52:54 PM PST 24 |
| Finished | Jan 21 09:53:56 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-99a43846-0f34-4dcb-a549-bbe9f06ce34f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108955119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1108955119 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1162855260 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 88197212710 ps |
| CPU time | 189.89 seconds |
| Started | Jan 21 09:52:54 PM PST 24 |
| Finished | Jan 21 09:56:06 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-207f97ba-a951-414a-b680-20b7f16342e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1162855260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1162855260 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2364912033 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 31529640 ps |
| CPU time | 4.67 seconds |
| Started | Jan 21 09:52:55 PM PST 24 |
| Finished | Jan 21 09:53:01 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-463655ac-0e26-434e-a69b-b836ba261495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364912033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2364912033 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.417803874 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 90949873 ps |
| CPU time | 6.35 seconds |
| Started | Jan 21 09:53:04 PM PST 24 |
| Finished | Jan 21 09:53:12 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-9e9c7e78-ad3b-401e-8fa4-9b4bf714e000 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417803874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.417803874 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.173870100 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 83785002 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 09:52:48 PM PST 24 |
| Finished | Jan 21 09:52:56 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-fddb93b2-1fc4-4977-a898-efcf3de248e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173870100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.173870100 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1798437042 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2331957654 ps |
| CPU time | 6.42 seconds |
| Started | Jan 21 09:52:56 PM PST 24 |
| Finished | Jan 21 09:53:04 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-1ee8ade8-fd0a-4b92-a276-f3638be8437a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798437042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1798437042 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4054358300 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1686140396 ps |
| CPU time | 7.25 seconds |
| Started | Jan 21 09:52:55 PM PST 24 |
| Finished | Jan 21 09:53:03 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-4c412fd0-b823-4bfb-8bb2-660f6cf01465 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4054358300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4054358300 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.16596170 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 10674077 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 09:52:48 PM PST 24 |
| Finished | Jan 21 09:52:56 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-6b4cf090-d68c-4d7d-84e5-378b93150911 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.16596170 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.144602121 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6001421186 ps |
| CPU time | 23.67 seconds |
| Started | Jan 21 09:53:04 PM PST 24 |
| Finished | Jan 21 09:53:29 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-aac78e9c-6a2d-4132-aba7-e38d41308d9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=144602121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.144602121 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3333628713 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 884181505 ps |
| CPU time | 13.33 seconds |
| Started | Jan 21 09:53:03 PM PST 24 |
| Finished | Jan 21 09:53:18 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-dbbcaa91-06a9-47fa-af68-0f3b851c7e6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333628713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3333628713 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1602663597 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 217379571 ps |
| CPU time | 27.25 seconds |
| Started | Jan 21 09:53:06 PM PST 24 |
| Finished | Jan 21 09:53:34 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-2f71f6cf-8da7-4d0c-9c59-8913204c9ee7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1602663597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.1602663597 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2258484961 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1338713585 ps |
| CPU time | 4.59 seconds |
| Started | Jan 21 09:53:06 PM PST 24 |
| Finished | Jan 21 09:53:12 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-6fe3e4e9-941a-4d5a-8490-0b3051d72100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258484961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2258484961 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.4108136241 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 59859204 ps |
| CPU time | 6.91 seconds |
| Started | Jan 21 09:53:11 PM PST 24 |
| Finished | Jan 21 09:53:20 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-71d14194-7de6-47dc-b77f-692a7a3e9a6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4108136241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4108136241 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2781906491 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4781229582 ps |
| CPU time | 30.29 seconds |
| Started | Jan 21 09:53:12 PM PST 24 |
| Finished | Jan 21 09:53:44 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-4b310b32-b9a4-439f-824e-8f1141b28568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2781906491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2781906491 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1172377112 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 414543701 ps |
| CPU time | 2.47 seconds |
| Started | Jan 21 09:53:12 PM PST 24 |
| Finished | Jan 21 09:53:16 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-c5cf62d4-7b6b-44d0-a093-ee7434e07107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1172377112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1172377112 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2455722650 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 60982353 ps |
| CPU time | 6.45 seconds |
| Started | Jan 21 09:53:10 PM PST 24 |
| Finished | Jan 21 09:53:17 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-24b0c725-14e2-446e-b9b9-3943404ca3d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455722650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2455722650 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.551612318 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 368619435 ps |
| CPU time | 7.63 seconds |
| Started | Jan 21 09:53:08 PM PST 24 |
| Finished | Jan 21 09:53:17 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-622f7c6c-30c7-4f05-8d6b-2eda233a8e91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551612318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.551612318 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1900113197 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 52635702409 ps |
| CPU time | 120.81 seconds |
| Started | Jan 21 09:53:05 PM PST 24 |
| Finished | Jan 21 09:55:06 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-3012f69b-ed52-47b9-940f-b999bc570961 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900113197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1900113197 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3656406571 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 13367418482 ps |
| CPU time | 103.17 seconds |
| Started | Jan 21 09:53:11 PM PST 24 |
| Finished | Jan 21 09:54:54 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-c6b33b86-8ed8-49db-ac18-d7b76a839aa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3656406571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3656406571 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1703664170 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 21755107 ps |
| CPU time | 1.93 seconds |
| Started | Jan 21 09:53:05 PM PST 24 |
| Finished | Jan 21 09:53:08 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-5b7b2bf9-e5aa-4505-be7c-db7e0d5898e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703664170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1703664170 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1585407606 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 354009297 ps |
| CPU time | 5.11 seconds |
| Started | Jan 21 09:53:12 PM PST 24 |
| Finished | Jan 21 09:53:18 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-e77a3494-1fba-4fd2-a193-c485efa340a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1585407606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1585407606 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3427573577 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 66495158 ps |
| CPU time | 1.4 seconds |
| Started | Jan 21 09:53:04 PM PST 24 |
| Finished | Jan 21 09:53:06 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-160b0c3b-8e3f-4a75-970b-1f24d5c73f23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3427573577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3427573577 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1687566663 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5794528415 ps |
| CPU time | 9.17 seconds |
| Started | Jan 21 09:53:06 PM PST 24 |
| Finished | Jan 21 09:53:16 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-1c93dcca-36f7-4565-b008-3b04878e4d59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687566663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1687566663 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1396142684 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1077328793 ps |
| CPU time | 5.14 seconds |
| Started | Jan 21 09:53:06 PM PST 24 |
| Finished | Jan 21 09:53:12 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-6d9d270e-9fb7-41ae-80c1-584146262efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1396142684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1396142684 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1539346022 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 14141892 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 09:53:07 PM PST 24 |
| Finished | Jan 21 09:53:09 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-b0ff2ed5-2040-492d-96c3-852b89276cb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539346022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1539346022 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1650748844 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7899046565 ps |
| CPU time | 66.69 seconds |
| Started | Jan 22 12:13:36 AM PST 24 |
| Finished | Jan 22 12:14:45 AM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-3be2bf54-65d2-4c19-a186-17038f83d538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1650748844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1650748844 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3684315199 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4168043449 ps |
| CPU time | 16.1 seconds |
| Started | Jan 21 09:53:11 PM PST 24 |
| Finished | Jan 21 09:53:28 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-d399fc50-4995-4651-ba07-24c2eacd6cab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3684315199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3684315199 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.36727064 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 95429065 ps |
| CPU time | 19.53 seconds |
| Started | Jan 21 09:53:11 PM PST 24 |
| Finished | Jan 21 09:53:32 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-f6b686a3-d2a7-4ad6-a773-8d7ab24f62ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36727064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_ reset.36727064 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.302991938 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 356925453 ps |
| CPU time | 31.67 seconds |
| Started | Jan 21 09:53:10 PM PST 24 |
| Finished | Jan 21 09:53:42 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-b6c66420-d145-42c2-b0ee-94b6dbdf0d1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302991938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res et_error.302991938 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1460344488 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1232210964 ps |
| CPU time | 10.13 seconds |
| Started | Jan 21 09:53:09 PM PST 24 |
| Finished | Jan 21 09:53:20 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-fb9e2131-3ea9-4231-96ee-ce30e62e49ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460344488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1460344488 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2095741668 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 53350351 ps |
| CPU time | 5.85 seconds |
| Started | Jan 21 09:53:26 PM PST 24 |
| Finished | Jan 21 09:53:33 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-2442914e-619d-4dda-8fa8-01651d2b0d1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2095741668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2095741668 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1944340300 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 14327794095 ps |
| CPU time | 18.56 seconds |
| Started | Jan 21 09:53:27 PM PST 24 |
| Finished | Jan 21 09:53:47 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-b9205a6d-25c7-46b2-a280-c84ee8650399 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1944340300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1944340300 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2463882114 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 960466912 ps |
| CPU time | 4.17 seconds |
| Started | Jan 21 09:53:39 PM PST 24 |
| Finished | Jan 21 09:53:44 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-5c9239a7-4e4a-4fa2-980a-f55e7334fc47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2463882114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2463882114 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.3039593780 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 218736818 ps |
| CPU time | 4.47 seconds |
| Started | Jan 21 09:53:30 PM PST 24 |
| Finished | Jan 21 09:53:36 PM PST 24 |
| Peak memory | 201768 kb |
| Host | smart-74be0f9e-9913-4c49-84cb-218cff91079c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039593780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3039593780 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.883253778 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 159431160 ps |
| CPU time | 6.17 seconds |
| Started | Jan 21 09:53:29 PM PST 24 |
| Finished | Jan 21 09:53:37 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-e1cff9fd-1bc8-4ba2-b7ea-756fdb6ba8d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883253778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.883253778 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2132764932 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 8120156153 ps |
| CPU time | 19.09 seconds |
| Started | Jan 21 09:53:23 PM PST 24 |
| Finished | Jan 21 09:53:43 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-b978044e-5a8c-40ee-aab5-57dc98fef793 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132764932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2132764932 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1261885514 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 61851859369 ps |
| CPU time | 121.76 seconds |
| Started | Jan 21 09:53:27 PM PST 24 |
| Finished | Jan 21 09:55:30 PM PST 24 |
| Peak memory | 201900 kb |
| Host | smart-d13ad158-a110-4ecb-80ba-f39d86458f69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1261885514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1261885514 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2616751472 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 16090013 ps |
| CPU time | 1.35 seconds |
| Started | Jan 21 09:53:24 PM PST 24 |
| Finished | Jan 21 09:53:26 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-0e2915da-1655-45e8-95eb-ec6390bdc752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616751472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2616751472 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.3486740755 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 480095404 ps |
| CPU time | 4.03 seconds |
| Started | Jan 21 09:53:27 PM PST 24 |
| Finished | Jan 21 09:53:32 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-0a0fc4f2-5634-48e2-8cf5-6622f950d08c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3486740755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3486740755 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3490630804 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 229672252 ps |
| CPU time | 1.41 seconds |
| Started | Jan 21 09:53:27 PM PST 24 |
| Finished | Jan 21 09:53:30 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-9fe7cfe9-8ffe-486d-94bd-4143fc8e0bae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3490630804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3490630804 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.613389212 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 7216273053 ps |
| CPU time | 8.98 seconds |
| Started | Jan 21 09:53:21 PM PST 24 |
| Finished | Jan 21 09:53:31 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-d85e0304-8858-4646-954d-8df806b02efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=613389212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.613389212 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4128305761 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3329617130 ps |
| CPU time | 6.48 seconds |
| Started | Jan 21 09:53:22 PM PST 24 |
| Finished | Jan 21 09:53:29 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-76b4bc58-e1e2-4232-be6d-a6c4ce84dabb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4128305761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4128305761 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2562767801 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13444622 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 09:53:20 PM PST 24 |
| Finished | Jan 21 09:53:22 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-02f22b99-ab5b-4d8c-9a4b-68a6e89db82f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562767801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2562767801 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.233085689 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3327072262 ps |
| CPU time | 36.62 seconds |
| Started | Jan 21 09:53:38 PM PST 24 |
| Finished | Jan 21 09:54:16 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-7cf58005-e5b7-44b3-8032-a57997bfa1a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=233085689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.233085689 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3710989205 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 176587389 ps |
| CPU time | 20.01 seconds |
| Started | Jan 21 09:53:44 PM PST 24 |
| Finished | Jan 21 09:54:05 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-6f4a0b40-aa40-4ad1-8cb9-844891d1b625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3710989205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3710989205 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1326684266 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 18715683801 ps |
| CPU time | 126.59 seconds |
| Started | Jan 21 09:53:38 PM PST 24 |
| Finished | Jan 21 09:55:46 PM PST 24 |
| Peak memory | 206556 kb |
| Host | smart-bdd1bc08-55a8-492e-8033-2b9c5a6c7a5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1326684266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1326684266 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2610902447 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4047865270 ps |
| CPU time | 101.63 seconds |
| Started | Jan 21 09:53:41 PM PST 24 |
| Finished | Jan 21 09:55:25 PM PST 24 |
| Peak memory | 205752 kb |
| Host | smart-948ea15b-c684-48ff-b1ff-306d2e1635e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610902447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2610902447 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4018555177 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1797470697 ps |
| CPU time | 8.31 seconds |
| Started | Jan 21 09:53:42 PM PST 24 |
| Finished | Jan 21 09:53:53 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-a4be651c-49d2-4fda-984e-780af8eb176a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018555177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4018555177 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2221208199 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 29881054 ps |
| CPU time | 4.21 seconds |
| Started | Jan 21 09:53:43 PM PST 24 |
| Finished | Jan 21 09:53:49 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-52a3ac27-26fa-4378-974f-8545bc33a1c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221208199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2221208199 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3932827330 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 24206148348 ps |
| CPU time | 186.07 seconds |
| Started | Jan 21 09:53:45 PM PST 24 |
| Finished | Jan 21 09:56:53 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-a0a056bd-0f33-42ef-86ca-caebf63208c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3932827330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3932827330 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3730138152 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 20128890 ps |
| CPU time | 1.92 seconds |
| Started | Jan 21 09:53:46 PM PST 24 |
| Finished | Jan 21 09:53:50 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-2805d9fe-d4d0-4e59-a1de-1f32951f2b18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730138152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3730138152 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.404267666 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 988557671 ps |
| CPU time | 11.72 seconds |
| Started | Jan 21 11:59:25 PM PST 24 |
| Finished | Jan 21 11:59:40 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-9622605b-afde-45c0-b6fd-89f18923f33c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404267666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.404267666 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2931454999 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1134251402 ps |
| CPU time | 16.36 seconds |
| Started | Jan 21 09:53:40 PM PST 24 |
| Finished | Jan 21 09:53:59 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-847dab42-2303-4fa7-b944-e5332e7a6ee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931454999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2931454999 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3107195374 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 30856959499 ps |
| CPU time | 171.51 seconds |
| Started | Jan 21 09:53:40 PM PST 24 |
| Finished | Jan 21 09:56:34 PM PST 24 |
| Peak memory | 201884 kb |
| Host | smart-5a2d9f56-0884-43ab-abfd-d35f7acdd5a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3107195374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3107195374 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3757644689 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 60446961 ps |
| CPU time | 6.31 seconds |
| Started | Jan 21 09:53:38 PM PST 24 |
| Finished | Jan 21 09:53:46 PM PST 24 |
| Peak memory | 201700 kb |
| Host | smart-b63fc543-912f-4a6e-9049-05518ffe6f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757644689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3757644689 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2531096285 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1324317739 ps |
| CPU time | 14.24 seconds |
| Started | Jan 21 09:53:48 PM PST 24 |
| Finished | Jan 21 09:54:09 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-f9ee7e7a-c4fe-4883-90ac-cebc301a8523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2531096285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2531096285 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.2866787084 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 78247722 ps |
| CPU time | 1.79 seconds |
| Started | Jan 21 09:53:38 PM PST 24 |
| Finished | Jan 21 09:53:41 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-131448a8-dc53-4b9e-9ee9-62bcff44847f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866787084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2866787084 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2581916398 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 7637784303 ps |
| CPU time | 15.88 seconds |
| Started | Jan 21 09:53:39 PM PST 24 |
| Finished | Jan 21 09:53:56 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-a42626f7-bd8e-43a0-88c3-6ed1b5745ac3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581916398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2581916398 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2184501399 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1793199934 ps |
| CPU time | 7.99 seconds |
| Started | Jan 21 09:53:40 PM PST 24 |
| Finished | Jan 21 09:53:49 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-7145852e-c0e8-485e-bc0d-9fcb3c0b7fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2184501399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2184501399 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1085929670 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 34325396 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 09:53:41 PM PST 24 |
| Finished | Jan 21 09:53:44 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-eaccf996-aa75-4e42-86c5-9b003fec39ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085929670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1085929670 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3436123385 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3783151246 ps |
| CPU time | 58.76 seconds |
| Started | Jan 21 09:53:51 PM PST 24 |
| Finished | Jan 21 09:55:02 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-326d409a-45d6-4986-a888-814447b6313a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3436123385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3436123385 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.99559041 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5789221469 ps |
| CPU time | 107.74 seconds |
| Started | Jan 21 09:53:47 PM PST 24 |
| Finished | Jan 21 09:55:39 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-ceaa9c40-81fd-4520-a9ef-7eb3e00892cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=99559041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.99559041 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2808124446 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5938032884 ps |
| CPU time | 143.04 seconds |
| Started | Jan 21 11:24:45 PM PST 24 |
| Finished | Jan 21 11:27:09 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-ef47e8a9-9b92-44f2-bcf1-6b0b214272b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2808124446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2808124446 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4270714110 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 69244928 ps |
| CPU time | 15.88 seconds |
| Started | Jan 21 09:53:45 PM PST 24 |
| Finished | Jan 21 09:54:03 PM PST 24 |
| Peak memory | 202004 kb |
| Host | smart-d7c7d509-c12e-4e1b-a8b9-cf8c5f89f90f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4270714110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.4270714110 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1167558062 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 13737773 ps |
| CPU time | 1.35 seconds |
| Started | Jan 21 09:53:45 PM PST 24 |
| Finished | Jan 21 09:53:48 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-4ebfe2a6-79ff-447e-bf07-aa105ef8ffd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1167558062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1167558062 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1370429675 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 85112120 ps |
| CPU time | 11 seconds |
| Started | Jan 21 09:53:56 PM PST 24 |
| Finished | Jan 21 09:54:21 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-cebdf29a-544b-4314-8e97-1b409aca6902 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1370429675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1370429675 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2722022439 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 50254236574 ps |
| CPU time | 328.59 seconds |
| Started | Jan 21 09:53:56 PM PST 24 |
| Finished | Jan 21 09:59:40 PM PST 24 |
| Peak memory | 202956 kb |
| Host | smart-bdc7b1f2-2c37-460b-9bde-6ed6e9f34d12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2722022439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2722022439 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.389045721 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 440419430 ps |
| CPU time | 4.67 seconds |
| Started | Jan 21 09:54:02 PM PST 24 |
| Finished | Jan 21 09:54:21 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-2455f8b5-371f-4bf0-a30a-12a5464931f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=389045721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.389045721 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1441395743 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 40413160 ps |
| CPU time | 1.5 seconds |
| Started | Jan 21 09:53:55 PM PST 24 |
| Finished | Jan 21 09:54:11 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-808225a9-8343-42e7-8432-547a947ed419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1441395743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1441395743 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1807385365 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 273106092 ps |
| CPU time | 3.37 seconds |
| Started | Jan 21 09:53:51 PM PST 24 |
| Finished | Jan 21 09:54:07 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-d4bba07c-ebb5-4787-8649-b737fc601a43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1807385365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1807385365 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2537634783 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 36164443082 ps |
| CPU time | 145.05 seconds |
| Started | Jan 21 09:53:54 PM PST 24 |
| Finished | Jan 21 09:56:33 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-a94e72aa-63ee-42cf-b8a8-8cacf61c4f50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537634783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2537634783 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2089620139 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 30964054270 ps |
| CPU time | 192.83 seconds |
| Started | Jan 21 09:53:55 PM PST 24 |
| Finished | Jan 21 09:57:23 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-054c3a2a-3c19-45c9-8628-9d49f170b3a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2089620139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2089620139 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2999400967 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 58420794 ps |
| CPU time | 4.18 seconds |
| Started | Jan 21 09:53:48 PM PST 24 |
| Finished | Jan 21 09:53:56 PM PST 24 |
| Peak memory | 201708 kb |
| Host | smart-0f9d0aab-0f37-4da5-a06d-deee9a136ab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999400967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2999400967 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1935558388 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 308657956 ps |
| CPU time | 1.41 seconds |
| Started | Jan 21 09:54:02 PM PST 24 |
| Finished | Jan 21 09:54:16 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-fd4fed1a-c035-4d87-80ce-017db9cec530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1935558388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1935558388 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.622792958 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 9552194 ps |
| CPU time | 1.27 seconds |
| Started | Jan 21 10:21:39 PM PST 24 |
| Finished | Jan 21 10:21:48 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-9579ed47-b0ed-4890-a722-4697d6e6a57d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=622792958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.622792958 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2129284928 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3682255916 ps |
| CPU time | 6.87 seconds |
| Started | Jan 21 09:53:51 PM PST 24 |
| Finished | Jan 21 09:54:10 PM PST 24 |
| Peak memory | 201608 kb |
| Host | smart-0594a79e-a23d-4a2d-848e-7b6028fb9d6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129284928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2129284928 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.943372402 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1612520421 ps |
| CPU time | 8.82 seconds |
| Started | Jan 21 11:17:08 PM PST 24 |
| Finished | Jan 21 11:17:24 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-b516a34c-4817-43c6-87f4-7ee934b83821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=943372402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.943372402 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.823962439 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 9584482 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 09:53:47 PM PST 24 |
| Finished | Jan 21 09:53:50 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-74ac4f4c-09b2-422f-8408-b847549e03d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823962439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.823962439 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.682723439 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 837574348 ps |
| CPU time | 48.62 seconds |
| Started | Jan 21 09:53:55 PM PST 24 |
| Finished | Jan 21 09:54:58 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-9293cc56-45da-4d0a-ac1d-ddd4ec846011 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682723439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.682723439 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.672618078 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3736944857 ps |
| CPU time | 38.7 seconds |
| Started | Jan 21 09:54:01 PM PST 24 |
| Finished | Jan 21 09:54:53 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-14bf8839-43a7-4393-a28c-23dd694204c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=672618078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.672618078 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1874781771 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 414319772 ps |
| CPU time | 66.6 seconds |
| Started | Jan 21 09:53:55 PM PST 24 |
| Finished | Jan 21 09:55:17 PM PST 24 |
| Peak memory | 203880 kb |
| Host | smart-fada1ffa-eef9-4a5a-8a4c-1f8c8ee41381 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1874781771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1874781771 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1904906752 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 182826518 ps |
| CPU time | 11.77 seconds |
| Started | Jan 21 09:53:55 PM PST 24 |
| Finished | Jan 21 09:54:22 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-7be373d3-f5ff-4c57-99c6-1e31450c7b2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1904906752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1904906752 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2593995162 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 165354912 ps |
| CPU time | 6.25 seconds |
| Started | Jan 21 09:53:54 PM PST 24 |
| Finished | Jan 21 09:54:14 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-f9cfa2bf-e6a4-4097-b060-e4e482188a8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2593995162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2593995162 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1220132115 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 521390204 ps |
| CPU time | 8.08 seconds |
| Started | Jan 21 09:54:02 PM PST 24 |
| Finished | Jan 21 09:54:23 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-f4e88dfc-eb59-437b-9bbe-29478d7f9968 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220132115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1220132115 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.4061011230 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 22845750851 ps |
| CPU time | 49.31 seconds |
| Started | Jan 21 09:54:02 PM PST 24 |
| Finished | Jan 21 09:55:04 PM PST 24 |
| Peak memory | 201884 kb |
| Host | smart-397f8e5c-2f84-4201-9765-e43f741fcde1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4061011230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.4061011230 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1658773845 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 300105813 ps |
| CPU time | 3.89 seconds |
| Started | Jan 21 09:54:04 PM PST 24 |
| Finished | Jan 21 09:54:21 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-a541d23b-28ae-4e14-bc8e-fafea63b2817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658773845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1658773845 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.4080480650 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 269554656 ps |
| CPU time | 4.45 seconds |
| Started | Jan 21 09:54:05 PM PST 24 |
| Finished | Jan 21 09:54:22 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-c75b587e-acd3-4e96-ae75-de17e2058b00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4080480650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4080480650 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.3129016754 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 18463370 ps |
| CPU time | 1.77 seconds |
| Started | Jan 21 09:54:04 PM PST 24 |
| Finished | Jan 21 09:54:18 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-af793f67-a7dc-4035-8fd3-d24548574da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3129016754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3129016754 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.865860695 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 22709330045 ps |
| CPU time | 56.55 seconds |
| Started | Jan 21 09:54:03 PM PST 24 |
| Finished | Jan 21 09:55:13 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-7003db1d-4fe9-4598-b2d9-f9c4a13397b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=865860695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.865860695 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2443260394 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 17154915377 ps |
| CPU time | 41.56 seconds |
| Started | Jan 21 09:54:09 PM PST 24 |
| Finished | Jan 21 09:55:07 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-ec4c1a3e-368d-4b3c-81d2-34e1e57b82e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2443260394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2443260394 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2217875382 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 101584281 ps |
| CPU time | 5.56 seconds |
| Started | Jan 21 09:54:09 PM PST 24 |
| Finished | Jan 21 09:54:31 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-a707a3ad-8d58-4e8d-9454-17863c135f70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217875382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2217875382 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1767759027 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 696447109 ps |
| CPU time | 5.57 seconds |
| Started | Jan 21 09:54:03 PM PST 24 |
| Finished | Jan 21 09:54:21 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-7b3eb45e-5ab1-435f-9cc6-d77b73f1bbf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1767759027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1767759027 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.3671813312 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 58724516 ps |
| CPU time | 1.58 seconds |
| Started | Jan 21 09:54:02 PM PST 24 |
| Finished | Jan 21 09:54:16 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-a083873b-1f81-42f4-819f-d01b87e26e64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3671813312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3671813312 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2059519873 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2369321976 ps |
| CPU time | 12.02 seconds |
| Started | Jan 21 09:53:56 PM PST 24 |
| Finished | Jan 21 09:54:22 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-735aa3db-f4f6-4e44-9499-b48f30f21018 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059519873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2059519873 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1190599947 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1719173186 ps |
| CPU time | 6.38 seconds |
| Started | Jan 21 09:54:04 PM PST 24 |
| Finished | Jan 21 09:54:24 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-bff55f8a-6855-4873-ae57-76ade17dac84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1190599947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1190599947 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3534953259 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 10347542 ps |
| CPU time | 1.27 seconds |
| Started | Jan 21 09:53:57 PM PST 24 |
| Finished | Jan 21 09:54:13 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-1886aaef-1bfa-4f46-8814-d90f858c7ce3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534953259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3534953259 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1936491611 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 39477435374 ps |
| CPU time | 76.86 seconds |
| Started | Jan 21 09:54:08 PM PST 24 |
| Finished | Jan 21 09:55:39 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-f9fc2ee3-af14-4775-985b-c31dbfb1b69f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1936491611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1936491611 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2845834192 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3847439324 ps |
| CPU time | 54.18 seconds |
| Started | Jan 21 09:54:13 PM PST 24 |
| Finished | Jan 21 09:55:25 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-014c6506-ddf7-4e1c-955c-5163b433a4c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2845834192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2845834192 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4021832587 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2290223908 ps |
| CPU time | 71.47 seconds |
| Started | Jan 21 09:54:05 PM PST 24 |
| Finished | Jan 21 09:55:29 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-7e94d29f-72d4-4098-bb85-8f306f47573a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4021832587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.4021832587 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2557458967 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 661707621 ps |
| CPU time | 109.96 seconds |
| Started | Jan 21 09:54:11 PM PST 24 |
| Finished | Jan 21 09:56:18 PM PST 24 |
| Peak memory | 207296 kb |
| Host | smart-dc7c5ee1-2199-43ba-a6a0-1d095c6f18e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2557458967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2557458967 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1788168503 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 666995919 ps |
| CPU time | 10.55 seconds |
| Started | Jan 21 09:54:07 PM PST 24 |
| Finished | Jan 21 09:54:32 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-7606dcab-714d-458d-bde0-a7e60da803e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788168503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1788168503 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1707676891 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 336506630 ps |
| CPU time | 5.02 seconds |
| Started | Jan 21 10:27:21 PM PST 24 |
| Finished | Jan 21 10:27:45 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-53eb964d-92ea-4612-b2f1-f4f8ba095526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707676891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1707676891 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.290152123 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 26399624475 ps |
| CPU time | 38.92 seconds |
| Started | Jan 21 09:41:32 PM PST 24 |
| Finished | Jan 21 09:42:12 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-1eeb88a9-3565-4669-8d6e-13557f9ac132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=290152123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.290152123 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3010567653 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 572259721 ps |
| CPU time | 6.65 seconds |
| Started | Jan 21 09:41:37 PM PST 24 |
| Finished | Jan 21 09:41:45 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-9d771a81-abd9-43f1-9e4d-29603a72d122 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3010567653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3010567653 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3402200957 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 272669790 ps |
| CPU time | 5.41 seconds |
| Started | Jan 21 10:07:20 PM PST 24 |
| Finished | Jan 21 10:07:28 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-d5fa5783-2105-4fc4-93d7-1baad04c93c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3402200957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3402200957 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2489638136 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2694504510 ps |
| CPU time | 14.78 seconds |
| Started | Jan 21 10:23:17 PM PST 24 |
| Finished | Jan 21 10:23:37 PM PST 24 |
| Peak memory | 201856 kb |
| Host | smart-3596f28b-0fbc-4c55-8a80-64e3e17226fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2489638136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2489638136 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.456891329 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 51053202086 ps |
| CPU time | 95.68 seconds |
| Started | Jan 21 09:41:32 PM PST 24 |
| Finished | Jan 21 09:43:09 PM PST 24 |
| Peak memory | 202072 kb |
| Host | smart-bce3e26d-9cc9-4a4d-bf83-9b7765083a22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=456891329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.456891329 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.119223505 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 17295117175 ps |
| CPU time | 97.48 seconds |
| Started | Jan 21 09:41:34 PM PST 24 |
| Finished | Jan 21 09:43:13 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-c02df0d2-0e91-4ffb-ae26-638197b41e07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=119223505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.119223505 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.243234035 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 63695079 ps |
| CPU time | 12.75 seconds |
| Started | Jan 21 09:41:34 PM PST 24 |
| Finished | Jan 21 09:41:48 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-793efa80-43fd-4e25-a172-8e995fcb3e63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243234035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.243234035 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2116630065 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 62212544 ps |
| CPU time | 6.84 seconds |
| Started | Jan 21 09:41:40 PM PST 24 |
| Finished | Jan 21 09:41:48 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-eabd3847-2181-41b8-a36b-30139e179eb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2116630065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2116630065 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.71617515 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 11375423 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 09:41:27 PM PST 24 |
| Finished | Jan 21 09:41:30 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-459c6afd-53ba-4d34-a532-a970b558c25e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=71617515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.71617515 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.281403798 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 7796531266 ps |
| CPU time | 7.71 seconds |
| Started | Jan 21 09:41:29 PM PST 24 |
| Finished | Jan 21 09:41:38 PM PST 24 |
| Peak memory | 201872 kb |
| Host | smart-e3234b99-66de-4a99-ba0c-866be54499fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=281403798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.281403798 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1271716332 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1805191707 ps |
| CPU time | 7.84 seconds |
| Started | Jan 21 09:41:27 PM PST 24 |
| Finished | Jan 21 09:41:36 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-fe3ecea8-4eea-4cfb-8179-0929b8c0920c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1271716332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1271716332 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.517415657 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 10974386 ps |
| CPU time | 1.25 seconds |
| Started | Jan 21 09:41:30 PM PST 24 |
| Finished | Jan 21 09:41:33 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-c8684656-bb9e-40ee-aa4d-989f4e984fdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517415657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.517415657 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3085921457 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 10720213534 ps |
| CPU time | 61.56 seconds |
| Started | Jan 21 09:41:38 PM PST 24 |
| Finished | Jan 21 09:42:41 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-c0de613d-4783-49e0-b233-8a237c18bc88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085921457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3085921457 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2834343158 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1998160064 ps |
| CPU time | 18.9 seconds |
| Started | Jan 21 10:29:33 PM PST 24 |
| Finished | Jan 21 10:29:56 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-f4663846-a055-40ec-8c81-89f4ac02a0d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834343158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2834343158 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2180826749 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 117145083 ps |
| CPU time | 9.71 seconds |
| Started | Jan 21 09:41:38 PM PST 24 |
| Finished | Jan 21 09:41:48 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-0b258b67-b311-4f31-90d8-374d85bd8af8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2180826749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2180826749 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1251073407 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 776926050 ps |
| CPU time | 111.95 seconds |
| Started | Jan 21 09:41:53 PM PST 24 |
| Finished | Jan 21 09:43:52 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-fe1df3d2-fa9b-41de-be24-48b6f024d316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251073407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1251073407 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1620627868 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 67504771 ps |
| CPU time | 8.3 seconds |
| Started | Jan 21 09:41:38 PM PST 24 |
| Finished | Jan 21 09:41:48 PM PST 24 |
| Peak memory | 201840 kb |
| Host | smart-eda80a2e-a41e-4b13-9caf-84d39bd3fc58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620627868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1620627868 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.4279935244 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 50054667 ps |
| CPU time | 4.53 seconds |
| Started | Jan 21 09:42:09 PM PST 24 |
| Finished | Jan 21 09:42:18 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-bcfa6bd7-676a-4684-9353-0e5afe5df1fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4279935244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.4279935244 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2233319300 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 34742033128 ps |
| CPU time | 173.31 seconds |
| Started | Jan 21 09:42:16 PM PST 24 |
| Finished | Jan 21 09:45:12 PM PST 24 |
| Peak memory | 203000 kb |
| Host | smart-3f97b698-855f-46f0-b80d-a2e318c347b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2233319300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.2233319300 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3968385004 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 508850255 ps |
| CPU time | 2.96 seconds |
| Started | Jan 21 09:42:19 PM PST 24 |
| Finished | Jan 21 09:42:25 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-ba732736-324b-4748-b48e-3c9b5cd9ef56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968385004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3968385004 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.2860312316 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 98998090 ps |
| CPU time | 4.85 seconds |
| Started | Jan 21 09:42:15 PM PST 24 |
| Finished | Jan 21 09:42:22 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-6062d484-5c94-420b-8de1-4cebef031e13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860312316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2860312316 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.2637163050 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 72929431 ps |
| CPU time | 1.73 seconds |
| Started | Jan 21 09:42:02 PM PST 24 |
| Finished | Jan 21 09:42:12 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-0a940e18-bf15-48c8-973d-8773266ad6bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2637163050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2637163050 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2514557640 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 32777099969 ps |
| CPU time | 149.48 seconds |
| Started | Jan 21 09:42:08 PM PST 24 |
| Finished | Jan 21 09:44:43 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-17e3abbe-2a3b-430d-a33e-b23b438a082f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514557640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2514557640 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3653793212 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 54416437665 ps |
| CPU time | 171.73 seconds |
| Started | Jan 21 09:42:08 PM PST 24 |
| Finished | Jan 21 09:45:05 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-6deee747-1e13-40b8-b752-3020b3dee6a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3653793212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3653793212 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2087035606 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 40951105 ps |
| CPU time | 4.61 seconds |
| Started | Jan 21 09:42:12 PM PST 24 |
| Finished | Jan 21 09:42:20 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-a665c9b5-5f28-4611-b52c-15a84fc01a75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087035606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2087035606 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.2641414922 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 73970949 ps |
| CPU time | 6.6 seconds |
| Started | Jan 21 09:42:21 PM PST 24 |
| Finished | Jan 21 09:42:30 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-41483137-5d3d-4c90-b8c6-864effcc9bb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2641414922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2641414922 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.528667469 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17812245 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 09:42:01 PM PST 24 |
| Finished | Jan 21 09:42:12 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-e3bd10e7-e8b2-4f20-aedb-6a816e7f225c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=528667469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.528667469 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4191805645 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 5483612220 ps |
| CPU time | 7.66 seconds |
| Started | Jan 21 09:42:02 PM PST 24 |
| Finished | Jan 21 09:42:19 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-90c22174-3a98-43e5-a5b2-e856fb3c433a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191805645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4191805645 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.884461747 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 5083193642 ps |
| CPU time | 11.04 seconds |
| Started | Jan 21 09:42:01 PM PST 24 |
| Finished | Jan 21 09:42:21 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-deebcd3d-6d23-4772-9f5e-8277520ee626 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=884461747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.884461747 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1673780754 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 9656484 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 09:42:02 PM PST 24 |
| Finished | Jan 21 09:42:12 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-49937bb6-db20-4448-8fe6-1bddfc24482f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673780754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1673780754 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3109820067 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2156952866 ps |
| CPU time | 37.66 seconds |
| Started | Jan 21 09:42:19 PM PST 24 |
| Finished | Jan 21 09:42:59 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-5f2335ff-e13e-4cc1-bbb0-f011f7b20231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109820067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3109820067 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.117377282 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6894305241 ps |
| CPU time | 149.61 seconds |
| Started | Jan 21 09:42:18 PM PST 24 |
| Finished | Jan 21 09:44:51 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-40034a0f-b971-44b5-907c-638576dad0c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117377282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.117377282 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2390584323 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1882355179 ps |
| CPU time | 39.69 seconds |
| Started | Jan 21 09:42:17 PM PST 24 |
| Finished | Jan 21 09:43:00 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-b1ef92e6-9d94-4245-9f3a-2a2c987632b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390584323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2390584323 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2028963633 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 71129879 ps |
| CPU time | 4.35 seconds |
| Started | Jan 21 09:42:18 PM PST 24 |
| Finished | Jan 21 09:42:25 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-233fffd2-7b68-406d-a767-22300ea9c8d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028963633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2028963633 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2834245664 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 209436117 ps |
| CPU time | 4.36 seconds |
| Started | Jan 21 09:42:31 PM PST 24 |
| Finished | Jan 21 09:42:37 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-da2c1b98-38f6-4c20-8517-4f9fa819160e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834245664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2834245664 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1865770556 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2057882400 ps |
| CPU time | 16.52 seconds |
| Started | Jan 21 10:00:12 PM PST 24 |
| Finished | Jan 21 10:00:38 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-ec97a981-465a-42cf-aa7c-68fe1a016b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1865770556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1865770556 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.443249985 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 724625887 ps |
| CPU time | 6.22 seconds |
| Started | Jan 21 09:42:39 PM PST 24 |
| Finished | Jan 21 09:42:48 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-89d09316-daf9-40cd-bbe4-e73a1dbf98a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=443249985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.443249985 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2173498209 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1250866826 ps |
| CPU time | 5.58 seconds |
| Started | Jan 21 10:30:23 PM PST 24 |
| Finished | Jan 21 10:30:44 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-cd67852b-20ad-4dbb-8e11-1dcb19adc996 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2173498209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2173498209 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.642152374 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1597147326 ps |
| CPU time | 3.83 seconds |
| Started | Jan 21 09:42:24 PM PST 24 |
| Finished | Jan 21 09:42:30 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-4d046c39-2123-4ea2-a6d7-a01ef772084f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642152374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.642152374 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3004269379 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 32692993437 ps |
| CPU time | 85.02 seconds |
| Started | Jan 21 09:42:31 PM PST 24 |
| Finished | Jan 21 09:43:57 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-40b4e5f0-63c2-4099-a1b7-9d23227fa12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004269379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3004269379 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.805465819 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4305938067 ps |
| CPU time | 25.03 seconds |
| Started | Jan 21 11:33:47 PM PST 24 |
| Finished | Jan 21 11:34:18 PM PST 24 |
| Peak memory | 202008 kb |
| Host | smart-f6037001-2331-44e8-a544-02a615ad3f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=805465819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.805465819 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.413725184 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 20836743 ps |
| CPU time | 2.72 seconds |
| Started | Jan 21 09:42:31 PM PST 24 |
| Finished | Jan 21 09:42:35 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-f2d392d7-5f24-4441-9a31-97740c54f115 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413725184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.413725184 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1730077473 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1532976290 ps |
| CPU time | 10.4 seconds |
| Started | Jan 21 09:42:29 PM PST 24 |
| Finished | Jan 21 09:42:41 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-59447053-7ac5-49f2-bc20-6d8b8473b61c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1730077473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1730077473 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1814754643 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 59026655 ps |
| CPU time | 1.47 seconds |
| Started | Jan 21 09:42:25 PM PST 24 |
| Finished | Jan 21 09:42:28 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-bb741c41-4589-497b-a8ac-a61ba53812a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814754643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1814754643 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.652566670 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2525031301 ps |
| CPU time | 8.59 seconds |
| Started | Jan 21 09:42:23 PM PST 24 |
| Finished | Jan 21 09:42:34 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-efad7002-d562-4add-affa-2e768ed22072 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=652566670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.652566670 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2824848269 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 868103091 ps |
| CPU time | 5.39 seconds |
| Started | Jan 21 10:02:38 PM PST 24 |
| Finished | Jan 21 10:02:50 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-bd8da63a-ac3e-401e-9185-1e36e8e751ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2824848269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2824848269 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.698950805 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 13822544 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 09:42:24 PM PST 24 |
| Finished | Jan 21 09:42:27 PM PST 24 |
| Peak memory | 201800 kb |
| Host | smart-43b66d30-d63c-4217-9882-03a83c764ac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698950805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.698950805 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2123153463 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 7724612070 ps |
| CPU time | 103.32 seconds |
| Started | Jan 21 09:42:39 PM PST 24 |
| Finished | Jan 21 09:44:25 PM PST 24 |
| Peak memory | 205684 kb |
| Host | smart-5713f382-1ed5-4bc7-932b-fca94cac7620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123153463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2123153463 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.291744237 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 227946775 ps |
| CPU time | 13.84 seconds |
| Started | Jan 21 09:42:39 PM PST 24 |
| Finished | Jan 21 09:42:55 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-1bf1248d-cda0-4225-8919-c7635dfbe295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291744237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.291744237 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1531762421 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1039181591 ps |
| CPU time | 167.18 seconds |
| Started | Jan 21 09:42:39 PM PST 24 |
| Finished | Jan 21 09:45:28 PM PST 24 |
| Peak memory | 204324 kb |
| Host | smart-5cefdfac-6644-46e9-aac9-5d400089b415 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1531762421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1531762421 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4278358327 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 881810349 ps |
| CPU time | 125.36 seconds |
| Started | Jan 21 09:42:39 PM PST 24 |
| Finished | Jan 21 09:44:47 PM PST 24 |
| Peak memory | 206608 kb |
| Host | smart-978a1075-b036-418e-a672-b452a394c1fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4278358327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.4278358327 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1060121816 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 573679284 ps |
| CPU time | 8.87 seconds |
| Started | Jan 21 09:42:38 PM PST 24 |
| Finished | Jan 21 09:42:49 PM PST 24 |
| Peak memory | 201792 kb |
| Host | smart-c51c57e4-2e7a-4669-bde9-8c3a00311488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1060121816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1060121816 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2458379104 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 57375529 ps |
| CPU time | 8.83 seconds |
| Started | Jan 21 09:43:03 PM PST 24 |
| Finished | Jan 21 09:43:14 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-8c63bc55-7fe9-4dc4-8c34-2b9127aa8d92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2458379104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2458379104 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3432460823 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 26810666899 ps |
| CPU time | 164.22 seconds |
| Started | Jan 21 09:43:02 PM PST 24 |
| Finished | Jan 21 09:45:47 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-fa021857-86d4-499d-83f0-36f3d0b4fafb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3432460823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3432460823 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2954101547 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1676324794 ps |
| CPU time | 6.72 seconds |
| Started | Jan 21 09:43:03 PM PST 24 |
| Finished | Jan 21 09:43:11 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-1f6ba0b7-ee42-4aa3-83f6-dd4fe70b681e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2954101547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2954101547 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.1233781476 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 33366539 ps |
| CPU time | 3.37 seconds |
| Started | Jan 21 09:43:03 PM PST 24 |
| Finished | Jan 21 09:43:07 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-0cdde4c5-0ce9-4121-97e6-eaafc201ec47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233781476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1233781476 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.2913110881 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 645028226 ps |
| CPU time | 9.53 seconds |
| Started | Jan 21 09:42:49 PM PST 24 |
| Finished | Jan 21 09:43:00 PM PST 24 |
| Peak memory | 201696 kb |
| Host | smart-50c517fd-db1c-4944-8435-c3ef605f0c7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913110881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2913110881 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1795483258 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 87033579605 ps |
| CPU time | 74.38 seconds |
| Started | Jan 21 09:42:57 PM PST 24 |
| Finished | Jan 21 09:44:13 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-dceffd89-ff30-438d-8323-10e749f481ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795483258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1795483258 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1692748349 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5917994975 ps |
| CPU time | 38.48 seconds |
| Started | Jan 21 09:42:54 PM PST 24 |
| Finished | Jan 21 09:43:35 PM PST 24 |
| Peak memory | 201852 kb |
| Host | smart-a83a8a49-69f5-4c62-9fcb-94cb331b0626 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1692748349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1692748349 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1325047727 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 39178014 ps |
| CPU time | 7.02 seconds |
| Started | Jan 21 09:42:53 PM PST 24 |
| Finished | Jan 21 09:43:03 PM PST 24 |
| Peak memory | 201812 kb |
| Host | smart-b321bb08-a957-4b25-8da3-aeaabf77eb2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325047727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1325047727 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3875334728 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 733976990 ps |
| CPU time | 9.56 seconds |
| Started | Jan 21 09:43:02 PM PST 24 |
| Finished | Jan 21 09:43:13 PM PST 24 |
| Peak memory | 201804 kb |
| Host | smart-dcc14dbd-e4c7-4186-a7a4-c66feac0c7f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3875334728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3875334728 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.2459493609 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 268451945 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 09:42:42 PM PST 24 |
| Finished | Jan 21 09:42:44 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-2878ce8f-5f1d-4ffd-8989-c8f3d2d14826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459493609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2459493609 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.355783440 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1393512053 ps |
| CPU time | 7.36 seconds |
| Started | Jan 21 09:42:40 PM PST 24 |
| Finished | Jan 21 09:42:49 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-2275fed9-10d7-44ed-9242-e7647e6c52d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=355783440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.355783440 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2613244138 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 6990089991 ps |
| CPU time | 9.16 seconds |
| Started | Jan 21 09:42:49 PM PST 24 |
| Finished | Jan 21 09:43:00 PM PST 24 |
| Peak memory | 201780 kb |
| Host | smart-2f398edc-aa72-484a-8a5e-72cfa7d0aca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2613244138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2613244138 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1114054101 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 8307358 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 09:42:38 PM PST 24 |
| Finished | Jan 21 09:42:41 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-bd9c2da4-20ae-4fcb-a902-68c248f363dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114054101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1114054101 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.368378007 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 715676698 ps |
| CPU time | 9.81 seconds |
| Started | Jan 21 09:43:03 PM PST 24 |
| Finished | Jan 21 09:43:14 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-5d03a921-ad39-42e4-9159-adda77645524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=368378007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.368378007 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3788802899 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1314609632 ps |
| CPU time | 124.13 seconds |
| Started | Jan 21 09:43:02 PM PST 24 |
| Finished | Jan 21 09:45:07 PM PST 24 |
| Peak memory | 206840 kb |
| Host | smart-c98c1d77-a5d0-4d2d-855f-31beb1df8acc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788802899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3788802899 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2128335886 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 184740069 ps |
| CPU time | 12.39 seconds |
| Started | Jan 21 09:43:15 PM PST 24 |
| Finished | Jan 21 09:43:32 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-9699a5e1-d0cb-4419-8372-7972ec6f8eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128335886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2128335886 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.557359360 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 574373189 ps |
| CPU time | 9.65 seconds |
| Started | Jan 21 09:43:04 PM PST 24 |
| Finished | Jan 21 09:43:16 PM PST 24 |
| Peak memory | 201844 kb |
| Host | smart-c41f89d6-3743-4100-a420-a71737c78ff4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=557359360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.557359360 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3926541506 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 218483401 ps |
| CPU time | 9.94 seconds |
| Started | Jan 21 09:43:22 PM PST 24 |
| Finished | Jan 21 09:43:40 PM PST 24 |
| Peak memory | 201836 kb |
| Host | smart-7e44e7f3-a43a-4122-b444-9bf2fddce541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926541506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3926541506 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1777102280 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 42593857 ps |
| CPU time | 4.92 seconds |
| Started | Jan 21 09:43:22 PM PST 24 |
| Finished | Jan 21 09:43:34 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-89e4a828-02ea-478c-979a-9ac07ccce1ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1777102280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1777102280 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.3992217806 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 32380178 ps |
| CPU time | 2.15 seconds |
| Started | Jan 21 09:43:21 PM PST 24 |
| Finished | Jan 21 09:43:31 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-12e501b8-f6a2-4ce5-915d-83896e8531cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3992217806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3992217806 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3448235956 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 330827032 ps |
| CPU time | 5.84 seconds |
| Started | Jan 21 09:43:15 PM PST 24 |
| Finished | Jan 21 09:43:25 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-979462d6-8d52-455b-8c9c-013f65bed4ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3448235956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3448235956 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3697744699 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 42202827730 ps |
| CPU time | 95.27 seconds |
| Started | Jan 21 09:43:18 PM PST 24 |
| Finished | Jan 21 09:44:58 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-f1277e29-8308-4e0a-9f8e-68f03af8c521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697744699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3697744699 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3141801561 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 33720561574 ps |
| CPU time | 187.56 seconds |
| Started | Jan 21 09:43:14 PM PST 24 |
| Finished | Jan 21 09:46:24 PM PST 24 |
| Peak memory | 201832 kb |
| Host | smart-91bda9f6-4137-4693-9916-6d5a6a4e0b5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3141801561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3141801561 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3283188346 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 12121678 ps |
| CPU time | 1.67 seconds |
| Started | Jan 21 09:43:18 PM PST 24 |
| Finished | Jan 21 09:43:25 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-5be7d8ff-6207-4695-8d4f-16e163727f7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283188346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3283188346 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.686826835 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 29354744 ps |
| CPU time | 2.32 seconds |
| Started | Jan 21 10:07:13 PM PST 24 |
| Finished | Jan 21 10:07:21 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-f55a5cff-93bb-4e0a-a008-6f84395177a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686826835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.686826835 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3846055163 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 67223175 ps |
| CPU time | 1.59 seconds |
| Started | Jan 21 09:43:18 PM PST 24 |
| Finished | Jan 21 09:43:24 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-90bf2ffc-652d-4295-9b32-04a1aeade6a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3846055163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3846055163 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1834111677 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2993431485 ps |
| CPU time | 10.88 seconds |
| Started | Jan 21 09:43:13 PM PST 24 |
| Finished | Jan 21 09:43:26 PM PST 24 |
| Peak memory | 201816 kb |
| Host | smart-ec0ab8b8-366d-49e7-9c4b-a59e6c1d041e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834111677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1834111677 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3503264774 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1244281225 ps |
| CPU time | 7.68 seconds |
| Started | Jan 21 09:43:16 PM PST 24 |
| Finished | Jan 21 09:43:28 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-89c2baa8-1a38-4537-b1f9-69d26336a547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3503264774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3503264774 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4183208119 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 8813801 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 09:43:15 PM PST 24 |
| Finished | Jan 21 09:43:20 PM PST 24 |
| Peak memory | 201796 kb |
| Host | smart-e471e967-af6a-4911-aa7c-9fc2886e5858 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183208119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4183208119 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2442754210 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1941954418 ps |
| CPU time | 30.05 seconds |
| Started | Jan 21 10:05:49 PM PST 24 |
| Finished | Jan 21 10:06:27 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-926430c1-e761-4b60-824f-a6db57842091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442754210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2442754210 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.828836790 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2628859122 ps |
| CPU time | 35.29 seconds |
| Started | Jan 21 09:43:23 PM PST 24 |
| Finished | Jan 21 09:44:06 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-d202f4b1-80b4-4d7c-a405-c5e8ca4e3aed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828836790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.828836790 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.4269989648 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 287321135 ps |
| CPU time | 28.24 seconds |
| Started | Jan 21 09:43:21 PM PST 24 |
| Finished | Jan 21 09:43:56 PM PST 24 |
| Peak memory | 202872 kb |
| Host | smart-643b1e77-3e90-409a-8921-9c42b853c28e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4269989648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.4269989648 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.554584008 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1094743452 ps |
| CPU time | 11.12 seconds |
| Started | Jan 21 09:43:22 PM PST 24 |
| Finished | Jan 21 09:43:40 PM PST 24 |
| Peak memory | 201820 kb |
| Host | smart-77c231ff-4df0-47a6-bc25-950ecee86ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=554584008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.554584008 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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