Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354	1			T4	2		T14	1		T196	3
all_values[1]	411	1			T4	1		T18	1		T196	9
all_values[2]	403	1			T4	1		T196	5		T22	2
all_values[3]	417	1			T4	2		T14	1		T196	4
all_values[4]	455	1			T14	1		T18	1		T196	3
all_values[5]	402	1			T4	2		T196	2		T202	1
all_values[6]	425	1			T18	1		T196	2		T6	1
all_values[7]	419	1			T4	5		T20	1		T196	3
all_values[8]	446	1			T4	1		T14	1		T196	5
all_values[9]	402	1			T4	3		T18	2		T196	9
all_values[10]	412	1			T4	3		T14	1		T196	5
all_values[11]	379	1			T18	1		T6	2		T34	6
all_values[12]	398	1			T4	4		T196	2		T22	2
all_values[13]	417	1			T4	1		T18	1		T20	1
all_values[14]	405	1			T196	4		T6	1		T35	1
all_values[15]	425	1			T18	1		T196	3		T22	1
all_values[16]	417	1			T4	2		T196	7		T22	2
all_values[17]	432	1			T4	1		T196	4		T6	4
all_values[18]	372	1			T4	1		T196	4		T6	1
all_values[19]	400	1			T4	1		T18	1		T196	7
all_values[20]	371	1			T4	1		T196	5		T6	1
all_values[21]	407	1			T18	1		T196	5		T22	1
all_values[22]	415	1			T4	1		T18	1		T196	2
all_values[23]	387	1			T18	1		T196	1		T22	1
all_values[24]	427	1			T4	1		T20	1		T196	3
all_values[25]	405	1			T4	1		T14	1		T20	1
all_values[26]	399	1			T4	1		T196	4		T6	4