| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.32 | 100.00 | 95.90 | 100.00 | 100.00 | 100.00 | 100.00 |
| T770 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3163800585 | Feb 07 12:26:55 PM PST 24 | Feb 07 12:27:03 PM PST 24 | 2101820706 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3394926543 | Feb 07 12:27:10 PM PST 24 | Feb 07 12:27:24 PM PST 24 | 1417237670 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3700484645 | Feb 07 12:27:28 PM PST 24 | Feb 07 12:27:45 PM PST 24 | 709081235 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3021707694 | Feb 07 12:32:54 PM PST 24 | Feb 07 12:33:24 PM PST 24 | 56988218 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2145638610 | Feb 07 12:27:28 PM PST 24 | Feb 07 12:28:29 PM PST 24 | 4840104040 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3985898436 | Feb 07 12:28:09 PM PST 24 | Feb 07 12:28:15 PM PST 24 | 136504290 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2838861515 | Feb 07 12:26:59 PM PST 24 | Feb 07 12:27:07 PM PST 24 | 295002339 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2616902425 | Feb 07 12:33:07 PM PST 24 | Feb 07 12:33:25 PM PST 24 | 37512184 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2731557178 | Feb 07 12:32:53 PM PST 24 | Feb 07 12:33:12 PM PST 24 | 22197205 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3140833634 | Feb 07 12:28:21 PM PST 24 | Feb 07 12:28:25 PM PST 24 | 87092023 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3631181167 | Feb 07 12:27:54 PM PST 24 | Feb 07 12:28:02 PM PST 24 | 38940580 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3520529929 | Feb 07 12:32:23 PM PST 24 | Feb 07 12:32:35 PM PST 24 | 52651759 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.562225780 | Feb 07 12:33:10 PM PST 24 | Feb 07 12:34:24 PM PST 24 | 24122430681 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1092749539 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:28:59 PM PST 24 | 304600249 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1438578266 | Feb 07 12:27:28 PM PST 24 | Feb 07 12:27:40 PM PST 24 | 948446025 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3469141253 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:29 PM PST 24 | 909342014 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1632733841 | Feb 07 12:33:09 PM PST 24 | Feb 07 12:34:14 PM PST 24 | 3066756688 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3303754561 | Feb 07 12:27:49 PM PST 24 | Feb 07 12:30:36 PM PST 24 | 21790305081 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.444989126 | Feb 07 12:27:58 PM PST 24 | Feb 07 12:30:13 PM PST 24 | 24641667758 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3468916860 | Feb 07 12:27:43 PM PST 24 | Feb 07 12:27:49 PM PST 24 | 476740382 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.583719648 | Feb 07 12:28:56 PM PST 24 | Feb 07 12:30:13 PM PST 24 | 5267482789 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/13.xbar_same_source.183477509 | Feb 07 12:27:44 PM PST 24 | Feb 07 12:27:56 PM PST 24 | 1006148931 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2216798488 | Feb 07 12:27:26 PM PST 24 | Feb 07 12:27:37 PM PST 24 | 444102984 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/0.xbar_random.1126275406 | Feb 07 12:26:44 PM PST 24 | Feb 07 12:26:51 PM PST 24 | 60525367 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3663430725 | Feb 07 12:27:29 PM PST 24 | Feb 07 12:28:31 PM PST 24 | 48718775190 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1210014577 | Feb 07 12:32:58 PM PST 24 | Feb 07 12:33:56 PM PST 24 | 3626900197 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3961432646 | Feb 07 12:32:27 PM PST 24 | Feb 07 12:32:46 PM PST 24 | 1799631130 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3285588782 | Feb 07 12:27:19 PM PST 24 | Feb 07 12:27:25 PM PST 24 | 33001689 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1856136790 | Feb 07 12:33:07 PM PST 24 | Feb 07 12:33:30 PM PST 24 | 2795506413 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/44.xbar_random.3597523474 | Feb 07 12:32:58 PM PST 24 | Feb 07 12:33:18 PM PST 24 | 1031664790 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2635398763 | Feb 07 12:32:59 PM PST 24 | Feb 07 12:33:38 PM PST 24 | 642482304 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.854481717 | Feb 07 12:28:17 PM PST 24 | Feb 07 12:28:19 PM PST 24 | 12404493 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1887000639 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:55 PM PST 24 | 19217845104 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1847639134 | Feb 07 12:28:40 PM PST 24 | Feb 07 12:28:50 PM PST 24 | 21571584 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3705737762 | Feb 07 12:32:20 PM PST 24 | Feb 07 12:32:34 PM PST 24 | 163653140 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.965863727 | Feb 07 12:32:24 PM PST 24 | Feb 07 12:32:47 PM PST 24 | 979049818 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1259168047 | Feb 07 12:32:56 PM PST 24 | Feb 07 12:34:09 PM PST 24 | 7850941178 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1787271870 | Feb 07 12:27:42 PM PST 24 | Feb 07 12:27:50 PM PST 24 | 486854951 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2420097617 | Feb 07 12:27:56 PM PST 24 | Feb 07 12:28:05 PM PST 24 | 334664951 ps | ||
| T133 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2024203906 | Feb 07 12:28:31 PM PST 24 | Feb 07 12:30:58 PM PST 24 | 5980062593 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.253542296 | Feb 07 12:27:28 PM PST 24 | Feb 07 12:27:38 PM PST 24 | 775954614 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.813437941 | Feb 07 12:27:11 PM PST 24 | Feb 07 12:27:25 PM PST 24 | 6137434295 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2949170280 | Feb 07 12:26:50 PM PST 24 | Feb 07 12:26:55 PM PST 24 | 75946306 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1323358653 | Feb 07 12:32:12 PM PST 24 | Feb 07 12:34:36 PM PST 24 | 55596500080 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.12024720 | Feb 07 12:32:54 PM PST 24 | Feb 07 12:33:13 PM PST 24 | 18293821 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2731439292 | Feb 07 12:26:58 PM PST 24 | Feb 07 12:28:43 PM PST 24 | 33025199473 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.4104248691 | Feb 07 12:27:56 PM PST 24 | Feb 07 12:28:04 PM PST 24 | 17771139 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.811477354 | Feb 07 12:32:26 PM PST 24 | Feb 07 12:33:29 PM PST 24 | 15469347102 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.4015965930 | Feb 07 12:27:14 PM PST 24 | Feb 07 12:27:25 PM PST 24 | 718692019 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.66937624 | Feb 07 12:28:58 PM PST 24 | Feb 07 12:29:28 PM PST 24 | 12375298144 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2939376703 | Feb 07 12:28:58 PM PST 24 | Feb 07 12:29:23 PM PST 24 | 748765898 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1242389670 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:53 PM PST 24 | 34596247101 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/1.xbar_random.684876165 | Feb 07 12:26:47 PM PST 24 | Feb 07 12:26:56 PM PST 24 | 470846973 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.175346830 | Feb 07 12:28:21 PM PST 24 | Feb 07 12:31:26 PM PST 24 | 7851937992 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2469519059 | Feb 07 12:32:37 PM PST 24 | Feb 07 12:32:56 PM PST 24 | 358458383 ps | ||
| T113 | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1360418473 | Feb 07 12:27:48 PM PST 24 | Feb 07 12:30:41 PM PST 24 | 29408521484 ps | ||
| T171 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.12452586 | Feb 07 12:28:00 PM PST 24 | Feb 07 12:33:07 PM PST 24 | 108770406704 ps | ||
| T172 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.4224041176 | Feb 07 12:27:40 PM PST 24 | Feb 07 12:27:43 PM PST 24 | 62800490 ps | ||
| T122 | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.763900303 | Feb 07 12:27:39 PM PST 24 | Feb 07 12:29:17 PM PST 24 | 54588785782 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.41948094 | Feb 07 12:32:37 PM PST 24 | Feb 07 12:32:56 PM PST 24 | 44741186 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2968548513 | Feb 07 12:28:04 PM PST 24 | Feb 07 12:29:02 PM PST 24 | 5888800831 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2432341849 | Feb 07 12:27:15 PM PST 24 | Feb 07 12:27:21 PM PST 24 | 30663603 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4224126238 | Feb 07 12:27:35 PM PST 24 | Feb 07 12:27:44 PM PST 24 | 1334482099 ps | ||
| T123 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.4185242274 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:20 PM PST 24 | 940490855 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/11.xbar_random.1432268025 | Feb 07 12:27:36 PM PST 24 | Feb 07 12:27:44 PM PST 24 | 603496613 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2085547771 | Feb 07 12:27:42 PM PST 24 | Feb 07 12:28:02 PM PST 24 | 349316837 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2009788427 | Feb 07 12:27:43 PM PST 24 | Feb 07 12:27:45 PM PST 24 | 8108799 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1537573674 | Feb 07 12:27:46 PM PST 24 | Feb 07 12:28:00 PM PST 24 | 2653037390 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2141303077 | Feb 07 12:28:41 PM PST 24 | Feb 07 12:29:01 PM PST 24 | 547338349 ps | ||
| T114 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2495098712 | Feb 07 12:27:27 PM PST 24 | Feb 07 12:31:24 PM PST 24 | 46867992751 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2867619875 | Feb 07 12:27:50 PM PST 24 | Feb 07 12:28:07 PM PST 24 | 971889895 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/6.xbar_error_random.184860123 | Feb 07 12:27:19 PM PST 24 | Feb 07 12:27:32 PM PST 24 | 1062866542 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3107890880 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:30:09 PM PST 24 | 959952225 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1346531868 | Feb 07 12:32:49 PM PST 24 | Feb 07 12:33:10 PM PST 24 | 26832712 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3717925506 | Feb 07 12:27:58 PM PST 24 | Feb 07 12:28:12 PM PST 24 | 2241237121 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.978172681 | Feb 07 12:27:57 PM PST 24 | Feb 07 12:29:08 PM PST 24 | 387871763 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2252433030 | Feb 07 12:27:12 PM PST 24 | Feb 07 12:29:44 PM PST 24 | 20253060394 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1572882489 | Feb 07 12:27:42 PM PST 24 | Feb 07 12:27:47 PM PST 24 | 212253143 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/31.xbar_same_source.4271694919 | Feb 07 12:28:34 PM PST 24 | Feb 07 12:28:38 PM PST 24 | 27250785 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/16.xbar_random.2943913364 | Feb 07 12:27:55 PM PST 24 | Feb 07 12:28:12 PM PST 24 | 1476174114 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2744942135 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:18 PM PST 24 | 53027544 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.4099123366 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:28:27 PM PST 24 | 30666731 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4018257898 | Feb 07 12:27:38 PM PST 24 | Feb 07 12:29:26 PM PST 24 | 2635459316 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1464479917 | Feb 07 12:32:19 PM PST 24 | Feb 07 12:32:32 PM PST 24 | 1707439464 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.240570175 | Feb 07 12:32:28 PM PST 24 | Feb 07 12:32:40 PM PST 24 | 9369303 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2061712113 | Feb 07 12:33:01 PM PST 24 | Feb 07 12:33:21 PM PST 24 | 313856820 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/17.xbar_smoke.404613698 | Feb 07 12:28:02 PM PST 24 | Feb 07 12:28:06 PM PST 24 | 270564136 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.723171369 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:28:25 PM PST 24 | 9459617 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4185177241 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:30:23 PM PST 24 | 17127553352 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4222997498 | Feb 07 12:33:09 PM PST 24 | Feb 07 12:33:32 PM PST 24 | 3819243738 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2102435494 | Feb 07 12:32:47 PM PST 24 | Feb 07 12:35:32 PM PST 24 | 11996176961 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3674095994 | Feb 07 12:32:26 PM PST 24 | Feb 07 12:32:44 PM PST 24 | 4576506503 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2379531785 | Feb 07 12:27:08 PM PST 24 | Feb 07 12:27:16 PM PST 24 | 766143108 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2544791044 | Feb 07 12:26:57 PM PST 24 | Feb 07 12:27:09 PM PST 24 | 6499717149 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1190974012 | Feb 07 12:33:15 PM PST 24 | Feb 07 12:34:31 PM PST 24 | 39853878087 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.226958949 | Feb 07 12:27:45 PM PST 24 | Feb 07 12:28:10 PM PST 24 | 1546247377 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.17350704 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:28:35 PM PST 24 | 3491392699 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3103250777 | Feb 07 12:28:22 PM PST 24 | Feb 07 12:28:39 PM PST 24 | 722221472 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4057191132 | Feb 07 12:32:46 PM PST 24 | Feb 07 12:33:14 PM PST 24 | 2521050115 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1232097832 | Feb 07 12:27:09 PM PST 24 | Feb 07 12:32:10 PM PST 24 | 44382934716 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.122258356 | Feb 07 12:32:15 PM PST 24 | Feb 07 12:32:26 PM PST 24 | 64136060 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3116348764 | Feb 07 12:28:21 PM PST 24 | Feb 07 12:28:25 PM PST 24 | 8505978 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4267301703 | Feb 07 12:32:31 PM PST 24 | Feb 07 12:32:51 PM PST 24 | 3625054077 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2402913926 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:28:23 PM PST 24 | 239988900 ps | ||
| T184 | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1322654655 | Feb 07 12:27:37 PM PST 24 | Feb 07 12:28:20 PM PST 24 | 32548832425 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3119803006 | Feb 07 12:33:04 PM PST 24 | Feb 07 12:33:21 PM PST 24 | 288618055 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1498747186 | Feb 07 12:28:32 PM PST 24 | Feb 07 12:28:41 PM PST 24 | 1277274580 ps | ||
| T155 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1033084873 | Feb 07 12:27:23 PM PST 24 | Feb 07 12:28:10 PM PST 24 | 3605958666 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4160293999 | Feb 07 12:32:29 PM PST 24 | Feb 07 12:33:16 PM PST 24 | 334806220 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1364856703 | Feb 07 12:28:15 PM PST 24 | Feb 07 12:30:33 PM PST 24 | 70834169424 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1908122031 | Feb 07 12:32:37 PM PST 24 | Feb 07 12:32:58 PM PST 24 | 136898190 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2293854144 | Feb 07 12:27:48 PM PST 24 | Feb 07 12:27:56 PM PST 24 | 96142241 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1782014572 | Feb 07 12:26:46 PM PST 24 | Feb 07 12:26:49 PM PST 24 | 17075299 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2058636314 | Feb 07 12:29:00 PM PST 24 | Feb 07 12:29:16 PM PST 24 | 3377791780 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.416627878 | Feb 07 12:33:16 PM PST 24 | Feb 07 12:33:31 PM PST 24 | 56225163 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/3.xbar_random.2803419430 | Feb 07 12:27:05 PM PST 24 | Feb 07 12:27:16 PM PST 24 | 183466125 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3878971912 | Feb 07 12:32:56 PM PST 24 | Feb 07 12:33:15 PM PST 24 | 19398377 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2055678147 | Feb 07 12:28:34 PM PST 24 | Feb 07 12:28:37 PM PST 24 | 13701561 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.407251743 | Feb 07 12:33:00 PM PST 24 | Feb 07 12:34:02 PM PST 24 | 361032034 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.478724818 | Feb 07 12:28:06 PM PST 24 | Feb 07 12:28:29 PM PST 24 | 9883137048 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2215948918 | Feb 07 12:27:29 PM PST 24 | Feb 07 12:27:36 PM PST 24 | 38046556 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.919118787 | Feb 07 12:32:52 PM PST 24 | Feb 07 12:34:05 PM PST 24 | 2572379450 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3411575446 | Feb 07 12:32:41 PM PST 24 | Feb 07 12:33:02 PM PST 24 | 3747356988 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.697257908 | Feb 07 12:28:40 PM PST 24 | Feb 07 12:29:42 PM PST 24 | 9424687157 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3810090930 | Feb 07 12:27:19 PM PST 24 | Feb 07 12:27:23 PM PST 24 | 51238275 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.739505841 | Feb 07 12:28:51 PM PST 24 | Feb 07 12:28:53 PM PST 24 | 9959022 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1662249809 | Feb 07 12:28:03 PM PST 24 | Feb 07 12:33:07 PM PST 24 | 62148093539 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3535077153 | Feb 07 12:32:59 PM PST 24 | Feb 07 12:34:28 PM PST 24 | 527350874 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.288129044 | Feb 07 12:28:02 PM PST 24 | Feb 07 12:28:36 PM PST 24 | 1193264723 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.144971338 | Feb 07 12:33:01 PM PST 24 | Feb 07 12:33:53 PM PST 24 | 15115888455 ps | ||
| T115 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3047761983 | Feb 07 12:32:21 PM PST 24 | Feb 07 12:33:49 PM PST 24 | 3029603075 ps | ||
| T7 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1505906815 | Feb 07 12:33:06 PM PST 24 | Feb 07 12:35:31 PM PST 24 | 5096368111 ps | ||
| T163 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4171964586 | Feb 07 12:27:17 PM PST 24 | Feb 07 12:28:27 PM PST 24 | 12791426381 ps | ||
| T164 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.566773159 | Feb 07 12:32:58 PM PST 24 | Feb 07 12:33:17 PM PST 24 | 17348893 ps | ||
| T165 | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1760912504 | Feb 07 12:27:23 PM PST 24 | Feb 07 12:27:39 PM PST 24 | 5103829461 ps | ||
| T166 | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1449780639 | Feb 07 12:32:32 PM PST 24 | Feb 07 12:33:26 PM PST 24 | 21089682074 ps | ||
| T167 | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2907342836 | Feb 07 12:28:09 PM PST 24 | Feb 07 12:31:16 PM PST 24 | 41353537570 ps | ||
| T168 | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2240968680 | Feb 07 12:32:56 PM PST 24 | Feb 07 12:33:15 PM PST 24 | 128522106 ps | ||
| T169 | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2825884756 | Feb 07 12:32:38 PM PST 24 | Feb 07 12:32:53 PM PST 24 | 38485935 ps | ||
| T170 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1213760690 | Feb 07 12:27:23 PM PST 24 | Feb 07 12:29:32 PM PST 24 | 4376083557 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.133014504 | Feb 07 12:27:37 PM PST 24 | Feb 07 12:27:41 PM PST 24 | 28598454 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3537084331 | Feb 07 12:27:19 PM PST 24 | Feb 07 12:27:27 PM PST 24 | 167778501 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3435717657 | Feb 07 12:28:24 PM PST 24 | Feb 07 12:28:34 PM PST 24 | 4165693283 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2093124116 | Feb 07 12:28:26 PM PST 24 | Feb 07 12:28:34 PM PST 24 | 1565872377 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/14.xbar_random.3645810885 | Feb 07 12:27:44 PM PST 24 | Feb 07 12:28:01 PM PST 24 | 729988292 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2385037722 | Feb 07 12:27:21 PM PST 24 | Feb 07 12:29:52 PM PST 24 | 1239838956 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1482614979 | Feb 07 12:32:40 PM PST 24 | Feb 07 12:33:00 PM PST 24 | 604856538 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2291363729 | Feb 07 12:32:25 PM PST 24 | Feb 07 12:32:46 PM PST 24 | 193362527 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1728433667 | Feb 07 12:26:48 PM PST 24 | Feb 07 12:28:41 PM PST 24 | 9232591043 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2801923614 | Feb 07 12:32:12 PM PST 24 | Feb 07 12:33:27 PM PST 24 | 16309141327 ps |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3973193424 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8659302619 ps |
| CPU time | 110.27 seconds |
| Started | Feb 07 12:32:46 PM PST 24 |
| Finished | Feb 07 12:34:53 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-95c6084f-0694-4be6-8f07-c87412db4fa2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3973193424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3973193424 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.4204130524 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 51065230030 ps |
| CPU time | 393.55 seconds |
| Started | Feb 07 12:32:22 PM PST 24 |
| Finished | Feb 07 12:39:03 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-ed9ba144-6564-4fc5-9b9c-34a123bb57a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4204130524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.4204130524 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.321228628 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 112026585809 ps |
| CPU time | 360.09 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:34:43 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-1afc24af-ed2e-4987-85d4-ca14e45ea3f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=321228628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.321228628 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2986236845 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28193560280 ps |
| CPU time | 209.78 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:36:43 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-4a44e430-5335-4684-9455-d6a3872cc796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2986236845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2986236845 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2397401633 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 52921159644 ps |
| CPU time | 102.27 seconds |
| Started | Feb 07 12:32:54 PM PST 24 |
| Finished | Feb 07 12:34:54 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-f1bb5f9b-62a1-4e13-b8ee-1b0de7df2da5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2397401633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2397401633 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3647260694 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 143951578 ps |
| CPU time | 16.98 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:33:06 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-8e7ca2f9-6148-4077-ae03-472b6429c5df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3647260694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3647260694 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2536294530 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 47301874881 ps |
| CPU time | 194.39 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:31:19 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-7d7a4bf6-b33e-440c-9c2b-8db8aa952e2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2536294530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2536294530 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1023258744 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1642057192 ps |
| CPU time | 28.14 seconds |
| Started | Feb 07 12:28:08 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-e216994f-8e78-41c4-bfee-805a69de5753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1023258744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1023258744 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1560382539 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 849372544 ps |
| CPU time | 179.58 seconds |
| Started | Feb 07 12:28:42 PM PST 24 |
| Finished | Feb 07 12:31:45 PM PST 24 |
| Peak memory | 207340 kb |
| Host | smart-efcd2eb7-af7e-440a-8e73-56b8592e2884 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1560382539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1560382539 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.665821427 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2984874849 ps |
| CPU time | 9.45 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:26:57 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-33992958-0c4a-41c6-b1b3-85337651abcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=665821427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.665821427 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1565381734 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 528415505 ps |
| CPU time | 82.75 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-651c8a36-d69a-4f12-9569-d22c0be7b9c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1565381734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1565381734 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.826845626 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 39492495991 ps |
| CPU time | 309.72 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:38:25 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-64b89658-f4e8-4b8d-8760-114dcd146df2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=826845626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.826845626 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.737788014 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 434004836 ps |
| CPU time | 57.87 seconds |
| Started | Feb 07 12:32:12 PM PST 24 |
| Finished | Feb 07 12:33:13 PM PST 24 |
| Peak memory | 204344 kb |
| Host | smart-1623d3b6-5681-4da8-932f-16c20ebb0ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=737788014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.737788014 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3043761297 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 22374789777 ps |
| CPU time | 124.77 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:29:20 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-3a5f55f5-afa4-4e3a-a92a-634980c9ef70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3043761297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3043761297 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1189702160 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6018719798 ps |
| CPU time | 120.98 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:29:16 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-4bbabfb7-6d8b-4fa2-892f-e5986e0e4068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1189702160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1189702160 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.4244282011 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 318698844 ps |
| CPU time | 30.23 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:28:08 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-a7e8934a-a57c-417b-a3dc-33375d9a3533 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244282011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.4244282011 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1505906815 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5096368111 ps |
| CPU time | 131.1 seconds |
| Started | Feb 07 12:33:06 PM PST 24 |
| Finished | Feb 07 12:35:31 PM PST 24 |
| Peak memory | 207892 kb |
| Host | smart-3d716e05-1fc7-4c56-880a-ac817bf554a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505906815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1505906815 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3538547268 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1774859493 ps |
| CPU time | 29.47 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 199616 kb |
| Host | smart-d6c62610-a7d7-4f6c-90c2-12e4357f296f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538547268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3538547268 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3573762170 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 539334541 ps |
| CPU time | 48.06 seconds |
| Started | Feb 07 12:27:05 PM PST 24 |
| Finished | Feb 07 12:27:57 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-64c1db9e-bcab-4848-b376-d9fdfcc88bfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3573762170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3573762170 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2844094810 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 39409946328 ps |
| CPU time | 199.64 seconds |
| Started | Feb 07 12:26:48 PM PST 24 |
| Finished | Feb 07 12:30:09 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-44545c8e-ef24-4263-9cea-4b0148fb3d19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2844094810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2844094810 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2024203906 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5980062593 ps |
| CPU time | 145.45 seconds |
| Started | Feb 07 12:28:31 PM PST 24 |
| Finished | Feb 07 12:30:58 PM PST 24 |
| Peak memory | 206904 kb |
| Host | smart-b1f087f5-308f-43f0-911d-3bb0e71320ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2024203906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.2024203906 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.33197890 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 29041183412 ps |
| CPU time | 175.08 seconds |
| Started | Feb 07 12:26:43 PM PST 24 |
| Finished | Feb 07 12:29:39 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-588aa930-56db-4540-a4ea-29169da298c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=33197890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.33197890 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1937432601 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 628997621 ps |
| CPU time | 92.98 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:29:20 PM PST 24 |
| Peak memory | 206140 kb |
| Host | smart-463bc376-7033-4c54-99ce-21f0ef8e565c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1937432601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1937432601 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.824294889 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 5305197427 ps |
| CPU time | 41.27 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-12e4eac1-fbe9-4df8-81ad-cf3fa4b991d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824294889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.824294889 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2560664586 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 156664603161 ps |
| CPU time | 205.65 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:31:12 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-99175ebf-d517-436d-a1f7-8fe624f1ecad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2560664586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2560664586 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3983184006 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 8552195306 ps |
| CPU time | 185.75 seconds |
| Started | Feb 07 12:27:47 PM PST 24 |
| Finished | Feb 07 12:30:58 PM PST 24 |
| Peak memory | 207276 kb |
| Host | smart-1c7c4008-c777-43de-a63e-ec5b1582fc30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983184006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3983184006 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3047761983 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3029603075 ps |
| CPU time | 81.4 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:33:49 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-f7d9e002-4296-40e6-905e-c50154c8a738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047761983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3047761983 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.4104210628 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 131410680 ps |
| CPU time | 3.17 seconds |
| Started | Feb 07 12:26:42 PM PST 24 |
| Finished | Feb 07 12:26:46 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-5d15fa56-e224-4291-b254-09d0e31d9f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104210628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4104210628 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2971749849 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 733353556 ps |
| CPU time | 6.02 seconds |
| Started | Feb 07 12:26:43 PM PST 24 |
| Finished | Feb 07 12:26:50 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-1a9c674f-ca47-4478-9200-749d5f466ade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971749849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2971749849 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1249459556 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 424557059 ps |
| CPU time | 7.93 seconds |
| Started | Feb 07 12:26:45 PM PST 24 |
| Finished | Feb 07 12:26:55 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-9bcc94f7-bd29-4452-a89d-55408c4a9486 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1249459556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1249459556 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.1126275406 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 60525367 ps |
| CPU time | 5.59 seconds |
| Started | Feb 07 12:26:44 PM PST 24 |
| Finished | Feb 07 12:26:51 PM PST 24 |
| Peak memory | 202152 kb |
| Host | smart-674b5896-1aec-4786-af87-ef984565aacf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1126275406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1126275406 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1271889103 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 58941571128 ps |
| CPU time | 62.71 seconds |
| Started | Feb 07 12:26:48 PM PST 24 |
| Finished | Feb 07 12:27:52 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-5a5a90c9-706c-4905-8371-f0756576ac6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271889103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1271889103 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2758175680 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 47608186 ps |
| CPU time | 4.02 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:03 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-0eca95f5-8aa0-4d3b-974d-bce8d16b8d21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758175680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2758175680 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3178629835 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2012256085 ps |
| CPU time | 12.67 seconds |
| Started | Feb 07 12:26:44 PM PST 24 |
| Finished | Feb 07 12:26:58 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-f4760091-b11b-4b99-b83b-c4da037bbc62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3178629835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3178629835 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.126325163 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 12546846 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:00 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-a0fa05dd-9b5d-4ae9-ac2e-375c78b993a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=126325163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.126325163 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1488929123 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2060579746 ps |
| CPU time | 11.07 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:26:58 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-940ab768-95fc-42c5-9e5d-82991787ec88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1488929123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1488929123 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.216397549 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 10249127 ps |
| CPU time | 1.3 seconds |
| Started | Feb 07 12:26:44 PM PST 24 |
| Finished | Feb 07 12:26:46 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-15ac7aaa-0b3d-486d-b88f-bff7ff8cd80b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216397549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.216397549 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1277238213 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6223197 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:26:45 PM PST 24 |
| Finished | Feb 07 12:26:47 PM PST 24 |
| Peak memory | 194060 kb |
| Host | smart-7c775d68-3752-4a7f-8b9e-06dc3e68196f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1277238213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1277238213 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1543317660 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 147312381 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:26:54 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-ea3a9303-111c-4e0f-9459-4463cec6a820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543317660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1543317660 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1728433667 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 9232591043 ps |
| CPU time | 111.6 seconds |
| Started | Feb 07 12:26:48 PM PST 24 |
| Finished | Feb 07 12:28:41 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-81107288-fe53-4021-b680-67d2aa65698f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1728433667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1728433667 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2082537601 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 7241225733 ps |
| CPU time | 97.1 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:28:25 PM PST 24 |
| Peak memory | 205500 kb |
| Host | smart-eafea42e-3cfc-4b28-957c-3fe909967544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2082537601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2082537601 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1285962640 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1052749999 ps |
| CPU time | 7.95 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:26:55 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-5219de72-fb3a-4cc9-8ae6-cae10dff3dfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1285962640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1285962640 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.448298190 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 55584720 ps |
| CPU time | 8.38 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:07 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-8d505bd5-842c-4057-964c-071d8c65a814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=448298190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.448298190 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2143307364 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 6799895324 ps |
| CPU time | 21.81 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-a2799ea4-dddd-4be7-878e-766a2bae7dbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2143307364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2143307364 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2300478546 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 795096313 ps |
| CPU time | 11.13 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-6d90d34e-4ed6-4f0b-841c-d30015d8685a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300478546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2300478546 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2135995041 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 20010934 ps |
| CPU time | 1.77 seconds |
| Started | Feb 07 12:26:54 PM PST 24 |
| Finished | Feb 07 12:26:57 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-230d283e-9da8-4df1-a47f-a45fccfe3810 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135995041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2135995041 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.684876165 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 470846973 ps |
| CPU time | 7.01 seconds |
| Started | Feb 07 12:26:47 PM PST 24 |
| Finished | Feb 07 12:26:56 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-2de05c79-6291-4998-a482-cd23baebdaab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=684876165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.684876165 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2544791044 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6499717149 ps |
| CPU time | 9.48 seconds |
| Started | Feb 07 12:26:57 PM PST 24 |
| Finished | Feb 07 12:27:09 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-b9684483-92b5-4aa8-80fa-5b190604d35b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544791044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2544791044 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.308266031 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 18417357527 ps |
| CPU time | 45.06 seconds |
| Started | Feb 07 12:26:55 PM PST 24 |
| Finished | Feb 07 12:27:42 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-a9d87bdf-38f2-4361-a374-ce4ed051c5fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=308266031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.308266031 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2949170280 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 75946306 ps |
| CPU time | 4.3 seconds |
| Started | Feb 07 12:26:50 PM PST 24 |
| Finished | Feb 07 12:26:55 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-653bed20-f6e6-4f41-9760-836cd02ff6e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949170280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2949170280 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.888854096 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 23320963 ps |
| CPU time | 2.97 seconds |
| Started | Feb 07 12:27:00 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-bf81f9f7-9b25-46ea-96d3-1e1e30397406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=888854096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.888854096 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1782014572 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 17075299 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:26:46 PM PST 24 |
| Finished | Feb 07 12:26:49 PM PST 24 |
| Peak memory | 202120 kb |
| Host | smart-bd22b715-f3e1-41ff-85ca-1b3195cc0570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782014572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1782014572 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1346534365 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3416154336 ps |
| CPU time | 6.41 seconds |
| Started | Feb 07 12:26:49 PM PST 24 |
| Finished | Feb 07 12:26:57 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-e89590c9-3249-4fd5-ae27-5fd6232c5afa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346534365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1346534365 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2088131565 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1451138350 ps |
| CPU time | 5.3 seconds |
| Started | Feb 07 12:26:47 PM PST 24 |
| Finished | Feb 07 12:26:54 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-a95a4494-925f-4b28-8225-77a296fe1948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2088131565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2088131565 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3850499181 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8573966 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 12:26:44 PM PST 24 |
| Finished | Feb 07 12:26:47 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-6dc0030a-d3e9-4391-92f2-a7a97b9e4f24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850499181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3850499181 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3381087497 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 392109902 ps |
| CPU time | 17.01 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-0c5325ad-fdfd-4245-8ccf-7f818b700d1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381087497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3381087497 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3510713533 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 503423769 ps |
| CPU time | 4.32 seconds |
| Started | Feb 07 12:27:09 PM PST 24 |
| Finished | Feb 07 12:27:18 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-3646c48e-b592-4a61-8d67-0aef3fad8836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3510713533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3510713533 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1091869131 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 18307697 ps |
| CPU time | 7.73 seconds |
| Started | Feb 07 12:26:59 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-b2b22e25-7c27-4127-b898-db03a5d4b8b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1091869131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1091869131 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3774859538 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1104101798 ps |
| CPU time | 8.35 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-c39183d4-32b2-4033-a0d3-7c8a6eced4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3774859538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3774859538 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.133014504 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 28598454 ps |
| CPU time | 2.79 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:27:41 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-1afad3a3-c65f-4af7-8b9b-2ec10512fb84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=133014504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.133014504 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1857389419 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 84630797042 ps |
| CPU time | 162.47 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:30:17 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-243cf75b-3497-4cdc-a195-2a4e9b321a3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1857389419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1857389419 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.778425883 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 69589608 ps |
| CPU time | 1.76 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-d2b0a075-79bd-4b80-92f8-2d604e724213 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=778425883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.778425883 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2337920765 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 75938854 ps |
| CPU time | 4.26 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-aeb037a8-c201-4f4f-a3d4-436b6e1894b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337920765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2337920765 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.317256305 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5194394700 ps |
| CPU time | 9.48 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:27:41 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-fad6171a-a06f-45f7-95e5-e419c9efd01a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317256305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.317256305 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1322654655 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 32548832425 ps |
| CPU time | 41.65 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-507aab1d-1502-4944-a375-12115598cdc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322654655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1322654655 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2681506239 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 70646675083 ps |
| CPU time | 66.34 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:40 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-ca7b7d9b-f845-4698-82b1-60234ee6c938 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2681506239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2681506239 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.4098727519 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 25857824 ps |
| CPU time | 2.41 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:33 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-88ff7ef7-6ded-4d41-af05-d0edcd91b61f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098727519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.4098727519 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.977703998 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 843194308 ps |
| CPU time | 10.45 seconds |
| Started | Feb 07 12:27:25 PM PST 24 |
| Finished | Feb 07 12:27:41 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-c8e7d675-4956-4855-ad78-f4cb4ef97467 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977703998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.977703998 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2215948918 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 38046556 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:36 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-715eefd4-5591-4d85-af45-229b6e766ab1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2215948918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2215948918 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2191650199 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 8609442836 ps |
| CPU time | 7.18 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:41 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-9fc88bdd-9ea4-432c-b223-bc2c38b610cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191650199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2191650199 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.253542296 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 775954614 ps |
| CPU time | 4.57 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:38 PM PST 24 |
| Peak memory | 201960 kb |
| Host | smart-26895278-1687-4558-ad53-1c0231ee93bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=253542296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.253542296 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3034722255 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 7944067 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-149922e7-5080-4f1b-949b-3e71cb33a82a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034722255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3034722255 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1858288928 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 728876746 ps |
| CPU time | 73.3 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:28:44 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-cc459de1-a953-4de7-8339-a7cae53df0a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1858288928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1858288928 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.531330837 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 6537098223 ps |
| CPU time | 48.05 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-04fc3a3e-f67d-4c74-8fca-3129ba60a646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531330837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.531330837 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.4035077507 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2808782072 ps |
| CPU time | 70.98 seconds |
| Started | Feb 07 12:27:31 PM PST 24 |
| Finished | Feb 07 12:28:47 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-aa7ff8e0-0682-47fc-bbe1-86417e07e298 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4035077507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.4035077507 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2827591948 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 86587535 ps |
| CPU time | 5.35 seconds |
| Started | Feb 07 12:27:31 PM PST 24 |
| Finished | Feb 07 12:27:41 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-a506e153-c012-483a-b92d-bf9c83ad508a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827591948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2827591948 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1342419015 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 71572293 ps |
| CPU time | 6.6 seconds |
| Started | Feb 07 12:27:26 PM PST 24 |
| Finished | Feb 07 12:27:37 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-095a69c2-48c3-4a72-9362-6dd3c08c2f66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1342419015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1342419015 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2549985848 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1056405422 ps |
| CPU time | 22.87 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:57 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-787912ab-103c-4516-8ed8-bdea8cd00410 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549985848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2549985848 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2377308653 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 29845583099 ps |
| CPU time | 132.43 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:29:48 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-4cde7f02-8538-4228-9acc-bf42ac7e13ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2377308653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.2377308653 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2703376719 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 165143987 ps |
| CPU time | 2.11 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-f3a1ccf7-4a3c-4015-9a37-bafde017af8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703376719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2703376719 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3700484645 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 709081235 ps |
| CPU time | 10.73 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-f4f4f654-8a0d-4117-b312-2255cef29ec1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700484645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3700484645 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1432268025 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 603496613 ps |
| CPU time | 7.29 seconds |
| Started | Feb 07 12:27:36 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-f0e81702-2009-47dd-8c56-30722eeb4377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432268025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1432268025 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3663430725 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 48718775190 ps |
| CPU time | 56.13 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-31b4afc8-d427-47c7-815d-0cf3da8ac12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663430725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3663430725 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2686035894 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 31931327089 ps |
| CPU time | 166.83 seconds |
| Started | Feb 07 12:27:35 PM PST 24 |
| Finished | Feb 07 12:30:24 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-bd58b61e-409d-49f1-aaa5-59c80d93cae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2686035894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2686035894 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.149770524 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 81731329 ps |
| CPU time | 5.21 seconds |
| Started | Feb 07 12:27:25 PM PST 24 |
| Finished | Feb 07 12:27:35 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-52554b5d-08fb-43bf-8956-a4b3ff9106a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149770524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.149770524 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.960771673 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 260225693 ps |
| CPU time | 3.76 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-6fd1f330-34c7-472b-ae9f-3de3fee0132a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960771673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.960771673 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2524692256 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 414756898 ps |
| CPU time | 1.71 seconds |
| Started | Feb 07 12:27:31 PM PST 24 |
| Finished | Feb 07 12:27:38 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-c438cec0-0b5f-4e7c-bb7e-eac619491278 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2524692256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2524692256 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4097740698 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2342456286 ps |
| CPU time | 10.68 seconds |
| Started | Feb 07 12:27:31 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-1d7a9368-8f90-434a-9d32-ffb352a8d584 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097740698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4097740698 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.560135927 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2238336614 ps |
| CPU time | 7.89 seconds |
| Started | Feb 07 12:27:30 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-2007db43-6550-4c03-af27-a9a347f9e9d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=560135927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.560135927 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2597747753 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 9016693 ps |
| CPU time | 1.26 seconds |
| Started | Feb 07 12:27:25 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-d22f2fc0-8bbd-48a9-a620-81f256687945 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597747753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2597747753 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2085547771 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 349316837 ps |
| CPU time | 18.85 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:28:02 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-1803b188-028c-4a58-8a84-132498c62292 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2085547771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2085547771 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.320255800 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 750014499 ps |
| CPU time | 63.34 seconds |
| Started | Feb 07 12:27:39 PM PST 24 |
| Finished | Feb 07 12:28:44 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-0fa791ac-9ba0-47c0-b569-db5071769382 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320255800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.320255800 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.52044595 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1064418064 ps |
| CPU time | 102.5 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:29:37 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-56b54c18-2f87-41b8-be01-6b6f41ce5362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52044595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rese t_error.52044595 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2216798488 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 444102984 ps |
| CPU time | 6.24 seconds |
| Started | Feb 07 12:27:26 PM PST 24 |
| Finished | Feb 07 12:27:37 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-fe517b42-f48a-4ce8-a62c-137c454cb657 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2216798488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2216798488 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.380175232 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 309193009 ps |
| CPU time | 4.09 seconds |
| Started | Feb 07 12:27:38 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-d64da314-72b3-49a3-90a9-db7f1fb7fa8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=380175232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.380175232 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3842014622 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 202084841 ps |
| CPU time | 3.54 seconds |
| Started | Feb 07 12:27:47 PM PST 24 |
| Finished | Feb 07 12:27:56 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-b9e37f9d-6407-4881-beb0-07a6156ba935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3842014622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3842014622 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1450746979 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 118684410 ps |
| CPU time | 2.27 seconds |
| Started | Feb 07 12:27:41 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-2504bc2f-33d7-46c1-a715-20630b6fafe0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450746979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1450746979 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2873510198 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2663853901 ps |
| CPU time | 8.3 seconds |
| Started | Feb 07 12:27:40 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-91753c4b-9e8b-4c84-80ad-e78f52e735de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2873510198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2873510198 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.500692045 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 53949547025 ps |
| CPU time | 85.38 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:29:13 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-c531d8f4-c946-4765-a655-d1bb8d882ea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=500692045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.500692045 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3167272199 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 23142854643 ps |
| CPU time | 109.6 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:29:32 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c1f88c3e-7140-4b0e-9000-a203137199ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3167272199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3167272199 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3719758631 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26432202 ps |
| CPU time | 3.59 seconds |
| Started | Feb 07 12:27:35 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-bdfb5857-51c9-432a-81b0-eca5e8e4a845 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719758631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3719758631 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.2086647640 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 46875561 ps |
| CPU time | 3.36 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-190de963-195b-41ec-ad52-e8f44a7bf8e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086647640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2086647640 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.4224041176 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 62800490 ps |
| CPU time | 1.3 seconds |
| Started | Feb 07 12:27:40 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-f9f41e88-adbb-4b3a-9ff2-4c314e9ce8da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224041176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4224041176 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3756729031 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1609071501 ps |
| CPU time | 8.14 seconds |
| Started | Feb 07 12:27:39 PM PST 24 |
| Finished | Feb 07 12:27:48 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-20ba272e-239e-4b56-84e6-74f2c490c8ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756729031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3756729031 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2674235380 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1743184830 ps |
| CPU time | 11.67 seconds |
| Started | Feb 07 12:27:36 PM PST 24 |
| Finished | Feb 07 12:27:49 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-f0c99180-ce6a-4a44-a158-2899281bb9e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2674235380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2674235380 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.507366833 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 40114449 ps |
| CPU time | 1.31 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-f6ff814b-cd41-45b9-98fa-56f47968b413 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507366833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.507366833 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1184543503 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1157201446 ps |
| CPU time | 12.73 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-c79f1495-412a-4c41-9807-7639f4380a11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184543503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1184543503 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3027975449 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 9163372880 ps |
| CPU time | 40 seconds |
| Started | Feb 07 12:27:40 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-3d36605b-13fb-4ce9-96d1-8c6ed0df4313 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3027975449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3027975449 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2673400786 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 32067329 ps |
| CPU time | 3.53 seconds |
| Started | Feb 07 12:27:43 PM PST 24 |
| Finished | Feb 07 12:27:49 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-71dea6c8-9065-4998-b622-c2a3893067f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673400786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2673400786 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2330215913 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 520540537 ps |
| CPU time | 11.4 seconds |
| Started | Feb 07 12:27:40 PM PST 24 |
| Finished | Feb 07 12:27:52 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-e833c155-1046-4ff4-be39-3c468addfda2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2330215913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2330215913 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1401338051 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 188181904431 ps |
| CPU time | 230.1 seconds |
| Started | Feb 07 12:27:38 PM PST 24 |
| Finished | Feb 07 12:31:30 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-530ffa6d-b53e-4c19-a177-5012fca0a863 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1401338051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1401338051 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1044118483 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 747676447 ps |
| CPU time | 11.52 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:57 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-e479e67f-0856-4a4e-adbc-6d6974ce425a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1044118483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1044118483 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.237224552 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1008287143 ps |
| CPU time | 11.02 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:54 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-99b7f830-5b63-418c-ba58-9127fff2d647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237224552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.237224552 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.3326698702 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 434840121 ps |
| CPU time | 4.34 seconds |
| Started | Feb 07 12:27:37 PM PST 24 |
| Finished | Feb 07 12:27:42 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-eebf26bc-a3e4-4748-a431-3be55f901612 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3326698702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3326698702 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.763900303 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 54588785782 ps |
| CPU time | 96.82 seconds |
| Started | Feb 07 12:27:39 PM PST 24 |
| Finished | Feb 07 12:29:17 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-a6ff5e8f-5c07-4401-bff4-9d2aa4d7db18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=763900303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.763900303 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4090040973 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5402640632 ps |
| CPU time | 18.82 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:28:13 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-b556586e-2fb0-4a38-a1a5-efe5b788e861 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4090040973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4090040973 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1787271870 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 486854951 ps |
| CPU time | 7.42 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-222b69ed-4655-4da3-80da-b5cdd811f0d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787271870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1787271870 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.183477509 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1006148931 ps |
| CPU time | 9.35 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:56 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-3c5286eb-6621-464d-8c36-084970abfda5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=183477509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.183477509 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1258807837 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 12736724 ps |
| CPU time | 1.27 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-77a435ec-8d25-497b-a109-056dbd02f4df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258807837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1258807837 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1890483840 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 9563490029 ps |
| CPU time | 7.33 seconds |
| Started | Feb 07 12:27:39 PM PST 24 |
| Finished | Feb 07 12:27:48 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-8cebee3f-d4c5-4f4b-887f-bb1f64b3ed91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890483840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1890483840 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2392491680 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2342602244 ps |
| CPU time | 11.77 seconds |
| Started | Feb 07 12:27:43 PM PST 24 |
| Finished | Feb 07 12:27:55 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-049aa2b8-3323-47fa-aa15-f7849b67b9cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2392491680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2392491680 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2731411834 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 11501699 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:27:35 PM PST 24 |
| Finished | Feb 07 12:27:38 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-dde6eb2f-b5b9-4f70-bde0-911d53c9bf0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731411834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2731411834 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3549778604 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 349453879 ps |
| CPU time | 19.54 seconds |
| Started | Feb 07 12:27:39 PM PST 24 |
| Finished | Feb 07 12:28:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-fa37014e-2023-4893-a867-412b63bf54fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549778604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3549778604 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3333642218 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 97080250 ps |
| CPU time | 12.31 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:59 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-be534317-c9c2-42ca-9f0c-4d0be90e8559 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333642218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3333642218 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1462169317 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2686336549 ps |
| CPU time | 78.97 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:29:06 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-2da0d803-cab2-4ee2-99f8-c1c3240b2158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1462169317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1462169317 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3468916860 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 476740382 ps |
| CPU time | 4.58 seconds |
| Started | Feb 07 12:27:43 PM PST 24 |
| Finished | Feb 07 12:27:49 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-c3b0ceaf-89f7-4916-ad7f-0d10a28c85a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3468916860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3468916860 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.226958949 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1546247377 ps |
| CPU time | 22.97 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:28:10 PM PST 24 |
| Peak memory | 202044 kb |
| Host | smart-6b633f2a-403c-4271-881f-85fe6d4dbf73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=226958949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.226958949 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3303754561 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 21790305081 ps |
| CPU time | 160.77 seconds |
| Started | Feb 07 12:27:49 PM PST 24 |
| Finished | Feb 07 12:30:36 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-3072eef7-facd-4b7d-8c7b-4ff965f8f10b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3303754561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3303754561 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1537573674 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2653037390 ps |
| CPU time | 10.79 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:28:00 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-103c0e26-58c2-48cf-8407-1fbb1ed4dbb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1537573674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1537573674 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.534784851 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 548694527 ps |
| CPU time | 8.53 seconds |
| Started | Feb 07 12:27:47 PM PST 24 |
| Finished | Feb 07 12:27:58 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-7fc89776-cb57-485e-8899-93fb97c69c8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534784851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.534784851 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3645810885 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 729988292 ps |
| CPU time | 15.09 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:28:01 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-2f4df88a-3d2f-4435-bb7d-749340722e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3645810885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3645810885 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2660004044 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 29657367857 ps |
| CPU time | 139.11 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:30:07 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-f8d81f9f-9d6c-44f3-9ca1-215aad0a9b4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660004044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2660004044 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.509657215 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 26969075360 ps |
| CPU time | 116.79 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:29:40 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-d4d1c959-96bc-4606-b7ef-8fe9425f4d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=509657215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.509657215 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3156829032 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 101212314 ps |
| CPU time | 4.48 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:51 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-82d9b144-6951-4eba-a26a-cf2a3b6a4c6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156829032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3156829032 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1572882489 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 212253143 ps |
| CPU time | 3.46 seconds |
| Started | Feb 07 12:27:42 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-0877de0b-61a1-4066-b65c-913baa369ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1572882489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1572882489 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.1439704683 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 18942340 ps |
| CPU time | 1.16 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-5991f319-edcc-4790-b7c6-3ea2b6455db9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1439704683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1439704683 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1698098445 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 20314035345 ps |
| CPU time | 12.2 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:28:01 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-782b5646-0acc-4aba-88e4-de9d91cfaac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698098445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1698098445 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.439100788 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1967396079 ps |
| CPU time | 5.25 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:27:53 PM PST 24 |
| Peak memory | 201992 kb |
| Host | smart-e697f06a-e6ab-4ca8-872d-eaf1b602fc31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=439100788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.439100788 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1637472120 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 10968736 ps |
| CPU time | 1.36 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:27:49 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-e41955b0-f05f-4ee1-b0da-cea0d13083a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637472120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1637472120 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2358342381 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 7002091433 ps |
| CPU time | 99 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:29:41 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-11cb8fe8-07c8-4511-96b1-294b313a8674 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2358342381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2358342381 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2293854144 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 96142241 ps |
| CPU time | 1.4 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:27:56 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-066fc343-57c2-4456-aa19-992019d015bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2293854144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2293854144 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.530489363 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 131763657 ps |
| CPU time | 9.48 seconds |
| Started | Feb 07 12:27:50 PM PST 24 |
| Finished | Feb 07 12:28:07 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-2a412ca3-a60e-40d7-b1be-65922322b4ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=530489363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.530489363 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2628790836 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2201427635 ps |
| CPU time | 50.42 seconds |
| Started | Feb 07 12:27:43 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-b2d962c0-c0e1-4198-bc1f-e5929052810c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2628790836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2628790836 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1669209302 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1207246817 ps |
| CPU time | 9.39 seconds |
| Started | Feb 07 12:27:55 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-3b0222b2-f78d-4e55-8aba-07fca6d7e6a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1669209302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1669209302 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.69712881 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 437895652 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:53 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-ef098e5f-f1d3-4207-b394-60d86cb6f03a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=69712881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.69712881 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3667761567 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 88160316772 ps |
| CPU time | 262.18 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:32:08 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-606f7799-ee5c-4cb1-aa77-36da85852a9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3667761567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.3667761567 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2946146284 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 14376715 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:27:56 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-2f4b36aa-cdc0-492c-b4bd-a79f22bfd21c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2946146284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2946146284 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2867619875 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 971889895 ps |
| CPU time | 9.67 seconds |
| Started | Feb 07 12:27:50 PM PST 24 |
| Finished | Feb 07 12:28:07 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-59124f65-98a2-4063-aa12-88c31519f29a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2867619875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2867619875 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.3937817559 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 380668140 ps |
| CPU time | 6.36 seconds |
| Started | Feb 07 12:27:40 PM PST 24 |
| Finished | Feb 07 12:27:48 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-6ca77440-5439-41a4-b229-52ebd1d9f3a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3937817559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3937817559 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3558892089 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 66571287815 ps |
| CPU time | 92.84 seconds |
| Started | Feb 07 12:27:50 PM PST 24 |
| Finished | Feb 07 12:29:30 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-e18d2405-cf6b-4b1f-9f76-8c148abd5fc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558892089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3558892089 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1360418473 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 29408521484 ps |
| CPU time | 166.51 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:30:41 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-8b400f65-820e-44ea-97e6-1cbc23fbc76f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1360418473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1360418473 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2674917828 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 55582267 ps |
| CPU time | 4.02 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:27:59 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-f23df8d4-5768-46da-be47-3378142164f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674917828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2674917828 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1067131105 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 89598685 ps |
| CPU time | 3.84 seconds |
| Started | Feb 07 12:27:50 PM PST 24 |
| Finished | Feb 07 12:28:01 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-fe935a41-8a6d-45b2-b0ab-77ad9ba9a322 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1067131105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1067131105 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.641236204 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 14482646 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:27:49 PM PST 24 |
| Finished | Feb 07 12:27:57 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-d3232fe3-b3a4-4727-be48-56da2c076de1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=641236204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.641236204 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.4056983617 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 6195697705 ps |
| CPU time | 11.34 seconds |
| Started | Feb 07 12:27:55 PM PST 24 |
| Finished | Feb 07 12:28:13 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-6e6acf77-eac6-4c63-bf7a-002040a6b5cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056983617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.4056983617 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.716563740 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2938635404 ps |
| CPU time | 5.98 seconds |
| Started | Feb 07 12:27:41 PM PST 24 |
| Finished | Feb 07 12:27:48 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-290b1db6-2dc0-406e-9515-cdee0f1eeb5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=716563740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.716563740 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2009788427 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 8108799 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:27:43 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-6ffd7a6b-a87c-4199-bf2c-7a3783e8ea24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009788427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2009788427 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2418576135 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 342146821 ps |
| CPU time | 16.91 seconds |
| Started | Feb 07 12:27:48 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-5cd5540e-d66a-4fa0-a229-316243d1bd16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418576135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2418576135 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3403059999 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13498301637 ps |
| CPU time | 71.07 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:29:00 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-912b4b39-0436-49bc-be4c-2a332b2e3536 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403059999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3403059999 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4018257898 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2635459316 ps |
| CPU time | 106.41 seconds |
| Started | Feb 07 12:27:38 PM PST 24 |
| Finished | Feb 07 12:29:26 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-1e2a4055-a163-4ca1-a723-f8a1c91c90b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018257898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.4018257898 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1038876400 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 218520371 ps |
| CPU time | 13.49 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-3dc646ec-94b7-4224-b0e6-336a9a16386b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1038876400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1038876400 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2546499266 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 88858153 ps |
| CPU time | 7.41 seconds |
| Started | Feb 07 12:27:50 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-ba606cc7-dc55-4fd7-842c-04df092a8a9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546499266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2546499266 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1646077759 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 922495825 ps |
| CPU time | 16.18 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-5e134472-b60f-4bd5-ad77-887b60584a1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646077759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1646077759 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1596977891 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 23783800843 ps |
| CPU time | 84.11 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:29:28 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-b9c011ef-86f8-4c0b-9e21-b064d5d2b40e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1596977891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.1596977891 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1665758109 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 231258138 ps |
| CPU time | 1.72 seconds |
| Started | Feb 07 12:27:57 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-5294276e-afe3-4c8a-8533-e0f35c176e00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1665758109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1665758109 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.1344530412 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 60795528 ps |
| CPU time | 5.16 seconds |
| Started | Feb 07 12:27:52 PM PST 24 |
| Finished | Feb 07 12:28:03 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-18cbaac9-9256-4a31-b4ce-2577a1398f14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1344530412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1344530412 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.2943913364 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1476174114 ps |
| CPU time | 11.72 seconds |
| Started | Feb 07 12:27:55 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-67897ecb-8aed-4d1f-9b16-32d80a48de35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2943913364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2943913364 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1183208786 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 68715993478 ps |
| CPU time | 123.09 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:30:08 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-ef097b30-3980-4a64-8495-be4e3ad3d58e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183208786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1183208786 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1515158184 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8249142848 ps |
| CPU time | 35.12 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:39 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-54a3c195-82a4-4514-8cec-4a42d2a362bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1515158184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1515158184 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4191649932 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 15668540 ps |
| CPU time | 1.67 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-5185baed-429c-45b4-83dd-6821dff3638c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191649932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4191649932 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2185775071 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 29165070 ps |
| CPU time | 1.68 seconds |
| Started | Feb 07 12:28:05 PM PST 24 |
| Finished | Feb 07 12:28:08 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-4ba19fe7-400f-499c-af06-7904cad52e51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185775071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2185775071 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3440796574 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 42755928 ps |
| CPU time | 1.59 seconds |
| Started | Feb 07 12:27:44 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-538e2951-fcc7-4aa6-b325-3ba37525a405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440796574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3440796574 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2337579277 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2101985375 ps |
| CPU time | 6.56 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:09 PM PST 24 |
| Peak memory | 202000 kb |
| Host | smart-6cc9c85f-c9d6-4400-be74-15a99ad53d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337579277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2337579277 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.614458375 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2360172257 ps |
| CPU time | 8.31 seconds |
| Started | Feb 07 12:27:46 PM PST 24 |
| Finished | Feb 07 12:27:58 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-08354db1-862d-4b7c-ad97-58067ff0ca87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=614458375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.614458375 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2503195706 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 13375603 ps |
| CPU time | 1.27 seconds |
| Started | Feb 07 12:27:45 PM PST 24 |
| Finished | Feb 07 12:27:48 PM PST 24 |
| Peak memory | 202036 kb |
| Host | smart-abc4c201-0ebc-44b2-b789-33f310f39b31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503195706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2503195706 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2238382654 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 12107871476 ps |
| CPU time | 28.07 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:33 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-c291ccf9-9b8f-4216-8e92-690420d8210d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2238382654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2238382654 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3813007553 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 7119349054 ps |
| CPU time | 32.09 seconds |
| Started | Feb 07 12:27:53 PM PST 24 |
| Finished | Feb 07 12:28:30 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-aa2c31ad-603a-4574-9f17-002fadd21485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3813007553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3813007553 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3079135002 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3779470913 ps |
| CPU time | 61.05 seconds |
| Started | Feb 07 12:27:57 PM PST 24 |
| Finished | Feb 07 12:29:05 PM PST 24 |
| Peak memory | 204388 kb |
| Host | smart-2de87139-0f3f-4b67-be45-c2582b28f12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3079135002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3079135002 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.978172681 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 387871763 ps |
| CPU time | 64.36 seconds |
| Started | Feb 07 12:27:57 PM PST 24 |
| Finished | Feb 07 12:29:08 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-b90fc1a6-b728-4c6a-b599-98224ff22df6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=978172681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res et_error.978172681 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2417150066 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 51054322 ps |
| CPU time | 1.31 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-a4d5851e-d5b4-40c9-90ec-28e056ed39aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2417150066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2417150066 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.548530253 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1801301108 ps |
| CPU time | 11.52 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-d1d731c6-6a67-4fa6-9102-e4bb5b30dbd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=548530253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.548530253 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3631181167 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 38940580 ps |
| CPU time | 4.07 seconds |
| Started | Feb 07 12:27:54 PM PST 24 |
| Finished | Feb 07 12:28:02 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-aa41fde0-d5c9-4c86-ba66-9128bdda2b4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631181167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3631181167 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.81406770 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1072132591 ps |
| CPU time | 13.25 seconds |
| Started | Feb 07 12:27:54 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-b7b0267b-f747-4489-88be-eb44256199c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81406770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.81406770 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.1515285722 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 739097468 ps |
| CPU time | 14.76 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-24588d5d-e40c-4da6-97c9-d4bf696cf7d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515285722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1515285722 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1353172441 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 50159934458 ps |
| CPU time | 108.64 seconds |
| Started | Feb 07 12:27:53 PM PST 24 |
| Finished | Feb 07 12:29:46 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-b777690b-24e7-4eb5-a3a9-8f42796226f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353172441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1353172441 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.444989126 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 24641667758 ps |
| CPU time | 128.8 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:30:13 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-e9302885-a3a8-413f-aa21-5f4c672d3c07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=444989126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.444989126 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1071099447 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 147154998 ps |
| CPU time | 7.81 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-e1fc6f31-6359-4beb-a7a2-638f6f19f4c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071099447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1071099447 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.473991614 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 951399263 ps |
| CPU time | 12.37 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-2558b1e3-f403-42e5-b58b-e963ba81afaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473991614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.473991614 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.404613698 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 270564136 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-8d380363-9419-4f09-81d6-91ce0daf5cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404613698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.404613698 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1294965435 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2517108321 ps |
| CPU time | 8.98 seconds |
| Started | Feb 07 12:28:01 PM PST 24 |
| Finished | Feb 07 12:28:14 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-c623d421-2c30-45a5-864b-b14bd7fb7b61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294965435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1294965435 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2412633048 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2679632195 ps |
| CPU time | 7.52 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 199168 kb |
| Host | smart-0a8e6a5a-e69e-44d6-a86e-7d4c4254cdc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2412633048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2412633048 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.4104248691 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 17771139 ps |
| CPU time | 1.2 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:04 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-eea76058-5a73-4088-9fb5-c548fdfd518c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104248691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.4104248691 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.981432207 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 232861447 ps |
| CPU time | 13.57 seconds |
| Started | Feb 07 12:27:54 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-cda7222d-9734-4b60-ae7e-1d0c35c4627d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981432207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.981432207 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.288129044 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1193264723 ps |
| CPU time | 31.35 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:36 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-6ec03d76-259c-4776-93ad-f77054a1cf98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=288129044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.288129044 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.444009845 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 150608932 ps |
| CPU time | 15.92 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:18 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-21e3c5d1-863d-43ef-a010-ce36efdfafc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=444009845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.444009845 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1815836007 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 497449907 ps |
| CPU time | 57.66 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-f8c66697-24de-4201-aa86-6260ca1c3f8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815836007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1815836007 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2420097617 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 334664951 ps |
| CPU time | 2.33 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-e3923c0e-4ab1-4d85-883f-842217a94b20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420097617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2420097617 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3472369010 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 905312718 ps |
| CPU time | 21.81 seconds |
| Started | Feb 07 12:27:59 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-5c67967d-251f-4ab1-a0a1-569a2ee31a79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472369010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3472369010 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4024215242 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 130078680866 ps |
| CPU time | 160.29 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:30:51 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-f3ecbbfd-ef9d-47c0-809b-078feb204b78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4024215242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.4024215242 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3730551609 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 600384215 ps |
| CPU time | 11.04 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-7b169cde-8c4f-4a66-be78-61df72a3f0f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730551609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3730551609 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1319670420 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 726875261 ps |
| CPU time | 10.4 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:14 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-298e055c-f632-4bad-b228-23683c3bcbec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1319670420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1319670420 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.652996330 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 77144686 ps |
| CPU time | 7.01 seconds |
| Started | Feb 07 12:28:01 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-11fa6b27-71b6-4a03-a3f1-5a4f47fed0f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652996330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.652996330 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4023760489 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 11131236203 ps |
| CPU time | 33.44 seconds |
| Started | Feb 07 12:28:03 PM PST 24 |
| Finished | Feb 07 12:28:39 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-9f510542-b6ff-43c2-832d-08df77cd72a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023760489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4023760489 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1978256743 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6993891739 ps |
| CPU time | 49.56 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:55 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-f3647396-7ab5-401d-b5a1-52e55fc69567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1978256743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1978256743 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2820679383 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 18093953 ps |
| CPU time | 2.12 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:13 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-e5d2d554-0be4-4ba9-9d04-79b0f6bad26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820679383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2820679383 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.167941902 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 792674313 ps |
| CPU time | 1.91 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:18 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-cce164fa-f0cb-4799-8c32-22c1817a8b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=167941902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.167941902 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.2906532505 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 68191093 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:28:03 PM PST 24 |
| Finished | Feb 07 12:28:07 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-a3ddbb8a-f170-472a-803c-418d5741ef2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2906532505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2906532505 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3717925506 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2241237121 ps |
| CPU time | 7.83 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-4915659c-4439-4506-8d84-b97e5cb3c48d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717925506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3717925506 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.136807508 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1199312594 ps |
| CPU time | 6.74 seconds |
| Started | Feb 07 12:28:04 PM PST 24 |
| Finished | Feb 07 12:28:13 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-ba537a3c-12ef-4dcd-a2f3-ba40007409e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=136807508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.136807508 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2867451551 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10718068 ps |
| CPU time | 1.38 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:14 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-97da3d81-89a1-4e19-9118-c2455beb707d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867451551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2867451551 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3075784118 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3194226470 ps |
| CPU time | 49.03 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 200856 kb |
| Host | smart-d96d4a2d-8610-47eb-9aeb-27be4af8a7df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075784118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3075784118 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3426113739 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 219384659 ps |
| CPU time | 15.42 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 201928 kb |
| Host | smart-bcf37dc5-7664-4562-871f-c95fd9e9e5f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426113739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3426113739 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.608095574 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 98514286 ps |
| CPU time | 9.13 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 199500 kb |
| Host | smart-05e2d9ba-3003-422c-b586-506ee7691b57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=608095574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.608095574 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2137155858 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 397283491 ps |
| CPU time | 28.42 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:39 PM PST 24 |
| Peak memory | 204324 kb |
| Host | smart-fed975c9-1d45-4764-a3d7-b4d376a6f4ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2137155858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2137155858 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3444417098 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 85193600 ps |
| CPU time | 5.66 seconds |
| Started | Feb 07 12:27:56 PM PST 24 |
| Finished | Feb 07 12:28:08 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-48244538-48c8-4ce3-8f4e-7e61b0e67a2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444417098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3444417098 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2989620407 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1370463386 ps |
| CPU time | 19.7 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 201608 kb |
| Host | smart-a834afd2-ce4e-40f4-b0e1-f0fd75f13eab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2989620407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2989620407 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1662249809 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 62148093539 ps |
| CPU time | 301.95 seconds |
| Started | Feb 07 12:28:03 PM PST 24 |
| Finished | Feb 07 12:33:07 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-64bcc0c0-a1bf-4303-a539-711b7226bfef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1662249809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1662249809 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.115621877 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1138923239 ps |
| CPU time | 6.3 seconds |
| Started | Feb 07 12:28:07 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-ef42cb83-230b-4c4f-bd22-2be6148f03c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=115621877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.115621877 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.2135447137 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 639761543 ps |
| CPU time | 11.91 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:17 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-86134123-3fbe-4aff-8ef8-fe9f07f0a053 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135447137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2135447137 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.1755644553 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 176131022 ps |
| CPU time | 1.67 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-752a4691-226c-4106-b4ad-dbf2a09c72ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1755644553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1755644553 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1887000639 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 19217845104 ps |
| CPU time | 39.05 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:55 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-694028ce-548c-4e31-aa7f-c182ee8e7b67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887000639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1887000639 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1217914948 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 19442859040 ps |
| CPU time | 134.62 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:30:26 PM PST 24 |
| Peak memory | 201628 kb |
| Host | smart-e119b3ca-a8bb-49a6-8d69-cf77f0eed45f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1217914948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1217914948 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.164251890 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 43075901 ps |
| CPU time | 4.98 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-7264ad96-5864-4161-a468-999a03f30368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164251890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.164251890 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1809023127 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 110153357 ps |
| CPU time | 3.95 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-c3b81c92-b16e-410c-a570-9de540030a74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1809023127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1809023127 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3578210520 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 86110275 ps |
| CPU time | 1.49 seconds |
| Started | Feb 07 12:27:59 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-17b0e24b-05a6-4b25-8a13-64dc49f1f6fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3578210520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3578210520 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1220567539 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 8684169924 ps |
| CPU time | 9.36 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:25 PM PST 24 |
| Peak memory | 202136 kb |
| Host | smart-c236d3a9-7cd6-40e3-803d-070c75631937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220567539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1220567539 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2401509479 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4508874311 ps |
| CPU time | 8.48 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-1074d789-d58e-4d0d-8a3b-06d5a4f72a96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2401509479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2401509479 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2541683851 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 8655667 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:14 PM PST 24 |
| Peak memory | 199652 kb |
| Host | smart-4067a189-06d8-4e90-927b-9537128e4592 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541683851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2541683851 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.543757347 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3891011494 ps |
| CPU time | 45.42 seconds |
| Started | Feb 07 12:28:08 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-bba8282d-f1c9-4b07-9556-c467e8b6398a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=543757347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.543757347 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.615390368 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3711956720 ps |
| CPU time | 54.53 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:59 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-10d0add7-295a-4c02-a101-2ad3886724ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=615390368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.615390368 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2250891652 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1159797169 ps |
| CPU time | 157.22 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:30:48 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-2879bfb0-209b-4691-9aef-56901317c1fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250891652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2250891652 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.734605555 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1203593818 ps |
| CPU time | 83.74 seconds |
| Started | Feb 07 12:28:11 PM PST 24 |
| Finished | Feb 07 12:29:37 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-d1616b97-3792-4ee0-b31b-3e471667d6ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734605555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.734605555 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1012211964 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 78005504 ps |
| CPU time | 4.14 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-dc7e1898-2c3c-448f-b502-e77cb6e5a705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1012211964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1012211964 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2025069597 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 791266550 ps |
| CPU time | 9.59 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:27:11 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-75bc24f2-0a39-41eb-88d2-8964100ed1e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2025069597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2025069597 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.365822585 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 60965743044 ps |
| CPU time | 253.07 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:31:14 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-02d03132-acb4-4531-83f7-7adf027f9709 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=365822585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow _rsp.365822585 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1146984601 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 496979431 ps |
| CPU time | 7.27 seconds |
| Started | Feb 07 12:27:02 PM PST 24 |
| Finished | Feb 07 12:27:15 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-8d9c6a64-8556-4583-ad65-0d936515cdd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1146984601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1146984601 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.828938320 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 82951721 ps |
| CPU time | 7.65 seconds |
| Started | Feb 07 12:26:59 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-a7178a19-3f22-4bbe-b43a-1e1ac8cee923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828938320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.828938320 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.4139393618 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 990972442 ps |
| CPU time | 14.76 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:14 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-d52eeaad-a66c-45f6-9029-8691d14a02f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4139393618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4139393618 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2731439292 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 33025199473 ps |
| CPU time | 101.7 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:28:43 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-0ca13017-ba81-4ac1-9d00-1b9d1a4163a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731439292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2731439292 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3740968644 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 45931168724 ps |
| CPU time | 64.1 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-800a6220-b71a-4cf8-9e8e-cbebaa425d15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3740968644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3740968644 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3914564131 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 41942430 ps |
| CPU time | 4.79 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:04 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-f508cd87-7e51-4bea-967f-a044e189875a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914564131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3914564131 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.969566576 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 105905113 ps |
| CPU time | 6.02 seconds |
| Started | Feb 07 12:27:00 PM PST 24 |
| Finished | Feb 07 12:27:13 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-71bf6622-b69e-4c13-8a89-860787aa1a0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=969566576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.969566576 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.216284074 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 9657870 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:26:56 PM PST 24 |
| Finished | Feb 07 12:27:00 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-4c17a190-4e7d-4e84-873a-36b52c4659d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=216284074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.216284074 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3163800585 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2101820706 ps |
| CPU time | 7.32 seconds |
| Started | Feb 07 12:26:55 PM PST 24 |
| Finished | Feb 07 12:27:03 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-1b684832-3fb0-4f35-a47d-c7c33c03f16c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163800585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3163800585 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.686187245 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1302356629 ps |
| CPU time | 9.92 seconds |
| Started | Feb 07 12:27:00 PM PST 24 |
| Finished | Feb 07 12:27:17 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-e4936c62-f115-4fd4-b067-066180a3afde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=686187245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.686187245 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1673696943 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 8154021 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:26:59 PM PST 24 |
| Finished | Feb 07 12:27:03 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-13835484-2d06-47a6-bde9-0e8736dbf787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673696943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1673696943 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2551871817 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 478960579 ps |
| CPU time | 44.44 seconds |
| Started | Feb 07 12:27:02 PM PST 24 |
| Finished | Feb 07 12:27:53 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-3cab4b22-e6b5-49d3-ae32-a455c9978376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2551871817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2551871817 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3542726461 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1432939119 ps |
| CPU time | 11.9 seconds |
| Started | Feb 07 12:27:05 PM PST 24 |
| Finished | Feb 07 12:27:21 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-f1a31702-90d5-4ce0-ac7f-4465ba1cfc64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542726461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3542726461 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1733737510 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 211986240 ps |
| CPU time | 49.37 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:28:00 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-48aea5f2-0ece-4ca6-94c4-76d992e53200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1733737510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1733737510 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1014631577 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 170562373 ps |
| CPU time | 2.95 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:27:03 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-347ecd69-f562-4293-a118-b33e749b8bcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1014631577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1014631577 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3214627883 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 6104697727 ps |
| CPU time | 18.05 seconds |
| Started | Feb 07 12:28:00 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-371a5549-8c9f-4e20-a648-cde7033bac2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3214627883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3214627883 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.12452586 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 108770406704 ps |
| CPU time | 302.53 seconds |
| Started | Feb 07 12:28:00 PM PST 24 |
| Finished | Feb 07 12:33:07 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-d7b952ff-ead9-4c39-b94b-48aefe133590 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=12452586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow _rsp.12452586 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1252633876 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 23938568 ps |
| CPU time | 2.3 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-14986e00-6815-4ec6-97dd-7ad7f3cc9e84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252633876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1252633876 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3438516555 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 912398789 ps |
| CPU time | 12 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:17 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-b22d35a9-c131-442f-bee1-26ecf518cfe7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3438516555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3438516555 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3457315649 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 844304568 ps |
| CPU time | 10.67 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-fc19cb6b-e83b-4c59-8919-2b66cd7e2d5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3457315649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3457315649 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1135346458 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2004359362 ps |
| CPU time | 6.58 seconds |
| Started | Feb 07 12:27:54 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-30063e3c-b1a1-491e-a918-bb68475f8d30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135346458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1135346458 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1409496067 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 472088198 ps |
| CPU time | 4.07 seconds |
| Started | Feb 07 12:28:00 PM PST 24 |
| Finished | Feb 07 12:28:08 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-b8a64a51-a3e6-457b-bea7-73cc7d45c246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1409496067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1409496067 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2535889503 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 194218843 ps |
| CPU time | 8.75 seconds |
| Started | Feb 07 12:27:54 PM PST 24 |
| Finished | Feb 07 12:28:07 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-2bce6674-829d-4888-ba22-c5360e9bfe61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535889503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2535889503 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1375264549 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 57775120 ps |
| CPU time | 5.23 seconds |
| Started | Feb 07 12:28:01 PM PST 24 |
| Finished | Feb 07 12:28:10 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-a451eae8-c05c-46de-b4c6-2a623de81df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1375264549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1375264549 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2667580242 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 118034085 ps |
| CPU time | 1.54 seconds |
| Started | Feb 07 12:28:02 PM PST 24 |
| Finished | Feb 07 12:28:07 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-d0249834-6e9a-4b33-bb84-69e193a2c2a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2667580242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2667580242 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1732711579 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1280308830 ps |
| CPU time | 6.15 seconds |
| Started | Feb 07 12:27:57 PM PST 24 |
| Finished | Feb 07 12:28:09 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-6280d2ab-c1c3-4ad3-8adc-c011e08724c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732711579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1732711579 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3429380478 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3009776163 ps |
| CPU time | 6.32 seconds |
| Started | Feb 07 12:28:00 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-19caec59-5783-4e5c-adb0-6d460f880f7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3429380478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3429380478 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2597819731 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 19517579 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:28:00 PM PST 24 |
| Finished | Feb 07 12:28:05 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-2ab85b40-ddab-4feb-b7c0-d6bee6ef775b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597819731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2597819731 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2968548513 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5888800831 ps |
| CPU time | 55.19 seconds |
| Started | Feb 07 12:28:04 PM PST 24 |
| Finished | Feb 07 12:29:02 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-c2f9a651-c3dd-496d-b7ef-4e4e0ac989fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2968548513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2968548513 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2579487912 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5876258795 ps |
| CPU time | 67.07 seconds |
| Started | Feb 07 12:28:04 PM PST 24 |
| Finished | Feb 07 12:29:13 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-3402473c-fc08-415f-b85c-b360fcc2391a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2579487912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2579487912 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2964671005 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 765703513 ps |
| CPU time | 147.01 seconds |
| Started | Feb 07 12:27:58 PM PST 24 |
| Finished | Feb 07 12:30:31 PM PST 24 |
| Peak memory | 208788 kb |
| Host | smart-62696b3b-48d5-4875-8d84-ad46f9f27acf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964671005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2964671005 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1677137435 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 641829901 ps |
| CPU time | 109.58 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:30:02 PM PST 24 |
| Peak memory | 201744 kb |
| Host | smart-66b10264-433a-46ea-a26a-7a3e5a5faac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1677137435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1677137435 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2226763173 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1163816983 ps |
| CPU time | 4.33 seconds |
| Started | Feb 07 12:27:55 PM PST 24 |
| Finished | Feb 07 12:28:03 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-7d54949e-0d67-429e-879e-938e3f261265 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2226763173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2226763173 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1981441848 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 74737198 ps |
| CPU time | 1.99 seconds |
| Started | Feb 07 12:28:05 PM PST 24 |
| Finished | Feb 07 12:28:09 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-6682d594-0104-44dd-9fa4-0d16d215d84d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1981441848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1981441848 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.355381653 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4064543078 ps |
| CPU time | 30.75 seconds |
| Started | Feb 07 12:28:08 PM PST 24 |
| Finished | Feb 07 12:28:40 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-343ca01d-d523-4049-b842-f714a6839acf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=355381653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slo w_rsp.355381653 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1099518435 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 729770775 ps |
| CPU time | 7.75 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-4065e677-e4da-4c0e-87fd-a2f9b0b4b273 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1099518435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1099518435 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1100475971 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2463880948 ps |
| CPU time | 12.23 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-868f6c17-55eb-4ad9-9901-f4c829206eb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1100475971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1100475971 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.170885156 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1140545020 ps |
| CPU time | 12.21 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-756fb7ef-2944-4144-9651-c083f8b1f1ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=170885156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.170885156 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3097767412 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 38660985086 ps |
| CPU time | 81.88 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:29:33 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-a186d6dc-2938-4d7c-b3fb-2ed8cb949daf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097767412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3097767412 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2775980111 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 15618927542 ps |
| CPU time | 19.54 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:36 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-d5e8b179-d48a-45ea-9fcd-be419621486c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2775980111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2775980111 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.798533188 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 80546976 ps |
| CPU time | 4.47 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-9f39b263-ef72-4a87-9f49-2ba1d0cc49a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798533188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.798533188 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.1168698162 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 36633253 ps |
| CPU time | 2 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:09 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-35330209-5941-4618-b885-8c789211e792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168698162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1168698162 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1017603248 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 9056999 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:27:59 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-04fec4d6-9031-444d-a84d-c10548152a36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017603248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1017603248 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.241638845 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1749718967 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 12:27:57 PM PST 24 |
| Finished | Feb 07 12:28:10 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-13fa0820-59ee-4892-9ee2-5fc408450f0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=241638845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.241638845 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3870069579 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2169657953 ps |
| CPU time | 14.36 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-b899430e-105e-4a14-80da-b913a8660da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3870069579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3870069579 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1915612215 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 20216287 ps |
| CPU time | 1.4 seconds |
| Started | Feb 07 12:27:59 PM PST 24 |
| Finished | Feb 07 12:28:06 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-fe88b08e-5de7-405e-92f5-26809c22b9e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915612215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1915612215 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1721180356 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 13050185429 ps |
| CPU time | 48.94 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:29:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-cc83cdc1-7efe-4884-9bef-427700428dc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721180356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1721180356 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2132369686 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 427258527 ps |
| CPU time | 58.24 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:29:14 PM PST 24 |
| Peak memory | 204660 kb |
| Host | smart-d975d895-7075-43ed-8e0d-e3afbe464995 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2132369686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2132369686 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3107890880 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 959952225 ps |
| CPU time | 113.17 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:30:09 PM PST 24 |
| Peak memory | 206772 kb |
| Host | smart-e2e78880-d7f9-40ed-9997-b2edd0885f34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107890880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3107890880 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3701628615 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 339245012 ps |
| CPU time | 3.37 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:14 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-d4bec975-2f1f-4598-88c6-c3fa51408337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3701628615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3701628615 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.478550080 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 300340222 ps |
| CPU time | 7.63 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-7d09897a-b9c6-45b4-9b0d-e33857a3e0be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=478550080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.478550080 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1729981572 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 13728529816 ps |
| CPU time | 38.83 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:46 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-1bbfefdb-f177-4ceb-be57-0343b0d37afa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1729981572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1729981572 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3978500258 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1222150717 ps |
| CPU time | 7.44 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-b70ceec5-582c-4835-8684-5c3d088f0e76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3978500258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3978500258 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2352971236 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 336745659 ps |
| CPU time | 4.84 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-58b548fe-6fbc-4c02-979f-5fd6aa906d87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2352971236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2352971236 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.203438833 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 453582013 ps |
| CPU time | 2.99 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-97813276-3888-4f82-a541-d35da9f4a326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=203438833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.203438833 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.478724818 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 9883137048 ps |
| CPU time | 21.96 seconds |
| Started | Feb 07 12:28:06 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-287ff978-61ef-4fcc-8b90-bdb84304eca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=478724818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.478724818 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1846247102 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 20339839980 ps |
| CPU time | 117.55 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:30:14 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-05c12550-0d71-482d-be3f-56e3f4179942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1846247102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1846247102 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3985898436 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 136504290 ps |
| CPU time | 3.75 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-0940c0f9-afda-4878-b91b-a7b8906c7ae5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985898436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3985898436 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.3752542497 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2265293688 ps |
| CPU time | 12.65 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-06bcc996-de4e-43b8-97f8-44b92fc2dcff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752542497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3752542497 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1872197059 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 133699813 ps |
| CPU time | 1.69 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-3f42d095-4ab0-461b-958a-adddf9974b0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872197059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1872197059 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1669334691 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2210177983 ps |
| CPU time | 10.17 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-de4fa9db-3169-4063-90a6-74378f2c2e0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669334691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1669334691 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2172725547 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2532268258 ps |
| CPU time | 9.01 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-b60c0f53-2d11-48e8-a8a7-eb1fe5fb7219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2172725547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2172725547 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1209378108 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 8388781 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:11 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-06f41ab0-e5ca-4620-83e1-814932bda949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209378108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1209378108 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1602710097 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2996682860 ps |
| CPU time | 42.36 seconds |
| Started | Feb 07 12:28:12 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-14a8f384-45c6-41c4-9954-8405f2944a59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1602710097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1602710097 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1456316358 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 986697930 ps |
| CPU time | 34.8 seconds |
| Started | Feb 07 12:28:11 PM PST 24 |
| Finished | Feb 07 12:28:47 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-a5873152-a29f-4803-a3e3-31038d910948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456316358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1456316358 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2672858916 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 466812147 ps |
| CPU time | 57.01 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:29:08 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-1d0eabaf-578f-443c-99e1-58fc6953de80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2672858916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.2672858916 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.610576960 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 59732088 ps |
| CPU time | 4.81 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-890dfd88-5ddc-4fca-a1d2-af898399ce7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610576960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.610576960 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.375151150 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 198499515 ps |
| CPU time | 1.88 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-56acb8e6-8505-462f-8556-a98856f54702 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=375151150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.375151150 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1693065836 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 54514427 ps |
| CPU time | 10.13 seconds |
| Started | Feb 07 12:28:08 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-58ec6402-0b36-47ba-ae18-87c1d496441d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1693065836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1693065836 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.564716108 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 54006501855 ps |
| CPU time | 245.96 seconds |
| Started | Feb 07 12:28:13 PM PST 24 |
| Finished | Feb 07 12:32:20 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-4ddd954d-919f-4a00-96ca-ddee0fe86d8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=564716108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.564716108 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1446581787 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2247327965 ps |
| CPU time | 10.45 seconds |
| Started | Feb 07 12:28:10 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-e609ee82-263c-43f9-a836-77f622a51741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446581787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1446581787 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3469141253 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 909342014 ps |
| CPU time | 11.53 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-f8be51a3-14ac-4dc4-bf61-d07ce1c8a283 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3469141253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3469141253 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.1010288813 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 496171999 ps |
| CPU time | 7.79 seconds |
| Started | Feb 07 12:28:13 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-f9c2d89d-2442-47b1-a7ea-3cbf9c1f3fba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1010288813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1010288813 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2031693141 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 195970438100 ps |
| CPU time | 168.65 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:31:13 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-15f4f127-695e-4a7e-b24b-e6d04fa774e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031693141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2031693141 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2907342836 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 41353537570 ps |
| CPU time | 186 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:31:16 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-376438e7-357f-4bbe-9281-65d1ccb6a2b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2907342836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2907342836 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1384083171 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 119818215 ps |
| CPU time | 6.03 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-fc77aa7d-be98-466c-a056-a952f9e0aaf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384083171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1384083171 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.609180137 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 372149447 ps |
| CPU time | 2.77 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:13 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-a295964e-062a-4343-b107-a926b9394d66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=609180137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.609180137 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3140833634 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 87092023 ps |
| CPU time | 1.74 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:25 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-742bae6b-1e55-4736-b907-d0341f8744f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3140833634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3140833634 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.246471907 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2314488903 ps |
| CPU time | 9.05 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:33 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-1f4a89b4-60a6-48f6-8af9-93eaf0782bd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=246471907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.246471907 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3512508856 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2194265387 ps |
| CPU time | 11.35 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:28:33 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-0d7fb5b4-6b7b-45e1-9de0-798f5d561c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3512508856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3512508856 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.290839015 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 8731505 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-9c81ef51-2746-45ff-84cc-69be3d041b7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290839015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.290839015 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2807300542 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 426663781 ps |
| CPU time | 20.43 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:45 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-006ec296-867c-446c-b0db-21883dfb37f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2807300542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2807300542 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1092749539 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 304600249 ps |
| CPU time | 35.23 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:59 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-385175b6-4aa2-493c-acfb-cbad3eff1ab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092749539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1092749539 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3135259629 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2455415901 ps |
| CPU time | 103.84 seconds |
| Started | Feb 07 12:28:08 PM PST 24 |
| Finished | Feb 07 12:29:53 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-85b155b7-42a8-4931-9015-dbc97f306ca3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3135259629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3135259629 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3899516169 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 4837368787 ps |
| CPU time | 105.39 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:30:07 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-fcafe3b6-c58f-4a3c-ab85-bbd6dbdfefcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3899516169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.3899516169 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.284288239 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 185158855 ps |
| CPU time | 3.94 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-28dbb6b6-3fec-4cd7-8fb8-99ea9128a40e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=284288239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.284288239 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.4185242274 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 940490855 ps |
| CPU time | 3.4 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202088 kb |
| Host | smart-864abd29-1947-4cc3-aa71-ce865cf5ceba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4185242274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.4185242274 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.753497691 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7966312164 ps |
| CPU time | 42.71 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:29:06 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-126b6a7b-1c34-4ef5-a246-17f2a2713d9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=753497691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.753497691 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3345796567 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 32972226 ps |
| CPU time | 1.68 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-c5a455e2-137a-4a60-9257-a49acf059149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345796567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3345796567 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.1164019992 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 7633975257 ps |
| CPU time | 14.73 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:32 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-b35c0f32-25c9-457c-aa27-cd420dcd6414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1164019992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1164019992 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.2569642351 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 58526791 ps |
| CPU time | 6.39 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-760cddfb-14bb-4c48-a194-e7905a8131f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2569642351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2569642351 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2190347699 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6886769291 ps |
| CPU time | 28.13 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:45 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-34248c99-93a5-44dd-b294-4f34912c6739 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190347699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2190347699 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3146517675 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 10304658759 ps |
| CPU time | 61.84 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:29:25 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-24063f2d-9f98-4b27-ba92-3a9342586877 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3146517675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3146517675 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.4099123366 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 30666731 ps |
| CPU time | 2.95 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-0becd057-ec55-4d7b-8377-a71e680fa112 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099123366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.4099123366 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1995196707 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 56434015 ps |
| CPU time | 1.87 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 201988 kb |
| Host | smart-525efd7e-a877-4a82-8315-8a1fb8ad747a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1995196707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1995196707 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.1119446771 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 90036266 ps |
| CPU time | 1.48 seconds |
| Started | Feb 07 12:28:12 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-33134a43-b63f-4d91-886d-319364ae137c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1119446771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1119446771 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1108050638 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1562941358 ps |
| CPU time | 7.39 seconds |
| Started | Feb 07 12:28:28 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-018204b5-905d-45f3-8f04-dcd326dce037 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108050638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1108050638 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3341190010 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1426582763 ps |
| CPU time | 5.42 seconds |
| Started | Feb 07 12:28:09 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-b46ee991-3dae-4180-a474-d2ff63b6b952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3341190010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3341190010 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.821587850 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 9676720 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:18 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-d160de7f-a8b1-4fab-8dae-1b193a866dbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821587850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.821587850 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2049470943 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 545554514 ps |
| CPU time | 44.96 seconds |
| Started | Feb 07 12:28:18 PM PST 24 |
| Finished | Feb 07 12:29:05 PM PST 24 |
| Peak memory | 204032 kb |
| Host | smart-dcd282a7-70c5-4f58-b69d-986e59de8526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2049470943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2049470943 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2309916911 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5271826683 ps |
| CPU time | 75.07 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:29:35 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-4f1ee3d5-d113-4b83-b06c-2be4e0510b1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2309916911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2309916911 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.856058062 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2894296151 ps |
| CPU time | 53.03 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:29:19 PM PST 24 |
| Peak memory | 200772 kb |
| Host | smart-47178edb-4d1f-4c00-8c4f-011fb975cc25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=856058062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.856058062 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2189310326 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 455580975 ps |
| CPU time | 29.55 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-427931ab-309c-4b8a-aee6-2d05d80d5eb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2189310326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2189310326 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1514503720 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 845099029 ps |
| CPU time | 11.51 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-2c4bc579-f014-4d3f-8e39-4e859fa9ba70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514503720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1514503720 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3103250777 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 722221472 ps |
| CPU time | 14.62 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:39 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-7f7a71ad-5ffb-4d35-babc-c1798d0d81a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103250777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3103250777 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2300920262 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 50567667702 ps |
| CPU time | 283.4 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:33:06 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-d39693f2-7e69-4405-858f-e5cb12a0d671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2300920262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2300920262 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.756411111 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 538883582 ps |
| CPU time | 9.5 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:28:30 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-37f4ea41-a330-49c5-aff7-b3a2c4a7df5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=756411111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.756411111 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.177589580 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 105510239 ps |
| CPU time | 5.74 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-ec3ac650-0d2f-4317-8e94-beebac2d797a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177589580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.177589580 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.1378384553 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 104378902 ps |
| CPU time | 5.31 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-411885e1-2d7b-4145-b0c3-55b81cac07f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378384553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1378384553 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1364856703 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 70834169424 ps |
| CPU time | 136.3 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:30:33 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-063b12d0-9944-45d2-925c-96be56737d28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364856703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1364856703 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4185177241 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 17127553352 ps |
| CPU time | 118.26 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:30:23 PM PST 24 |
| Peak memory | 202156 kb |
| Host | smart-edea94b6-6dd7-4b80-8057-b50526804432 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4185177241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4185177241 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2098736853 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 161928337 ps |
| CPU time | 6.82 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:33 PM PST 24 |
| Peak memory | 198696 kb |
| Host | smart-15c8d50f-24e7-43d6-9c88-7d988db3e307 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098736853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2098736853 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2912282275 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 73550365 ps |
| CPU time | 3.55 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-cb89ea42-9804-4424-a265-43ca746d57c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912282275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2912282275 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.143140374 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 258372123 ps |
| CPU time | 1.69 seconds |
| Started | Feb 07 12:28:36 PM PST 24 |
| Finished | Feb 07 12:28:40 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-51e73d3a-fbc8-442d-aa03-e17ba2600d07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=143140374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.143140374 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3923559690 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2466226411 ps |
| CPU time | 6.5 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:33 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-84dd82f4-431b-4dda-946a-62822a1fbb0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923559690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3923559690 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4018437724 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3981431224 ps |
| CPU time | 6.15 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:32 PM PST 24 |
| Peak memory | 199508 kb |
| Host | smart-04384a60-4b3e-454a-9fa5-58d26d252517 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4018437724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4018437724 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.568898323 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 21842489 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 12:28:13 PM PST 24 |
| Finished | Feb 07 12:28:16 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-38a8d1f4-1a04-45ac-98d0-f552c09e2253 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568898323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.568898323 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1377123777 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 19264562325 ps |
| CPU time | 93.42 seconds |
| Started | Feb 07 12:28:12 PM PST 24 |
| Finished | Feb 07 12:29:47 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-b9ede55f-0de1-466e-b42a-fbe260bf8eaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1377123777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1377123777 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1683410189 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 5461823131 ps |
| CPU time | 54.63 seconds |
| Started | Feb 07 12:28:30 PM PST 24 |
| Finished | Feb 07 12:29:26 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-aae6e5b7-9383-4337-9db4-7cfd22a4900d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683410189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1683410189 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2149948825 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 7569967910 ps |
| CPU time | 154.37 seconds |
| Started | Feb 07 12:28:35 PM PST 24 |
| Finished | Feb 07 12:31:10 PM PST 24 |
| Peak memory | 207364 kb |
| Host | smart-6b45ee92-5e52-4624-a2ab-5ee0a25692b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149948825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.2149948825 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3077039043 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 57485583 ps |
| CPU time | 2.93 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-92ff73a4-fbec-48b7-b422-f1066b60a106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3077039043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3077039043 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.308776319 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1722842996 ps |
| CPU time | 23.72 seconds |
| Started | Feb 07 12:28:12 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-ef9f7d42-4e8d-46d6-8c73-4049191d7954 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308776319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.308776319 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3192042815 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 16503512893 ps |
| CPU time | 99.83 seconds |
| Started | Feb 07 12:28:11 PM PST 24 |
| Finished | Feb 07 12:29:52 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-93be0e52-9b9c-481a-a81d-afaa3aa0f488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192042815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3192042815 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3093371109 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 304296741 ps |
| CPU time | 6.18 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-995561e0-b360-417f-a57f-b2696265f593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093371109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3093371109 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.943307774 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2959773713 ps |
| CPU time | 12.29 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:30 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-5cd424bc-8ca7-48d8-b0ee-2d9612eacdee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=943307774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.943307774 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.610159743 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 4270876690 ps |
| CPU time | 9.97 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-dc901044-7092-4c43-966c-3dd018b781b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610159743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.610159743 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1706080947 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 18252383355 ps |
| CPU time | 56.12 seconds |
| Started | Feb 07 12:28:23 PM PST 24 |
| Finished | Feb 07 12:29:21 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-34e3535d-670d-4fc1-8f08-6a0e5ba3b295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706080947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1706080947 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2793465110 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 10788655287 ps |
| CPU time | 69.37 seconds |
| Started | Feb 07 12:28:23 PM PST 24 |
| Finished | Feb 07 12:29:34 PM PST 24 |
| Peak memory | 202140 kb |
| Host | smart-ebd0c883-b6d3-4461-93e8-de9ead11489a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2793465110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2793465110 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3991720510 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 36485957 ps |
| CPU time | 1.4 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-a73c21b3-bfc1-487f-93b1-ebbf781394ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991720510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3991720510 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3349821522 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 436655765 ps |
| CPU time | 4.49 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-96b635d6-d905-4bf1-88f5-9873a62e801a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3349821522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3349821522 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1424451163 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 83817216 ps |
| CPU time | 1.37 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:28:22 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-3a4fd924-693e-460e-99db-dadcd03cd521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1424451163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1424451163 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2754313925 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2539838417 ps |
| CPU time | 8.03 seconds |
| Started | Feb 07 12:28:14 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-5f0f9c8c-3e71-41a1-961e-cd7f67780096 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754313925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2754313925 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3141683324 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2980442849 ps |
| CPU time | 10.79 seconds |
| Started | Feb 07 12:28:31 PM PST 24 |
| Finished | Feb 07 12:28:43 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-32ff444f-9878-463c-af3b-fca18b73d349 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3141683324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3141683324 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.968772359 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 10980097 ps |
| CPU time | 1.16 seconds |
| Started | Feb 07 12:28:14 PM PST 24 |
| Finished | Feb 07 12:28:17 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-ff019899-880b-49ea-b238-7066cb0b4530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968772359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.968772359 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2886906430 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 107143793 ps |
| CPU time | 9.94 seconds |
| Started | Feb 07 12:28:13 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-f92a6d51-86e2-4579-9666-04c8e1d1bdf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2886906430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2886906430 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3044183126 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 223852682 ps |
| CPU time | 20.08 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-fae895f5-eca5-4490-87f4-f74b7cf687b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3044183126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3044183126 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1626673166 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1609644736 ps |
| CPU time | 176.59 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:31:30 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-61598c7d-d5a9-4277-9ba9-113200ac5401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1626673166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1626673166 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1545732222 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 82063057 ps |
| CPU time | 19.68 seconds |
| Started | Feb 07 12:28:36 PM PST 24 |
| Finished | Feb 07 12:28:57 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-c1bc6dc3-d863-4b0f-8525-2cfe57e3fb3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1545732222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1545732222 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2744942135 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 53027544 ps |
| CPU time | 1.51 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:18 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-dd8280e1-9f0d-4e54-b345-d1f1a9ed6e29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2744942135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2744942135 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.640627001 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 269398829 ps |
| CPU time | 4.81 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-9f835fa6-c438-42c2-be8d-681b0b8ba213 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640627001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.640627001 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3833832263 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 78489088952 ps |
| CPU time | 116.33 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:30:17 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-d62118b8-e581-4556-8cee-78d061e61c1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3833832263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3833832263 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3015862957 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 71970096 ps |
| CPU time | 3.75 seconds |
| Started | Feb 07 12:28:16 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-33781783-703a-42ed-a40b-9a1cb4b96111 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3015862957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3015862957 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.447124452 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 863465057 ps |
| CPU time | 10.75 seconds |
| Started | Feb 07 12:28:18 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-e08ff80f-8ee7-4155-8a41-bd4dcff72056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=447124452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.447124452 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.1879455715 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 53582562 ps |
| CPU time | 1.56 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:18 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-d8b93629-3f88-445b-a2d9-8bc4599ccbe8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1879455715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1879455715 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1242389670 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 34596247101 ps |
| CPU time | 35.73 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:53 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-3888f017-f26b-4070-ad94-42a8c36f0765 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242389670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1242389670 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3777903552 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 22950197201 ps |
| CPU time | 98.8 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:29:59 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-caa495f4-f8b4-4fc3-9797-1ffdd2d8508f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3777903552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3777903552 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2402913926 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 239988900 ps |
| CPU time | 6.39 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-37a52e9f-5bc8-4661-851b-124b277a61c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402913926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2402913926 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3281734537 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 100255878 ps |
| CPU time | 4.02 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:21 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-c59a5d49-d133-4746-8a3e-249c710d81e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281734537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3281734537 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3697104422 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 8900830 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:35 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-599c9f48-99a6-435b-a903-103b1a5fbe81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697104422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3697104422 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.17350704 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 3491392699 ps |
| CPU time | 10.4 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:35 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-d2ee719f-4873-4d48-ac25-b4fd3b1af132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.17350704 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2365240134 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12309243130 ps |
| CPU time | 13.61 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-103863bd-a7b4-4986-8dbb-78608ec7ef3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2365240134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2365240134 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.854481717 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 12404493 ps |
| CPU time | 1.25 seconds |
| Started | Feb 07 12:28:17 PM PST 24 |
| Finished | Feb 07 12:28:19 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-891131c8-93f5-4891-997c-f51be77b9bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854481717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.854481717 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1169260778 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 62820505 ps |
| CPU time | 1.78 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 199584 kb |
| Host | smart-28fc1549-3b40-46ee-b824-1c4595d770c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1169260778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1169260778 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3005954261 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 442466013 ps |
| CPU time | 56.62 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:29:14 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-0a2737f5-19c8-47f0-a7fc-f3ff2242e56a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005954261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3005954261 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.29584371 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 191422173 ps |
| CPU time | 22.8 seconds |
| Started | Feb 07 12:28:36 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-242901b7-5243-4d97-b0fb-96e1be481464 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=29584371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rese t_error.29584371 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.4283581979 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1759813312 ps |
| CPU time | 7.8 seconds |
| Started | Feb 07 12:28:11 PM PST 24 |
| Finished | Feb 07 12:28:20 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-e89168c4-ccff-49ac-bee3-a0631ca95b2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283581979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4283581979 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1077323896 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1529982376 ps |
| CPU time | 9.46 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:28:52 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-1ab67f93-5def-4697-be8c-7cfc5943921c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077323896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1077323896 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3520246610 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 20861363111 ps |
| CPU time | 58.13 seconds |
| Started | Feb 07 12:28:29 PM PST 24 |
| Finished | Feb 07 12:29:29 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-66fadedd-cd68-4a04-9bf7-ebe0854e674c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3520246610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3520246610 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3209498202 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 75199660 ps |
| CPU time | 5.55 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-ed03d2fa-48da-467a-aee2-667d0070afca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3209498202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3209498202 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2420065755 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 204279544 ps |
| CPU time | 5.04 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-18f26cdc-ecba-4aad-a35a-2f6767d9f4ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420065755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2420065755 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.537867055 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 457736805 ps |
| CPU time | 6.48 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-9ba89cd4-308b-448e-ba00-0dd837a61600 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=537867055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.537867055 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1671548751 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 58077493188 ps |
| CPU time | 171.9 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:31:08 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-1070fddc-e828-4e30-be14-3634ab45b737 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671548751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1671548751 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2320927760 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 12007892648 ps |
| CPU time | 60.28 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:29:36 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-6b0d5377-3429-4366-84b7-c204808fdac0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2320927760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2320927760 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3259485998 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 171177184 ps |
| CPU time | 6.89 seconds |
| Started | Feb 07 12:28:18 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-62ae6577-5a1b-41a4-8e02-6744649a19bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259485998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3259485998 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3872288788 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3596463956 ps |
| CPU time | 5.96 seconds |
| Started | Feb 07 12:28:41 PM PST 24 |
| Finished | Feb 07 12:28:49 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-2d0b3dca-e3e9-412e-ac93-d0115fa4d885 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872288788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3872288788 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.1803345250 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 72625315 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 12:28:42 PM PST 24 |
| Finished | Feb 07 12:28:46 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-af0a7071-177b-44c0-bf9b-f1037489a8ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803345250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1803345250 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.742131967 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3524726478 ps |
| CPU time | 10.33 seconds |
| Started | Feb 07 12:28:15 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-e4872d53-4b70-4e0c-9c9e-59a6e8dfe271 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=742131967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.742131967 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2383115408 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4356679346 ps |
| CPU time | 7.82 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-031bdd9e-ffb8-485c-9b4a-adb8fbd2b97b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2383115408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2383115408 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.723171369 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 9459617 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:25 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a9eb1ba4-a60f-4c95-8e98-1d87e80cd17e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723171369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.723171369 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.60914129 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1119689104 ps |
| CPU time | 17.92 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:51 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-980c1526-4de2-4505-90af-1232124a865f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=60914129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.60914129 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1062334459 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 866282473 ps |
| CPU time | 33.45 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-9a96da3c-c0d2-414c-81e6-af00070e608a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1062334459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1062334459 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.474122242 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 249108529 ps |
| CPU time | 47.83 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:29:30 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-6473dd03-e799-4140-beb8-bfe81f0ab3e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=474122242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.474122242 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2018038976 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 935691632 ps |
| CPU time | 69.05 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:29:42 PM PST 24 |
| Peak memory | 203348 kb |
| Host | smart-c35bbc04-c545-4982-8c5b-77561c288623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2018038976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.2018038976 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2410085315 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 20490511 ps |
| CPU time | 2.2 seconds |
| Started | Feb 07 12:28:44 PM PST 24 |
| Finished | Feb 07 12:28:48 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-cde9a0bd-2ed4-459c-ba4b-263c9b445e4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2410085315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2410085315 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1959137056 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 933725780 ps |
| CPU time | 23.72 seconds |
| Started | Feb 07 12:28:35 PM PST 24 |
| Finished | Feb 07 12:29:00 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-683f05e1-286c-445f-ae1c-50ae9cce75f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1959137056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1959137056 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2300594130 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13987857469 ps |
| CPU time | 99.88 seconds |
| Started | Feb 07 12:28:29 PM PST 24 |
| Finished | Feb 07 12:30:10 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-e6e51706-0763-4261-a627-7fc01427e1f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2300594130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2300594130 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3888973857 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 113593259 ps |
| CPU time | 1.83 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-57263dd8-5191-4d11-898d-e2c5ce7261e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888973857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3888973857 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.4287176424 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 367229751 ps |
| CPU time | 5.54 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:41 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-d7e9d420-5394-46e0-a1bd-8ca4235a858a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4287176424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4287176424 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2856743518 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 332136022 ps |
| CPU time | 6.38 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:42 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-576a1d9f-3a3b-4eb2-bf1b-13e429137fde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856743518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2856743518 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.227591253 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 2537320324 ps |
| CPU time | 8.55 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:35 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-9a2959e0-46a4-4bf0-af8e-6bf7ca16e665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=227591253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.227591253 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4244389323 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 53649613466 ps |
| CPU time | 50.29 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:29:33 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-e413f87f-9979-4ced-a09c-9c72da715df7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4244389323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4244389323 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.835695208 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 43018956 ps |
| CPU time | 3.17 seconds |
| Started | Feb 07 12:28:23 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 202060 kb |
| Host | smart-4edc0f35-8630-45b7-a8e9-2a0be59fde66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835695208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.835695208 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.1636518550 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 100950213 ps |
| CPU time | 3.01 seconds |
| Started | Feb 07 12:28:37 PM PST 24 |
| Finished | Feb 07 12:28:42 PM PST 24 |
| Peak memory | 202124 kb |
| Host | smart-bb513a6e-9120-41b6-b908-ec73f1a2e20b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636518550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1636518550 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3116348764 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 8505978 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:25 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-d1f3de55-0a67-479c-b853-8a1752040cbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3116348764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3116348764 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.587755399 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 12848623065 ps |
| CPU time | 8.51 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:44 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-7f48dcc0-90ee-4269-9e48-0deadd1f7f69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=587755399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.587755399 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1498747186 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1277274580 ps |
| CPU time | 8.13 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:41 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-880e0a83-e550-4cbf-b573-e487a373b0da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1498747186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1498747186 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.4030725099 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 12349540 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:28:24 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-db7baca2-ec16-4c6e-9de8-fea6e4ba8a80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030725099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.4030725099 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.224295670 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 22297760507 ps |
| CPU time | 78.23 seconds |
| Started | Feb 07 12:28:37 PM PST 24 |
| Finished | Feb 07 12:29:57 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-c748567a-6c21-4efa-aacb-f11c5192bdce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=224295670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.224295670 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.583719648 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5267482789 ps |
| CPU time | 75.23 seconds |
| Started | Feb 07 12:28:56 PM PST 24 |
| Finished | Feb 07 12:30:13 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-273a7d7d-cb19-4bbf-a6b8-319915579a6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=583719648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.583719648 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2454431343 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 160060769 ps |
| CPU time | 10.94 seconds |
| Started | Feb 07 12:28:44 PM PST 24 |
| Finished | Feb 07 12:28:57 PM PST 24 |
| Peak memory | 203312 kb |
| Host | smart-5aeed09c-926b-4706-90fe-55b198dc4ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2454431343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2454431343 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1847639134 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 21571584 ps |
| CPU time | 7.89 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:28:50 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-1f072906-4d65-4147-850f-6d1cc38c19ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847639134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.1847639134 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.380853550 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 82019036 ps |
| CPU time | 5.26 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:41 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-fa660061-5cb0-433c-86eb-62e386632460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=380853550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.380853550 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.386349621 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3543765241 ps |
| CPU time | 19.72 seconds |
| Started | Feb 07 12:27:01 PM PST 24 |
| Finished | Feb 07 12:27:27 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-6f317771-041f-48d4-91c7-b5cb6c891ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=386349621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.386349621 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.983341751 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 13457834995 ps |
| CPU time | 76.85 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-ccf577b6-0b81-4c06-893c-5cfba3bda986 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=983341751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow _rsp.983341751 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3335756867 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 25045224 ps |
| CPU time | 2.65 seconds |
| Started | Feb 07 12:27:18 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-35a29172-3525-46c2-8eef-45657ef17ec2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335756867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3335756867 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2838861515 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 295002339 ps |
| CPU time | 4.81 seconds |
| Started | Feb 07 12:26:59 PM PST 24 |
| Finished | Feb 07 12:27:07 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-228cd708-aacb-42e3-a48f-f694df1a5de8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2838861515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2838861515 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.2803419430 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 183466125 ps |
| CPU time | 7.08 seconds |
| Started | Feb 07 12:27:05 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 201916 kb |
| Host | smart-f00fc743-c510-4106-bfc6-e28e78b70ac6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2803419430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2803419430 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1848538781 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1225600540 ps |
| CPU time | 5.61 seconds |
| Started | Feb 07 12:26:57 PM PST 24 |
| Finished | Feb 07 12:27:05 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-233e97ea-8131-4721-93db-6cdf2e48c28d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848538781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1848538781 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2586360161 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 8187198176 ps |
| CPU time | 22.05 seconds |
| Started | Feb 07 12:26:58 PM PST 24 |
| Finished | Feb 07 12:27:22 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-54881311-2655-4fd4-8c18-e683a09efd1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2586360161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2586360161 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2254398504 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 84176480 ps |
| CPU time | 4.3 seconds |
| Started | Feb 07 12:27:01 PM PST 24 |
| Finished | Feb 07 12:27:12 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-93287833-ed24-4d2e-8403-f1327c2f0aa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254398504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2254398504 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1428733197 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1064161994 ps |
| CPU time | 7.02 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:27:18 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-51d22686-3467-4be4-ad2f-dcce8987f970 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1428733197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1428733197 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.4092390274 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 11933846 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:27:05 PM PST 24 |
| Finished | Feb 07 12:27:10 PM PST 24 |
| Peak memory | 202012 kb |
| Host | smart-f7f54e52-8b2a-46b3-9957-8c6fabd10d0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4092390274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4092390274 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.693789183 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1874641518 ps |
| CPU time | 8.53 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-e37a3acb-af52-4142-bb26-74411f7301ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=693789183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.693789183 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2379531785 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 766143108 ps |
| CPU time | 5.11 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-22cd2ccf-b83a-425a-bd87-890224797702 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2379531785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2379531785 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2185365587 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 10709436 ps |
| CPU time | 1.27 seconds |
| Started | Feb 07 12:26:59 PM PST 24 |
| Finished | Feb 07 12:27:03 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-898fd6a1-5aee-4834-b711-5e45addd9efa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185365587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2185365587 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.374878240 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 12070335542 ps |
| CPU time | 84.23 seconds |
| Started | Feb 07 12:27:18 PM PST 24 |
| Finished | Feb 07 12:28:45 PM PST 24 |
| Peak memory | 203340 kb |
| Host | smart-b076feb1-f0eb-4c63-a9a9-dad3745ef8f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=374878240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.374878240 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2667862334 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 159639610 ps |
| CPU time | 11.2 seconds |
| Started | Feb 07 12:27:18 PM PST 24 |
| Finished | Feb 07 12:27:31 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-d250bd45-7ec8-44b4-b293-516967163ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2667862334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2667862334 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.702079379 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 585625023 ps |
| CPU time | 50.8 seconds |
| Started | Feb 07 12:27:05 PM PST 24 |
| Finished | Feb 07 12:28:00 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-b4b2c360-3e59-41ad-b241-9530cb2c594c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702079379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.702079379 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3810090930 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 51238275 ps |
| CPU time | 1.72 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-0f4a9b6c-d0de-4350-8fd1-4010ed8467d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810090930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3810090930 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1241498937 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 923204102 ps |
| CPU time | 8.51 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:44 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-ed12ce93-4537-473d-bc4a-96eb604496d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241498937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1241498937 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2850009689 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 208490658 ps |
| CPU time | 6.1 seconds |
| Started | Feb 07 12:28:37 PM PST 24 |
| Finished | Feb 07 12:28:46 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-d1bea2d0-e17c-44c3-9ec1-74075f8986ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850009689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2850009689 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3407576962 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 125480987 ps |
| CPU time | 4.5 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-f81a19da-10ff-4ebd-abf6-ed7ccfadbe86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3407576962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3407576962 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.3909624149 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 46186357 ps |
| CPU time | 1.66 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-4ccf4dc1-1d39-4246-80e3-78e034a604f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3909624149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3909624149 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3932991423 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 115521990962 ps |
| CPU time | 137.32 seconds |
| Started | Feb 07 12:28:49 PM PST 24 |
| Finished | Feb 07 12:31:07 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-093fbf32-5029-452d-a880-360b4dbbc659 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932991423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3932991423 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.938913921 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 21652795354 ps |
| CPU time | 115.98 seconds |
| Started | Feb 07 12:28:57 PM PST 24 |
| Finished | Feb 07 12:30:55 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-f5b221c7-4f36-433f-9fc1-2f22127c76c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=938913921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.938913921 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.392440794 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 196851619 ps |
| CPU time | 7.58 seconds |
| Started | Feb 07 12:28:25 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-34b54c81-ed64-4393-ac4a-ccb66a5e95e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392440794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.392440794 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1097412109 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 107950210 ps |
| CPU time | 3.52 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-58990e2d-818b-445c-9b8a-e14af0a47ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097412109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1097412109 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3623913641 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 9593535 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:28:35 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-086e9d18-7475-4a38-a66b-3ae3c27e7b1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3623913641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3623913641 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1021779659 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2413223562 ps |
| CPU time | 9.82 seconds |
| Started | Feb 07 12:28:39 PM PST 24 |
| Finished | Feb 07 12:28:50 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-fa9500b4-53b6-48f9-b6a5-a903d4cb5d70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021779659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1021779659 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2857839312 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 734467231 ps |
| CPU time | 6.13 seconds |
| Started | Feb 07 12:28:41 PM PST 24 |
| Finished | Feb 07 12:28:49 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-d140c3e8-046a-4663-85ac-6b510c6286af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2857839312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2857839312 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2055678147 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 13701561 ps |
| CPU time | 1.2 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-97124b95-2dab-48bf-b886-ae0edcb354bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055678147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2055678147 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2141303077 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 547338349 ps |
| CPU time | 18.14 seconds |
| Started | Feb 07 12:28:41 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-687ce15d-b230-4882-a7b0-22aeba8a48d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141303077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2141303077 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.679325184 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1871478381 ps |
| CPU time | 23.29 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:58 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-1f8de537-ddd3-421b-9d23-2bb6cc27d524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=679325184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.679325184 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4056935916 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 933426369 ps |
| CPU time | 88.55 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:30:11 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-643ed988-5047-4f66-99a9-b01b310abc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4056935916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.4056935916 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1732049642 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 690906500 ps |
| CPU time | 54.27 seconds |
| Started | Feb 07 12:28:35 PM PST 24 |
| Finished | Feb 07 12:29:31 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-a9d67f98-4a09-46b6-bc98-97fb3b6e09d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732049642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1732049642 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.50646529 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1555047204 ps |
| CPU time | 12.59 seconds |
| Started | Feb 07 12:28:43 PM PST 24 |
| Finished | Feb 07 12:28:58 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-ade27a7b-408c-4426-b771-f98505bac6fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=50646529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.50646529 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.395628555 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1465728649 ps |
| CPU time | 19.77 seconds |
| Started | Feb 07 12:28:33 PM PST 24 |
| Finished | Feb 07 12:28:55 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-2147ce96-3c20-4c3a-b61d-9835870f184f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=395628555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.395628555 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.904379680 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 111379948773 ps |
| CPU time | 335.8 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:34:10 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-6b8d57a0-3970-4333-997a-cc35df5c2d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=904379680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.904379680 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2050332463 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 291159005 ps |
| CPU time | 3.55 seconds |
| Started | Feb 07 12:28:37 PM PST 24 |
| Finished | Feb 07 12:28:42 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-6fde48a9-f308-4fb1-95df-59c05e49faef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050332463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2050332463 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.305166965 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 54391579 ps |
| CPU time | 5.2 seconds |
| Started | Feb 07 12:28:33 PM PST 24 |
| Finished | Feb 07 12:28:40 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-8b8a5ade-2217-468b-bfa3-473f5d56b515 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=305166965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.305166965 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.1583722120 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1077993981 ps |
| CPU time | 11.86 seconds |
| Started | Feb 07 12:28:47 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-e7bf5978-5d65-412b-a804-ec91a52a2814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583722120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1583722120 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3424866584 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1813797212 ps |
| CPU time | 8.4 seconds |
| Started | Feb 07 12:28:19 PM PST 24 |
| Finished | Feb 07 12:28:30 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-8bbcbf45-85ae-4011-bb09-94ac79cd6774 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424866584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3424866584 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1091056627 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 15662155580 ps |
| CPU time | 59.93 seconds |
| Started | Feb 07 12:28:17 PM PST 24 |
| Finished | Feb 07 12:29:18 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-7d112c81-7524-458d-a27b-536ec88f7976 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1091056627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1091056627 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.857371152 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 43776933 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:28:56 PM PST 24 |
| Finished | Feb 07 12:28:59 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-e9887c70-4c91-4197-987f-67c3188f5cd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857371152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.857371152 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.4271694919 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 27250785 ps |
| CPU time | 1.63 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-ceed0623-d212-4432-8309-962793023b9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271694919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4271694919 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.4274761971 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 61080216 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:28:37 PM PST 24 |
| Finished | Feb 07 12:28:40 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-30544897-4a32-471e-9ae4-faa6758999fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4274761971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4274761971 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2093124116 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1565872377 ps |
| CPU time | 6.61 seconds |
| Started | Feb 07 12:28:26 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-998b8f57-1ccc-49f6-bf34-1f62bcebc82f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093124116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2093124116 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1895122622 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1508954767 ps |
| CPU time | 11.84 seconds |
| Started | Feb 07 12:28:23 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-1b3e3de3-2cbd-468f-aa2e-9e27d5d3b782 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1895122622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1895122622 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.661462225 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10768295 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:28:51 PM PST 24 |
| Finished | Feb 07 12:28:53 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-4d3fdeed-af5c-4c3d-ab46-6bf703639c43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661462225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.661462225 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3896114239 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 553795240 ps |
| CPU time | 35.86 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:29:18 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-a16c798f-acf4-4880-9e05-caacd6094b7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3896114239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3896114239 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1443138731 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5886932113 ps |
| CPU time | 49.17 seconds |
| Started | Feb 07 12:28:30 PM PST 24 |
| Finished | Feb 07 12:29:21 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-9f4e37b1-6c27-4721-a38e-ea3a8dedc81b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443138731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1443138731 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.175346830 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 7851937992 ps |
| CPU time | 182.82 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:31:26 PM PST 24 |
| Peak memory | 205212 kb |
| Host | smart-074d84f3-a75e-4b0a-891c-ea8d39fb0436 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175346830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.175346830 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3252308142 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8385307 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-c539bfe1-cb3e-49da-ae5e-7d3dd7b6ac59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252308142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3252308142 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2377286588 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 344222043 ps |
| CPU time | 5.38 seconds |
| Started | Feb 07 12:28:57 PM PST 24 |
| Finished | Feb 07 12:29:04 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-78698c38-4fec-4db0-83e0-092a6ba385ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377286588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2377286588 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1846087103 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 26183207871 ps |
| CPU time | 101.25 seconds |
| Started | Feb 07 12:28:47 PM PST 24 |
| Finished | Feb 07 12:30:30 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-72b3e9e1-d416-4c16-a7c2-ee4b6286e6c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1846087103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1846087103 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3646842848 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1567114676 ps |
| CPU time | 8.34 seconds |
| Started | Feb 07 12:28:55 PM PST 24 |
| Finished | Feb 07 12:29:06 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-4803306a-5d2d-417e-83fa-88f119efdde7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3646842848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3646842848 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.153216671 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 895934255 ps |
| CPU time | 13.45 seconds |
| Started | Feb 07 12:28:51 PM PST 24 |
| Finished | Feb 07 12:29:06 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-868486c4-d5b4-46fb-91cd-b78dc13f8610 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=153216671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.153216671 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.4211929920 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 158678049 ps |
| CPU time | 5.44 seconds |
| Started | Feb 07 12:28:20 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-3245de2e-5c27-44c9-b2e3-b4039f0f5ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4211929920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4211929920 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.663337071 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 59600491976 ps |
| CPU time | 49.65 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:29:13 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-94c6d65c-7dff-4ff1-b487-2e4ef3f5db2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=663337071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.663337071 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.697257908 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 9424687157 ps |
| CPU time | 59.64 seconds |
| Started | Feb 07 12:28:40 PM PST 24 |
| Finished | Feb 07 12:29:42 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-fc899204-eb41-411c-8f4c-833fce0c184a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=697257908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.697257908 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.335103856 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 251163689 ps |
| CPU time | 4.6 seconds |
| Started | Feb 07 12:28:21 PM PST 24 |
| Finished | Feb 07 12:28:28 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-d0db366f-a60b-4f83-8579-a46066d3649d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335103856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.335103856 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1044344062 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 633034208 ps |
| CPU time | 7.12 seconds |
| Started | Feb 07 12:28:53 PM PST 24 |
| Finished | Feb 07 12:29:02 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-6cf01919-3e01-41f2-801b-843ff5e7f201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1044344062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1044344062 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2219501676 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 9926231 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:28:34 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-e48f6061-90c0-417a-94be-a1a2f3bdb333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2219501676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2219501676 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3435717657 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 4165693283 ps |
| CPU time | 8.9 seconds |
| Started | Feb 07 12:28:24 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-ed8de140-346b-4ab5-bb87-b50b38076bb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435717657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3435717657 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3356152550 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 954450989 ps |
| CPU time | 5.49 seconds |
| Started | Feb 07 12:28:32 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-cd9f4824-315d-4339-8daf-06925923b42d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3356152550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3356152550 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3687819697 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 10735142 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:28:22 PM PST 24 |
| Finished | Feb 07 12:28:26 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-fbc69b14-e5be-4538-a23b-94a31c5744dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687819697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3687819697 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1258341829 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 21278971819 ps |
| CPU time | 57.09 seconds |
| Started | Feb 07 12:28:58 PM PST 24 |
| Finished | Feb 07 12:29:57 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-e3ccd8e3-d359-494a-9086-630dd5f16736 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258341829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1258341829 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2939376703 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 748765898 ps |
| CPU time | 23.82 seconds |
| Started | Feb 07 12:28:58 PM PST 24 |
| Finished | Feb 07 12:29:23 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-93a785aa-0eec-4a28-8ccd-5b5e6a9521fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2939376703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2939376703 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2281901129 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 887614254 ps |
| CPU time | 81.5 seconds |
| Started | Feb 07 12:28:52 PM PST 24 |
| Finished | Feb 07 12:30:15 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-fb028ef7-86fd-4d99-9eab-aa137c00f324 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2281901129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2281901129 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3916492494 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 11531008120 ps |
| CPU time | 193.21 seconds |
| Started | Feb 07 12:29:00 PM PST 24 |
| Finished | Feb 07 12:32:17 PM PST 24 |
| Peak memory | 209168 kb |
| Host | smart-7bbb96e7-53d8-4a58-a6dd-9762462c8668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3916492494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3916492494 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3555328123 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2511725197 ps |
| CPU time | 12.87 seconds |
| Started | Feb 07 12:28:56 PM PST 24 |
| Finished | Feb 07 12:29:11 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-90bd2367-d3c9-4019-b878-f16b563e7343 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555328123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3555328123 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.480529243 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1231700264 ps |
| CPU time | 25.83 seconds |
| Started | Feb 07 12:28:53 PM PST 24 |
| Finished | Feb 07 12:29:21 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-03dfa80c-d076-4a24-a927-21410a37c73c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=480529243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.480529243 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4109720793 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 103758107365 ps |
| CPU time | 243.73 seconds |
| Started | Feb 07 12:29:00 PM PST 24 |
| Finished | Feb 07 12:33:07 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-f703bf0a-a6e4-47dd-ae4b-04818b2b1261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4109720793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.4109720793 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3535262189 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 239623133 ps |
| CPU time | 4.36 seconds |
| Started | Feb 07 12:29:01 PM PST 24 |
| Finished | Feb 07 12:29:09 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-df400ec2-996e-4ec0-9783-e8040888fc9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3535262189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3535262189 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2374528136 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 450207738 ps |
| CPU time | 4.06 seconds |
| Started | Feb 07 12:28:50 PM PST 24 |
| Finished | Feb 07 12:28:55 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-83484784-d55b-430f-a170-22b7f193fdde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2374528136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2374528136 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.3969767860 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 77116749 ps |
| CPU time | 4.83 seconds |
| Started | Feb 07 12:28:52 PM PST 24 |
| Finished | Feb 07 12:28:58 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-b461420a-7e49-459a-8b4c-f2cea4500c71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969767860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3969767860 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2627342289 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1683271586 ps |
| CPU time | 6.05 seconds |
| Started | Feb 07 12:28:53 PM PST 24 |
| Finished | Feb 07 12:29:01 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-ece5021b-d0b2-4b26-affc-ad08b9ee64a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627342289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2627342289 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3429087648 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 44504416119 ps |
| CPU time | 110.5 seconds |
| Started | Feb 07 12:28:59 PM PST 24 |
| Finished | Feb 07 12:30:52 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-8dbe67c6-3cc3-4b68-bdff-430b91504346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3429087648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3429087648 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1492787583 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 55322196 ps |
| CPU time | 4.21 seconds |
| Started | Feb 07 12:28:57 PM PST 24 |
| Finished | Feb 07 12:29:03 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-ca46800a-489f-400c-923f-cf1d7984ea42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492787583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1492787583 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.4113582843 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 50479705 ps |
| CPU time | 3.71 seconds |
| Started | Feb 07 12:28:51 PM PST 24 |
| Finished | Feb 07 12:28:56 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-9099aab0-0ddf-4fdb-a5b6-45145048e9cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4113582843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4113582843 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2078378268 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 54800161 ps |
| CPU time | 1.5 seconds |
| Started | Feb 07 12:28:59 PM PST 24 |
| Finished | Feb 07 12:29:03 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-733d1168-f3f4-4eee-a987-9a8fa3cf5f99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2078378268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2078378268 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2058636314 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3377791780 ps |
| CPU time | 12.28 seconds |
| Started | Feb 07 12:29:00 PM PST 24 |
| Finished | Feb 07 12:29:16 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-1ca68373-4c98-4a00-837b-3724bad4468d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058636314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2058636314 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2563578276 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2097463791 ps |
| CPU time | 8.91 seconds |
| Started | Feb 07 12:28:52 PM PST 24 |
| Finished | Feb 07 12:29:03 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-0d1aa804-d893-49c6-81f1-92d827470906 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2563578276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2563578276 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.739505841 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 9959022 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:28:51 PM PST 24 |
| Finished | Feb 07 12:28:53 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-55018a2d-2b84-4c7c-9088-7d25d03d70a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739505841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.739505841 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.66937624 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 12375298144 ps |
| CPU time | 26.84 seconds |
| Started | Feb 07 12:28:58 PM PST 24 |
| Finished | Feb 07 12:29:28 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-6c2b1e60-0b4f-4198-b11c-5c87f1d6c9a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=66937624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.66937624 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3758918523 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2020690371 ps |
| CPU time | 27.96 seconds |
| Started | Feb 07 12:29:01 PM PST 24 |
| Finished | Feb 07 12:29:33 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-21ce8549-baa2-438b-8acc-e16501a31ed3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3758918523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3758918523 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4033638592 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7554965281 ps |
| CPU time | 36.71 seconds |
| Started | Feb 07 12:28:57 PM PST 24 |
| Finished | Feb 07 12:29:36 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-7696d565-7aaf-48bb-9a2e-d04a73bf4304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033638592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.4033638592 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.64848857 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 391272371 ps |
| CPU time | 55.16 seconds |
| Started | Feb 07 12:28:56 PM PST 24 |
| Finished | Feb 07 12:29:53 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-f0b4531f-bfb6-4930-b7fc-6e6bb4824e99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=64848857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rese t_error.64848857 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3120215790 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 10684120 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:28:51 PM PST 24 |
| Finished | Feb 07 12:28:54 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-8c431616-b419-40a4-8691-fb827e2b0fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3120215790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3120215790 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.4183796639 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1600057035 ps |
| CPU time | 23.18 seconds |
| Started | Feb 07 12:32:02 PM PST 24 |
| Finished | Feb 07 12:32:32 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-919fdc84-18bb-4db9-ae7a-9a655f7ce26f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4183796639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4183796639 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1314769501 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 28969150638 ps |
| CPU time | 193.23 seconds |
| Started | Feb 07 12:32:18 PM PST 24 |
| Finished | Feb 07 12:35:38 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-a1180dc4-40ad-4c8f-bf53-5bcbbed07238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1314769501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1314769501 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.993186140 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 147779340 ps |
| CPU time | 2.37 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:47 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-79d992c3-971e-42cb-847e-36335934cb9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993186140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.993186140 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1255703453 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 74258260 ps |
| CPU time | 4.03 seconds |
| Started | Feb 07 12:32:20 PM PST 24 |
| Finished | Feb 07 12:32:31 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-4ce9af09-c9ff-4bed-a93b-24d57fe03989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1255703453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1255703453 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.1807713223 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 418544221 ps |
| CPU time | 9.07 seconds |
| Started | Feb 07 12:32:20 PM PST 24 |
| Finished | Feb 07 12:32:51 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-7093efdd-5e88-4f3b-bdf9-f3f041bb2f74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1807713223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1807713223 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1473059599 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 141834485140 ps |
| CPU time | 179.78 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:35:28 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-5b125ef5-ff40-4087-912d-db8fc9d3b9d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473059599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1473059599 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2530065062 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 7085836143 ps |
| CPU time | 57.56 seconds |
| Started | Feb 07 12:32:15 PM PST 24 |
| Finished | Feb 07 12:33:15 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-3186bd22-3950-4626-825a-c856bb07dd9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2530065062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2530065062 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3705737762 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 163653140 ps |
| CPU time | 6.24 seconds |
| Started | Feb 07 12:32:20 PM PST 24 |
| Finished | Feb 07 12:32:34 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-27d3240d-a7fe-41c7-b2c6-0195aacbbfe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705737762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3705737762 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.1454639556 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 468441454 ps |
| CPU time | 6.58 seconds |
| Started | Feb 07 12:32:20 PM PST 24 |
| Finished | Feb 07 12:32:33 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-a027f0f0-80b1-4946-b90b-feaea5b4d48d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1454639556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1454639556 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1773448037 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 95783831 ps |
| CPU time | 1.44 seconds |
| Started | Feb 07 12:29:01 PM PST 24 |
| Finished | Feb 07 12:29:06 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-52a3e473-56fe-42a7-a7c9-ea08b354d45c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773448037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1773448037 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1844285439 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2900422838 ps |
| CPU time | 11.06 seconds |
| Started | Feb 07 12:32:05 PM PST 24 |
| Finished | Feb 07 12:32:22 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-4d9288ba-2e81-409c-a2e5-c84e7e970d53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844285439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1844285439 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1796630921 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3366177855 ps |
| CPU time | 11.17 seconds |
| Started | Feb 07 12:32:19 PM PST 24 |
| Finished | Feb 07 12:32:37 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-545b30f7-ce51-4246-b4c9-4f986ff21f7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1796630921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1796630921 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3211501119 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 10144325 ps |
| CPU time | 1.24 seconds |
| Started | Feb 07 12:32:08 PM PST 24 |
| Finished | Feb 07 12:32:12 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-c9b9c867-ec27-4312-b579-e932b754fdfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211501119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3211501119 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1478007562 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 549644638 ps |
| CPU time | 30.1 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-139f0dcf-234d-443a-867f-d070263496a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1478007562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1478007562 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2159015164 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5433810323 ps |
| CPU time | 50.94 seconds |
| Started | Feb 07 12:32:16 PM PST 24 |
| Finished | Feb 07 12:33:13 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-2ca3c417-9661-4329-8e0a-d60265667710 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2159015164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2159015164 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1152096056 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 107783716 ps |
| CPU time | 20.2 seconds |
| Started | Feb 07 12:32:19 PM PST 24 |
| Finished | Feb 07 12:32:46 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-0c69af19-b19a-4f06-beb2-a878f7fc1bf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152096056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1152096056 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3710749310 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 500386351 ps |
| CPU time | 32.8 seconds |
| Started | Feb 07 12:31:59 PM PST 24 |
| Finished | Feb 07 12:32:38 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-c1193802-0485-4cf1-bd00-c99dda47230c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3710749310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3710749310 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3567572467 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 11228353 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 12:32:22 PM PST 24 |
| Finished | Feb 07 12:32:31 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-b7d23629-e798-4fab-97cb-ac9d0b0e42a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3567572467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3567572467 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2162285218 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 295050350 ps |
| CPU time | 5.86 seconds |
| Started | Feb 07 12:32:06 PM PST 24 |
| Finished | Feb 07 12:32:17 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-0d3f6bee-3e70-43f8-94c2-cb59c38d44c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162285218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2162285218 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3400421109 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 32662014928 ps |
| CPU time | 178.9 seconds |
| Started | Feb 07 12:32:16 PM PST 24 |
| Finished | Feb 07 12:35:21 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-8afc4c10-d45a-4eb2-9ef8-9f6c94fb41f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3400421109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.3400421109 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2412940864 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 436688017 ps |
| CPU time | 5.03 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:32:39 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-02ca0785-6045-4c7e-840f-68c67b9c3dbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2412940864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2412940864 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1310063225 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 846312650 ps |
| CPU time | 13.99 seconds |
| Started | Feb 07 12:32:07 PM PST 24 |
| Finished | Feb 07 12:32:25 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-6e6c2a98-ecf8-44ec-8850-f5834ad2b705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310063225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1310063225 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3661325859 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 214386433 ps |
| CPU time | 3.62 seconds |
| Started | Feb 07 12:32:13 PM PST 24 |
| Finished | Feb 07 12:32:18 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-14ddce14-5082-420a-9c90-42d6645b666d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661325859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3661325859 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1323358653 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 55596500080 ps |
| CPU time | 140.73 seconds |
| Started | Feb 07 12:32:12 PM PST 24 |
| Finished | Feb 07 12:34:36 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-38b0f339-682f-4e1e-b325-e04ef670d4f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323358653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1323358653 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2801923614 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 16309141327 ps |
| CPU time | 72.66 seconds |
| Started | Feb 07 12:32:12 PM PST 24 |
| Finished | Feb 07 12:33:27 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-3197013a-5790-4e87-ba07-f47865d69d07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2801923614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2801923614 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3520529929 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 52651759 ps |
| CPU time | 4.19 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:32:35 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-eba25027-c0be-46ff-a736-a77e9fba8314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520529929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3520529929 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3912996678 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 51468468 ps |
| CPU time | 3.31 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:32:34 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-0018a947-f93e-48ad-aef4-c008609f2563 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3912996678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3912996678 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.158716491 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 98657300 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 12:32:22 PM PST 24 |
| Finished | Feb 07 12:32:31 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-3799bb02-5d2a-4c95-ab91-3ef3e74cfb1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158716491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.158716491 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1464479917 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1707439464 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 12:32:19 PM PST 24 |
| Finished | Feb 07 12:32:32 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-daf75e86-8777-4f8c-947c-9b00e42537b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464479917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1464479917 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1571781921 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3072643282 ps |
| CPU time | 12.38 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:32:40 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6d593179-7e75-4315-9ad7-63fc3eca51fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1571781921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1571781921 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1042885689 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11840839 ps |
| CPU time | 1.21 seconds |
| Started | Feb 07 12:32:16 PM PST 24 |
| Finished | Feb 07 12:32:24 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-20a99ea1-4c1f-4a8e-b60b-a03f497dca85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042885689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1042885689 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1310288537 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1062478856 ps |
| CPU time | 6.81 seconds |
| Started | Feb 07 12:32:12 PM PST 24 |
| Finished | Feb 07 12:32:21 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-b1631675-bcc5-473b-a23e-1f6a38d7b5cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310288537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1310288537 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4160293999 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 334806220 ps |
| CPU time | 34.87 seconds |
| Started | Feb 07 12:32:29 PM PST 24 |
| Finished | Feb 07 12:33:16 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-41df13d0-808f-4e55-b9a8-ac5d0c5f40b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4160293999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4160293999 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3336140537 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 92726492 ps |
| CPU time | 7.86 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:32:47 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-8b7a4b1f-ae61-415c-969c-f2afdc013b4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3336140537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3336140537 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.122258356 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 64136060 ps |
| CPU time | 7.06 seconds |
| Started | Feb 07 12:32:15 PM PST 24 |
| Finished | Feb 07 12:32:26 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-7a8fa9a2-591e-4c03-b83a-d5bffda847eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=122258356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.122258356 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2291363729 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 193362527 ps |
| CPU time | 11.2 seconds |
| Started | Feb 07 12:32:25 PM PST 24 |
| Finished | Feb 07 12:32:46 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-1b35d18d-579d-4b19-86b0-c54e421f316f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291363729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2291363729 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4267301703 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3625054077 ps |
| CPU time | 6.92 seconds |
| Started | Feb 07 12:32:31 PM PST 24 |
| Finished | Feb 07 12:32:51 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-d9c06180-a592-4dab-87bd-9d021a295d0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4267301703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4267301703 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1096940385 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 91866628 ps |
| CPU time | 2.62 seconds |
| Started | Feb 07 12:32:25 PM PST 24 |
| Finished | Feb 07 12:32:37 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-0a0dda95-b5a6-4181-996e-b4189beedc9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1096940385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1096940385 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3918407589 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 10277463 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:37 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-d84c29dd-43cc-4889-89c9-8cd7df5e5786 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918407589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3918407589 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.811477354 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 15469347102 ps |
| CPU time | 49.47 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:33:29 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-3c96ac51-4aba-468a-ac87-8558e1abf84d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=811477354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.811477354 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.689934106 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 7123445959 ps |
| CPU time | 51.7 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:33:30 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6a9791d4-7ff3-4ebe-967e-d153dffcef3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=689934106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.689934106 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1000162999 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 21615415 ps |
| CPU time | 3.11 seconds |
| Started | Feb 07 12:32:21 PM PST 24 |
| Finished | Feb 07 12:32:31 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-fcaca4b5-35c8-4778-a2d4-becd1009857c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000162999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1000162999 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.1701863791 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 132690046 ps |
| CPU time | 1.76 seconds |
| Started | Feb 07 12:32:30 PM PST 24 |
| Finished | Feb 07 12:32:44 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-9f2c9f2e-eaa7-4efa-8bd0-ab593fea9094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1701863791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1701863791 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1847854742 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 112590392 ps |
| CPU time | 1.44 seconds |
| Started | Feb 07 12:32:17 PM PST 24 |
| Finished | Feb 07 12:32:26 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-db3a3618-65d0-43a9-b1d2-36b2e7bf0f45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847854742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1847854742 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.827992634 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 14727346216 ps |
| CPU time | 14.62 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:33:00 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-f1440a68-4119-4d2f-b2fa-ea2582ac1d90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=827992634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.827992634 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4014976169 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4170657847 ps |
| CPU time | 7.84 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:45 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-a791072f-5019-4340-82ce-036399fc1870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4014976169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4014976169 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3569185052 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 9354129 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:32:32 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-4ad4a2ff-e57d-4fc3-a606-d146de0370a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569185052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3569185052 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2401356145 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 561648687 ps |
| CPU time | 61.25 seconds |
| Started | Feb 07 12:32:35 PM PST 24 |
| Finished | Feb 07 12:33:49 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-e7769389-694d-4745-a004-5566074429bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401356145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2401356145 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.103253797 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4115562349 ps |
| CPU time | 30.09 seconds |
| Started | Feb 07 12:32:42 PM PST 24 |
| Finished | Feb 07 12:33:25 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-8631a7c8-868b-429f-a723-e21dedae5984 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=103253797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.103253797 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1074969030 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1189318028 ps |
| CPU time | 83.49 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:33:54 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-5aa654f0-e419-407e-81af-bd11cff32629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1074969030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1074969030 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2587464893 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1084665866 ps |
| CPU time | 123.27 seconds |
| Started | Feb 07 12:32:24 PM PST 24 |
| Finished | Feb 07 12:34:35 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-3ebacfaf-d454-4cd3-8063-eb971d3aa949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2587464893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2587464893 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2176101388 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 825227485 ps |
| CPU time | 7.52 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:44 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-d5c0c46f-d788-404c-b3c9-1fa2c40de676 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176101388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2176101388 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3626455928 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3367060041 ps |
| CPU time | 12.03 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:32:50 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-8e493cf8-654e-4169-9430-af23e76bee68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3626455928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3626455928 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2637758792 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8430792262 ps |
| CPU time | 64.41 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:33:35 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-bde37eff-4778-4b11-9d9f-2526f5524f0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2637758792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.2637758792 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.240570175 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 9369303 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:32:40 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-bf65e763-06cc-485e-a787-5d53c3a32e2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=240570175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.240570175 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.2625860078 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 472340469 ps |
| CPU time | 3.61 seconds |
| Started | Feb 07 12:32:24 PM PST 24 |
| Finished | Feb 07 12:32:35 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-923823e1-08b5-4718-a65b-158cda792214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2625860078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2625860078 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2602102466 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 20771762 ps |
| CPU time | 2.27 seconds |
| Started | Feb 07 12:32:29 PM PST 24 |
| Finished | Feb 07 12:32:43 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-fd2557e4-eefb-4310-9d7c-7ee43bb4b24e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2602102466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2602102466 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2904512834 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 63250439575 ps |
| CPU time | 140.9 seconds |
| Started | Feb 07 12:32:19 PM PST 24 |
| Finished | Feb 07 12:34:47 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-334bef11-3900-456a-9329-3aa5d0129650 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904512834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2904512834 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1317379100 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 12527369214 ps |
| CPU time | 77.71 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:33:54 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-8aa36afd-6261-4f01-a017-5b92677930ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1317379100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1317379100 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2975075122 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 96715326 ps |
| CPU time | 5.26 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:32:35 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-6e090d4f-d8c6-4540-9d4a-e2494655481b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975075122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2975075122 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2775008971 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 741579684 ps |
| CPU time | 10.12 seconds |
| Started | Feb 07 12:32:30 PM PST 24 |
| Finished | Feb 07 12:32:53 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-9653051a-daa3-4a2d-9e35-3d243576736a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2775008971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2775008971 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3712870947 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 47061902 ps |
| CPU time | 1.37 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:38 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-d25a3c9a-7674-4f5c-83a6-db04c9b6b64b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3712870947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3712870947 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4066369884 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3227578073 ps |
| CPU time | 7.6 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:52 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-ece034db-dba2-4a60-9ee8-350ba0821712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066369884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4066369884 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2804019114 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1538051998 ps |
| CPU time | 10.72 seconds |
| Started | Feb 07 12:32:24 PM PST 24 |
| Finished | Feb 07 12:32:42 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-89a02231-913a-407e-9bee-967034c2e0ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2804019114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2804019114 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2021546562 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 13046138 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:32:46 PM PST 24 |
| Finished | Feb 07 12:33:03 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-83795acd-5762-4389-abe2-c9df0cad3f9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021546562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2021546562 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.965863727 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 979049818 ps |
| CPU time | 15.23 seconds |
| Started | Feb 07 12:32:24 PM PST 24 |
| Finished | Feb 07 12:32:47 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-72b1a04d-602b-45dd-a627-b027b924bbd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=965863727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.965863727 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3244249436 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5470867284 ps |
| CPU time | 64.46 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:33:44 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-4b5b0f53-3e86-47d7-8f93-3b8b91ecc666 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3244249436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3244249436 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2399024958 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 833257820 ps |
| CPU time | 87.99 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:34:13 PM PST 24 |
| Peak memory | 206000 kb |
| Host | smart-5dc3caa3-352f-4f6a-b5f6-afbd2342dd94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399024958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.2399024958 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4211267794 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 904212990 ps |
| CPU time | 8.95 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:32:47 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-915056ec-49e0-46c1-82f8-b6dd21c5204b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4211267794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4211267794 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1233488672 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 865459693 ps |
| CPU time | 16.23 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-2490bda8-2f79-41d3-84ba-e77b69c4cfe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233488672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1233488672 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1552456962 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 35095884854 ps |
| CPU time | 268.48 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:37:08 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-63203962-eb20-4e5f-b61e-227be88fa64c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1552456962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1552456962 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3543908402 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 982868827 ps |
| CPU time | 9.63 seconds |
| Started | Feb 07 12:32:31 PM PST 24 |
| Finished | Feb 07 12:32:54 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-0add875f-a10c-4ce4-9493-8b53d44b8796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3543908402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3543908402 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2502528361 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 254965946 ps |
| CPU time | 3.89 seconds |
| Started | Feb 07 12:32:33 PM PST 24 |
| Finished | Feb 07 12:32:49 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-23bb124c-f968-46fa-af8b-cc9fd71a2289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2502528361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2502528361 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3306480926 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 839087470 ps |
| CPU time | 10.19 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-fbc33726-b7c9-4460-bf33-abf674ac69c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3306480926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3306480926 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1926622859 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 24924888659 ps |
| CPU time | 82.17 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:33:53 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-ce186c81-c94a-4310-91c8-a43255e96946 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926622859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1926622859 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3508066767 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 91809423689 ps |
| CPU time | 91.62 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:34:14 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-fc869ec6-2177-4219-825f-762bb7d731ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3508066767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3508066767 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1908122031 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 136898190 ps |
| CPU time | 8.14 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-4a760bb8-7325-48bf-b66f-9157c25425a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908122031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1908122031 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.3832194234 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1140099260 ps |
| CPU time | 3.03 seconds |
| Started | Feb 07 12:32:28 PM PST 24 |
| Finished | Feb 07 12:32:42 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-5081b9a2-0574-4e4c-a6ae-a61bd7e107c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3832194234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3832194234 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.4105002084 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 14659608 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:32:24 PM PST 24 |
| Finished | Feb 07 12:32:32 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-c3e7eeab-dae0-41f2-8ed3-c626e5b5261d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105002084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4105002084 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3961432646 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1799631130 ps |
| CPU time | 8.06 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:32:46 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-87c0195a-fd66-42f1-938e-ae2160dee554 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961432646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3961432646 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1315924943 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1298703337 ps |
| CPU time | 7.24 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:32:45 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-d1feaa9a-9f5b-41c1-816a-a4c81e012fef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1315924943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1315924943 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1723212602 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 9167612 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:38 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-419b4f54-cfcd-4b13-9b8d-00fc13481b31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723212602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1723212602 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.461060537 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1740194845 ps |
| CPU time | 19.11 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:33:08 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-268e108f-df5f-4890-86d5-7e2696ff2f4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461060537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.461060537 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1792772970 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 89802490 ps |
| CPU time | 4.24 seconds |
| Started | Feb 07 12:32:30 PM PST 24 |
| Finished | Feb 07 12:32:46 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-c8a220e5-1897-4a1b-bdd8-e627d36e3d26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792772970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1792772970 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2155989371 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3065756964 ps |
| CPU time | 101.72 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:34:19 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-b2005520-b89a-499a-b0c7-d6858a2636a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2155989371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2155989371 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2563716072 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 478587504 ps |
| CPU time | 58.02 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:33:35 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-544605c2-3c5b-4d6b-bdd9-c8765c2af530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2563716072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2563716072 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3652015685 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1200387075 ps |
| CPU time | 6.26 seconds |
| Started | Feb 07 12:32:53 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-a74a0e10-afba-45f7-bd8b-049a3f15f470 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652015685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3652015685 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3775269480 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26665218 ps |
| CPU time | 4.48 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:49 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-f1a903e5-04ed-4232-9d4f-5d3d3f5c8d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775269480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3775269480 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3135654042 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 47474286753 ps |
| CPU time | 253.67 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:37:08 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-10889035-f9e9-48ee-a125-f97463d2731e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3135654042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3135654042 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2310728227 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 391010183 ps |
| CPU time | 6.13 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-cdfcba1d-8d2d-4b10-bc34-ed8b858089a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2310728227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2310728227 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.566773159 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 17348893 ps |
| CPU time | 2.41 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 202064 kb |
| Host | smart-54fda9be-bac9-48af-baa9-7280e3e7fc10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=566773159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.566773159 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.2561993314 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 247873308 ps |
| CPU time | 3.54 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:49 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-6dbcbf6e-f8d0-41ba-8d59-63688211d3e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2561993314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2561993314 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1466361668 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 42989567873 ps |
| CPU time | 109.53 seconds |
| Started | Feb 07 12:32:44 PM PST 24 |
| Finished | Feb 07 12:34:47 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-5db37e39-0b67-4f2d-bac0-1c07e5a86940 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466361668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1466361668 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1449780639 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 21089682074 ps |
| CPU time | 40.78 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:33:26 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-8be257e4-1768-47a2-97c8-4c73ab96e542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1449780639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1449780639 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2469519059 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 358458383 ps |
| CPU time | 6.23 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-bb0c3774-3565-41f2-a9b6-296426be2dd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469519059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2469519059 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.3250794924 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 42011286 ps |
| CPU time | 2.18 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:33:02 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-227d2891-9080-4380-a9e0-6c2357abf996 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250794924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3250794924 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2760533706 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 251660693 ps |
| CPU time | 1.45 seconds |
| Started | Feb 07 12:32:35 PM PST 24 |
| Finished | Feb 07 12:32:49 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-7e378a60-ca91-4a14-a64e-3275bb7d73d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760533706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2760533706 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3674095994 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 4576506503 ps |
| CPU time | 7.15 seconds |
| Started | Feb 07 12:32:26 PM PST 24 |
| Finished | Feb 07 12:32:44 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-77018f8e-67c4-47fc-922d-ee420c864b29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674095994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3674095994 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1435525483 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2577313461 ps |
| CPU time | 4.99 seconds |
| Started | Feb 07 12:32:23 PM PST 24 |
| Finished | Feb 07 12:32:36 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-5a8ac432-5b2c-4e52-8798-30d97acc3fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1435525483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1435525483 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1083109225 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 10507968 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:32:48 PM PST 24 |
| Finished | Feb 07 12:33:07 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-93ad190c-2149-4001-9a82-733ac335b426 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083109225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1083109225 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3509287056 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2910025854 ps |
| CPU time | 33.74 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:33:27 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-975bc692-42d2-4bb8-bdfc-d944fe8e96d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3509287056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3509287056 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.497118517 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 960974137 ps |
| CPU time | 133.08 seconds |
| Started | Feb 07 12:32:40 PM PST 24 |
| Finished | Feb 07 12:35:12 PM PST 24 |
| Peak memory | 205800 kb |
| Host | smart-e1e41485-8bf7-4797-bcd1-5c645ab5bcad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=497118517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.497118517 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1933015881 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 351858936 ps |
| CPU time | 32.76 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:48 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-61ba3f16-ee7f-4ea3-85f6-9850d678a0fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1933015881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1933015881 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.4223014442 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 35255426 ps |
| CPU time | 4.01 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:19 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-cfb59459-7f72-4672-acab-84621e4f62df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4223014442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.4223014442 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.4015965930 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 718692019 ps |
| CPU time | 9.01 seconds |
| Started | Feb 07 12:27:14 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-0383adea-701a-4a69-b5fb-72fc3c13d88c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4015965930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4015965930 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1232097832 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 44382934716 ps |
| CPU time | 295.63 seconds |
| Started | Feb 07 12:27:09 PM PST 24 |
| Finished | Feb 07 12:32:10 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-55e0ceb8-365d-4b6a-9239-71a0c99da481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1232097832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1232097832 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3939534373 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 47838727 ps |
| CPU time | 5.58 seconds |
| Started | Feb 07 12:27:14 PM PST 24 |
| Finished | Feb 07 12:27:21 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-2c5cf44a-9b9d-46a0-a7ca-8ea26f35b849 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3939534373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3939534373 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3285588782 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 33001689 ps |
| CPU time | 3.05 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-b2c113b5-eeb5-4407-92fe-cdff4ae9fcea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3285588782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3285588782 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3720590708 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 226356259 ps |
| CPU time | 4.19 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 201676 kb |
| Host | smart-b75870f8-ec11-469e-8de8-caa7b14766a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3720590708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3720590708 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1126613458 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 16910980102 ps |
| CPU time | 24.53 seconds |
| Started | Feb 07 12:27:03 PM PST 24 |
| Finished | Feb 07 12:27:34 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-2ca143fc-0334-41e4-89cc-39e73eadd59e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126613458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1126613458 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.272859137 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5147621224 ps |
| CPU time | 35.5 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-8318ef5d-3141-4cec-a7df-89385b6c7a1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=272859137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.272859137 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2695126216 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 201296480 ps |
| CPU time | 6.78 seconds |
| Started | Feb 07 12:27:07 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-042ee8cb-17cf-4ec7-8915-64dc1c4d6eaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695126216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2695126216 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.2175917739 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 23398210 ps |
| CPU time | 2.3 seconds |
| Started | Feb 07 12:27:14 PM PST 24 |
| Finished | Feb 07 12:27:18 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-b6962ae5-eaf9-4bf3-9e10-97b1a4bfe7ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2175917739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2175917739 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.4167353066 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 10223051 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:22 PM PST 24 |
| Peak memory | 201684 kb |
| Host | smart-dc4078ab-1811-4c80-8a8b-c56202a0d7f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4167353066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4167353066 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3456794687 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3227205116 ps |
| CPU time | 6.89 seconds |
| Started | Feb 07 12:27:07 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-c538108c-02b8-4d47-bf49-a731a3ca9034 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456794687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3456794687 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1802331834 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 946872050 ps |
| CPU time | 7.49 seconds |
| Started | Feb 07 12:27:01 PM PST 24 |
| Finished | Feb 07 12:27:15 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-2afd367c-22fe-4710-aed1-383505c8cd78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1802331834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1802331834 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2545020927 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 32613705 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:22 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-5d7dee9b-41c5-4e02-b01c-30787536786a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545020927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2545020927 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2129736402 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2602155409 ps |
| CPU time | 10.54 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-734eff66-50e9-4265-a0a6-912015b2e0fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2129736402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2129736402 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.4191344751 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 244509771 ps |
| CPU time | 14.58 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-2f81d258-28db-4f83-bb2f-be4012c789d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4191344751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4191344751 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1033084873 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3605958666 ps |
| CPU time | 40.29 seconds |
| Started | Feb 07 12:27:23 PM PST 24 |
| Finished | Feb 07 12:28:10 PM PST 24 |
| Peak memory | 204436 kb |
| Host | smart-85c9a8e7-9ff8-487c-8bc6-d78e25a09a1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1033084873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1033084873 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2997164724 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 793862915 ps |
| CPU time | 75.54 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:28:37 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-940f6f84-23a3-46a8-a9ed-738145a657a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2997164724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.2997164724 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.317413653 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 208525025 ps |
| CPU time | 6.67 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-1fc488cf-53c4-4c35-b1b0-aa46b8a95661 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317413653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.317413653 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3054420736 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1080298344 ps |
| CPU time | 12.97 seconds |
| Started | Feb 07 12:32:53 PM PST 24 |
| Finished | Feb 07 12:33:23 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-8840768b-0ace-4b5e-ae6c-7ced89d594bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3054420736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3054420736 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.995776454 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 49505846484 ps |
| CPU time | 321.72 seconds |
| Started | Feb 07 12:32:42 PM PST 24 |
| Finished | Feb 07 12:38:16 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-3a97e865-195a-4106-8399-47639b583338 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=995776454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.995776454 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.181319538 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 78129635 ps |
| CPU time | 2.06 seconds |
| Started | Feb 07 12:32:36 PM PST 24 |
| Finished | Feb 07 12:32:50 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-177c54f1-a15e-4e63-9572-90e76c775362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=181319538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.181319538 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.1220061183 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 892634187 ps |
| CPU time | 6.3 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:33:30 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-484d04df-6fa6-42d8-8b2a-c17e8c80046a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220061183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1220061183 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.1860064390 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 449719867 ps |
| CPU time | 5.6 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:32:55 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-5a99f195-ccfd-4035-86cc-530bb3300461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1860064390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1860064390 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2483047377 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 187159088077 ps |
| CPU time | 150.94 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:35:45 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-4341a990-fc1d-499e-895e-c1c215073dbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483047377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2483047377 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1709963761 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3096286247 ps |
| CPU time | 22.39 seconds |
| Started | Feb 07 12:32:51 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-a0ca521d-7541-4f86-a7e0-ff7467467348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1709963761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1709963761 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1727792215 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 18287107 ps |
| CPU time | 1.52 seconds |
| Started | Feb 07 12:32:27 PM PST 24 |
| Finished | Feb 07 12:32:40 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-c4e6f20b-f354-463a-a03c-ac1728b61c15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727792215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1727792215 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.1027581256 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 38161289 ps |
| CPU time | 4.2 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 201936 kb |
| Host | smart-f8b30558-a169-45c8-811f-480182d4b760 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1027581256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1027581256 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1496530690 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 85864082 ps |
| CPU time | 1.82 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-0adfa85d-8a16-46b0-b145-b905fec37ebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496530690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1496530690 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3178390702 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3832533943 ps |
| CPU time | 11.95 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:33:12 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-f6133cdb-984b-418d-a893-3918d62d35e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178390702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3178390702 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3061309947 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1516281402 ps |
| CPU time | 9.5 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:24 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-206d7f1e-580e-48a5-996d-0279a9a8245c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3061309947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3061309947 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.681359939 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11536574 ps |
| CPU time | 1.2 seconds |
| Started | Feb 07 12:33:10 PM PST 24 |
| Finished | Feb 07 12:33:25 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-0f962567-56eb-4a2c-848a-b2a2904ee1bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681359939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.681359939 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.4062490132 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 24354371841 ps |
| CPU time | 129.19 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:35:12 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-ec052e43-a872-41cb-a40f-32985e22ef7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4062490132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4062490132 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4293379493 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3785523802 ps |
| CPU time | 54.68 seconds |
| Started | Feb 07 12:32:43 PM PST 24 |
| Finished | Feb 07 12:33:50 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-e8d7d65b-26e3-4285-bb97-abba8c8c3f0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293379493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4293379493 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2401914191 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 419877311 ps |
| CPU time | 73.72 seconds |
| Started | Feb 07 12:32:39 PM PST 24 |
| Finished | Feb 07 12:34:06 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-1400fe10-4c53-4877-8d53-ef46c8c3017f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401914191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2401914191 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.919118787 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2572379450 ps |
| CPU time | 55.41 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:34:05 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-36cceeff-4fc4-433f-9861-2736c04b70b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919118787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.919118787 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1382732195 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 537675677 ps |
| CPU time | 11.58 seconds |
| Started | Feb 07 12:32:43 PM PST 24 |
| Finished | Feb 07 12:33:09 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-fbf4aefd-fcc1-45d2-8e2a-6b746217b0ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382732195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1382732195 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1825283328 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1469150639 ps |
| CPU time | 18.85 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:33:04 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-ad8ca9dc-7469-4ea5-8bcb-d0115220988d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825283328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1825283328 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3239062139 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 23485156790 ps |
| CPU time | 133.01 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:35:07 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-01e8788b-c647-4a7e-a06b-ed6b3222563a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3239062139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3239062139 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1346531868 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 26832712 ps |
| CPU time | 2.43 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:10 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-a5f11583-6d60-446c-ae59-5a92b2e6c4b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1346531868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1346531868 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1699641953 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 804188804 ps |
| CPU time | 13.92 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:33:08 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-debce87c-c2cb-46e8-8eb6-0d5bc121c73c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699641953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1699641953 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.962591663 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 773453455 ps |
| CPU time | 8.5 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:54 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-db4c52e9-f6ed-471e-9bba-4db9fb7d49ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=962591663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.962591663 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1903007471 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 19373338305 ps |
| CPU time | 73.04 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:34:29 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-774bcd0e-9cdb-40d2-9815-9d86b082481b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903007471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1903007471 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.4174368147 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 15570040573 ps |
| CPU time | 13.88 seconds |
| Started | Feb 07 12:32:39 PM PST 24 |
| Finished | Feb 07 12:33:06 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-9b596f5e-65ce-44f6-b9ba-66fed8175b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4174368147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4174368147 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.41948094 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 44741186 ps |
| CPU time | 6.58 seconds |
| Started | Feb 07 12:32:37 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-2aab8234-e3c7-432b-a343-67bd48197041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.41948094 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1492608917 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1195780307 ps |
| CPU time | 10.36 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:19 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-806b1212-0d6d-40ae-966d-f1df4b2f1505 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492608917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1492608917 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3697610322 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 89957638 ps |
| CPU time | 1.59 seconds |
| Started | Feb 07 12:32:36 PM PST 24 |
| Finished | Feb 07 12:32:50 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-b3b6738c-6055-462d-b63b-cdd948bb283e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697610322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3697610322 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1117026316 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 12811816415 ps |
| CPU time | 12.95 seconds |
| Started | Feb 07 12:32:35 PM PST 24 |
| Finished | Feb 07 12:33:00 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-4645ec83-fe3d-4360-8ce2-d0c7bd040b12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117026316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1117026316 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2998854979 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1012624605 ps |
| CPU time | 8.22 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:33:07 PM PST 24 |
| Peak memory | 202072 kb |
| Host | smart-830622b9-c1a4-46af-9a20-0e18c0ea8ef0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2998854979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2998854979 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3273552700 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 10512542 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:08 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-41f9723e-5733-4259-a9b1-c3373d65b208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273552700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3273552700 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.276997860 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 21083995894 ps |
| CPU time | 86.67 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:34:42 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-5d55fb46-ed3d-4ea6-9a3f-ea883fb47049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276997860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.276997860 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.122252920 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 9031922360 ps |
| CPU time | 112.29 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:34:51 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-9b0f9cb1-01da-4eec-bb29-d23f257ad0f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=122252920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.122252920 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1895459077 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 5089743373 ps |
| CPU time | 105.93 seconds |
| Started | Feb 07 12:33:06 PM PST 24 |
| Finished | Feb 07 12:35:06 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-c7a1b82d-ae67-4f3e-baaf-c460d327c386 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895459077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1895459077 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1307058871 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 208085204 ps |
| CPU time | 7.8 seconds |
| Started | Feb 07 12:32:33 PM PST 24 |
| Finished | Feb 07 12:32:54 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-3fdfc2fb-d90c-4602-8f57-82fda30ed1d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307058871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1307058871 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3981919086 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 25523001 ps |
| CPU time | 4.68 seconds |
| Started | Feb 07 12:33:11 PM PST 24 |
| Finished | Feb 07 12:33:29 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-950f8d39-182a-4c7a-90dc-125ff5555f8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981919086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3981919086 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3119803006 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 288618055 ps |
| CPU time | 2.6 seconds |
| Started | Feb 07 12:33:04 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-35271216-837b-43c3-a18f-3edb38a436ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119803006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3119803006 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.1590954309 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 641459960 ps |
| CPU time | 7.08 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:16 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-97392d6f-12e9-439b-8d02-d3c8cd8ab5fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590954309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1590954309 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.925283008 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 191172026 ps |
| CPU time | 1.98 seconds |
| Started | Feb 07 12:32:43 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-5e7c5d02-5ce1-4da8-b362-489b44a0e744 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=925283008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.925283008 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3756352596 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 11913534722 ps |
| CPU time | 21.64 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:30 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-13ec126e-509a-46e8-9970-8bafcd91cb31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756352596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3756352596 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1259168047 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 7850941178 ps |
| CPU time | 55.83 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:34:09 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-b1311e4d-5642-4a60-9d16-5a12ca319d2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1259168047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1259168047 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2674750586 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 62888439 ps |
| CPU time | 4.79 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-bddf680c-f17a-4316-a597-c7f6b2ce53f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674750586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2674750586 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.1453463122 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 230096521 ps |
| CPU time | 3.42 seconds |
| Started | Feb 07 12:33:05 PM PST 24 |
| Finished | Feb 07 12:33:23 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-6580a088-aa67-423b-902d-33057c268ec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1453463122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1453463122 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2240968680 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 128522106 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:15 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-7703126c-da29-44df-a6e4-ca24c9da8b80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2240968680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2240968680 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3877072050 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2025372066 ps |
| CPU time | 10.25 seconds |
| Started | Feb 07 12:32:33 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-d484bec1-4e68-441f-ab1f-874e936ab570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877072050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3877072050 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3291280826 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1098664222 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 12:32:38 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-300b3585-7485-44d1-95f9-7531be486a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3291280826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3291280826 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3056532105 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 41383977 ps |
| CPU time | 1.23 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-83bb3fce-2990-420c-9784-badb213a78aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056532105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3056532105 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2581552676 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 47430146759 ps |
| CPU time | 111.4 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:35:06 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-5b8af239-4a47-4eee-8a1c-76ba2ac57212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581552676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2581552676 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3957820655 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 874437188 ps |
| CPU time | 15.66 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:34 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-cf0cd378-f060-4904-9abc-763542ce0fc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957820655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3957820655 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3535077153 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 527350874 ps |
| CPU time | 72.59 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:34:28 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-9e959a0a-cf56-481d-a744-36731b436b88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3535077153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3535077153 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2244189200 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 14744584865 ps |
| CPU time | 180.56 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:36:15 PM PST 24 |
| Peak memory | 207276 kb |
| Host | smart-3d8c591a-7ea5-4298-95cf-c7a448ca0d9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2244189200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.2244189200 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.4144130851 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 54818055 ps |
| CPU time | 6.68 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-4260ce8f-658d-4b49-a1fb-a1ba9b0b6963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4144130851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.4144130851 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1046166138 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 74126406 ps |
| CPU time | 10.54 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:33:34 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-9c1e9838-1ba1-4ad6-a175-43449b8ad337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046166138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1046166138 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3333430990 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 90577922718 ps |
| CPU time | 345.76 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:39:02 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-62974f8f-ebfc-4b1c-afa1-4a5ffaa7e526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3333430990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3333430990 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2201884132 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 15610495 ps |
| CPU time | 1.44 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:33:01 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-ab58927e-7cb1-4d26-adb6-7554a480cab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2201884132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2201884132 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.1064237392 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 187459555 ps |
| CPU time | 3.31 seconds |
| Started | Feb 07 12:32:50 PM PST 24 |
| Finished | Feb 07 12:33:12 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-00504379-b0d4-44c4-9ac7-a20cc14506fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064237392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1064237392 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.75743927 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2478354900 ps |
| CPU time | 7.34 seconds |
| Started | Feb 07 12:33:06 PM PST 24 |
| Finished | Feb 07 12:33:28 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-1673fda2-0f6b-4856-af01-157fee8f84c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75743927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.75743927 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2456073894 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 108375108815 ps |
| CPU time | 118.93 seconds |
| Started | Feb 07 12:32:54 PM PST 24 |
| Finished | Feb 07 12:35:11 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-8d2fe28e-8a87-4bbc-a795-ad5c1f0ac4b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456073894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2456073894 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.562225780 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 24122430681 ps |
| CPU time | 59.55 seconds |
| Started | Feb 07 12:33:10 PM PST 24 |
| Finished | Feb 07 12:34:24 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-9d55840f-9dc8-4945-911e-62e789200178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=562225780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.562225780 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2598393806 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 242535140 ps |
| CPU time | 7.13 seconds |
| Started | Feb 07 12:32:51 PM PST 24 |
| Finished | Feb 07 12:33:15 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-9222e488-20e9-44f3-90ae-82ca25f3ae93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598393806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2598393806 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.4080510832 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 27816351 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-b502923b-78ab-4c3f-a9bb-7fa41e1711ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4080510832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4080510832 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1127319390 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 8639609 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-f2b8cf84-65a0-4514-b0e1-a4f4613043f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1127319390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1127319390 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4176517201 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5239052271 ps |
| CPU time | 10.55 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-1c4ccd82-115c-45d9-9f7f-96441cdab733 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176517201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4176517201 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1467233226 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 760396070 ps |
| CPU time | 4.9 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-4a8b2c5e-61dc-42fb-ac78-92fd84aea5b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1467233226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1467233226 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4126066481 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 7874999 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:19 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-f06fa5d7-12ef-4293-b458-cc2b6db30700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126066481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4126066481 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3558618864 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 15808770494 ps |
| CPU time | 41.64 seconds |
| Started | Feb 07 12:33:02 PM PST 24 |
| Finished | Feb 07 12:33:58 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-6d6cc9ed-9e89-496c-8970-8d508bb2ce2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3558618864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3558618864 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1548745015 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5604059341 ps |
| CPU time | 67.95 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:34:22 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-99efb712-0c71-4413-ab04-94df347c85b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1548745015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1548745015 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3692334213 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 349942562 ps |
| CPU time | 25.3 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:33:11 PM PST 24 |
| Peak memory | 204388 kb |
| Host | smart-7eb39961-d49a-4a22-b63e-3ee64430b07b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3692334213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3692334213 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2635398763 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 642482304 ps |
| CPU time | 22.64 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:38 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-92f3397b-13fe-4efa-9636-49e81ceeac34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2635398763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2635398763 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2591554993 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 404855445 ps |
| CPU time | 5.52 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:19 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-99643e5c-0157-461f-8b64-bf0a7636e5f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2591554993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2591554993 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3021707694 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 56988218 ps |
| CPU time | 11.24 seconds |
| Started | Feb 07 12:32:54 PM PST 24 |
| Finished | Feb 07 12:33:24 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-8fad7684-20fe-4619-83ce-461565017fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021707694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3021707694 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3590163570 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 35222668561 ps |
| CPU time | 195.71 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:36:31 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-73fffad3-4b48-4d7b-9e3b-f2fc4f1db43e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3590163570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3590163570 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1403085484 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 42991321 ps |
| CPU time | 2.12 seconds |
| Started | Feb 07 12:32:51 PM PST 24 |
| Finished | Feb 07 12:33:10 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-7e28b245-9ede-45c6-816c-1f7c08c10eb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403085484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1403085484 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2825884756 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 38485935 ps |
| CPU time | 2.38 seconds |
| Started | Feb 07 12:32:38 PM PST 24 |
| Finished | Feb 07 12:32:53 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-f6c35e32-e671-41d6-b280-491497d89c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2825884756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2825884756 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.3597523474 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1031664790 ps |
| CPU time | 2.97 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:18 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-5ddd60da-62f2-443a-a0d3-05ecd215ef8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597523474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3597523474 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1295619835 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 9702979338 ps |
| CPU time | 49.15 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:56 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-eb7c479c-5980-4eab-bb8c-ac2efe790757 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295619835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1295619835 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.468272202 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 20387005202 ps |
| CPU time | 107.03 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:34:54 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-80c9480f-0bd4-416c-a7de-a91c8a876c75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=468272202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.468272202 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2037101710 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 95542173 ps |
| CPU time | 8.35 seconds |
| Started | Feb 07 12:32:35 PM PST 24 |
| Finished | Feb 07 12:32:56 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-70c234ee-6f85-4355-9100-4d6e8cd86cd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037101710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2037101710 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3126351907 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4018063405 ps |
| CPU time | 13.47 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-d3cfbb2d-8b1d-4e69-bb22-9d087e42d425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126351907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3126351907 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.2957842359 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 19025558 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 12:33:02 PM PST 24 |
| Finished | Feb 07 12:33:18 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-82f9ee64-338f-45d2-8591-e54094639ea4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957842359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2957842359 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.931601199 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9213133421 ps |
| CPU time | 9.72 seconds |
| Started | Feb 07 12:32:36 PM PST 24 |
| Finished | Feb 07 12:32:58 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-feee4538-2cf7-43e0-9706-f4458b1d6111 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=931601199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.931601199 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2684796594 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1344031905 ps |
| CPU time | 7.34 seconds |
| Started | Feb 07 12:32:33 PM PST 24 |
| Finished | Feb 07 12:32:54 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-674240ef-0f4d-4a19-b5af-55d9955e6416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2684796594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2684796594 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2479068608 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 9709063 ps |
| CPU time | 1.2 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:16 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-8ef28c81-7a5d-4872-9e91-715ac811a927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479068608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2479068608 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3886186471 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 119951016 ps |
| CPU time | 8.9 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 203552 kb |
| Host | smart-d49998a1-ab4f-462a-8bb4-20fd3813f404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3886186471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3886186471 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3783134821 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2606395844 ps |
| CPU time | 50.59 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:33:51 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-217cac73-55bb-4824-b734-b8b9f87897a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3783134821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3783134821 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.407251743 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 361032034 ps |
| CPU time | 45.88 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:34:02 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-088fbf9e-8233-4b6f-bf6d-88be32887cd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407251743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.407251743 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2894269749 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 149898541 ps |
| CPU time | 17.31 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:33 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-38865f11-d63a-4cd2-92ac-c5ba619d1bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894269749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2894269749 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2539632585 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 40845684 ps |
| CPU time | 4.81 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:20 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-f9f15fd7-05e5-413e-9ba6-5eb797bb8842 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539632585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2539632585 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2390476219 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1791068475 ps |
| CPU time | 11.66 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:27 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-b8a18dfa-ec16-43dc-a3a8-f42167693433 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390476219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2390476219 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1238376829 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 69033749 ps |
| CPU time | 2.87 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-f4984e8b-c33a-47b4-ba28-a08ece37c8f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238376829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1238376829 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.3869611206 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 56810330 ps |
| CPU time | 2.07 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:20 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-971182c3-214e-4da3-ac0c-f1bf788d8c7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3869611206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3869611206 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3176889763 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 89594299 ps |
| CPU time | 1.39 seconds |
| Started | Feb 07 12:32:42 PM PST 24 |
| Finished | Feb 07 12:32:55 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-86d3ddbd-f697-4cc8-8339-0ab75284f61b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3176889763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3176889763 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3351504749 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 34936238586 ps |
| CPU time | 129.94 seconds |
| Started | Feb 07 12:32:45 PM PST 24 |
| Finished | Feb 07 12:35:11 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-4d5a980e-c2b9-4f09-9f62-be4f4d894647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351504749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3351504749 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2480072962 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 15948984395 ps |
| CPU time | 21.16 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:36 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-0c154a4a-930d-4344-94f3-164cfda19210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2480072962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2480072962 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1633668607 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 68009065 ps |
| CPU time | 8.51 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-15a5b99a-b577-4156-a2f3-3daf3b6f86e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633668607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1633668607 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2731557178 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 22197205 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 12:32:53 PM PST 24 |
| Finished | Feb 07 12:33:12 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-4e69d34a-c201-4a9f-8a11-ac4f9aa59e6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2731557178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2731557178 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.1909354647 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 51434861 ps |
| CPU time | 1.34 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:10 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-89c15a64-50c0-4f1d-b03c-34bea8e53458 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909354647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1909354647 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4261848114 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2933408116 ps |
| CPU time | 9.04 seconds |
| Started | Feb 07 12:32:48 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-7b8203e3-af6d-4dbb-8dc3-19defd3441f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261848114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4261848114 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1515059792 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3753185816 ps |
| CPU time | 6.72 seconds |
| Started | Feb 07 12:32:43 PM PST 24 |
| Finished | Feb 07 12:33:04 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-9694f523-733b-4bfa-8a3a-30764454c96e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1515059792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1515059792 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1127220750 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9175354 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:33:08 PM PST 24 |
| Finished | Feb 07 12:33:24 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-45a0b653-f69f-408a-90a9-ee66413ddacd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127220750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1127220750 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2787129122 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1401463527 ps |
| CPU time | 13.03 seconds |
| Started | Feb 07 12:33:04 PM PST 24 |
| Finished | Feb 07 12:33:32 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-26f00709-14d7-41bf-88e7-516fe82470e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2787129122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2787129122 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2650358304 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 874617939 ps |
| CPU time | 9.48 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:33:23 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-37a3413b-f4f1-4af7-84fd-abcdd9d4f54e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2650358304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2650358304 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2210666884 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 544221288 ps |
| CPU time | 52.8 seconds |
| Started | Feb 07 12:33:11 PM PST 24 |
| Finished | Feb 07 12:34:18 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-b7d014c6-92cb-45f9-a026-f514a7b15512 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2210666884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2210666884 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3259012608 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 370562316 ps |
| CPU time | 52.03 seconds |
| Started | Feb 07 12:33:02 PM PST 24 |
| Finished | Feb 07 12:34:10 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-d1d852b3-db98-4042-98dc-855a8eff6b81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3259012608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3259012608 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.679798226 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 605402529 ps |
| CPU time | 11.93 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:33:33 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-f395f899-b527-41ec-b66e-528b2eec56ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=679798226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.679798226 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2616902425 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 37512184 ps |
| CPU time | 3.05 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:33:25 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-7d681340-1160-4130-8cee-d512720a791c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2616902425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2616902425 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.898532458 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 57372458947 ps |
| CPU time | 299.63 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:38:23 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-06f57d3d-2d16-4b36-bed5-4329cd1f2c13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=898532458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.898532458 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2061712113 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 313856820 ps |
| CPU time | 4.52 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-9b612364-85bf-42c4-a817-396373b118c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2061712113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2061712113 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.2303139096 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1872721561 ps |
| CPU time | 4.06 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:33:18 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-9b38e45b-1f74-4e37-ae76-6fcc7aae0623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2303139096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2303139096 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.1257509796 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 520921139 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 12:32:42 PM PST 24 |
| Finished | Feb 07 12:33:01 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-5cfd6e1b-f996-4a9c-aa63-a61a37ac61b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1257509796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1257509796 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1190974012 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 39853878087 ps |
| CPU time | 64.09 seconds |
| Started | Feb 07 12:33:15 PM PST 24 |
| Finished | Feb 07 12:34:31 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-facf3490-6b6e-4d16-abe8-1dfa46343a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190974012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1190974012 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1323379508 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6996379094 ps |
| CPU time | 36.27 seconds |
| Started | Feb 07 12:32:43 PM PST 24 |
| Finished | Feb 07 12:33:32 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-f2883b31-b268-4cdb-a8f3-2ab4bbcf7551 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1323379508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1323379508 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.416627878 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 56225163 ps |
| CPU time | 4.05 seconds |
| Started | Feb 07 12:33:16 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-0e0cbada-349b-4080-bfe1-bf9b6dc7d386 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416627878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.416627878 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.3591345899 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 760526241 ps |
| CPU time | 4.48 seconds |
| Started | Feb 07 12:32:53 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-d8f4f153-955f-4a71-97b4-2070bd870e89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3591345899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3591345899 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.698782485 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 114747811 ps |
| CPU time | 1.6 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:20 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-d01f4d03-6a9f-4d57-a9b4-8636ab30866b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698782485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.698782485 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2934380905 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3452325469 ps |
| CPU time | 6.05 seconds |
| Started | Feb 07 12:33:05 PM PST 24 |
| Finished | Feb 07 12:33:26 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-d7dc81d7-afc6-48b5-b99e-b9417e5c92a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934380905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2934380905 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1675152144 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 15414008427 ps |
| CPU time | 12.51 seconds |
| Started | Feb 07 12:33:08 PM PST 24 |
| Finished | Feb 07 12:33:36 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-28d0909b-cc0c-4292-adb5-dab3074b6de1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1675152144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1675152144 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1173401167 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 10608038 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:32:48 PM PST 24 |
| Finished | Feb 07 12:33:13 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-0c253024-f26f-45b6-97f5-a5034092cfa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173401167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1173401167 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1210014577 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3626900197 ps |
| CPU time | 40.99 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:56 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-c2521158-850f-4e71-b18a-968eda959e03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1210014577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1210014577 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.4001860636 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1217483745 ps |
| CPU time | 14.18 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:33:38 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-5c284aeb-a0cb-42e9-8362-ebd8733521d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4001860636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.4001860636 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.269144731 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 277333864 ps |
| CPU time | 15.89 seconds |
| Started | Feb 07 12:32:47 PM PST 24 |
| Finished | Feb 07 12:33:20 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-7181d8fd-9360-4244-a5a3-b13855dc3c1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269144731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.269144731 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2599796065 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 591362874 ps |
| CPU time | 54.39 seconds |
| Started | Feb 07 12:32:34 PM PST 24 |
| Finished | Feb 07 12:33:41 PM PST 24 |
| Peak memory | 203980 kb |
| Host | smart-5ee42101-8c73-4955-9787-04bac9b17d31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2599796065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2599796065 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1482614979 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 604856538 ps |
| CPU time | 7.54 seconds |
| Started | Feb 07 12:32:40 PM PST 24 |
| Finished | Feb 07 12:33:00 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-1c6c5e6d-5e9d-4fbb-9174-5eceef9ddf04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1482614979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1482614979 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.4122457409 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 454903237 ps |
| CPU time | 7.87 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-754ffe2f-0822-4c59-adb4-bdb1f9ac0fd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4122457409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4122457409 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3725929249 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 26784804828 ps |
| CPU time | 85.63 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:34:39 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-9ae27358-e2c6-4fe6-a181-8c9b8c9d6f6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3725929249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3725929249 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3047544370 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1865771944 ps |
| CPU time | 7.06 seconds |
| Started | Feb 07 12:32:48 PM PST 24 |
| Finished | Feb 07 12:33:13 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-4be3a2f4-671c-4a67-aa6a-f05a73cf1e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047544370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3047544370 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.4179544091 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 718432929 ps |
| CPU time | 6.99 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-784288e9-6efa-4aff-9e27-dcdda3f47f49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4179544091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.4179544091 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.88213948 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 11846436 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:32:55 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-92c9ce92-867f-4622-b016-37c9d0613ff6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=88213948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.88213948 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3573128556 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 283263555627 ps |
| CPU time | 155.66 seconds |
| Started | Feb 07 12:32:44 PM PST 24 |
| Finished | Feb 07 12:35:33 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-414dde90-de0e-402b-9722-7a37b055edce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573128556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3573128556 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1662753482 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 19998667152 ps |
| CPU time | 141.13 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:35:45 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-98af6e3b-8ff2-4035-998b-69ff63f7f1e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1662753482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1662753482 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.798366981 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 80412616 ps |
| CPU time | 8.28 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-09b2f9e3-a5f8-456f-a4cc-4a395456cddc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798366981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.798366981 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.784232670 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 24278312 ps |
| CPU time | 2.01 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:20 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-6ad86f1d-a85b-4d44-9246-2f9afd0c0c91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784232670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.784232670 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.81096163 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 78064008 ps |
| CPU time | 1.54 seconds |
| Started | Feb 07 12:32:52 PM PST 24 |
| Finished | Feb 07 12:33:11 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-7aa89575-8d9e-43f9-ad56-91af7d701808 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81096163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.81096163 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.405844452 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 15329079047 ps |
| CPU time | 10.42 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-73d79cc2-baab-4d2c-84f5-153aa136a599 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=405844452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.405844452 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2922965635 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1058016819 ps |
| CPU time | 5.44 seconds |
| Started | Feb 07 12:33:08 PM PST 24 |
| Finished | Feb 07 12:33:28 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-688c7e6c-eb3d-4c7f-bc51-16454dc6a5f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2922965635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2922965635 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.12024720 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 18293821 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:32:54 PM PST 24 |
| Finished | Feb 07 12:33:13 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-236c413c-3d35-4c4f-8a86-f3cbaab44d24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.12024720 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.675495408 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 231726765 ps |
| CPU time | 31.91 seconds |
| Started | Feb 07 12:32:32 PM PST 24 |
| Finished | Feb 07 12:33:17 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-adbb45ef-50c9-4c23-98e4-276624f18537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=675495408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.675495408 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3561007194 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 145317405 ps |
| CPU time | 8.8 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-5a4aa2da-67c5-46be-ade0-939e8ea647fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3561007194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3561007194 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2102435494 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 11996176961 ps |
| CPU time | 148.22 seconds |
| Started | Feb 07 12:32:47 PM PST 24 |
| Finished | Feb 07 12:35:32 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-479f4e8a-45fa-46c8-a020-9656278604f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2102435494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2102435494 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.6955643 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 18754983 ps |
| CPU time | 2.05 seconds |
| Started | Feb 07 12:32:49 PM PST 24 |
| Finished | Feb 07 12:33:09 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-10477589-35ed-4d7f-9542-1cddacb7778f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=6955643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.6955643 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3133607170 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 43156577 ps |
| CPU time | 8.38 seconds |
| Started | Feb 07 12:32:42 PM PST 24 |
| Finished | Feb 07 12:33:03 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-128f1127-6f18-40ae-baf8-b87c568a6a5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133607170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3133607170 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4116438780 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8976987545 ps |
| CPU time | 15.66 seconds |
| Started | Feb 07 12:32:47 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6d95c735-564b-40c7-9f15-c62edc84924d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4116438780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.4116438780 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3878971912 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 19398377 ps |
| CPU time | 1.61 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:15 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-4b2ad402-e914-4e8e-8e3f-7b47ef4371c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878971912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3878971912 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.985852151 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 138057880 ps |
| CPU time | 5.63 seconds |
| Started | Feb 07 12:33:10 PM PST 24 |
| Finished | Feb 07 12:33:30 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-1d8f32de-7649-408b-a1b5-b7a8abe81629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=985852151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.985852151 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.487707729 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1012305087 ps |
| CPU time | 14.53 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-fb0889a0-a26d-462e-ac16-2fe1ccc88901 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=487707729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.487707729 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1532768470 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3548845328 ps |
| CPU time | 10.66 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:26 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-cb1e1fcc-1633-48ac-81c9-cd8975a9984e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532768470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1532768470 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.788824284 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2380550278 ps |
| CPU time | 9.04 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:33:25 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-8132af10-343c-4002-8daf-b7d0f4a2dc78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=788824284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.788824284 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.4208852212 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 24955585 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-f2f3fa9a-2733-44ee-a168-aadada267270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208852212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4208852212 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3685438260 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 174542126 ps |
| CPU time | 3.37 seconds |
| Started | Feb 07 12:33:02 PM PST 24 |
| Finished | Feb 07 12:33:21 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-021587e6-6724-4619-9e7a-35edd8d7b401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3685438260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3685438260 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.2422465931 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 11778605 ps |
| CPU time | 1.26 seconds |
| Started | Feb 07 12:32:56 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-eca6478a-ad24-42e1-ab01-88f384720a50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422465931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2422465931 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3411575446 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3747356988 ps |
| CPU time | 8.14 seconds |
| Started | Feb 07 12:32:41 PM PST 24 |
| Finished | Feb 07 12:33:02 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-90a245eb-80b1-4e18-b443-0cd2f81e9185 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411575446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3411575446 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4057191132 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2521050115 ps |
| CPU time | 12.75 seconds |
| Started | Feb 07 12:32:46 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-3b4670f8-9888-4585-b3c5-c3484e00f79c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4057191132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4057191132 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4203944184 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10194648 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:33:23 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-0735aa20-c022-42c4-8000-3dd0308613bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203944184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.4203944184 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.144971338 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 15115888455 ps |
| CPU time | 37.18 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:33:53 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-5fd9ab57-4d9d-48ed-a5a5-ef10570fcbf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=144971338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.144971338 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1632733841 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3066756688 ps |
| CPU time | 50.2 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:34:14 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-ac64bc6e-58b5-42b7-bdb4-5e7ec271a2a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1632733841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1632733841 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3483456324 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 113834324 ps |
| CPU time | 13.47 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:33:28 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-91195777-d07c-46bb-99eb-dd1a30a73051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3483456324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3483456324 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1859116529 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2291440566 ps |
| CPU time | 67.15 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:34:31 PM PST 24 |
| Peak memory | 205220 kb |
| Host | smart-6c29b4bc-bdf6-40d3-9d81-41fcc7daf8e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1859116529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1859116529 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2936668187 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1061015583 ps |
| CPU time | 5.8 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-bd93c7d3-1e88-4a8e-9b65-4865fa0184c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2936668187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2936668187 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3767951831 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 68495419 ps |
| CPU time | 5.66 seconds |
| Started | Feb 07 12:33:08 PM PST 24 |
| Finished | Feb 07 12:33:28 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-61e23def-5813-4bd2-9fe3-6eda60ecc224 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767951831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3767951831 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1123994803 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 349849261 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 12:33:03 PM PST 24 |
| Finished | Feb 07 12:33:25 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-f0ba9329-c557-4105-a819-352c19ff2532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1123994803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1123994803 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.1952677219 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 609143625 ps |
| CPU time | 3.15 seconds |
| Started | Feb 07 12:33:13 PM PST 24 |
| Finished | Feb 07 12:33:29 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-619b5805-714a-49fe-905f-0bd1e84848c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1952677219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1952677219 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1804356604 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 76450719 ps |
| CPU time | 5.86 seconds |
| Started | Feb 07 12:33:00 PM PST 24 |
| Finished | Feb 07 12:33:22 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-89e80b89-94d4-4e5e-8558-2ef72945d40e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1804356604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1804356604 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3968483102 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 54979467548 ps |
| CPU time | 127.13 seconds |
| Started | Feb 07 12:32:57 PM PST 24 |
| Finished | Feb 07 12:35:21 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-04b5f513-1c0c-4c4c-ae28-a02343e80890 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968483102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3968483102 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2072334776 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13561925632 ps |
| CPU time | 97.99 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:35:00 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-ae54c393-10ff-4c4f-8648-f5f7b97572ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2072334776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2072334776 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3845735067 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 65270621 ps |
| CPU time | 8.11 seconds |
| Started | Feb 07 12:32:59 PM PST 24 |
| Finished | Feb 07 12:33:24 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-a598a567-749f-4a79-ae0b-cba8ce8ea49b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845735067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3845735067 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4222997498 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3819243738 ps |
| CPU time | 8.64 seconds |
| Started | Feb 07 12:33:09 PM PST 24 |
| Finished | Feb 07 12:33:32 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-66410b9a-4923-4730-b927-079314864fbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222997498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4222997498 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.752185143 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 64571719 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:32:55 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-496ba832-f433-4faf-8195-99615c9403c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=752185143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.752185143 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2657071179 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4629294369 ps |
| CPU time | 8.81 seconds |
| Started | Feb 07 12:32:48 PM PST 24 |
| Finished | Feb 07 12:33:14 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-f70d2ca2-da82-45db-a8a5-905d421b4a17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657071179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2657071179 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1856136790 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2795506413 ps |
| CPU time | 8.39 seconds |
| Started | Feb 07 12:33:07 PM PST 24 |
| Finished | Feb 07 12:33:30 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-02767140-2823-48e5-8081-e4c6b6933ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1856136790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1856136790 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1755583008 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 13020555 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:33:08 PM PST 24 |
| Finished | Feb 07 12:33:24 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-dac25452-08f2-4945-a84b-87f084fa86ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755583008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1755583008 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1844374251 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 2435509887 ps |
| CPU time | 20.35 seconds |
| Started | Feb 07 12:32:58 PM PST 24 |
| Finished | Feb 07 12:33:35 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-609b7836-f80e-48d9-987f-1b890a934346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844374251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1844374251 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3106903026 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2515250530 ps |
| CPU time | 20.29 seconds |
| Started | Feb 07 12:33:06 PM PST 24 |
| Finished | Feb 07 12:33:41 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-eefd3c2f-891b-4dc8-92d5-e9b9d4d3fe9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3106903026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3106903026 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1771757438 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 145109865 ps |
| CPU time | 24.58 seconds |
| Started | Feb 07 12:32:53 PM PST 24 |
| Finished | Feb 07 12:33:34 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-29d58f46-90ca-45cc-9744-50bcb9ced811 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771757438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1771757438 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2573839977 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1469820342 ps |
| CPU time | 52.88 seconds |
| Started | Feb 07 12:33:01 PM PST 24 |
| Finished | Feb 07 12:34:09 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-2828ed73-ac72-4703-810a-f714c2ea8162 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573839977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2573839977 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3400009583 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 869012522 ps |
| CPU time | 10.08 seconds |
| Started | Feb 07 12:33:06 PM PST 24 |
| Finished | Feb 07 12:33:31 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-c324c294-233a-4bf9-9b01-70698c79b351 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3400009583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3400009583 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.733134454 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 71990884 ps |
| CPU time | 8.26 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-e7d2d044-d169-4a3a-98ae-c3440ffb3ea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733134454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.733134454 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2432341849 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 30663603 ps |
| CPU time | 3.41 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:21 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-eb3dbe46-0715-4d9d-a39b-1970b308471b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2432341849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2432341849 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.258591413 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 21980416 ps |
| CPU time | 2.25 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:19 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-3d71e71e-041b-447e-961c-f4b81689fe44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=258591413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.258591413 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2925491997 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 471315305 ps |
| CPU time | 7.91 seconds |
| Started | Feb 07 12:27:20 PM PST 24 |
| Finished | Feb 07 12:27:30 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-41161dfc-ae11-4b0e-9523-e59755193719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925491997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2925491997 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.797383347 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 23469403392 ps |
| CPU time | 88.68 seconds |
| Started | Feb 07 12:27:20 PM PST 24 |
| Finished | Feb 07 12:28:50 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-7ab38a10-c921-4881-a6c0-7ecbc9397840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=797383347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.797383347 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2194989431 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 36123653133 ps |
| CPU time | 75.05 seconds |
| Started | Feb 07 12:27:09 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-1048da92-6600-4194-8d94-50f881eb49f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2194989431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2194989431 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1624582128 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 85540260 ps |
| CPU time | 9.51 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:24 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-fa10f12c-6e78-4406-864d-7a1b8bf9063c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624582128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1624582128 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.500199364 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 38450225 ps |
| CPU time | 3.39 seconds |
| Started | Feb 07 12:27:12 PM PST 24 |
| Finished | Feb 07 12:27:18 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-e4153504-e3a4-4454-bfe8-cc739396c14b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500199364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.500199364 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2068451695 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 66875186 ps |
| CPU time | 1.51 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-938a5de0-0ce7-4689-adfb-86a26d0ebdf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068451695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2068451695 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.911727829 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9633407807 ps |
| CPU time | 7.39 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:22 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-4a10459c-e8b8-4f94-a97b-9529647ea2e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=911727829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.911727829 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.80323973 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4718508869 ps |
| CPU time | 9.7 seconds |
| Started | Feb 07 12:27:12 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-7a31f23a-4c41-4d14-a845-aa9f9312ac9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=80323973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.80323973 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1423161206 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 15081896 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:27:20 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-2e415923-8a62-4a71-9c9b-c23f1723cbf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423161206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1423161206 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.4170184883 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 523682436 ps |
| CPU time | 48.46 seconds |
| Started | Feb 07 12:27:09 PM PST 24 |
| Finished | Feb 07 12:28:02 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-1be220d1-80b5-4ad5-8d03-81bd90f787c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4170184883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4170184883 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4171964586 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 12791426381 ps |
| CPU time | 67.59 seconds |
| Started | Feb 07 12:27:17 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6380becb-583a-40f8-bd8c-e3e2c3976e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4171964586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4171964586 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1632744054 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 7229697445 ps |
| CPU time | 173.94 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:30:11 PM PST 24 |
| Peak memory | 207080 kb |
| Host | smart-3a3df6a9-e6c2-4331-9ec5-f464154e942c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1632744054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1632744054 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4073995064 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 679936056 ps |
| CPU time | 22.74 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:37 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-5fe46321-ade0-4fac-a2ce-1d29abf2055a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073995064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.4073995064 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2334145972 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 45008938 ps |
| CPU time | 4.32 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:27:17 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-311c7c6c-949a-43d0-aeda-dccafc1b8c25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334145972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2334145972 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3000005005 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 43211230 ps |
| CPU time | 4.02 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:18 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-f8bdb476-93ac-4ef6-97dc-6afd2db464fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3000005005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3000005005 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2725634548 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 16113570189 ps |
| CPU time | 99.35 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:28:52 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-6679716f-7c01-4900-8466-52fe5903308b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2725634548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.2725634548 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3246024649 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 164874135 ps |
| CPU time | 2.83 seconds |
| Started | Feb 07 12:27:20 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-7500d4c2-6de9-4df4-a31e-92c813ee85e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3246024649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3246024649 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.184860123 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1062866542 ps |
| CPU time | 10.17 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-60f61b0d-9083-41f2-a155-27eac7237688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184860123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.184860123 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1388161232 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 219708909 ps |
| CPU time | 7.12 seconds |
| Started | Feb 07 12:27:14 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-a0b49d3e-e553-4e83-92df-7e6ef9d3dd79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1388161232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1388161232 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.265892630 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 23428854962 ps |
| CPU time | 41.03 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:55 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-7240a987-f5dd-4ff4-bc3d-b0f1a98cbe0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=265892630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.265892630 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2252433030 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 20253060394 ps |
| CPU time | 149.34 seconds |
| Started | Feb 07 12:27:12 PM PST 24 |
| Finished | Feb 07 12:29:44 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-5617b1b3-c369-4eea-864e-c98baa57a566 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2252433030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2252433030 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3537084331 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 167778501 ps |
| CPU time | 6.45 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:27 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-50079ae3-c41e-4b96-926d-08986e80ed26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537084331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3537084331 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3394926543 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1417237670 ps |
| CPU time | 9.93 seconds |
| Started | Feb 07 12:27:10 PM PST 24 |
| Finished | Feb 07 12:27:24 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-329da69d-554f-42ca-90b4-cd71358eda34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394926543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3394926543 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3028182558 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18273608 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:27:13 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-05800c8e-8f3e-4ddb-9b4e-b5959cd40817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3028182558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3028182558 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.813437941 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 6137434295 ps |
| CPU time | 9.86 seconds |
| Started | Feb 07 12:27:11 PM PST 24 |
| Finished | Feb 07 12:27:25 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-7f8ced3f-1a92-425b-bfd0-7b804c578e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=813437941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.813437941 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2755840779 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2053054748 ps |
| CPU time | 13.92 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202144 kb |
| Host | smart-541e692f-b193-4534-ae26-35153c07bf94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2755840779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2755840779 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1088940104 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 14339613 ps |
| CPU time | 1.21 seconds |
| Started | Feb 07 12:27:12 PM PST 24 |
| Finished | Feb 07 12:27:16 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-5bf81697-1cad-48bc-a87a-ff74051ee8f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088940104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1088940104 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.362411361 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 955466659 ps |
| CPU time | 23.3 seconds |
| Started | Feb 07 12:27:08 PM PST 24 |
| Finished | Feb 07 12:27:35 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-d6b00acc-5188-48fe-81e5-57b7b2906e41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362411361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.362411361 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1361332173 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 7686708358 ps |
| CPU time | 67.59 seconds |
| Started | Feb 07 12:27:20 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-a6114658-f13a-4fe7-8279-d748edd86ba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1361332173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1361332173 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1213760690 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4376083557 ps |
| CPU time | 121.91 seconds |
| Started | Feb 07 12:27:23 PM PST 24 |
| Finished | Feb 07 12:29:32 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-70eb48c1-4602-4709-8d87-db4435e46c5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1213760690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1213760690 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2675560297 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 640855256 ps |
| CPU time | 87.02 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:28:50 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-40fd62d2-3de6-4ffa-8a53-b6b2c346ea57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2675560297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2675560297 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1628868882 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 16858544 ps |
| CPU time | 2.24 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:19 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-dca3168e-3aa0-48a0-8758-65d07f517311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628868882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1628868882 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2678483957 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 408737763 ps |
| CPU time | 10.48 seconds |
| Started | Feb 07 12:27:14 PM PST 24 |
| Finished | Feb 07 12:27:27 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-f3435972-792a-465b-986b-235a8f8f36b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2678483957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2678483957 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2782849986 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 45978696662 ps |
| CPU time | 142.1 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:29:39 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-2199dd27-71f4-46d4-adbc-853c8512f54b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2782849986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2782849986 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1430890230 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 9713328 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:27:28 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-1e3e7ddb-6147-42e2-a633-8b4ad237bbdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1430890230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1430890230 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2725025486 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 135590896 ps |
| CPU time | 3.03 seconds |
| Started | Feb 07 12:27:15 PM PST 24 |
| Finished | Feb 07 12:27:20 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-f2a7ca74-a892-417b-976e-831f99865f57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2725025486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2725025486 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.1994142155 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 734035196 ps |
| CPU time | 5.86 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:27:35 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-77ec1af2-bf4e-4b88-8f02-2ae48f3a4980 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1994142155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1994142155 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1333376520 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 85678886187 ps |
| CPU time | 105.09 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:29:12 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-f29a867a-b0d0-4da2-936e-c4b8e497d8e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333376520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1333376520 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.705076812 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 10340128815 ps |
| CPU time | 29.36 seconds |
| Started | Feb 07 12:27:17 PM PST 24 |
| Finished | Feb 07 12:27:49 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-aa759c73-0fb0-44ce-8f9c-939cdc1e0a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=705076812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.705076812 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3693330450 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 209718381 ps |
| CPU time | 4.75 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:27:27 PM PST 24 |
| Peak memory | 201788 kb |
| Host | smart-f6e4c783-26c3-40cc-bfdb-8bc9c9331573 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693330450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3693330450 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.3856065680 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 785236696 ps |
| CPU time | 8.42 seconds |
| Started | Feb 07 12:27:23 PM PST 24 |
| Finished | Feb 07 12:27:39 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-9f501991-c11b-492d-b536-85f5fff5ea54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3856065680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3856065680 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.2348059863 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 34159381 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 12:27:19 PM PST 24 |
| Finished | Feb 07 12:27:23 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-1f5ef4c8-3b1b-4301-b5cd-b88ef25f5594 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348059863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2348059863 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3718897573 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1716172670 ps |
| CPU time | 8.3 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:39 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-3d5e3591-ae17-469b-928b-90c7723962c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718897573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3718897573 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3794418710 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2667043378 ps |
| CPU time | 11.32 seconds |
| Started | Feb 07 12:27:17 PM PST 24 |
| Finished | Feb 07 12:27:31 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-e8b632d5-a450-4f16-a14d-3a0a1daab6c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3794418710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3794418710 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3537183729 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 8600010 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:27:30 PM PST 24 |
| Peak memory | 202124 kb |
| Host | smart-905e4619-03d7-45d7-a4cc-7d8372976707 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537183729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3537183729 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2691275836 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4088083623 ps |
| CPU time | 60.29 seconds |
| Started | Feb 07 12:27:13 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-06aa6997-8f47-4b87-93cf-9fe64df65e9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2691275836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2691275836 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2388570590 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 15150754881 ps |
| CPU time | 46.76 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:28:09 PM PST 24 |
| Peak memory | 202108 kb |
| Host | smart-ce0d412c-01be-4f24-8ff4-a08db57e22d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388570590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2388570590 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.961745973 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 548243720 ps |
| CPU time | 52.58 seconds |
| Started | Feb 07 12:27:17 PM PST 24 |
| Finished | Feb 07 12:28:12 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-ba62626c-bc15-49c9-b9eb-c9dec29e3ad8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=961745973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.961745973 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2385037722 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1239838956 ps |
| CPU time | 149.32 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:29:52 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-d218741b-2a94-4376-9439-64ec37b249f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385037722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2385037722 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2401429492 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 611844866 ps |
| CPU time | 10.1 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:27:38 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-2ab9d198-8c3e-49a2-91c5-d6ea961c7494 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401429492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2401429492 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2729060988 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 580052241 ps |
| CPU time | 11.17 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:47 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-c629452c-dfd5-45d3-a634-774cc17b2145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729060988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2729060988 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.873553115 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 35582735233 ps |
| CPU time | 69.89 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:28:38 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-d6ba14ec-63c4-4177-8719-96415ca2596b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=873553115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.873553115 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.297250432 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 74140097 ps |
| CPU time | 2.91 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:38 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-54cd0270-33ed-4a18-80fd-fcda661e61b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=297250432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.297250432 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2860809531 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 212709150 ps |
| CPU time | 3.3 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:33 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-6f8657f5-590d-42d8-9e8d-e45874c345eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860809531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2860809531 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.3679596165 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 178409370 ps |
| CPU time | 3.59 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:39 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-b0154624-b6d3-4301-b320-e15fa227b34a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679596165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3679596165 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1312048294 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 25515013711 ps |
| CPU time | 38.91 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:28:10 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-a24d9212-cf3f-44e3-b1f8-4359e768b58c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312048294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1312048294 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2002792426 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 79431788438 ps |
| CPU time | 122.62 seconds |
| Started | Feb 07 12:27:23 PM PST 24 |
| Finished | Feb 07 12:29:33 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-0ec1588e-fa98-4472-91e2-cd7a950b718a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2002792426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2002792426 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3622595159 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 146729943 ps |
| CPU time | 5.43 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:36 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-03435564-ed5d-4bf2-98be-77cdbf716558 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622595159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3622595159 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1451088933 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 131620145 ps |
| CPU time | 4.95 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-1b90fcbc-026c-4378-ad99-32ac47ba488e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451088933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1451088933 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1222866732 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 10317863 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:27:25 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-a54c08e6-1b98-4ae3-8a54-39c947f11b89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1222866732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1222866732 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3252452027 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3966755808 ps |
| CPU time | 10.94 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-40fa86e3-00ab-4383-a29c-419795c23e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252452027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3252452027 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2460060277 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1856961971 ps |
| CPU time | 5.2 seconds |
| Started | Feb 07 12:27:25 PM PST 24 |
| Finished | Feb 07 12:27:35 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-38d7b349-36de-41ee-9684-eaa3328b415b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2460060277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2460060277 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.752310332 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 12531519 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:27:21 PM PST 24 |
| Finished | Feb 07 12:27:24 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-1337d265-43e8-44db-b12b-5943f222bbc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752310332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.752310332 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2365051821 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 544060092 ps |
| CPU time | 55.32 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:27 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-7b24deea-3e97-4e74-a987-30e8b465e70c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2365051821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2365051821 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3599007440 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4698459807 ps |
| CPU time | 51.14 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:23 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-ee9ea91a-8d8e-450e-9200-b65883b3e312 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3599007440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3599007440 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1590202120 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2843087440 ps |
| CPU time | 134.03 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:29:50 PM PST 24 |
| Peak memory | 206580 kb |
| Host | smart-34830347-5a66-49d7-b508-4d1597b62462 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590202120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.1590202120 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2914251573 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 301924222 ps |
| CPU time | 42.85 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:15 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-06ad2033-8bc1-4a20-a6a2-6ff031ce7d7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914251573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2914251573 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2308790789 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 58758280 ps |
| CPU time | 8.33 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-4d1bb8ea-156c-418f-822b-340d5241bc51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2308790789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2308790789 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1438578266 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 948446025 ps |
| CPU time | 8.42 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-993f161c-25ad-435d-b1f7-f00c4bcaf81f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1438578266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1438578266 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2495098712 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 46867992751 ps |
| CPU time | 232.8 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:31:24 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-aabd3c06-ef54-4295-b2bd-cab6a137a373 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2495098712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2495098712 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4224126238 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1334482099 ps |
| CPU time | 7.58 seconds |
| Started | Feb 07 12:27:35 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-13a43724-b453-4947-9851-efde7146aec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224126238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4224126238 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.651156381 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 456351117 ps |
| CPU time | 7.94 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-c896496e-9f91-4611-bf16-cd469e133e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651156381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.651156381 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3305026571 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 58742010 ps |
| CPU time | 7.87 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:43 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-6582b782-fa31-4a55-ab7f-06443c22680e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305026571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3305026571 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1760912504 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5103829461 ps |
| CPU time | 8.23 seconds |
| Started | Feb 07 12:27:23 PM PST 24 |
| Finished | Feb 07 12:27:39 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-e66fbe45-640f-4c62-bdf9-adf3306dba6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760912504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1760912504 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2977775052 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1774535280 ps |
| CPU time | 14.53 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:50 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-c8aa644a-729b-4132-85f7-1f83a267e15c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2977775052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2977775052 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2359853511 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 67922893 ps |
| CPU time | 9.43 seconds |
| Started | Feb 07 12:27:24 PM PST 24 |
| Finished | Feb 07 12:27:40 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-4ec1d838-7f1a-4883-a977-05357b41d6bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359853511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2359853511 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3344229150 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 17099500 ps |
| CPU time | 1.65 seconds |
| Started | Feb 07 12:27:22 PM PST 24 |
| Finished | Feb 07 12:27:30 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-d5f2484d-3977-4b15-abfb-da8c77bcaab4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3344229150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3344229150 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3130824439 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 14327614 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:27:26 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-6f80c548-fb83-4cfb-9b9e-d8953b077c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3130824439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3130824439 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3534992696 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 14761448888 ps |
| CPU time | 8.51 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:27:44 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-d8f793fa-bf78-4a0a-b6a9-7056edb399c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534992696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3534992696 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2727622272 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2066468913 ps |
| CPU time | 13.33 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:27:45 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-143c069d-39ad-47ba-af7d-c651f184ceea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2727622272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2727622272 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.419151585 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 17346820 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:27:26 PM PST 24 |
| Finished | Feb 07 12:27:32 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-210da868-7f8e-4a7d-9c66-063476f12806 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419151585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.419151585 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.285484434 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 11545137195 ps |
| CPU time | 60.12 seconds |
| Started | Feb 07 12:27:27 PM PST 24 |
| Finished | Feb 07 12:28:31 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-f73a9ad6-54cb-4bc9-98e8-333672753bfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285484434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.285484434 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2145638610 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4840104040 ps |
| CPU time | 55.12 seconds |
| Started | Feb 07 12:27:28 PM PST 24 |
| Finished | Feb 07 12:28:29 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-b5c8c330-1f26-4397-8aaa-59b5e66ca6f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2145638610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2145638610 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3356321730 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 501002684 ps |
| CPU time | 49.2 seconds |
| Started | Feb 07 12:27:29 PM PST 24 |
| Finished | Feb 07 12:28:24 PM PST 24 |
| Peak memory | 204436 kb |
| Host | smart-d72d8987-b1e1-4a01-88fb-beb5b388dfac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356321730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.3356321730 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2390102792 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 961933934 ps |
| CPU time | 57.58 seconds |
| Started | Feb 07 12:27:34 PM PST 24 |
| Finished | Feb 07 12:28:34 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-6e623134-1510-46c0-b344-4f9dafd7bb15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390102792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2390102792 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4250910725 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 503608843 ps |
| CPU time | 5.23 seconds |
| Started | Feb 07 12:27:34 PM PST 24 |
| Finished | Feb 07 12:27:42 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-80d0e2bb-ee07-48f7-8a4c-9b695e0efeeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4250910725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4250910725 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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