Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 401 1 T1 2 T13 8 T14 4
all_values[1] 436 1 T1 5 T13 4 T14 5
all_values[2] 436 1 T1 2 T13 5 T14 5
all_values[3] 428 1 T1 2 T13 5 T14 3
all_values[4] 456 1 T1 1 T13 7 T14 3
all_values[5] 425 1 T1 1 T13 11 T36 1
all_values[6] 392 1 T1 3 T13 8 T17 1
all_values[7] 439 1 T1 2 T13 5 T14 4
all_values[8] 443 1 T1 1 T13 8 T14 2
all_values[9] 433 1 T1 4 T13 11 T17 1
all_values[10] 432 1 T1 3 T13 5 T14 8
all_values[11] 472 1 T1 4 T13 11 T14 2
all_values[12] 424 1 T1 3 T13 7 T17 1
all_values[13] 402 1 T1 1 T13 10 T14 4
all_values[14] 456 1 T13 9 T14 2 T19 3
all_values[15] 439 1 T1 5 T13 8 T17 5
all_values[16] 430 1 T1 3 T13 7 T17 3
all_values[17] 435 1 T1 3 T13 8 T17 1
all_values[18] 437 1 T1 1 T13 3 T14 6
all_values[19] 429 1 T1 4 T13 7 T17 1
all_values[20] 461 1 T1 4 T13 4 T17 1
all_values[21] 430 1 T1 3 T13 4 T14 5
all_values[22] 432 1 T1 5 T13 5 T17 1
all_values[23] 474 1 T1 3 T13 6 T14 9
all_values[24] 466 1 T1 3 T13 13 T14 10
all_values[25] 449 1 T13 4 T14 5 T19 2
all_values[26] 454 1 T1 1 T13 8 T14 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%