| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.28 | 100.00 | 95.71 | 100.00 | 100.00 | 100.00 | 100.00 |
| T758 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1339568630 | Feb 18 12:49:05 PM PST 24 | Feb 18 12:49:19 PM PST 24 | 500326236 ps | ||
| T759 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2582541681 | Feb 18 12:49:51 PM PST 24 | Feb 18 12:55:34 PM PST 24 | 59083661391 ps | ||
| T122 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1630801977 | Feb 18 12:48:42 PM PST 24 | Feb 18 12:49:29 PM PST 24 | 2678809289 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.165970138 | Feb 18 12:48:55 PM PST 24 | Feb 18 12:49:30 PM PST 24 | 404276605 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4003693522 | Feb 18 12:48:55 PM PST 24 | Feb 18 12:49:07 PM PST 24 | 565363206 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1555056283 | Feb 18 12:49:17 PM PST 24 | Feb 18 12:49:25 PM PST 24 | 48519916 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3779362930 | Feb 18 12:49:33 PM PST 24 | Feb 18 12:49:55 PM PST 24 | 1583927585 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.999749187 | Feb 18 12:50:35 PM PST 24 | Feb 18 12:50:40 PM PST 24 | 52463827 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2103686758 | Feb 18 12:51:00 PM PST 24 | Feb 18 12:53:25 PM PST 24 | 30385592977 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1916801735 | Feb 18 12:49:10 PM PST 24 | Feb 18 12:49:22 PM PST 24 | 82989846 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3213451405 | Feb 18 12:48:32 PM PST 24 | Feb 18 12:48:37 PM PST 24 | 193831809 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2824050867 | Feb 18 12:50:13 PM PST 24 | Feb 18 12:50:27 PM PST 24 | 2316686750 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1445842513 | Feb 18 12:48:44 PM PST 24 | Feb 18 12:51:00 PM PST 24 | 1443987564 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.421176776 | Feb 18 12:49:22 PM PST 24 | Feb 18 12:50:31 PM PST 24 | 14973347050 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2221836834 | Feb 18 12:50:48 PM PST 24 | Feb 18 12:50:52 PM PST 24 | 36930834 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2203133826 | Feb 18 12:49:48 PM PST 24 | Feb 18 12:50:00 PM PST 24 | 3873546647 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.976635153 | Feb 18 12:49:33 PM PST 24 | Feb 18 12:49:45 PM PST 24 | 2348344000 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/42.xbar_smoke.4060813868 | Feb 18 12:50:38 PM PST 24 | Feb 18 12:50:42 PM PST 24 | 45245533 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.4153211411 | Feb 18 12:48:09 PM PST 24 | Feb 18 12:48:33 PM PST 24 | 5051707457 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.431609056 | Feb 18 12:49:56 PM PST 24 | Feb 18 12:50:03 PM PST 24 | 26686592 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/31.xbar_same_source.2600287174 | Feb 18 12:49:49 PM PST 24 | Feb 18 12:49:59 PM PST 24 | 76257010 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2426528541 | Feb 18 12:49:08 PM PST 24 | Feb 18 12:49:19 PM PST 24 | 96307384 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1525251109 | Feb 18 12:48:29 PM PST 24 | Feb 18 12:48:38 PM PST 24 | 36862402 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1191217161 | Feb 18 12:50:04 PM PST 24 | Feb 18 12:50:20 PM PST 24 | 1302539741 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2323175067 | Feb 18 12:50:37 PM PST 24 | Feb 18 12:50:59 PM PST 24 | 1296890203 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2726745052 | Feb 18 12:49:18 PM PST 24 | Feb 18 12:49:36 PM PST 24 | 3006772199 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1812110484 | Feb 18 12:50:25 PM PST 24 | Feb 18 12:51:25 PM PST 24 | 1865019064 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/6.xbar_error_random.837962720 | Feb 18 12:48:20 PM PST 24 | Feb 18 12:48:27 PM PST 24 | 269960170 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2445519147 | Feb 18 12:50:11 PM PST 24 | Feb 18 12:50:42 PM PST 24 | 304893978 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3969576998 | Feb 18 12:49:43 PM PST 24 | Feb 18 12:49:52 PM PST 24 | 661474878 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1987940461 | Feb 18 12:49:50 PM PST 24 | Feb 18 12:49:59 PM PST 24 | 531369417 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.576988274 | Feb 18 12:49:53 PM PST 24 | Feb 18 12:50:14 PM PST 24 | 63296415 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3434108628 | Feb 18 12:48:27 PM PST 24 | Feb 18 12:48:37 PM PST 24 | 123799074 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.207421864 | Feb 18 12:50:53 PM PST 24 | Feb 18 12:51:08 PM PST 24 | 6832883902 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3401987180 | Feb 18 12:50:49 PM PST 24 | Feb 18 12:50:56 PM PST 24 | 440524440 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2480384123 | Feb 18 12:50:37 PM PST 24 | Feb 18 12:50:51 PM PST 24 | 3200959957 ps | ||
| T147 | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1971540981 | Feb 18 12:49:17 PM PST 24 | Feb 18 12:55:25 PM PST 24 | 107258587261 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/15.xbar_smoke.252834785 | Feb 18 12:48:46 PM PST 24 | Feb 18 12:48:49 PM PST 24 | 9237161 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2584378077 | Feb 18 12:49:19 PM PST 24 | Feb 18 12:49:26 PM PST 24 | 79100667 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3912414071 | Feb 18 12:48:09 PM PST 24 | Feb 18 12:48:20 PM PST 24 | 72438501 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/35.xbar_error_random.576683745 | Feb 18 12:50:01 PM PST 24 | Feb 18 12:50:10 PM PST 24 | 730195366 ps | ||
| T123 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2525395256 | Feb 18 12:49:09 PM PST 24 | Feb 18 12:49:32 PM PST 24 | 3594242058 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1519563976 | Feb 18 12:50:08 PM PST 24 | Feb 18 12:50:31 PM PST 24 | 2187001724 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3219117659 | Feb 18 12:48:08 PM PST 24 | Feb 18 12:48:28 PM PST 24 | 1009438576 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2270466045 | Feb 18 12:50:51 PM PST 24 | Feb 18 12:51:03 PM PST 24 | 152543488 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3650107714 | Feb 18 12:49:43 PM PST 24 | Feb 18 12:49:50 PM PST 24 | 86449446 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.210665910 | Feb 18 12:48:08 PM PST 24 | Feb 18 12:48:20 PM PST 24 | 20271211 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4126491693 | Feb 18 12:49:15 PM PST 24 | Feb 18 12:49:22 PM PST 24 | 43679557 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3161018349 | Feb 18 12:49:14 PM PST 24 | Feb 18 12:49:45 PM PST 24 | 3511523107 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2995840873 | Feb 18 12:51:03 PM PST 24 | Feb 18 12:51:10 PM PST 24 | 130121244 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.110274215 | Feb 18 12:50:53 PM PST 24 | Feb 18 12:51:17 PM PST 24 | 420343591 ps | ||
| T175 | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3323193339 | Feb 18 12:48:40 PM PST 24 | Feb 18 12:49:43 PM PST 24 | 15904062774 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.910360917 | Feb 18 12:47:58 PM PST 24 | Feb 18 12:48:34 PM PST 24 | 10453709475 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/33.xbar_random.406909224 | Feb 18 12:49:57 PM PST 24 | Feb 18 12:50:14 PM PST 24 | 1547737395 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1075992512 | Feb 18 12:47:59 PM PST 24 | Feb 18 12:48:13 PM PST 24 | 74346867 ps | ||
| T6 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1114154444 | Feb 18 12:48:31 PM PST 24 | Feb 18 12:51:44 PM PST 24 | 2514857095 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.77821806 | Feb 18 12:50:59 PM PST 24 | Feb 18 12:51:08 PM PST 24 | 911311866 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2832984317 | Feb 18 12:48:41 PM PST 24 | Feb 18 12:48:49 PM PST 24 | 94409158 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/2.xbar_random.610881283 | Feb 18 12:48:02 PM PST 24 | Feb 18 12:48:18 PM PST 24 | 639604698 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/13.xbar_random.606881428 | Feb 18 12:48:43 PM PST 24 | Feb 18 12:48:54 PM PST 24 | 702912610 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3569631560 | Feb 18 12:50:25 PM PST 24 | Feb 18 12:50:33 PM PST 24 | 315968523 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2793343760 | Feb 18 12:49:22 PM PST 24 | Feb 18 12:49:28 PM PST 24 | 813415350 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.729146679 | Feb 18 12:48:28 PM PST 24 | Feb 18 12:48:31 PM PST 24 | 9599586 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2756338910 | Feb 18 12:48:54 PM PST 24 | Feb 18 12:49:03 PM PST 24 | 125888666 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1067774543 | Feb 18 12:48:36 PM PST 24 | Feb 18 12:48:50 PM PST 24 | 148713862 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3834701786 | Feb 18 12:49:06 PM PST 24 | Feb 18 12:49:16 PM PST 24 | 50318257 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3665858482 | Feb 18 12:49:53 PM PST 24 | Feb 18 12:50:01 PM PST 24 | 79374850 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1303584947 | Feb 18 12:48:00 PM PST 24 | Feb 18 12:48:21 PM PST 24 | 518325370 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.872352771 | Feb 18 12:49:00 PM PST 24 | Feb 18 12:49:03 PM PST 24 | 27465635 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3255656609 | Feb 18 12:49:24 PM PST 24 | Feb 18 12:49:55 PM PST 24 | 316579364 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.973270074 | Feb 18 12:48:36 PM PST 24 | Feb 18 12:51:11 PM PST 24 | 35010472689 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1158947303 | Feb 18 12:50:58 PM PST 24 | Feb 18 12:51:15 PM PST 24 | 1900004143 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.701348593 | Feb 18 12:49:10 PM PST 24 | Feb 18 12:49:55 PM PST 24 | 485712706 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.967474495 | Feb 18 12:49:52 PM PST 24 | Feb 18 12:50:12 PM PST 24 | 184164251 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/8.xbar_smoke.643926288 | Feb 18 12:48:26 PM PST 24 | Feb 18 12:48:29 PM PST 24 | 10141044 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/36.xbar_smoke.3005557521 | Feb 18 12:50:06 PM PST 24 | Feb 18 12:50:17 PM PST 24 | 98737623 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2814855127 | Feb 18 12:49:43 PM PST 24 | Feb 18 12:49:47 PM PST 24 | 799625958 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1028254062 | Feb 18 12:50:17 PM PST 24 | Feb 18 12:50:28 PM PST 24 | 180618606 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.87025919 | Feb 18 12:48:03 PM PST 24 | Feb 18 12:48:22 PM PST 24 | 474875082 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/35.xbar_smoke.3032744042 | Feb 18 12:50:08 PM PST 24 | Feb 18 12:50:18 PM PST 24 | 20619259 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3249743299 | Feb 18 12:50:10 PM PST 24 | Feb 18 12:50:25 PM PST 24 | 3567222241 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2250043176 | Feb 18 12:50:22 PM PST 24 | Feb 18 12:50:27 PM PST 24 | 34764619 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/48.xbar_random.596081337 | Feb 18 12:51:02 PM PST 24 | Feb 18 12:51:14 PM PST 24 | 64286607 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1088090541 | Feb 18 12:49:44 PM PST 24 | Feb 18 12:49:56 PM PST 24 | 1253755970 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1129027551 | Feb 18 12:50:50 PM PST 24 | Feb 18 12:50:57 PM PST 24 | 149434553 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2660969248 | Feb 18 12:50:06 PM PST 24 | Feb 18 12:50:20 PM PST 24 | 48407544 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3574682257 | Feb 18 12:49:58 PM PST 24 | Feb 18 12:50:26 PM PST 24 | 1529991169 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.169579682 | Feb 18 12:49:24 PM PST 24 | Feb 18 12:49:31 PM PST 24 | 228073432 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.226739951 | Feb 18 12:49:55 PM PST 24 | Feb 18 12:50:58 PM PST 24 | 10489669232 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.503749650 | Feb 18 12:50:34 PM PST 24 | Feb 18 12:50:41 PM PST 24 | 312515463 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.92783239 | Feb 18 12:48:39 PM PST 24 | Feb 18 12:50:57 PM PST 24 | 113501350790 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3331466407 | Feb 18 12:50:34 PM PST 24 | Feb 18 12:55:14 PM PST 24 | 69907340959 ps | ||
| T124 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2089802177 | Feb 18 12:47:56 PM PST 24 | Feb 18 12:53:04 PM PST 24 | 50713994059 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2560333988 | Feb 18 12:50:40 PM PST 24 | Feb 18 12:50:43 PM PST 24 | 96188008 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1986706460 | Feb 18 12:47:52 PM PST 24 | Feb 18 12:49:49 PM PST 24 | 43882004842 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.767604140 | Feb 18 12:50:48 PM PST 24 | Feb 18 12:50:52 PM PST 24 | 13131167 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2847265359 | Feb 18 12:51:03 PM PST 24 | Feb 18 12:53:03 PM PST 24 | 221976184420 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3796110585 | Feb 18 12:49:04 PM PST 24 | Feb 18 12:49:10 PM PST 24 | 90020240 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1424454435 | Feb 18 12:51:00 PM PST 24 | Feb 18 12:51:04 PM PST 24 | 82462542 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2587741122 | Feb 18 12:49:53 PM PST 24 | Feb 18 12:50:06 PM PST 24 | 866751359 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/21.xbar_random.2532261569 | Feb 18 12:49:12 PM PST 24 | Feb 18 12:49:26 PM PST 24 | 1648250203 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2489645851 | Feb 18 12:48:51 PM PST 24 | Feb 18 12:50:24 PM PST 24 | 22945501335 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2113757821 | Feb 18 12:50:41 PM PST 24 | Feb 18 12:53:38 PM PST 24 | 72368935942 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3252882976 | Feb 18 12:48:46 PM PST 24 | Feb 18 12:49:00 PM PST 24 | 3886937370 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3821879581 | Feb 18 12:50:09 PM PST 24 | Feb 18 12:56:23 PM PST 24 | 20768072865 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2461318079 | Feb 18 12:48:32 PM PST 24 | Feb 18 12:48:43 PM PST 24 | 9727984171 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3533181652 | Feb 18 12:48:24 PM PST 24 | Feb 18 12:48:38 PM PST 24 | 20476970563 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3528133330 | Feb 18 12:48:42 PM PST 24 | Feb 18 12:48:47 PM PST 24 | 309446939 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2755033386 | Feb 18 12:48:19 PM PST 24 | Feb 18 12:48:23 PM PST 24 | 24772355 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2703844818 | Feb 18 12:50:53 PM PST 24 | Feb 18 12:51:55 PM PST 24 | 16578423278 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3750037141 | Feb 18 12:48:04 PM PST 24 | Feb 18 12:48:23 PM PST 24 | 53769744 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1293565217 | Feb 18 12:50:33 PM PST 24 | Feb 18 12:50:41 PM PST 24 | 818977549 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3569361135 | Feb 18 12:49:35 PM PST 24 | Feb 18 12:50:44 PM PST 24 | 20322661559 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.835230462 | Feb 18 12:50:03 PM PST 24 | Feb 18 12:51:52 PM PST 24 | 14842136638 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.940750093 | Feb 18 12:50:20 PM PST 24 | Feb 18 12:50:40 PM PST 24 | 1022718404 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2337473426 | Feb 18 12:50:32 PM PST 24 | Feb 18 12:50:39 PM PST 24 | 186327461 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.964620372 | Feb 18 12:50:37 PM PST 24 | Feb 18 12:50:53 PM PST 24 | 102218661 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3070985307 | Feb 18 12:50:07 PM PST 24 | Feb 18 12:51:44 PM PST 24 | 794888459 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3045015588 | Feb 18 12:50:09 PM PST 24 | Feb 18 12:50:19 PM PST 24 | 9111129 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.170194808 | Feb 18 12:49:19 PM PST 24 | Feb 18 12:49:23 PM PST 24 | 21981944 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3740320156 | Feb 18 12:49:21 PM PST 24 | Feb 18 12:49:34 PM PST 24 | 664633054 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.586834687 | Feb 18 12:50:46 PM PST 24 | Feb 18 12:50:50 PM PST 24 | 8389273 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1638512369 | Feb 18 12:50:02 PM PST 24 | Feb 18 12:50:22 PM PST 24 | 1793856844 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.140841721 | Feb 18 12:51:00 PM PST 24 | Feb 18 12:51:14 PM PST 24 | 7290066423 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3284034795 | Feb 18 12:49:50 PM PST 24 | Feb 18 12:51:55 PM PST 24 | 15714502607 ps | ||
| T133 | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3913120074 | Feb 18 12:50:00 PM PST 24 | Feb 18 12:50:23 PM PST 24 | 1260293997 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2551345826 | Feb 18 12:49:10 PM PST 24 | Feb 18 12:52:10 PM PST 24 | 739841079 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3203991297 | Feb 18 12:48:41 PM PST 24 | Feb 18 12:49:08 PM PST 24 | 1206840569 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/46.xbar_random.55339899 | Feb 18 12:50:52 PM PST 24 | Feb 18 12:50:58 PM PST 24 | 44723756 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2843256388 | Feb 18 12:49:55 PM PST 24 | Feb 18 12:50:08 PM PST 24 | 322714815 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4145958263 | Feb 18 12:49:46 PM PST 24 | Feb 18 12:50:50 PM PST 24 | 9474063715 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3534705113 | Feb 18 12:48:49 PM PST 24 | Feb 18 12:50:36 PM PST 24 | 919085986 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2649141553 | Feb 18 12:48:32 PM PST 24 | Feb 18 12:48:36 PM PST 24 | 40321332 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/7.xbar_random.3446515164 | Feb 18 12:48:23 PM PST 24 | Feb 18 12:48:30 PM PST 24 | 144327626 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.765997687 | Feb 18 12:50:27 PM PST 24 | Feb 18 12:50:36 PM PST 24 | 9151271044 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/40.xbar_random.3192645833 | Feb 18 12:50:33 PM PST 24 | Feb 18 12:50:46 PM PST 24 | 939899406 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1389590681 | Feb 18 12:47:57 PM PST 24 | Feb 18 12:48:14 PM PST 24 | 6171007726 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2953696960 | Feb 18 12:49:27 PM PST 24 | Feb 18 12:49:30 PM PST 24 | 56554134 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2699426087 | Feb 18 12:48:43 PM PST 24 | Feb 18 12:48:53 PM PST 24 | 54951689 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1481193681 | Feb 18 12:49:57 PM PST 24 | Feb 18 12:50:06 PM PST 24 | 28080075 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2307476779 | Feb 18 12:49:35 PM PST 24 | Feb 18 12:53:00 PM PST 24 | 71142254209 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/25.xbar_random.2186595688 | Feb 18 12:49:19 PM PST 24 | Feb 18 12:49:25 PM PST 24 | 360433624 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2004374472 | Feb 18 12:49:13 PM PST 24 | Feb 18 12:49:27 PM PST 24 | 763520154 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2005960916 | Feb 18 12:50:14 PM PST 24 | Feb 18 12:50:21 PM PST 24 | 10997111 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2018111680 | Feb 18 12:50:58 PM PST 24 | Feb 18 12:55:57 PM PST 24 | 74618322077 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1955380289 | Feb 18 12:50:01 PM PST 24 | Feb 18 12:50:10 PM PST 24 | 8581810 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2187458722 | Feb 18 12:50:05 PM PST 24 | Feb 18 12:50:22 PM PST 24 | 6108576820 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1677433979 | Feb 18 12:50:10 PM PST 24 | Feb 18 12:50:25 PM PST 24 | 380027453 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.35325042 | Feb 18 12:48:55 PM PST 24 | Feb 18 12:49:11 PM PST 24 | 6342715845 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.451272179 | Feb 18 12:49:05 PM PST 24 | Feb 18 12:49:17 PM PST 24 | 1103337286 ps |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3750890915 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9427191283 ps |
| CPU time | 90.68 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:50:47 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-b8dd6130-9e92-4d0d-866a-317ab0216272 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750890915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3750890915 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.212639409 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 40880124013 ps |
| CPU time | 300.08 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:54:20 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-27447121-2a85-405d-a9c8-0560838646df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=212639409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.212639409 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1522954448 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 78274125549 ps |
| CPU time | 258.37 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:54:25 PM PST 24 |
| Peak memory | 203580 kb |
| Host | smart-1f80f9e0-f66d-473a-b8f2-c2ece2dc2150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1522954448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1522954448 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.938889098 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26011239277 ps |
| CPU time | 143.53 seconds |
| Started | Feb 18 12:48:26 PM PST 24 |
| Finished | Feb 18 12:50:52 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-7436b672-5ebf-4455-9257-e3f0cb7c7acb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=938889098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.938889098 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3727220621 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 94217029760 ps |
| CPU time | 237.75 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:54:17 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-ad0bddbf-b684-4be5-b2a1-fad0b3688384 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3727220621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3727220621 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2873159602 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7690585715 ps |
| CPU time | 107.45 seconds |
| Started | Feb 18 12:51:01 PM PST 24 |
| Finished | Feb 18 12:52:50 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-bbb9ea02-cdb6-4c36-80f6-b598583aaf3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2873159602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2873159602 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1728827777 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 86382106323 ps |
| CPU time | 223.07 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:52:00 PM PST 24 |
| Peak memory | 203580 kb |
| Host | smart-f880845d-4f3e-4104-ae9a-8376fcbe191c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1728827777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1728827777 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.497357685 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2358933809 ps |
| CPU time | 10.16 seconds |
| Started | Feb 18 12:48:56 PM PST 24 |
| Finished | Feb 18 12:49:10 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-e2e091ab-1e81-44fc-aa49-6e60f9f8b12d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=497357685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.497357685 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3948661624 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28492625377 ps |
| CPU time | 161.75 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:51:34 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-3f784ef6-2b85-4c42-b712-f594aacd68e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3948661624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.3948661624 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.156783391 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 48801972 ps |
| CPU time | 6.39 seconds |
| Started | Feb 18 12:49:34 PM PST 24 |
| Finished | Feb 18 12:49:42 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-8c22e312-42fe-40e4-8065-34f81af2c5d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156783391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.156783391 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.141625860 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 22186264636 ps |
| CPU time | 143.6 seconds |
| Started | Feb 18 12:50:22 PM PST 24 |
| Finished | Feb 18 12:52:47 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-dd181401-2965-4d7f-bb3c-78ba15bff4d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=141625860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.141625860 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.190838664 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 36101504490 ps |
| CPU time | 161.74 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:52:57 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-4d02d817-220f-429c-bbd7-829c10a634a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=190838664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.190838664 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.440527348 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 38743289912 ps |
| CPU time | 304.03 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:55:58 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-778e2b65-0dae-42b9-92e6-85d6250056fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=440527348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.440527348 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.841243143 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 527584812 ps |
| CPU time | 70.14 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:26 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-820b97d1-ae5b-4ac4-b365-67da5c912a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841243143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.841243143 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1600478524 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 435679873 ps |
| CPU time | 94.65 seconds |
| Started | Feb 18 12:49:55 PM PST 24 |
| Finished | Feb 18 12:51:36 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-2b6f7044-8c19-4ac5-8b86-06b098d100b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1600478524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1600478524 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.728448455 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 408251338 ps |
| CPU time | 60.16 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:51:16 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-d8acfa9e-dc76-4559-abac-bd0eeb5b18da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=728448455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.728448455 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3959315871 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1141099244 ps |
| CPU time | 157.95 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:52:57 PM PST 24 |
| Peak memory | 209472 kb |
| Host | smart-24c898e0-7f24-4f81-a245-4eeb9c29920c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3959315871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3959315871 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2159683380 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1264660857 ps |
| CPU time | 9.77 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-cae61cf2-62f8-48a3-b075-caff8338f0eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2159683380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2159683380 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3568544190 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 22084361249 ps |
| CPU time | 123.99 seconds |
| Started | Feb 18 12:49:41 PM PST 24 |
| Finished | Feb 18 12:51:46 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-fe83b621-4b9f-416c-b1ac-0cfdbee43e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3568544190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3568544190 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2544670139 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 50996768051 ps |
| CPU time | 106.66 seconds |
| Started | Feb 18 12:50:33 PM PST 24 |
| Finished | Feb 18 12:52:21 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-a85bc5da-198b-4a7d-b638-912e81eac836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544670139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2544670139 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2089802177 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 50713994059 ps |
| CPU time | 297.01 seconds |
| Started | Feb 18 12:47:56 PM PST 24 |
| Finished | Feb 18 12:53:04 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-2ca53c29-3f27-46f8-81a2-a99b4943636d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2089802177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2089802177 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2984304792 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5194915624 ps |
| CPU time | 99.72 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:51:02 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-652d0d1f-3695-4ca8-a5b9-4089c15f7d5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2984304792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2984304792 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.4196277404 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 11368956776 ps |
| CPU time | 69.04 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-e3183e4d-4f21-4112-a27d-cdd998d278b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4196277404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4196277404 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.701348593 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 485712706 ps |
| CPU time | 39.89 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-ee5bec4f-356f-43b9-a8fc-e9914fc938e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=701348593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.701348593 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1903742133 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 12480043130 ps |
| CPU time | 134.7 seconds |
| Started | Feb 18 12:48:25 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-b14e0507-bf84-4e95-95bc-e0b74c6911c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1903742133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1903742133 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.92585738 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2106973860 ps |
| CPU time | 5.48 seconds |
| Started | Feb 18 12:48:46 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-96e11288-ac1e-4d51-89c0-014d59b48f23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92585738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.92585738 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2702047203 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1104802634 ps |
| CPU time | 20.91 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:49:05 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-351b4be7-1adc-4c2b-9cc6-e8192265c19d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702047203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2702047203 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1630801977 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2678809289 ps |
| CPU time | 44.43 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-97ef05d5-e47b-4447-a482-74082e8094c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1630801977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1630801977 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.2668331122 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 478276537 ps |
| CPU time | 6.26 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:21 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-2eab059e-7b67-45ea-ad53-7dd7e313d5cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2668331122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2668331122 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2346559373 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1674634420 ps |
| CPU time | 18.11 seconds |
| Started | Feb 18 12:47:56 PM PST 24 |
| Finished | Feb 18 12:48:25 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-b2d017cd-ee9c-472f-afa8-275b5e120dc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2346559373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2346559373 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.87025919 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 474875082 ps |
| CPU time | 7.61 seconds |
| Started | Feb 18 12:48:03 PM PST 24 |
| Finished | Feb 18 12:48:22 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-f5d936b6-9e6b-4583-8bc4-d2efb7a16208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87025919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.87025919 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2556998126 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2301945536 ps |
| CPU time | 14.64 seconds |
| Started | Feb 18 12:48:00 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-79c1e962-6fde-4238-88fb-ddb4cbf2ff6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2556998126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2556998126 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.3798859224 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 35463853 ps |
| CPU time | 3.9 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:13 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-d711e37d-e5ae-4e3a-8a84-0e3ace25f973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3798859224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3798859224 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.226363856 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 55386148108 ps |
| CPU time | 133.83 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-10b13e00-5446-486e-b3ed-7cccb87702b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=226363856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.226363856 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1986706460 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 43882004842 ps |
| CPU time | 105.28 seconds |
| Started | Feb 18 12:47:52 PM PST 24 |
| Finished | Feb 18 12:49:49 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-849628f7-35d4-4b4c-8a0a-ad58c7e04914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1986706460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1986706460 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2197361893 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 25041721 ps |
| CPU time | 3.59 seconds |
| Started | Feb 18 12:47:52 PM PST 24 |
| Finished | Feb 18 12:48:07 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-fa004d0c-5384-4af5-a29e-e19f8fc398be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197361893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2197361893 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.4174381712 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 34344647 ps |
| CPU time | 3.17 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:12 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-6802f386-8ae9-4aac-bb46-c71ae64c11fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4174381712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4174381712 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.4065139164 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 137989596 ps |
| CPU time | 1.45 seconds |
| Started | Feb 18 12:47:54 PM PST 24 |
| Finished | Feb 18 12:48:07 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-8d94cc6a-f145-4fb3-af42-de03dc70ecdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4065139164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4065139164 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3758481852 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4840966160 ps |
| CPU time | 11.93 seconds |
| Started | Feb 18 12:47:53 PM PST 24 |
| Finished | Feb 18 12:48:17 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-4d02a388-6273-4359-b9dc-fc08f865e13e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758481852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3758481852 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1710672846 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1624475099 ps |
| CPU time | 8.4 seconds |
| Started | Feb 18 12:47:52 PM PST 24 |
| Finished | Feb 18 12:48:12 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-83938709-7c29-4230-ae14-0822c2ca33c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1710672846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1710672846 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3986101573 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15352904 ps |
| CPU time | 1.22 seconds |
| Started | Feb 18 12:47:55 PM PST 24 |
| Finished | Feb 18 12:48:08 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-6c6ef412-31b2-46f3-a5e8-c0916b000fff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986101573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3986101573 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2846953212 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6594342681 ps |
| CPU time | 89.34 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:49:39 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-8f0b579e-c95f-4d4b-8973-7dd20012310b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846953212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2846953212 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3293240615 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 488007916 ps |
| CPU time | 21.79 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-8a9a70f8-8469-482d-a321-3db07f96f7be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3293240615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3293240615 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.874397630 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5685675064 ps |
| CPU time | 71.66 seconds |
| Started | Feb 18 12:47:55 PM PST 24 |
| Finished | Feb 18 12:49:18 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-a2b65bd3-18ee-4037-b3c5-81d8d5e32015 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874397630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.874397630 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.618243571 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 142166155 ps |
| CPU time | 10.3 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:20 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-71d7728d-392d-4140-a71d-88d33623e2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=618243571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.618243571 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1075992512 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 74346867 ps |
| CPU time | 2.52 seconds |
| Started | Feb 18 12:47:59 PM PST 24 |
| Finished | Feb 18 12:48:13 PM PST 24 |
| Peak memory | 202020 kb |
| Host | smart-7b421224-0cbc-40c9-8d26-333771a39f21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075992512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1075992512 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.550286703 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 616059784 ps |
| CPU time | 10.22 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-b2eeb4c3-3757-4dac-a603-d9f797adc561 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=550286703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.550286703 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.308185103 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10879224854 ps |
| CPU time | 82.99 seconds |
| Started | Feb 18 12:48:02 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-5ce9857f-5023-4db6-a34e-820002ef8910 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=308185103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.308185103 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1303584947 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 518325370 ps |
| CPU time | 8.81 seconds |
| Started | Feb 18 12:48:00 PM PST 24 |
| Finished | Feb 18 12:48:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-466c3f10-5d21-4ac1-af8d-bf3aebbf8948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1303584947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1303584947 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2366774589 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 175535259 ps |
| CPU time | 3.91 seconds |
| Started | Feb 18 12:48:07 PM PST 24 |
| Finished | Feb 18 12:48:22 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-37bc92a9-e703-4f12-90be-370ecc6dc7eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2366774589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2366774589 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2901802038 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 67835267 ps |
| CPU time | 6.6 seconds |
| Started | Feb 18 12:48:00 PM PST 24 |
| Finished | Feb 18 12:48:18 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-37a2bd17-4b50-44bc-9572-fd4d142f06b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2901802038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2901802038 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1494324956 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 28662000145 ps |
| CPU time | 125.5 seconds |
| Started | Feb 18 12:47:55 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-d0f27b0f-46d6-41ae-a9f1-d36d7425a05d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494324956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1494324956 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.910360917 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10453709475 ps |
| CPU time | 23.53 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:34 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-beb84b8e-87af-4f5c-b398-77969c87fa87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=910360917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.910360917 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3900475157 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 83832108 ps |
| CPU time | 7.49 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:16 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-f185f5bf-4672-4542-a45d-079ad5c9e833 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900475157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3900475157 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.1310390521 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 859477490 ps |
| CPU time | 12.53 seconds |
| Started | Feb 18 12:47:55 PM PST 24 |
| Finished | Feb 18 12:48:19 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-802559a3-55f7-4b15-a506-d95f33374d81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310390521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1310390521 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1084416488 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 10096068 ps |
| CPU time | 1.04 seconds |
| Started | Feb 18 12:47:56 PM PST 24 |
| Finished | Feb 18 12:48:08 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-1aee66f6-be0f-4619-8c2e-44e986e88525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084416488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1084416488 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.268374251 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 7992036301 ps |
| CPU time | 7.57 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:18 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-01750323-0a6a-4727-9314-5cd85900a4f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=268374251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.268374251 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2427320771 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4752056351 ps |
| CPU time | 8.9 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:17 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-6e41b70c-ec50-4696-a4aa-175e8c5e5994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2427320771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2427320771 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4020452485 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 17975424 ps |
| CPU time | 1.28 seconds |
| Started | Feb 18 12:47:59 PM PST 24 |
| Finished | Feb 18 12:48:12 PM PST 24 |
| Peak memory | 201956 kb |
| Host | smart-a6466ff3-9f4b-412b-beb1-7c7cc1303799 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020452485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4020452485 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3545360100 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 411455708 ps |
| CPU time | 7.02 seconds |
| Started | Feb 18 12:48:02 PM PST 24 |
| Finished | Feb 18 12:48:20 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-0c869cf7-27b1-47bb-9e24-3c977f0fd983 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3545360100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3545360100 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.777659262 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1795054760 ps |
| CPU time | 12.16 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:21 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-e6ae0533-1bd0-41a9-b768-70db6b7b5594 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=777659262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.777659262 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1728077421 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 7040288876 ps |
| CPU time | 179.84 seconds |
| Started | Feb 18 12:48:01 PM PST 24 |
| Finished | Feb 18 12:51:13 PM PST 24 |
| Peak memory | 206240 kb |
| Host | smart-6db04bfb-d52e-4fb0-8c21-143c7782855f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1728077421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1728077421 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2913452459 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 774648974 ps |
| CPU time | 49.87 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:49:05 PM PST 24 |
| Peak memory | 203316 kb |
| Host | smart-46c1dd52-ad43-49ef-a024-6bd46e00bdeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913452459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.2913452459 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3765641450 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 99308347 ps |
| CPU time | 2.05 seconds |
| Started | Feb 18 12:48:02 PM PST 24 |
| Finished | Feb 18 12:48:15 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-3aab1911-7cd1-40cd-a89c-c2a21397e6b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3765641450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3765641450 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1379569704 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1392294162 ps |
| CPU time | 14.08 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-68536a0e-c5e5-4ca7-b881-aec57b5ce493 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379569704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1379569704 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1484607270 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 18918277138 ps |
| CPU time | 34.49 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:49:12 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-d785c9cd-ca37-48b0-bd3d-d98070a7f194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1484607270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1484607270 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3213451405 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 193831809 ps |
| CPU time | 2.65 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:37 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-13a2c5e0-d678-4747-8e55-d0efd10c39fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3213451405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3213451405 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2635614182 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 135216094 ps |
| CPU time | 7.89 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:42 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-51dcfff2-7c6d-4581-a0bd-f1b87bcd3b65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2635614182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2635614182 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.2241543080 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 672363572 ps |
| CPU time | 8.79 seconds |
| Started | Feb 18 12:48:40 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-04c24b14-f460-4115-9c1e-dce1bab58d98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2241543080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2241543080 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3323193339 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 15904062774 ps |
| CPU time | 61.52 seconds |
| Started | Feb 18 12:48:40 PM PST 24 |
| Finished | Feb 18 12:49:43 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-767b8a9d-cdbc-4dc4-9859-9bcdd8318522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323193339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3323193339 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2850505705 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 26113406845 ps |
| CPU time | 87.68 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-f1d3e5d2-320c-4b62-929c-7a3c6a5108ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2850505705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2850505705 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3849069307 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 59260667 ps |
| CPU time | 6 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:48:44 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-5c92adac-b266-4f82-96cb-390dcf1574bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849069307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3849069307 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2505147461 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 80083270 ps |
| CPU time | 1.73 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:46 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-d5995cd3-a1a3-40bc-a2c6-2794716f387d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2505147461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2505147461 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.1583608205 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 181610080 ps |
| CPU time | 1.7 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:40 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-c4dfb0bd-bced-417b-b0ac-caff8526fbff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583608205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1583608205 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.4031323436 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 8716254340 ps |
| CPU time | 9.91 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:44 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-e97fdda4-5c2b-44ee-9829-a356949509c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031323436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.4031323436 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3585509859 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1063223697 ps |
| CPU time | 5.16 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:40 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-91c06052-f4ce-4542-98b1-7e0a8a5597e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3585509859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3585509859 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.4015179756 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 8582220 ps |
| CPU time | 1.13 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:36 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-1229d791-bda7-4cdd-a809-2c4d80d0bd8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015179756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.4015179756 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3530724637 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 510981548 ps |
| CPU time | 31.1 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:49:09 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-b2d3aee9-271e-4f6f-a87e-e70dd62d5ef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3530724637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3530724637 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3203991297 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1206840569 ps |
| CPU time | 25.72 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:49:08 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-713eb403-35ce-432c-9a64-edd5eabc72bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203991297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3203991297 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1827304233 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 7687280 ps |
| CPU time | 1.27 seconds |
| Started | Feb 18 12:48:38 PM PST 24 |
| Finished | Feb 18 12:48:41 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-10efa553-644c-4a60-9bc7-38ba197f71c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1827304233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1827304233 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1445842513 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1443987564 ps |
| CPU time | 133.81 seconds |
| Started | Feb 18 12:48:44 PM PST 24 |
| Finished | Feb 18 12:51:00 PM PST 24 |
| Peak memory | 208036 kb |
| Host | smart-f1d72569-5068-4b4d-95a7-c3db99c9a114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1445842513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1445842513 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.24677014 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 67415999 ps |
| CPU time | 6.4 seconds |
| Started | Feb 18 12:48:34 PM PST 24 |
| Finished | Feb 18 12:48:42 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-422be180-996d-4681-af0a-ce8b3e56cc5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24677014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.24677014 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1067774543 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 148713862 ps |
| CPU time | 11.93 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-cba6c1a7-c364-4428-be62-aa2e2188bb92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1067774543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1067774543 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3079207892 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 4774499604 ps |
| CPU time | 18.48 seconds |
| Started | Feb 18 12:48:35 PM PST 24 |
| Finished | Feb 18 12:48:56 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-30ba0c3c-f238-4eba-8fca-a00907963b57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3079207892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3079207892 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3739294056 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1474148752 ps |
| CPU time | 7.61 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-347b1185-b8f8-474a-8333-b23c54658f67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739294056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3739294056 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2093343941 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1547334999 ps |
| CPU time | 8.42 seconds |
| Started | Feb 18 12:48:38 PM PST 24 |
| Finished | Feb 18 12:48:48 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-c6b2e095-078d-43e6-88c3-989ae8e5dfcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093343941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2093343941 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1106466849 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 676447983 ps |
| CPU time | 9.32 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-a8f6a0a8-8beb-42fb-b830-aebd228c6734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1106466849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1106466849 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1741759312 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 21349604984 ps |
| CPU time | 46.44 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-83eab3e4-a127-4ea1-aa93-8e9cb546c6fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741759312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1741759312 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2219606306 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 86400620430 ps |
| CPU time | 175.38 seconds |
| Started | Feb 18 12:48:38 PM PST 24 |
| Finished | Feb 18 12:51:35 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-de0ae0af-94ce-4749-b7a8-ccf58b77aa47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2219606306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2219606306 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2699426087 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 54951689 ps |
| CPU time | 8.51 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-b0b7beec-8ef4-4ebc-a2c9-73f69f15c6ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699426087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2699426087 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2832984317 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 94409158 ps |
| CPU time | 6.79 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-193e386e-d635-4a89-b38a-b323662d6b5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2832984317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2832984317 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.4028179747 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 91928813 ps |
| CPU time | 1.3 seconds |
| Started | Feb 18 12:48:33 PM PST 24 |
| Finished | Feb 18 12:48:36 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-ccb52812-d4cb-46d2-8536-b12dfb83c19d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4028179747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4028179747 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4166615732 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2265552993 ps |
| CPU time | 9.8 seconds |
| Started | Feb 18 12:48:31 PM PST 24 |
| Finished | Feb 18 12:48:43 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-6b01fa1c-cbb3-4293-9d0c-40108145b61a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166615732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4166615732 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.497068294 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2802626185 ps |
| CPU time | 8.62 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:51 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-e33dcff6-6776-4ef8-a8ae-c42f8c26ca6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=497068294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.497068294 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2381718196 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 8962532 ps |
| CPU time | 1.07 seconds |
| Started | Feb 18 12:48:35 PM PST 24 |
| Finished | Feb 18 12:48:39 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-c6ab20d5-caac-4508-a2bf-390365739646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381718196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2381718196 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.624281279 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 756654400 ps |
| CPU time | 10.46 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-aaf9bf95-35f9-4ec0-8a6d-a00bae9c1a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=624281279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.624281279 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3018652793 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 935261323 ps |
| CPU time | 120.8 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 207416 kb |
| Host | smart-f2109ca3-1095-4c01-8511-59d0103ffd0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018652793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3018652793 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1149862808 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 81168313 ps |
| CPU time | 8.19 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:47 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-5eccf8c1-9ff3-42fa-bffa-978fea35df7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149862808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1149862808 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3528133330 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 309446939 ps |
| CPU time | 3.4 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:47 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-aae306ae-3f81-440a-895b-62b0141dea51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3528133330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3528133330 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1263889634 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 51984467 ps |
| CPU time | 8.94 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-207baee3-eb00-4987-9024-d70d873de26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1263889634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1263889634 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.92783239 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 113501350790 ps |
| CPU time | 136.37 seconds |
| Started | Feb 18 12:48:39 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-3f58d428-05da-4155-8445-281f48ee693b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=92783239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow _rsp.92783239 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3387317009 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 144911976 ps |
| CPU time | 5.33 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:48:59 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-a79c52e1-6125-495a-9374-5a67c21cc979 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3387317009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3387317009 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.4255822050 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 21270784 ps |
| CPU time | 1.99 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:41 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-05a5cccf-521a-42a3-84de-7ad1fc55b888 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4255822050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4255822050 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2150016716 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 851692481 ps |
| CPU time | 7.71 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:02 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-470ceb70-b519-4ab7-b297-d9bf0f1aaaa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2150016716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2150016716 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.973270074 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 35010472689 ps |
| CPU time | 152.72 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:51:11 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-ce4c516f-183a-417b-826b-a3092c8ebdb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=973270074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.973270074 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1210599329 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 52654712005 ps |
| CPU time | 183.73 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:51:49 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-2cbbcc3a-70dc-4487-8605-c44a948e94e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1210599329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1210599329 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.418512898 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 90410669 ps |
| CPU time | 9.9 seconds |
| Started | Feb 18 12:48:44 PM PST 24 |
| Finished | Feb 18 12:48:56 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-a54c57c7-38a8-4113-a8cb-9a1c43f7adff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418512898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.418512898 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.3498568809 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 69600307 ps |
| CPU time | 5.97 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:00 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-7c955e8b-ff95-4fd3-8120-02b0d65eca9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498568809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3498568809 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.4090317968 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 49350825 ps |
| CPU time | 1.66 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:41 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-99ecf7bb-2096-4d60-a967-5a24bb8fe964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090317968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4090317968 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3642900270 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3038024181 ps |
| CPU time | 8.94 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:52 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-bdd3146a-21e5-4c9e-b3d3-203320c9237b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642900270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3642900270 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1504504109 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3570453104 ps |
| CPU time | 9.43 seconds |
| Started | Feb 18 12:48:40 PM PST 24 |
| Finished | Feb 18 12:48:51 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-437229e4-2d12-4642-a86f-7526ca73d5d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1504504109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1504504109 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.992187449 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 10162368 ps |
| CPU time | 1.11 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:44 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-e952ec72-44cb-43a8-9b39-64ac740b227a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992187449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.992187449 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1643326145 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 947035125 ps |
| CPU time | 37.55 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-491d84f8-d9d7-49ce-b5a8-d99defd2950c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1643326145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1643326145 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.160284424 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 284769753 ps |
| CPU time | 20.73 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:49:06 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-1364a9e6-1aaa-4718-a8ec-b8d6c287bda4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=160284424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand _reset.160284424 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.817791279 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 10077729561 ps |
| CPU time | 174.57 seconds |
| Started | Feb 18 12:48:39 PM PST 24 |
| Finished | Feb 18 12:51:35 PM PST 24 |
| Peak memory | 206124 kb |
| Host | smart-81cdb3a6-122e-4a13-9e13-fa76e8d2562c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=817791279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.817791279 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2816705593 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 81065930 ps |
| CPU time | 4.65 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:48:58 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-5ff80288-7de1-4b01-a454-f64da888237f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2816705593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2816705593 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1544020574 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 670724637 ps |
| CPU time | 6.4 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:51 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-61173e2a-3ccf-427f-9aa5-b2ebbd0992e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1544020574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1544020574 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.349200355 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 7835444623 ps |
| CPU time | 34.2 seconds |
| Started | Feb 18 12:48:56 PM PST 24 |
| Finished | Feb 18 12:49:34 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-3674e496-7455-4bf1-adc2-f359ac6fcfb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=349200355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.349200355 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1847506378 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 677637823 ps |
| CPU time | 2.14 seconds |
| Started | Feb 18 12:48:46 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-94daf925-6723-46cc-b641-23fa5903fa6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847506378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1847506378 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.24329759 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 97540872 ps |
| CPU time | 2.03 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:48:54 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-d95510ca-c5e8-4ece-b038-5dcfe9b7b4a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24329759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.24329759 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.606881428 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 702912610 ps |
| CPU time | 8.6 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:54 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-071ff50a-5363-41d0-ab42-33f705a8f72a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=606881428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.606881428 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2754308258 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 23295933736 ps |
| CPU time | 61.9 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:56 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-fb7c2b0a-e022-4fb7-80bc-bf6315d779e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754308258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2754308258 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.923943180 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 29862036044 ps |
| CPU time | 113.05 seconds |
| Started | Feb 18 12:48:39 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-764ae4dd-3bac-4605-afb0-07d0f8d2092a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=923943180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.923943180 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.944082044 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 49335138 ps |
| CPU time | 6.47 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:52 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-44612bc6-3d58-40e9-b37e-faedd14713de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944082044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.944082044 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.504313073 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 61949719 ps |
| CPU time | 6.5 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:00 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-5b11c1ec-b557-46fe-b631-3f8ca3022f9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=504313073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.504313073 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.232621265 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 10726729 ps |
| CPU time | 1.05 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:46 PM PST 24 |
| Peak memory | 201760 kb |
| Host | smart-d518433d-24c9-4a55-81b4-a853f7ea3b1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=232621265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.232621265 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.202575649 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 6174622987 ps |
| CPU time | 10.38 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:55 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-7c852743-1e6e-4f32-b0c1-9a25e9ba761a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=202575649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.202575649 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4237127370 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 973601250 ps |
| CPU time | 5.01 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-e1f20c04-f354-4cb4-ac5c-2f2ec54bcb5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4237127370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4237127370 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3527859994 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 16905614 ps |
| CPU time | 1.01 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-78211ac4-90ef-4801-b325-9c89ee7897c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527859994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3527859994 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1382346950 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 4277038746 ps |
| CPU time | 24.96 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:49:18 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-7ef77af1-d834-4b26-a94b-94264fe7f013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382346950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1382346950 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.992123739 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3005154767 ps |
| CPU time | 9.25 seconds |
| Started | Feb 18 12:48:56 PM PST 24 |
| Finished | Feb 18 12:49:08 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-ad7726e6-ebc6-4966-a789-2da9ad406296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992123739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.992123739 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3534705113 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 919085986 ps |
| CPU time | 105.91 seconds |
| Started | Feb 18 12:48:49 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 207524 kb |
| Host | smart-60b05c64-b199-4271-b35d-7c1c58f643c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534705113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3534705113 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2013399919 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 557728156 ps |
| CPU time | 84.55 seconds |
| Started | Feb 18 12:48:47 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-fbc1012e-75ba-4cbd-83f3-ca126c2cb2c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2013399919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.2013399919 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2886578619 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 77884911 ps |
| CPU time | 4.51 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:48:51 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-0768fc1e-51b1-4f63-bb84-f490973cb5c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2886578619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2886578619 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1887510815 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1202919506 ps |
| CPU time | 22.35 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:49:10 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-375e3d18-b29e-47f8-858d-b86361fac9b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887510815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1887510815 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.657389564 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 38949960263 ps |
| CPU time | 188.73 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:52:02 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-2526e9ae-3d74-4653-875a-000ea2357ff6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=657389564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slo w_rsp.657389564 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4003693522 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 565363206 ps |
| CPU time | 8.15 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:07 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-df6d2aaf-6469-47d8-ab0d-5af5293e90cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4003693522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4003693522 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.195600217 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1470370994 ps |
| CPU time | 7.22 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:06 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-197ca634-74c4-4a91-9a5c-6af3b5b8bf11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=195600217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.195600217 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1010491599 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 82564475 ps |
| CPU time | 4.95 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:48:59 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-25a9975a-312d-4235-9878-2265bf30eadd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1010491599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1010491599 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2489645851 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 22945501335 ps |
| CPU time | 91.72 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:50:24 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-600c3c0c-ef60-4d48-9ce7-af4aa995c249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489645851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2489645851 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3835576607 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 66519836861 ps |
| CPU time | 151.86 seconds |
| Started | Feb 18 12:48:46 PM PST 24 |
| Finished | Feb 18 12:51:20 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-82383329-4738-4b54-bec9-235a1d3677b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3835576607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3835576607 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3044616454 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 49253257 ps |
| CPU time | 6.97 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:48:59 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-fd1aceea-dfba-4bbb-b6f3-cde180179cdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044616454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3044616454 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3239024843 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 81575735 ps |
| CPU time | 2.1 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-5c95f4a2-5644-47f9-801f-ffa2bcbb9754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3239024843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3239024843 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.4273088593 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2489251864 ps |
| CPU time | 9.72 seconds |
| Started | Feb 18 12:48:48 PM PST 24 |
| Finished | Feb 18 12:48:59 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-bda3412d-93e5-4d77-a8a2-367f685eaafd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273088593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4273088593 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.112713265 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2096567045 ps |
| CPU time | 10.56 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:48:57 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-f90d783d-91a3-47c8-90ae-c95fab5700b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=112713265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.112713265 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3265447085 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 12716361 ps |
| CPU time | 1.45 seconds |
| Started | Feb 18 12:48:48 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-09069e8d-cfe5-49de-9607-8245d91f15db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265447085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3265447085 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3394554317 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 395029976 ps |
| CPU time | 9.16 seconds |
| Started | Feb 18 12:48:49 PM PST 24 |
| Finished | Feb 18 12:48:59 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-1732107e-d1ee-4683-9a8d-20d8316af820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394554317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3394554317 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1732858767 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3065872675 ps |
| CPU time | 42.66 seconds |
| Started | Feb 18 12:48:49 PM PST 24 |
| Finished | Feb 18 12:49:32 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-46bf0751-176b-4758-b6ae-2528bda62296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732858767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1732858767 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.165970138 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 404276605 ps |
| CPU time | 32.25 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:30 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-c703f37a-dcaf-4b4f-87a9-4e8f910222d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=165970138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.165970138 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1530879781 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6062452905 ps |
| CPU time | 75.13 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:50:02 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-2724254e-1cef-4297-974a-31bf3618af64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1530879781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1530879781 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3490676494 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 121935024 ps |
| CPU time | 9.54 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:48:57 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-590dfe7e-97ae-474b-aff2-bdbedd269741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3490676494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3490676494 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1927897243 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 925250947 ps |
| CPU time | 19.98 seconds |
| Started | Feb 18 12:48:52 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-87071323-6d33-4a43-aa95-09569a9510b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1927897243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1927897243 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3880902970 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 198980079 ps |
| CPU time | 2.63 seconds |
| Started | Feb 18 12:48:58 PM PST 24 |
| Finished | Feb 18 12:49:04 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-313c0b66-b13c-4d4d-9f53-b6b0a4aa8ee5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880902970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3880902970 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.3499705812 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 199673403 ps |
| CPU time | 4.48 seconds |
| Started | Feb 18 12:48:49 PM PST 24 |
| Finished | Feb 18 12:48:54 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-3903a45f-3c68-4648-ab42-e77797a1ce50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499705812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3499705812 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2349019972 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 39828009 ps |
| CPU time | 1.33 seconds |
| Started | Feb 18 12:48:47 PM PST 24 |
| Finished | Feb 18 12:48:50 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-7c85a6dd-1bfb-4abd-b803-0184b60e54ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2349019972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2349019972 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.987134238 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 41408765372 ps |
| CPU time | 110.73 seconds |
| Started | Feb 18 12:48:50 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-768e3732-09b3-46e4-8ea1-81e6eaeaad97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=987134238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.987134238 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.9513121 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4788247998 ps |
| CPU time | 17.46 seconds |
| Started | Feb 18 12:48:44 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-8e95271b-a421-42fb-914e-ceae588d7aa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=9513121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.9513121 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2199996605 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 115418678 ps |
| CPU time | 10.57 seconds |
| Started | Feb 18 12:48:48 PM PST 24 |
| Finished | Feb 18 12:49:00 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-df1ea47d-a5d8-4aa6-96d8-ea822503ef77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199996605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2199996605 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1925061351 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 787372443 ps |
| CPU time | 4.88 seconds |
| Started | Feb 18 12:48:51 PM PST 24 |
| Finished | Feb 18 12:48:58 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-33556367-ab99-481d-b112-c587a7f891be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925061351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1925061351 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.252834785 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 9237161 ps |
| CPU time | 1.08 seconds |
| Started | Feb 18 12:48:46 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-e4764ce6-f68b-49a3-bb16-acd833f3f523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252834785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.252834785 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3252882976 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3886937370 ps |
| CPU time | 12.56 seconds |
| Started | Feb 18 12:48:46 PM PST 24 |
| Finished | Feb 18 12:49:00 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-c2e50d8e-bb1f-4444-af98-20d84e78e030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252882976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3252882976 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.155472772 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 692369658 ps |
| CPU time | 6.14 seconds |
| Started | Feb 18 12:48:45 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-0b350cfe-1083-452a-a690-50fd61846bb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155472772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.155472772 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2901963345 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 9961260 ps |
| CPU time | 1.16 seconds |
| Started | Feb 18 12:48:50 PM PST 24 |
| Finished | Feb 18 12:48:53 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-cf4e0638-d319-456f-a4ba-f61a3b21b942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901963345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2901963345 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.381159062 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5909405 ps |
| CPU time | 0.76 seconds |
| Started | Feb 18 12:48:54 PM PST 24 |
| Finished | Feb 18 12:48:57 PM PST 24 |
| Peak memory | 194208 kb |
| Host | smart-43f41ca1-ef18-40c1-a05c-7e0217712fb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381159062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.381159062 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1590308448 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 13762673857 ps |
| CPU time | 76.71 seconds |
| Started | Feb 18 12:48:59 PM PST 24 |
| Finished | Feb 18 12:50:19 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-eb393330-a21a-4264-ae4f-003a47d8e024 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590308448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1590308448 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2412079325 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 274495251 ps |
| CPU time | 49.14 seconds |
| Started | Feb 18 12:48:54 PM PST 24 |
| Finished | Feb 18 12:49:46 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-76dccc86-a0de-45c3-b0a2-31b234ae861a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2412079325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2412079325 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.963370195 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1374422665 ps |
| CPU time | 30.21 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-a1790f40-2a97-4b2a-a414-d87f3578d082 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963370195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.963370195 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.4212978805 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 132139785 ps |
| CPU time | 6.08 seconds |
| Started | Feb 18 12:48:56 PM PST 24 |
| Finished | Feb 18 12:49:06 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-0ae63659-4cf0-4ff8-bc06-da4d6490361f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4212978805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4212978805 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2525395256 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3594242058 ps |
| CPU time | 18.77 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:32 PM PST 24 |
| Peak memory | 202096 kb |
| Host | smart-03f42182-834d-4247-8a10-0fecf0e3239c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2525395256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2525395256 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3418508249 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 16009667478 ps |
| CPU time | 52.02 seconds |
| Started | Feb 18 12:48:53 PM PST 24 |
| Finished | Feb 18 12:49:47 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-cb9ee4ba-b4d3-45c7-9192-e3cdcdbbfa61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3418508249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3418508249 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3700182106 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 704701586 ps |
| CPU time | 7.73 seconds |
| Started | Feb 18 12:49:02 PM PST 24 |
| Finished | Feb 18 12:49:11 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-26c8cd3e-8c2c-4c28-9526-7867875314de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700182106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3700182106 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.2809883075 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1096166615 ps |
| CPU time | 4.38 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-aac1e163-1f45-4057-a9bd-732b1606d119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809883075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2809883075 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1661147244 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 95145170 ps |
| CPU time | 11.14 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:10 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-584d3e25-d0b9-4dfc-a4fc-055146072378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1661147244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1661147244 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2262354201 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 14656922315 ps |
| CPU time | 59.22 seconds |
| Started | Feb 18 12:49:02 PM PST 24 |
| Finished | Feb 18 12:50:03 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-bf4c9564-b271-41fa-a6fb-dcd173e7b559 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262354201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2262354201 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2042203498 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 6730721793 ps |
| CPU time | 24.07 seconds |
| Started | Feb 18 12:48:58 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-16b30295-9fa5-4495-a872-22eb2363be4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2042203498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2042203498 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2756338910 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 125888666 ps |
| CPU time | 7.04 seconds |
| Started | Feb 18 12:48:54 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-bf3fb11c-9aba-4626-8329-35a37eae1676 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756338910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2756338910 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1455111606 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1007680752 ps |
| CPU time | 8.92 seconds |
| Started | Feb 18 12:49:03 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-e9359a0b-f131-4e95-890e-f9f4eb430b10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1455111606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1455111606 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3027876261 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 81764848 ps |
| CPU time | 1.57 seconds |
| Started | Feb 18 12:49:03 PM PST 24 |
| Finished | Feb 18 12:49:07 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-52848dc7-159c-44c2-9bee-8e0edf37ff05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3027876261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3027876261 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3073218986 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 11887832519 ps |
| CPU time | 11.73 seconds |
| Started | Feb 18 12:49:02 PM PST 24 |
| Finished | Feb 18 12:49:16 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-c6ffd5d4-6c4f-4123-8a35-650e6044cddc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073218986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3073218986 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.35325042 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 6342715845 ps |
| CPU time | 13.85 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:49:11 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-fc375b2d-7db9-4b3c-9745-b644a5f03d5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=35325042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.35325042 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1929091317 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 12882238 ps |
| CPU time | 1.22 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:49:02 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-3d1ededd-6ed0-44d8-bf97-83e80783b401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929091317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1929091317 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3754178152 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 220918115 ps |
| CPU time | 12.05 seconds |
| Started | Feb 18 12:48:58 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-71d70dde-833f-4f1c-b774-9154786b6f86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754178152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3754178152 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1884338256 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 362905153 ps |
| CPU time | 38.45 seconds |
| Started | Feb 18 12:48:54 PM PST 24 |
| Finished | Feb 18 12:49:35 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-fd1037da-669f-4e8c-b606-1e28550c75e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884338256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1884338256 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1253039749 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 7523281943 ps |
| CPU time | 80.92 seconds |
| Started | Feb 18 12:49:00 PM PST 24 |
| Finished | Feb 18 12:50:23 PM PST 24 |
| Peak memory | 206076 kb |
| Host | smart-943aaeb5-acda-4522-a1bc-9b062056cb32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1253039749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.1253039749 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.41276087 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1284134263 ps |
| CPU time | 109.44 seconds |
| Started | Feb 18 12:48:59 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 206500 kb |
| Host | smart-f29f6c03-c85e-44c3-8fe6-cd292ce4ca03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41276087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rese t_error.41276087 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1956323005 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 46889262 ps |
| CPU time | 1.31 seconds |
| Started | Feb 18 12:48:58 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-4af389b3-e8ee-488d-9918-a3b0ece7aa67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956323005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1956323005 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2055572487 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 95979748 ps |
| CPU time | 9.04 seconds |
| Started | Feb 18 12:48:59 PM PST 24 |
| Finished | Feb 18 12:49:11 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-b4f657d1-40f4-4558-b212-8e5868d3d9eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2055572487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2055572487 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3868386925 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2713634079 ps |
| CPU time | 16.44 seconds |
| Started | Feb 18 12:48:58 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-61383ed4-b57c-43fd-9318-ce915713103e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3868386925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3868386925 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2991182461 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 37488533 ps |
| CPU time | 2.48 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-2e58b995-f546-480b-8788-3c159b8e6863 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991182461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2991182461 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2343411606 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1801875465 ps |
| CPU time | 14.18 seconds |
| Started | Feb 18 12:48:59 PM PST 24 |
| Finished | Feb 18 12:49:16 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-7446069d-2901-4f95-8bfe-36e09ef6d105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2343411606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2343411606 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.372757857 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 284774726 ps |
| CPU time | 5.04 seconds |
| Started | Feb 18 12:49:00 PM PST 24 |
| Finished | Feb 18 12:49:07 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-de8fdb2f-f92b-4eb6-a683-de19bb0de1de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=372757857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.372757857 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.528012724 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 37219532669 ps |
| CPU time | 146.06 seconds |
| Started | Feb 18 12:48:55 PM PST 24 |
| Finished | Feb 18 12:51:24 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-9703ed2d-9694-428e-ab08-03ec989c5e97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=528012724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.528012724 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3284289756 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 29502724130 ps |
| CPU time | 109.72 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-7dd2beaa-b39b-4aed-bb6e-45d365bac08f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3284289756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3284289756 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2415500909 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 133852239 ps |
| CPU time | 7.7 seconds |
| Started | Feb 18 12:48:54 PM PST 24 |
| Finished | Feb 18 12:49:05 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-236e12b2-d6fb-456e-9e3d-66ebb2ae0aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415500909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2415500909 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1322837861 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 461273969 ps |
| CPU time | 6.35 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:49:07 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-ee8a6ffe-974b-4fb5-a55b-9d31d5fcf91a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322837861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1322837861 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.788350001 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 90528548 ps |
| CPU time | 1.79 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:49:02 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-168bd551-e62b-4de9-a937-2566a64a5518 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788350001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.788350001 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3578805886 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 978814529 ps |
| CPU time | 5.17 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:49:06 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-9d9d4bcc-fabc-4c5f-b417-451541094aca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3578805886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3578805886 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.872352771 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 27465635 ps |
| CPU time | 1.18 seconds |
| Started | Feb 18 12:49:00 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-10ac2ae1-2bb2-44b8-985b-e32dcbf0e660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872352771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.872352771 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3118936783 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 458034436 ps |
| CPU time | 8.36 seconds |
| Started | Feb 18 12:48:56 PM PST 24 |
| Finished | Feb 18 12:49:08 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-0541ed5e-19ef-4008-ba14-14cadda8d231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118936783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3118936783 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3440590329 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 12061462390 ps |
| CPU time | 52.7 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:49:53 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-59278ec9-66a8-4238-9cff-7c566d8c2118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440590329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3440590329 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2178132799 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 148060343 ps |
| CPU time | 25.42 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:39 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-84153653-52f1-4c4c-9e34-ad4817f6ca83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2178132799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.2178132799 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3263993465 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2392747058 ps |
| CPU time | 101.55 seconds |
| Started | Feb 18 12:48:57 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-e18bfbc8-a870-419e-b332-6c36bc3e23fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3263993465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3263993465 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3672611348 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1735923238 ps |
| CPU time | 9.43 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-e16b838a-6d34-4bb0-9270-969c06d07dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3672611348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3672611348 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3008654987 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 32299888 ps |
| CPU time | 6.04 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-d421a51f-0367-4a3a-be14-83b51adefe01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008654987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3008654987 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4237120116 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 24349367192 ps |
| CPU time | 106.82 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-666a9a61-ffc8-4020-a372-15f620550777 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4237120116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.4237120116 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1916801735 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 82989846 ps |
| CPU time | 7.25 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:22 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-f2acfea2-ed7b-42fc-a77c-2e43469571cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1916801735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1916801735 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1131916019 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 167570775 ps |
| CPU time | 2.87 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:15 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-56f4c0d4-0693-42b9-9fc1-ac8250513faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1131916019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1131916019 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1620744310 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3180729136 ps |
| CPU time | 7.96 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-c62fb3b1-ddcb-419e-867b-c2eedc67f88c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620744310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1620744310 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1380667167 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 110543120984 ps |
| CPU time | 71.12 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:50:24 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-0a037564-1b59-403d-b038-7a87b95da851 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380667167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1380667167 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2991535434 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 44021778389 ps |
| CPU time | 74.52 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:50:24 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-321f4aba-7fe8-4637-b69b-bd874841e22f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2991535434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2991535434 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3834701786 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 50318257 ps |
| CPU time | 5.26 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:16 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-f18bc4cc-dd52-4b1b-8911-23b05c3cf342 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834701786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3834701786 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.2241193511 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9816295 ps |
| CPU time | 1.15 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:11 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-9da681bc-c760-4881-9cec-c3a7ea9b0042 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2241193511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2241193511 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.1190264027 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 12299442 ps |
| CPU time | 1 seconds |
| Started | Feb 18 12:48:59 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-62e8f894-ebeb-4c00-9a2e-2ce7ca62d28c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1190264027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1190264027 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1239289558 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2144643465 ps |
| CPU time | 7.4 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-03fbf27d-2427-4db2-b4e1-b3d4cdba9521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239289558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1239289558 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.451272179 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1103337286 ps |
| CPU time | 6.98 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-f1f79c15-5425-43e0-baeb-334c602384d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=451272179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.451272179 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3626032689 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 12968685 ps |
| CPU time | 1.35 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-affd0f85-8d31-4519-835f-9de93635c64b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626032689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3626032689 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2000174443 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 10588464558 ps |
| CPU time | 61.1 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-a7896f26-2c53-4844-9a64-5107bec83156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000174443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2000174443 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2358795855 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 594281072 ps |
| CPU time | 39.92 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:57 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-5b4464f0-96f2-474e-b391-a90f5b85722e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2358795855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2358795855 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3795084734 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1871797330 ps |
| CPU time | 109.82 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:51:01 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-6bd13a8a-84c5-42ca-8ee8-d50c85f9f285 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3795084734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3795084734 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1262910831 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 143051673 ps |
| CPU time | 9.02 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-41915773-4362-41bf-8beb-febbdfe99063 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262910831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1262910831 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3698200801 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 222591204 ps |
| CPU time | 6.08 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-f9289e7d-f188-4af1-8a3c-bded2dba80a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3698200801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3698200801 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1732538190 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 77624096 ps |
| CPU time | 1.87 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-53383c36-6366-4dfb-9d39-cd7d1f4962db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732538190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1732538190 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3974909498 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 55676396150 ps |
| CPU time | 225.53 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:52:57 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-c1063cee-3ecd-41be-81bb-c5649e5bb073 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3974909498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3974909498 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3902815702 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 245002863 ps |
| CPU time | 3.09 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 201864 kb |
| Host | smart-04c46550-4607-49ba-bd87-047987d830a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3902815702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3902815702 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.4001734065 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 128048526 ps |
| CPU time | 2.21 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-6c011a23-a62a-49f9-8022-8da302c5a26a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4001734065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.4001734065 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.1773458208 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 85294446 ps |
| CPU time | 10.19 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-aea81a18-995b-419f-a76d-60b6f4d1099c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773458208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1773458208 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1802742907 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 31763766616 ps |
| CPU time | 141.87 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:51:29 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-41615158-bd67-4b68-ab2c-2c427be05acf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802742907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1802742907 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1614445094 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 21870801362 ps |
| CPU time | 148.81 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:51:41 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-8f798ae4-465f-4e4b-9dc8-0279fe004174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1614445094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1614445094 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2584589486 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 24784820 ps |
| CPU time | 2.36 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-3d71c35f-47ad-4ed5-9012-f492597305e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584589486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2584589486 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.2546429413 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 12559446 ps |
| CPU time | 1.12 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:16 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-5bce63d5-8025-4f2f-8195-f2cf431efc9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546429413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2546429413 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.586081939 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 62855961 ps |
| CPU time | 1.49 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-56cd2df9-c9e6-4f1a-82c5-5f17b4133133 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=586081939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.586081939 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2131140227 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1452751733 ps |
| CPU time | 6.75 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-dc9bcd53-65db-413a-8478-ea92e70e0e5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131140227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2131140227 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1345622695 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1119985981 ps |
| CPU time | 4.96 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202080 kb |
| Host | smart-8865b0e1-a399-4f37-a19d-c105144b0029 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1345622695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1345622695 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3221738824 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 19421856 ps |
| CPU time | 1.14 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:49:09 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-ff94c3be-f157-43ff-bd0f-5d0cc0ef020a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221738824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3221738824 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.2389881335 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 519941079 ps |
| CPU time | 58.97 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:50:11 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-398e1c9a-db67-48ed-a536-219f3e0d908a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2389881335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2389881335 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1967553167 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 12307063160 ps |
| CPU time | 67.11 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:50:24 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-4fc38817-94ad-4299-b6c7-d7829cc99da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1967553167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1967553167 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2551345826 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 739841079 ps |
| CPU time | 174.7 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:52:10 PM PST 24 |
| Peak memory | 207356 kb |
| Host | smart-24222add-43a1-46f1-9cbe-0a84f597eb59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2551345826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2551345826 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3595396333 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1131048512 ps |
| CPU time | 6.15 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:49:18 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-e2fee388-266a-4f15-826e-2a4cc37f8e97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3595396333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3595396333 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.27721785 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 236196268 ps |
| CPU time | 1.63 seconds |
| Started | Feb 18 12:47:56 PM PST 24 |
| Finished | Feb 18 12:48:09 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-1b38f3e4-8001-481c-bb13-c965cab1b00b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27721785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.27721785 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1241979937 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 63269446919 ps |
| CPU time | 141.57 seconds |
| Started | Feb 18 12:48:00 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-a91c07c7-0c2d-42f9-aa02-93a80c4306c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1241979937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1241979937 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.12120848 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 928914586 ps |
| CPU time | 7.33 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-52a77776-b8c2-4335-98a4-fb5f6384bdab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=12120848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.12120848 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1080436106 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 352406546 ps |
| CPU time | 7.55 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:15 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-9e28464b-1ef2-44bb-9006-f47c1bd50334 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1080436106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1080436106 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.610881283 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 639604698 ps |
| CPU time | 4.45 seconds |
| Started | Feb 18 12:48:02 PM PST 24 |
| Finished | Feb 18 12:48:18 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-3f3eaa5f-26bd-461f-915f-aeb6233711b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610881283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.610881283 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2034501596 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 68850752222 ps |
| CPU time | 137.64 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-625e826c-125a-4ae1-9a35-b86bddfbcfc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034501596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2034501596 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1454035011 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 45052094432 ps |
| CPU time | 184.6 seconds |
| Started | Feb 18 12:47:59 PM PST 24 |
| Finished | Feb 18 12:51:15 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-a4bbda3c-5c1c-4b8f-be41-ee013eee1201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1454035011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1454035011 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2350195754 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 59471658 ps |
| CPU time | 4.94 seconds |
| Started | Feb 18 12:47:56 PM PST 24 |
| Finished | Feb 18 12:48:12 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-577309a9-7fb1-4f5a-acfd-f7ec695f9eca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350195754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2350195754 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3541240288 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 56979459 ps |
| CPU time | 3.78 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:14 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-c0b15429-6d6c-41ee-a881-e0a64a82aeca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3541240288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3541240288 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.1996247512 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 82047249 ps |
| CPU time | 1.36 seconds |
| Started | Feb 18 12:48:00 PM PST 24 |
| Finished | Feb 18 12:48:13 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-cf309b41-fb32-4be4-8666-ea008c778c47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996247512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1996247512 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1389590681 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6171007726 ps |
| CPU time | 5.87 seconds |
| Started | Feb 18 12:47:57 PM PST 24 |
| Finished | Feb 18 12:48:14 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-a46d9fd7-b268-4b7e-99bf-d75b8e713cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389590681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1389590681 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3146920918 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1856638971 ps |
| CPU time | 14.49 seconds |
| Started | Feb 18 12:48:07 PM PST 24 |
| Finished | Feb 18 12:48:32 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-56826a3d-b78a-4729-997b-efeece6cf3fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3146920918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3146920918 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1863145866 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8671053 ps |
| CPU time | 1.16 seconds |
| Started | Feb 18 12:47:58 PM PST 24 |
| Finished | Feb 18 12:48:11 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-50d68313-7dbc-4856-90fd-e022abbf3218 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863145866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1863145866 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3338501017 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 7773071639 ps |
| CPU time | 83.38 seconds |
| Started | Feb 18 12:48:07 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-9bbaf93d-d3a1-4679-9506-19b98e0072cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3338501017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3338501017 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3094584235 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 20528428 ps |
| CPU time | 1.25 seconds |
| Started | Feb 18 12:48:08 PM PST 24 |
| Finished | Feb 18 12:48:19 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-79cf028a-4f30-42ea-bf4f-57ba9a3ec8e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094584235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3094584235 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3247288672 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 19378607 ps |
| CPU time | 11.44 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:48:27 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-bd266d79-2ffa-4e21-b009-b6f3fe677cce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247288672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3247288672 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4165988931 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 157659211 ps |
| CPU time | 1.98 seconds |
| Started | Feb 18 12:48:16 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-5ea992a4-5294-424e-a7e5-f192324b51e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4165988931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4165988931 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3692785088 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 8278576 ps |
| CPU time | 1.31 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-73547393-9d82-486f-a245-eae76561ba80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3692785088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3692785088 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2650899234 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 112267309004 ps |
| CPU time | 317.04 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:54:27 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-8bdf39f4-dd57-470f-816d-70dfc050c168 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2650899234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2650899234 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3423258386 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 69532886 ps |
| CPU time | 5.76 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-67bcbe1e-614d-4b23-be86-eabcafe35969 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3423258386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3423258386 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.780647139 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 64668609 ps |
| CPU time | 3.51 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-f4e074bf-be67-48f8-b7ca-2e742f02d08a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=780647139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.780647139 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.411231335 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 76527653 ps |
| CPU time | 1.99 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:49:10 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-1378cf0d-5599-4548-adc0-daace8a6816d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=411231335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.411231335 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1320808573 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 41605314948 ps |
| CPU time | 136.53 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:51:30 PM PST 24 |
| Peak memory | 202020 kb |
| Host | smart-8543a6ee-0257-4347-9fd6-760347511666 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320808573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1320808573 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2536758925 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 32269173795 ps |
| CPU time | 38.23 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:49:50 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-6b63e268-d88e-4cea-97f6-9fa1a9efd5b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2536758925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2536758925 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2579604808 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 67427925 ps |
| CPU time | 8.68 seconds |
| Started | Feb 18 12:49:06 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-8d294aa9-6f00-4bfc-a136-f4729b6a0bc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579604808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2579604808 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.796726520 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6747410866 ps |
| CPU time | 11.36 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-d70aa35a-762a-4693-98f3-7d7839f50fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796726520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.796726520 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2250037963 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 66532965 ps |
| CPU time | 1.77 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:14 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-9b47ae83-f5dd-4b13-8e59-1a031bc110fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250037963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2250037963 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3074249606 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1868827201 ps |
| CPU time | 9.52 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-3a72dd1f-0737-4dc2-9abf-dab954546cb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074249606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3074249606 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2068173998 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2045238313 ps |
| CPU time | 8.87 seconds |
| Started | Feb 18 12:49:07 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-c30232dc-2dc8-408c-b420-30d2e9ccb08e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2068173998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2068173998 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2584732747 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 8356538 ps |
| CPU time | 1.04 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:15 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-76b5b012-242c-4914-b57c-7403a6dacc8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584732747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2584732747 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1339568630 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 500326236 ps |
| CPU time | 9.58 seconds |
| Started | Feb 18 12:49:05 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-bdd0045a-5c65-402d-85ea-f5f8b2c394ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1339568630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1339568630 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.835189425 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 32235381269 ps |
| CPU time | 91.19 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:50:46 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-0460086a-31c6-44f4-a54d-50dffbb252c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=835189425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.835189425 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.281183421 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 87282848 ps |
| CPU time | 16.43 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:33 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-a8486633-3657-4f68-a34e-eb3eda005248 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=281183421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.281183421 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3915248157 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 36322321 ps |
| CPU time | 10.76 seconds |
| Started | Feb 18 12:49:15 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-b8b5aa09-29e0-4d8a-8574-76af16dce4ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3915248157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.3915248157 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3796110585 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 90020240 ps |
| CPU time | 2.94 seconds |
| Started | Feb 18 12:49:04 PM PST 24 |
| Finished | Feb 18 12:49:10 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-5ec36ec9-749f-4129-8535-33619f785985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3796110585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3796110585 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1635557422 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 161369394 ps |
| CPU time | 2.84 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-40e0cc7b-da2c-47b1-a646-6de41ca1724d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1635557422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1635557422 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3206446538 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 6282253988 ps |
| CPU time | 39.15 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-cc935d44-16de-4a90-b277-bf6c12046952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3206446538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3206446538 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2426528541 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 96307384 ps |
| CPU time | 6.2 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-a7927e86-001f-4f27-ac63-aff55bf8ea52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426528541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2426528541 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1979691729 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 120229035 ps |
| CPU time | 2.57 seconds |
| Started | Feb 18 12:49:16 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-11c1ee72-ba41-428c-b5a4-16510743b461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1979691729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1979691729 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.2532261569 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1648250203 ps |
| CPU time | 9.07 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:26 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-bb9a5f5e-7ed9-4525-b471-df94c2049fda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2532261569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2532261569 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4164204096 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 52139340527 ps |
| CPU time | 119.98 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:51:18 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-c25398d4-6838-4ee7-a26e-3fdb9bf671c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164204096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4164204096 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.67477218 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5578801443 ps |
| CPU time | 43.21 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:50:08 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-bad45fc4-bc5e-401a-a156-3f2fa1951b7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=67477218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.67477218 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.703418483 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 50589577 ps |
| CPU time | 4.16 seconds |
| Started | Feb 18 12:49:12 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-8e82c4b2-ee47-4945-9348-fd780bc6274c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703418483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.703418483 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.3175993715 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 897955359 ps |
| CPU time | 6.75 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-c32486e4-0833-4ffc-824f-5b650ab1cd56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175993715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3175993715 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2387311337 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 10215797 ps |
| CPU time | 1.08 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-fa250a4e-272e-42ec-8815-a623801e9f49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2387311337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2387311337 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.790144429 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 6556326384 ps |
| CPU time | 11.64 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-af3b864f-420a-49ca-9d49-4510ad5312c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=790144429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.790144429 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3501186154 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2768476703 ps |
| CPU time | 7.32 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-406f852d-7d81-4090-a2f1-4a1fa82297ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3501186154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3501186154 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2207978725 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8427239 ps |
| CPU time | 1.12 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-690a4425-727a-4aba-b8bc-2417619a7400 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207978725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2207978725 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2201943531 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 248349283 ps |
| CPU time | 35.66 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:53 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-31688da3-a903-4fd3-b4be-96298a7e9d80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2201943531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2201943531 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3911573267 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 237073293 ps |
| CPU time | 22.82 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:43 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-72aaf135-eaa4-488f-bf61-105562239570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3911573267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3911573267 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.708577688 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 760230280 ps |
| CPU time | 80.92 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:50:35 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-9d88bcad-317a-42c4-85ae-77726e20e521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708577688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.708577688 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2935287802 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 14074356315 ps |
| CPU time | 230.39 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:53:08 PM PST 24 |
| Peak memory | 209756 kb |
| Host | smart-6e670116-ac3b-4c29-a795-997a475d42d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2935287802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2935287802 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2004374472 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 763520154 ps |
| CPU time | 9.93 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-6297515a-78f7-41bb-84e4-dff3b32e6bf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2004374472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2004374472 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2793343760 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 813415350 ps |
| CPU time | 3.21 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:49:28 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-51ed0f59-6a2a-4856-bd1b-a0bf574dcd97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2793343760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2793343760 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1971540981 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 107258587261 ps |
| CPU time | 365.19 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:55:25 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-0faaa234-0d10-4412-b1c3-991551a6ec65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1971540981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1971540981 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4126491693 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 43679557 ps |
| CPU time | 4.26 seconds |
| Started | Feb 18 12:49:15 PM PST 24 |
| Finished | Feb 18 12:49:22 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-a2fdf3a0-3fa9-493f-869b-328f8016a7ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4126491693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4126491693 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2498967189 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 400609798 ps |
| CPU time | 6.29 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-674d5736-d6a5-4c34-8688-13a1ba7a51d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2498967189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2498967189 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.2493714566 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 33810199 ps |
| CPU time | 4.17 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:20 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-26c205f4-42cc-48d4-b2f2-f8b476e42c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2493714566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2493714566 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.421176776 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 14973347050 ps |
| CPU time | 65.73 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:50:31 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-cda60d9a-b674-4999-b331-dc6312ab0cc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=421176776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.421176776 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2713894390 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2625237877 ps |
| CPU time | 17.33 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:49:42 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-108057d1-affc-4814-86c6-7ec2e183e68e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2713894390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2713894390 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3520489597 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 37876814 ps |
| CPU time | 4.13 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:49:22 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-3023fe5e-2337-493b-9112-b7dd5e53757d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520489597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3520489597 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.3885010965 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 954761040 ps |
| CPU time | 12.18 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:31 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-5b469b7b-36f5-4e15-b2c3-bef8a6400dde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3885010965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3885010965 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.3805245809 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 67801688 ps |
| CPU time | 1.29 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:49:19 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-e3d8e161-dc74-40b8-bf15-504867b44cd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805245809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3805245809 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.368554599 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6868096869 ps |
| CPU time | 11.73 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-60b9e7ee-c901-4c13-9fe4-fde6f8997933 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=368554599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.368554599 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3534760489 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2114303258 ps |
| CPU time | 8.65 seconds |
| Started | Feb 18 12:49:10 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-b0b7d3f3-3e08-4d6e-9e0d-48a6d969c3bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3534760489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3534760489 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2518638225 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 37763307 ps |
| CPU time | 1.28 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-cf38f5ba-b036-4c50-a8b4-16108e1ef6ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518638225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2518638225 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3570760318 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3241365166 ps |
| CPU time | 65.25 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:50:23 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-3e83f48d-6d12-46f5-8a4d-e0a016f30fe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3570760318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3570760318 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1912306899 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3482515373 ps |
| CPU time | 59.11 seconds |
| Started | Feb 18 12:49:08 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-9fe3ee32-6e14-4527-b068-288a44e5f023 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1912306899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1912306899 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3557954790 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3003075039 ps |
| CPU time | 73.6 seconds |
| Started | Feb 18 12:49:09 PM PST 24 |
| Finished | Feb 18 12:50:27 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-d3fba245-692a-4aa8-b038-13fd790edfb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3557954790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3557954790 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.947209293 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 401779167 ps |
| CPU time | 7.75 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-9a58b299-1fda-43a0-b2f6-18e63c1f1b2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=947209293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.947209293 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.85203659 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 16506162 ps |
| CPU time | 2.56 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:20 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-adf58c88-5124-49ae-b292-fa259ba14f2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85203659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.85203659 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2858360417 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 73569727 ps |
| CPU time | 5.84 seconds |
| Started | Feb 18 12:49:15 PM PST 24 |
| Finished | Feb 18 12:49:24 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-1c019dbf-237d-4fbf-a7e0-e290f862899c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2858360417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2858360417 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.859804779 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 506549808 ps |
| CPU time | 7.96 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-3e2bd13e-9347-420d-91a2-c412691b99f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=859804779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.859804779 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.2334863404 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 754393694 ps |
| CPU time | 13.72 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-3ed13709-5748-4ef5-bc5b-635f01fbb0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334863404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2334863404 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2842250199 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 36212336832 ps |
| CPU time | 129.16 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:51:33 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-fa484a80-a971-4a8a-8095-a1511128cd9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842250199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2842250199 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3458347354 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3196781036 ps |
| CPU time | 20.92 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:40 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-2efe35af-ed37-4f52-8032-ff12838597a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3458347354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3458347354 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1125497663 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 99175550 ps |
| CPU time | 4.35 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-5eaeaa65-f040-4f9f-a2a8-5d1968a8cc86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125497663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1125497663 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2998320037 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 397440917 ps |
| CPU time | 2.99 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-61a55f75-05b3-47be-bbd9-a96be51dd506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2998320037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2998320037 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.1211262168 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 59118776 ps |
| CPU time | 1.87 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-7d398fa2-e44c-448a-afee-7138457b91e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1211262168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1211262168 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.620356258 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6355026057 ps |
| CPU time | 8.24 seconds |
| Started | Feb 18 12:49:13 PM PST 24 |
| Finished | Feb 18 12:49:26 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-772ef234-ab57-4fb9-a63b-c0c1a536a406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=620356258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.620356258 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1155801658 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2805663691 ps |
| CPU time | 5.73 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-080d4dd2-3f36-471f-a497-9743a9cbc27f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1155801658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1155801658 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3784765144 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 9057264 ps |
| CPU time | 1.12 seconds |
| Started | Feb 18 12:49:11 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-eae68d00-b996-4381-a80b-c0d64fadc74c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784765144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3784765144 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2135583341 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11736878689 ps |
| CPU time | 36.35 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:49:59 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-9d5e8617-b3e7-48cc-b6e7-6fec65572b5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135583341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2135583341 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.812837506 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 16423089376 ps |
| CPU time | 45.31 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-bdcefcb4-d675-425d-a256-c61a2e4233af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812837506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.812837506 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.956972359 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3219822606 ps |
| CPU time | 127.37 seconds |
| Started | Feb 18 12:49:16 PM PST 24 |
| Finished | Feb 18 12:51:26 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-09bf1847-af7d-4590-bb78-52adbca32c4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=956972359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.956972359 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2970140890 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 634945103 ps |
| CPU time | 55.59 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-5b794c76-c056-42e7-804e-90a7091a3420 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970140890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2970140890 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1855342822 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 451306811 ps |
| CPU time | 6.57 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:26 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-0e933c63-e852-4df4-a2aa-81a0dfbe6369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1855342822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1855342822 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3161018349 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3511523107 ps |
| CPU time | 27.36 seconds |
| Started | Feb 18 12:49:14 PM PST 24 |
| Finished | Feb 18 12:49:45 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ec275cf2-197f-444b-a8b7-665b4d5f4a16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161018349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3161018349 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2726745052 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3006772199 ps |
| CPU time | 15.7 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-2f0536e8-af46-422a-bd02-c80a4ba2f17a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2726745052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2726745052 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1846781632 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1614526998 ps |
| CPU time | 5.11 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-8e067b41-723b-4e07-920b-cace95f77fc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1846781632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1846781632 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2584378077 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 79100667 ps |
| CPU time | 4.08 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:26 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-7da97cde-b60e-4690-9ca2-36c89d3852d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2584378077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2584378077 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.519237272 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 52391327 ps |
| CPU time | 1.68 seconds |
| Started | Feb 18 12:49:16 PM PST 24 |
| Finished | Feb 18 12:49:20 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-3ded8eda-5f38-41a3-8fd2-159b2df2d6cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=519237272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.519237272 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.222946707 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 29818963309 ps |
| CPU time | 104.95 seconds |
| Started | Feb 18 12:49:24 PM PST 24 |
| Finished | Feb 18 12:51:11 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-0ccea20d-8b40-4983-94a8-4c2a8c79d442 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=222946707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.222946707 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2967282996 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 26846158692 ps |
| CPU time | 186.7 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:52:31 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-5cb18787-3e88-4527-9247-f0cddb59174d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2967282996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2967282996 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1555056283 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 48519916 ps |
| CPU time | 5.6 seconds |
| Started | Feb 18 12:49:17 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-ff8c5683-baa9-4b9a-b80b-82bfbbc94653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555056283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1555056283 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3740320156 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 664633054 ps |
| CPU time | 9.47 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:49:34 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-ebd26242-1cfd-43e5-bb15-23d41437293b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740320156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3740320156 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.1186330632 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 18225127 ps |
| CPU time | 1.1 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-71f5e466-eb2e-4d3b-87b9-ba85ef91dc6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1186330632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1186330632 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1340921838 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 6998994686 ps |
| CPU time | 10.8 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:49:34 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-ccd5d2c3-5364-4273-964f-0b9374d41f02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340921838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1340921838 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.208073156 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3525410238 ps |
| CPU time | 7.68 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-882a7dfa-5937-4f8a-912f-5df360cf60bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=208073156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.208073156 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3751365916 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 21778365 ps |
| CPU time | 1.21 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-08037655-f00d-42f6-8b57-efa29ef70d24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751365916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3751365916 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.546312497 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 6924777049 ps |
| CPU time | 46.61 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:50:10 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-f4d66a83-7157-4e6e-91af-654c26e88817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546312497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.546312497 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.579262956 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 6172625610 ps |
| CPU time | 149.49 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:51:51 PM PST 24 |
| Peak memory | 207444 kb |
| Host | smart-ee2b8262-f8ae-495f-94cd-0079506d503e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579262956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.579262956 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3219528683 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 69912733 ps |
| CPU time | 2.21 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-f1e47579-bde9-4b1e-82ae-ebe2dd789f56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3219528683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3219528683 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2353743309 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1032587423 ps |
| CPU time | 18.96 seconds |
| Started | Feb 18 12:49:24 PM PST 24 |
| Finished | Feb 18 12:49:45 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-d1aea322-65f7-4cb3-9fe4-1bb3dfbf3736 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2353743309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2353743309 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.160597645 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10083201662 ps |
| CPU time | 48.89 seconds |
| Started | Feb 18 12:49:24 PM PST 24 |
| Finished | Feb 18 12:50:15 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-953905d6-2d9b-4241-9364-fb336fa09d4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=160597645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.160597645 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.169579682 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 228073432 ps |
| CPU time | 5.8 seconds |
| Started | Feb 18 12:49:24 PM PST 24 |
| Finished | Feb 18 12:49:31 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-9de6e06c-10d6-47d8-8962-33d8b9d92eff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=169579682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.169579682 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.489425712 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1013627667 ps |
| CPU time | 2.97 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:30 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-228a95b5-195f-4e85-af5e-2595ef4e6ee7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489425712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.489425712 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2186595688 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 360433624 ps |
| CPU time | 3.06 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:25 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-6f5c72a3-acb7-49f7-a05d-396456b07e66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186595688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2186595688 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2036810976 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 7485884397 ps |
| CPU time | 32.74 seconds |
| Started | Feb 18 12:49:21 PM PST 24 |
| Finished | Feb 18 12:49:57 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-42fad718-9c0e-4c9d-a2f1-9c7688381fb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036810976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2036810976 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.185602315 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 43884560046 ps |
| CPU time | 153.93 seconds |
| Started | Feb 18 12:49:20 PM PST 24 |
| Finished | Feb 18 12:51:57 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-e56717dc-7791-4f01-ac62-f112b288de64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=185602315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.185602315 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3348730212 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 62466084 ps |
| CPU time | 4.78 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-cea3e07b-6fb6-40dc-b09e-11bbbf17f0b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348730212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3348730212 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3150631714 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 50976242 ps |
| CPU time | 2.86 seconds |
| Started | Feb 18 12:49:26 PM PST 24 |
| Finished | Feb 18 12:49:31 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-03905a91-aedc-4294-876c-a0b8ec8300b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3150631714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3150631714 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3373332274 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 33146952 ps |
| CPU time | 1.24 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:28 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-9992005e-f168-4c5f-8f43-1fe6dacd3a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3373332274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3373332274 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1994465184 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1426313950 ps |
| CPU time | 6.93 seconds |
| Started | Feb 18 12:49:18 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-5ef853a1-d48e-4b97-b4fa-1c73c62b5f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994465184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1994465184 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3854644242 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1608225630 ps |
| CPU time | 7.98 seconds |
| Started | Feb 18 12:49:22 PM PST 24 |
| Finished | Feb 18 12:49:33 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-edba162b-ce7b-4880-9ac2-ea5140b78b75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3854644242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3854644242 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.170194808 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 21981944 ps |
| CPU time | 1.28 seconds |
| Started | Feb 18 12:49:19 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-e32483f4-2334-4fd1-9496-e0d039679f88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170194808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.170194808 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3718421918 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 576988287 ps |
| CPU time | 53.66 seconds |
| Started | Feb 18 12:49:36 PM PST 24 |
| Finished | Feb 18 12:50:31 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-43a4e9c7-2d1d-44ba-98e5-c6da2f76dbdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718421918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3718421918 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1860218468 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 62334110 ps |
| CPU time | 1.66 seconds |
| Started | Feb 18 12:49:23 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-77a873c8-6ab1-4274-893f-d90c47c839c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1860218468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1860218468 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.951720505 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 264047780 ps |
| CPU time | 29.59 seconds |
| Started | Feb 18 12:49:30 PM PST 24 |
| Finished | Feb 18 12:50:01 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-fcbe48dd-540a-495e-a78b-ef1746fb4d61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=951720505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.951720505 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3255656609 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 316579364 ps |
| CPU time | 28.74 seconds |
| Started | Feb 18 12:49:24 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-cdb1f34e-ff9f-46a2-a6c3-022a2ef90e3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3255656609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3255656609 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3072973279 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1552119923 ps |
| CPU time | 9.28 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-8fc9f943-183f-417c-aa10-784894a043de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3072973279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3072973279 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4260508778 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 61134048 ps |
| CPU time | 12.77 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:40 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-3c2bd7c3-5e56-4863-8495-eae05827e882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4260508778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4260508778 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.421798345 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 20639183423 ps |
| CPU time | 152.93 seconds |
| Started | Feb 18 12:49:29 PM PST 24 |
| Finished | Feb 18 12:52:03 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-5c6ec613-5e42-412b-bf29-6fe2bf42d910 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=421798345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.421798345 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3373894519 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1477070473 ps |
| CPU time | 6.84 seconds |
| Started | Feb 18 12:49:32 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-9cc38ad1-51f4-4e1f-ba74-5b411d97a9f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3373894519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3373894519 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1119095158 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 161618038 ps |
| CPU time | 6.39 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:33 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-a135f3c8-c7d9-419f-8a63-ba08ae5c5b7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1119095158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1119095158 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3690872280 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 21894374 ps |
| CPU time | 2.28 seconds |
| Started | Feb 18 12:49:26 PM PST 24 |
| Finished | Feb 18 12:49:30 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-e9d3c86c-ffcb-442d-b515-3a2c920e19ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3690872280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3690872280 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4063550464 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 25010583627 ps |
| CPU time | 36.85 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:50:03 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-e8e2a7a5-7fb7-4aaf-85c6-a99cfb1db7ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063550464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4063550464 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.125575863 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7602758875 ps |
| CPU time | 36.21 seconds |
| Started | Feb 18 12:49:29 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-6774f16d-fc38-48aa-a686-51780faf0686 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=125575863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.125575863 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3078546781 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 142005199 ps |
| CPU time | 4.84 seconds |
| Started | Feb 18 12:49:26 PM PST 24 |
| Finished | Feb 18 12:49:33 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-90899b1e-ace7-4b85-95ff-889a444cd13d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078546781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3078546781 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.2594616226 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 108101283 ps |
| CPU time | 6.45 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:34 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-f4282f66-d944-4340-8275-5912a74833d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2594616226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2594616226 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2953696960 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 56554134 ps |
| CPU time | 1.97 seconds |
| Started | Feb 18 12:49:27 PM PST 24 |
| Finished | Feb 18 12:49:30 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ed768dce-763e-4b41-84fe-4b1560949378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953696960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2953696960 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.539988478 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 15542395527 ps |
| CPU time | 10.84 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:38 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-261e0dee-1f98-4e97-bd8d-48ce77a15aca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=539988478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.539988478 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.340359298 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4084507901 ps |
| CPU time | 10.87 seconds |
| Started | Feb 18 12:49:25 PM PST 24 |
| Finished | Feb 18 12:49:38 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-957c2b38-048d-449c-884c-f3b82dd086d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=340359298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.340359298 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3926781291 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 13383239 ps |
| CPU time | 1.05 seconds |
| Started | Feb 18 12:49:27 PM PST 24 |
| Finished | Feb 18 12:49:29 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-2b0d8fb1-6eea-483e-a0d8-809bc247d686 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926781291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3926781291 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.1373443696 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 253168668 ps |
| CPU time | 22.56 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:57 PM PST 24 |
| Peak memory | 203508 kb |
| Host | smart-447c7c3c-9a60-4252-afea-4b6f8e921f9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1373443696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1373443696 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2854147008 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7971291125 ps |
| CPU time | 35.79 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-c377d8ce-575d-49dd-9cea-ab68579887d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854147008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2854147008 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.847323255 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 719757321 ps |
| CPU time | 109.69 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:51:26 PM PST 24 |
| Peak memory | 207568 kb |
| Host | smart-90c742ea-50e5-4b34-b2f4-74e499568659 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=847323255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.847323255 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3935952847 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 17683606450 ps |
| CPU time | 137.87 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:51:53 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-be9ea5e9-294c-4e43-9156-701a62601dec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3935952847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3935952847 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.18182519 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 129949036 ps |
| CPU time | 5.66 seconds |
| Started | Feb 18 12:49:27 PM PST 24 |
| Finished | Feb 18 12:49:34 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-978f6a92-a340-4aee-a1cf-7d76f57ad160 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18182519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.18182519 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1501702182 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 752639955 ps |
| CPU time | 10.58 seconds |
| Started | Feb 18 12:49:37 PM PST 24 |
| Finished | Feb 18 12:49:49 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-1744e36e-4993-4a3f-94da-fcaf92796759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1501702182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1501702182 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2307476779 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 71142254209 ps |
| CPU time | 203.14 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:53:00 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-80afdcc3-fd74-4298-b035-0d6c06abcd19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2307476779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2307476779 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3578481392 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 566552243 ps |
| CPU time | 11.06 seconds |
| Started | Feb 18 12:49:34 PM PST 24 |
| Finished | Feb 18 12:49:47 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-78606a94-f7bc-4e18-b647-5637046fb063 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3578481392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3578481392 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.18343795 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 49802765 ps |
| CPU time | 6.82 seconds |
| Started | Feb 18 12:49:37 PM PST 24 |
| Finished | Feb 18 12:49:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-6d8f02c2-c69d-4311-a883-069c759acc31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18343795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.18343795 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2725238334 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1370474041 ps |
| CPU time | 5.9 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-bb40c43d-a4c4-47f9-a485-501bbfd319bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2725238334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2725238334 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2761281600 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 115085379679 ps |
| CPU time | 109.29 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:51:27 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-bebb5eea-c479-44ce-a3ff-726317f8e6c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761281600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2761281600 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3569361135 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 20322661559 ps |
| CPU time | 66.59 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-383531e6-4429-4234-b73e-7fe06417a485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3569361135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3569361135 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3940178875 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 216262518 ps |
| CPU time | 6.13 seconds |
| Started | Feb 18 12:49:35 PM PST 24 |
| Finished | Feb 18 12:49:42 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-3d1eae77-eb05-43f2-939b-30a74e2d2075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940178875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3940178875 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3337863411 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 32653667 ps |
| CPU time | 2.53 seconds |
| Started | Feb 18 12:49:34 PM PST 24 |
| Finished | Feb 18 12:49:38 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-f2c8e657-a573-4295-9ed1-5e30192c862d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3337863411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3337863411 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3145272879 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17646080 ps |
| CPU time | 1.17 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-85b4ba4a-9c5b-4a2b-a974-07de1b0baef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3145272879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3145272879 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1127370762 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2524276438 ps |
| CPU time | 8.32 seconds |
| Started | Feb 18 12:49:31 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-575c9a51-f022-4fea-925b-7885f17295bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127370762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1127370762 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3437705189 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2295483764 ps |
| CPU time | 11.14 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:46 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-fb093bc5-0243-4248-8770-e4187247d447 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3437705189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3437705189 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4231391343 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 9331127 ps |
| CPU time | 1.26 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:36 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-2e11fa38-ccb6-4098-b10a-24d3e98cc92c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231391343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4231391343 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1059153864 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 533647050 ps |
| CPU time | 60.16 seconds |
| Started | Feb 18 12:49:34 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-241fbbac-e3d6-4889-834f-9a92271ad0de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1059153864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1059153864 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3779362930 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1583927585 ps |
| CPU time | 20.02 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-04b865ef-05f5-41a9-8df2-467b582012ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3779362930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3779362930 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.958148838 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 157519770 ps |
| CPU time | 20.86 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:56 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-bf8f8334-1825-4a2f-825d-8ec16d10326a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958148838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.958148838 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2550700884 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1047056167 ps |
| CPU time | 134.95 seconds |
| Started | Feb 18 12:49:32 PM PST 24 |
| Finished | Feb 18 12:51:49 PM PST 24 |
| Peak memory | 208120 kb |
| Host | smart-9c5d1a4a-f6e8-4315-bef1-723133f5bf31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2550700884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.2550700884 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3386200417 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 406823786 ps |
| CPU time | 6.52 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:42 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-dcbbbdb5-7a94-4468-92e2-39d2fdd7c960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386200417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3386200417 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3013801667 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4300852109 ps |
| CPU time | 18.5 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:50:04 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-4c99ee90-82b9-449b-9f0d-8b0c08aa8763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013801667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3013801667 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1088090541 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1253755970 ps |
| CPU time | 10.52 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:49:56 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-b1c9de72-e7d8-419a-990b-64a7cc545fa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1088090541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1088090541 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2203133826 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3873546647 ps |
| CPU time | 10.11 seconds |
| Started | Feb 18 12:49:48 PM PST 24 |
| Finished | Feb 18 12:50:00 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-3ecb8e73-b5e5-4ed5-b53e-99f9f3aed695 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203133826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2203133826 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1341274795 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 44105789762 ps |
| CPU time | 160.37 seconds |
| Started | Feb 18 12:49:43 PM PST 24 |
| Finished | Feb 18 12:52:24 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-6ab16fef-daca-4be4-a319-238effe59961 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341274795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1341274795 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2241306833 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 49847871501 ps |
| CPU time | 166.97 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:52:33 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-fa81b767-8167-4544-bff2-5aebbc3b7d41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2241306833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2241306833 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1775666475 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 92729777 ps |
| CPU time | 4.8 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:49:50 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-e33c7628-965c-41da-8ede-166ea81b4be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775666475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1775666475 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3969576998 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 661474878 ps |
| CPU time | 8.37 seconds |
| Started | Feb 18 12:49:43 PM PST 24 |
| Finished | Feb 18 12:49:52 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-803ac64f-79fe-4c35-95ae-b9219cb5c54b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969576998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3969576998 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.222672529 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 70886353 ps |
| CPU time | 1.69 seconds |
| Started | Feb 18 12:49:34 PM PST 24 |
| Finished | Feb 18 12:49:38 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-ccf8f3c5-baa9-44e9-aa04-9374ecf483cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=222672529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.222672529 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.976635153 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2348344000 ps |
| CPU time | 9.86 seconds |
| Started | Feb 18 12:49:33 PM PST 24 |
| Finished | Feb 18 12:49:45 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-3dd040c9-4b20-49be-a6a8-9a19bbcd172b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=976635153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.976635153 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.565462598 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1590521410 ps |
| CPU time | 7.16 seconds |
| Started | Feb 18 12:49:31 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-fb636e4c-4e9c-4ece-b79b-acc871bd0f86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=565462598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.565462598 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2968375393 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 11784305 ps |
| CPU time | 1.17 seconds |
| Started | Feb 18 12:49:31 PM PST 24 |
| Finished | Feb 18 12:49:35 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3c91c116-42dd-4618-b4f7-14c602d9d5ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968375393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2968375393 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2020164548 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 10386108039 ps |
| CPU time | 31.7 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-4026afd5-64f0-4e04-90f1-7cb9b1e7c5cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020164548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2020164548 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.4230545939 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 526220840 ps |
| CPU time | 17.27 seconds |
| Started | Feb 18 12:49:48 PM PST 24 |
| Finished | Feb 18 12:50:07 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-85bb05d0-4835-4b56-8ad3-22c564f5a4b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230545939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4230545939 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1806615924 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 139690699 ps |
| CPU time | 21.62 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:50:08 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-85a81381-a25a-422d-b7d1-de24ce9c4a0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1806615924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1806615924 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2766469016 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 5077677266 ps |
| CPU time | 65.14 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:50:52 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-1a924038-df53-41b2-8470-1bba4ef8cc09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2766469016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.2766469016 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2814855127 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 799625958 ps |
| CPU time | 3.13 seconds |
| Started | Feb 18 12:49:43 PM PST 24 |
| Finished | Feb 18 12:49:47 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-8b4f2cea-b15e-461c-bf6b-0a0cce857d89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2814855127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2814855127 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2108562802 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 383236375 ps |
| CPU time | 9.95 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-97529f1a-cf48-417e-b54a-ef3f12ae9930 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2108562802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2108562802 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3764773496 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 9529558353 ps |
| CPU time | 72.13 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-eb06d6c6-4437-4abd-8a5a-c751b64409ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3764773496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3764773496 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3650107714 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 86449446 ps |
| CPU time | 6.22 seconds |
| Started | Feb 18 12:49:43 PM PST 24 |
| Finished | Feb 18 12:49:50 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-2bc75d37-dd3e-436f-809b-08d7745a8faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3650107714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3650107714 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.586495279 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1263605648 ps |
| CPU time | 9.14 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-23f04be3-2044-43a4-847d-cb2353fc4d35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=586495279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.586495279 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.663689652 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 385864877 ps |
| CPU time | 1.77 seconds |
| Started | Feb 18 12:49:47 PM PST 24 |
| Finished | Feb 18 12:49:51 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-f6517faf-d7e1-439f-ad35-6cad2a71e8c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=663689652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.663689652 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3294139274 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 87264393013 ps |
| CPU time | 165.93 seconds |
| Started | Feb 18 12:49:47 PM PST 24 |
| Finished | Feb 18 12:52:35 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-f3c543e1-31aa-42b2-9261-5362bb008739 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294139274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3294139274 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4145958263 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 9474063715 ps |
| CPU time | 63.24 seconds |
| Started | Feb 18 12:49:46 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-2aef4134-60d0-48e4-88a0-21345adc3e7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4145958263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4145958263 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3079448986 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 12171759 ps |
| CPU time | 1.38 seconds |
| Started | Feb 18 12:49:46 PM PST 24 |
| Finished | Feb 18 12:49:48 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-547a0ab4-7655-4150-b017-94da02ad996a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079448986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3079448986 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.411596394 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2847249457 ps |
| CPU time | 7.54 seconds |
| Started | Feb 18 12:49:44 PM PST 24 |
| Finished | Feb 18 12:49:52 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-99372d3b-51b9-4c41-8c1a-d5e267d59ae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=411596394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.411596394 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2128161599 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 16920442 ps |
| CPU time | 1.12 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:49:48 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-658d71bd-0420-4af1-8b90-f767ea2b838f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128161599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2128161599 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2192893333 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6027502876 ps |
| CPU time | 8.77 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:49:56 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-3f0887d8-9173-46b0-ad93-cf8251be0680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192893333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2192893333 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1564075056 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1830289375 ps |
| CPU time | 12.01 seconds |
| Started | Feb 18 12:49:47 PM PST 24 |
| Finished | Feb 18 12:50:00 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-365b0b05-8f76-461a-9ad9-387ca292753c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1564075056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1564075056 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1560617602 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 8475824 ps |
| CPU time | 1.38 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:49:48 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-46636a89-95ff-4a71-bc92-222bd2ac767d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560617602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1560617602 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3786417444 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1096129288 ps |
| CPU time | 18.54 seconds |
| Started | Feb 18 12:49:45 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-ad30c3dc-5a52-4067-bb51-5a375edd632d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3786417444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3786417444 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.791261576 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1283359199 ps |
| CPU time | 17.24 seconds |
| Started | Feb 18 12:49:47 PM PST 24 |
| Finished | Feb 18 12:50:07 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-17ced357-1b64-4d6e-9623-13d915557bc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791261576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.791261576 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1064813853 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 100911718 ps |
| CPU time | 9.03 seconds |
| Started | Feb 18 12:49:42 PM PST 24 |
| Finished | Feb 18 12:49:52 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-5911683d-3c69-4913-9d5d-31a91bf9ecf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064813853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1064813853 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3284034795 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 15714502607 ps |
| CPU time | 120.81 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:51:55 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-08090d6b-6f02-4df2-8f90-7e05dec30c52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284034795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3284034795 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.904409932 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 687837214 ps |
| CPU time | 5.84 seconds |
| Started | Feb 18 12:49:43 PM PST 24 |
| Finished | Feb 18 12:49:50 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-76c1fd25-f648-4e24-8afd-fb081d0f1a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=904409932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.904409932 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.4153211411 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5051707457 ps |
| CPU time | 14.87 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:33 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-f5ecccc5-0aa0-438e-bfe6-69f55803375d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4153211411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.4153211411 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2137413897 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 597963413 ps |
| CPU time | 4.1 seconds |
| Started | Feb 18 12:48:14 PM PST 24 |
| Finished | Feb 18 12:48:25 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-8339d890-00e0-4681-8fcc-f16f4c4465ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2137413897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2137413897 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.210665910 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 20271211 ps |
| CPU time | 1.85 seconds |
| Started | Feb 18 12:48:08 PM PST 24 |
| Finished | Feb 18 12:48:20 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-78f233a0-7f58-4176-be71-39680c124da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=210665910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.210665910 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3986104278 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 34678466 ps |
| CPU time | 4.08 seconds |
| Started | Feb 18 12:48:16 PM PST 24 |
| Finished | Feb 18 12:48:25 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-b7f99f3f-bdde-4c27-9389-3cc65f6fd70e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986104278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3986104278 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2144553510 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 117882397170 ps |
| CPU time | 161.51 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-98b9bd64-4083-41db-b783-764163b3a5f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144553510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2144553510 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.10542936 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 10464087363 ps |
| CPU time | 83.6 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:41 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-27a15157-29c1-4f2f-90aa-e5c8d71a6664 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=10542936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.10542936 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.280316926 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 14281209 ps |
| CPU time | 2.07 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:48:19 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-1286f80f-5bf9-4ec7-9b92-e7e7e39eb35e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280316926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.280316926 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.462375539 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 55766434 ps |
| CPU time | 4.16 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:19 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-dc92cbbf-a29e-489d-8ceb-e8422bcf874a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=462375539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.462375539 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.3526444886 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 59064147 ps |
| CPU time | 1.55 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:17 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-b3c063ea-e5ea-433c-8c4b-68917eedb451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3526444886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3526444886 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.959729836 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3279986810 ps |
| CPU time | 8.75 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:29 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-ca10476f-c4b5-4660-a814-239b6aadac85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=959729836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.959729836 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4077788107 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 754827026 ps |
| CPU time | 6.31 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:21 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-6e643602-9dec-4fbb-a690-c3f4474d5814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4077788107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4077788107 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3481816636 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 23261555 ps |
| CPU time | 1.07 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:48:17 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-53566b54-7659-49a9-b339-9b447cc2b9b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481816636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3481816636 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2582289709 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4095087729 ps |
| CPU time | 63.51 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-4b15bb76-4d14-4ca7-abfb-780c1d676214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582289709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2582289709 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3014127874 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 468964818 ps |
| CPU time | 69.65 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:27 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-2ac7afac-89ad-49f1-b81e-738268dbd887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3014127874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3014127874 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2955664689 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1752225801 ps |
| CPU time | 82.01 seconds |
| Started | Feb 18 12:48:02 PM PST 24 |
| Finished | Feb 18 12:49:35 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-99476eb2-57e5-4429-a94a-5a2222c1966e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955664689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2955664689 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.893282831 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2273245798 ps |
| CPU time | 50.57 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:08 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-26251042-f4c6-448f-a0d9-0912782d4e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893282831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.893282831 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3301591468 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1316318821 ps |
| CPU time | 10.18 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-6dde2d6d-81a8-4ce9-aabb-cfcdf94fcbde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3301591468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3301591468 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3872014906 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 250399481 ps |
| CPU time | 3.78 seconds |
| Started | Feb 18 12:49:51 PM PST 24 |
| Finished | Feb 18 12:49:59 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-9e339ab8-a516-487c-8905-2c83124eea05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872014906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3872014906 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.423436925 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 71247123690 ps |
| CPU time | 332.62 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:55:29 PM PST 24 |
| Peak memory | 205016 kb |
| Host | smart-0775b1ef-dd6c-4194-94bf-95dbbc58e595 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=423436925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.423436925 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3531078718 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2084824017 ps |
| CPU time | 8.71 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:50:03 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-07fbdbbe-a7a5-4a55-9bbc-9df87d303258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531078718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3531078718 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3118094488 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 863854393 ps |
| CPU time | 8.96 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-9a7348b8-3591-4301-a6fa-2661cd972143 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118094488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3118094488 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2622656787 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1132253824 ps |
| CPU time | 4.27 seconds |
| Started | Feb 18 12:49:48 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-802119fd-a76f-4404-911f-0521726cacd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2622656787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2622656787 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3107800351 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 78753902743 ps |
| CPU time | 55.62 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-756cd433-d82b-4038-a7d2-f7e3b7383c9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107800351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3107800351 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.150447351 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 122039093916 ps |
| CPU time | 163.92 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:52:38 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-217f7fe7-e06a-4a87-b781-b9e815eb5964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=150447351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.150447351 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.957081970 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 93844333 ps |
| CPU time | 5.52 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:04 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-0f1d07a8-2d81-43a0-b071-828e3a98d6b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957081970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.957081970 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1917697042 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 58620115 ps |
| CPU time | 3.87 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:01 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-c5247c3e-795f-4833-8a0a-014ea096847d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1917697042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1917697042 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.2087611674 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11715795 ps |
| CPU time | 1.09 seconds |
| Started | Feb 18 12:49:48 PM PST 24 |
| Finished | Feb 18 12:49:51 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-c7d2f774-2a59-4c44-b320-045ea359a7e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2087611674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2087611674 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1783453814 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2409600495 ps |
| CPU time | 11.54 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:10 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-e66a477f-a6a1-4a5b-b262-046eaad5297c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783453814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1783453814 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.597511578 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1085129497 ps |
| CPU time | 7.72 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-3718b091-c80f-4167-9959-0bdadf6bfe08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=597511578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.597511578 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1849671176 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 9316099 ps |
| CPU time | 1.05 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:49:59 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-c5fb4357-a411-4623-9ec7-33e8b232869e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849671176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1849671176 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.967474495 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 184164251 ps |
| CPU time | 14.04 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-698de4cf-f546-4c49-95ec-a505600ac8d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=967474495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.967474495 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2657573225 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 5083725184 ps |
| CPU time | 32.49 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:29 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-d21dcc8d-c930-41e1-af4e-5b1511cc5a55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657573225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2657573225 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1104991641 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 108563943 ps |
| CPU time | 9.3 seconds |
| Started | Feb 18 12:49:51 PM PST 24 |
| Finished | Feb 18 12:50:04 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-3feb4da1-c1ec-46fa-bf30-91a578381212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1104991641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.1104991641 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.782926645 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3211032865 ps |
| CPU time | 31.12 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-0ea37ccb-6650-45fa-a6a4-07025ae5e453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=782926645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.782926645 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.87533133 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 29084444 ps |
| CPU time | 1.14 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-0341a080-c881-4646-8283-ffa5d8a4aa76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87533133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.87533133 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1076031537 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 505998377 ps |
| CPU time | 6.39 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:50:01 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-49ca6671-5498-4131-8717-7ac21f0a74df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1076031537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1076031537 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2582541681 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 59083661391 ps |
| CPU time | 339.14 seconds |
| Started | Feb 18 12:49:51 PM PST 24 |
| Finished | Feb 18 12:55:34 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-16843fa0-3e77-4f1e-b2aa-bf44aadebd10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2582541681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2582541681 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3759949346 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2201460302 ps |
| CPU time | 10.91 seconds |
| Started | Feb 18 12:49:55 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-828bfda7-fdc0-4d3b-8ac5-72adca178b8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3759949346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3759949346 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.4093116818 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1372620166 ps |
| CPU time | 10.09 seconds |
| Started | Feb 18 12:49:47 PM PST 24 |
| Finished | Feb 18 12:49:58 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-805b2f13-dacd-40f9-a109-68a09c2f910c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4093116818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4093116818 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.1998910365 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 732558094 ps |
| CPU time | 11.26 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-689d380c-9785-4674-93d5-48a10929193e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1998910365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1998910365 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3297246534 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 17034939034 ps |
| CPU time | 73.47 seconds |
| Started | Feb 18 12:49:49 PM PST 24 |
| Finished | Feb 18 12:51:05 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-397fb104-7889-4cd4-b23a-e2d861012bbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297246534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3297246534 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2263061578 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 12369539032 ps |
| CPU time | 56.11 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-32f8f729-cb80-48b9-b8b2-2877fbbde1eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2263061578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2263061578 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1828957071 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 83082443 ps |
| CPU time | 7.51 seconds |
| Started | Feb 18 12:49:48 PM PST 24 |
| Finished | Feb 18 12:49:58 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-81b4dd91-fe1a-440c-af9e-4a6e0e6c3ebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828957071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1828957071 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.2600287174 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 76257010 ps |
| CPU time | 6.63 seconds |
| Started | Feb 18 12:49:49 PM PST 24 |
| Finished | Feb 18 12:49:59 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-0059dc8b-fb25-4dba-ad8a-046559105a7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2600287174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2600287174 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2450230139 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9152688 ps |
| CPU time | 1.04 seconds |
| Started | Feb 18 12:49:49 PM PST 24 |
| Finished | Feb 18 12:49:53 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-7b9d8cb8-076f-4b53-a317-fe068d21b112 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2450230139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2450230139 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.309464640 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4828439995 ps |
| CPU time | 6.77 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-0d12e06f-375d-496f-94e0-fd203b533d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=309464640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.309464640 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2587741122 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 866751359 ps |
| CPU time | 7.32 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-b537d8bf-0225-401d-809b-997f35de8895 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2587741122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2587741122 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.816250130 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 14071056 ps |
| CPU time | 1.13 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:00 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-42d2077e-87eb-4fd7-9464-b3c2acf04d27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816250130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.816250130 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2858393522 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 112495790 ps |
| CPU time | 19.32 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-5a87e4dc-90fc-4068-b382-6c0b1964c3e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2858393522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2858393522 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3930303588 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 262378775 ps |
| CPU time | 20.34 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:29 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-a60a9d9c-3958-4372-a5c8-5d4e679ea057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930303588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3930303588 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.576988274 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 63296415 ps |
| CPU time | 15.19 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-1d4df4f6-bc4f-493f-9e26-76f815ce26b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576988274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.576988274 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1987940461 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 531369417 ps |
| CPU time | 5.16 seconds |
| Started | Feb 18 12:49:50 PM PST 24 |
| Finished | Feb 18 12:49:59 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-9a767d12-02ed-4d92-b4e8-e487c13ae57d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1987940461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1987940461 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.735428002 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 45750404 ps |
| CPU time | 11.86 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:11 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-103db612-e64f-4f5a-adb3-6bad3b662357 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=735428002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.735428002 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1618783268 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 67601505107 ps |
| CPU time | 131.95 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:52:11 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-617fe93e-1b2e-4af9-9e66-1bb9f4e68e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1618783268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1618783268 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2843256388 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 322714815 ps |
| CPU time | 6.51 seconds |
| Started | Feb 18 12:49:55 PM PST 24 |
| Finished | Feb 18 12:50:08 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-c3313b31-dbe0-4963-9b60-3b8139bfba2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2843256388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2843256388 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.2728741035 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 101525772 ps |
| CPU time | 6.86 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:15 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-20372a2d-1175-432a-be82-1d793ec4102f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2728741035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2728741035 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2575230294 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 18757308 ps |
| CPU time | 2.7 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:03 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-38d89bfd-cfd5-4043-b13d-6eec90afa7cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2575230294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2575230294 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.23617146 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8848926637 ps |
| CPU time | 36.36 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-2eaf895a-4a49-4d6a-baff-b9f4414dac63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=23617146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.23617146 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.28907472 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 30811824674 ps |
| CPU time | 181.73 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:53:00 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-86d8464a-9e4c-43c2-ac23-1cb8c8714eb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=28907472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.28907472 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1229763011 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 50648619 ps |
| CPU time | 5.59 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-d5f9d528-6a7a-432e-af62-12dbabe1aeaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229763011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1229763011 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.893912272 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 118851587 ps |
| CPU time | 7.11 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-e5dbe86a-32f9-42f2-b069-074281722b30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893912272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.893912272 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.723793583 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 15856997 ps |
| CPU time | 1.3 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-cd94c8b4-7843-43ca-a722-6c387757931b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723793583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.723793583 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1325736316 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3166014132 ps |
| CPU time | 9.98 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:10 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-238dde82-eeae-46aa-8acb-a21dea5306c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325736316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1325736316 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3559161243 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 893517123 ps |
| CPU time | 6.28 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-7a6704bc-42de-4483-971a-ddd888f8a3b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3559161243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3559161243 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1573274232 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 8512594 ps |
| CPU time | 1.04 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:16 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-498d5ac1-204a-48f4-8c66-3071ce164c7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573274232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1573274232 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2154487314 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4385995694 ps |
| CPU time | 85.27 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:51:25 PM PST 24 |
| Peak memory | 203880 kb |
| Host | smart-2bbe3eec-05c0-4fd6-8bbd-64a02d2eb0f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2154487314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2154487314 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1577577150 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2678589177 ps |
| CPU time | 27.85 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:43 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-8f0ef89a-7553-4d16-aa32-58bb33dfff81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577577150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1577577150 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1807273156 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 8140465291 ps |
| CPU time | 63.93 seconds |
| Started | Feb 18 12:49:56 PM PST 24 |
| Finished | Feb 18 12:51:06 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-21bec2c0-32ff-48c7-9e53-1987eed789a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1807273156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.1807273156 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2704399529 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 50223322 ps |
| CPU time | 5.12 seconds |
| Started | Feb 18 12:50:02 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-3d71cb2a-ff2b-4c4d-9b77-c1b26feb52c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2704399529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.2704399529 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1481193681 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 28080075 ps |
| CPU time | 2.96 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-f8bc29bc-852a-4376-ac03-c610664fa1b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1481193681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1481193681 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3326220574 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 22645784 ps |
| CPU time | 3.91 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-d7bf01f9-696d-4c6a-9453-eab665bbce3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3326220574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3326220574 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3800740309 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2615034202 ps |
| CPU time | 15.92 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:31 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-39038c76-f3cc-45bb-9a0d-73781a7f7b2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3800740309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3800740309 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.404772142 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 65085687 ps |
| CPU time | 3.46 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:04 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-ee8f5cbe-090b-4ed4-b1f9-2f0490f863da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404772142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.404772142 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.6473760 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 52779597 ps |
| CPU time | 2.54 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:06 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-49ab57f4-76fc-4954-ae59-1c483e96dfc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=6473760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.6473760 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.406909224 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1547737395 ps |
| CPU time | 11.52 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-51059a5b-c69b-4e76-987f-0ba6b82e7387 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406909224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.406909224 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2247607152 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 49929340050 ps |
| CPU time | 199.67 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:53:20 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-35db7a1a-f0ca-4a08-a9d6-a84dac03a22e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247607152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2247607152 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.226739951 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 10489669232 ps |
| CPU time | 56.17 seconds |
| Started | Feb 18 12:49:55 PM PST 24 |
| Finished | Feb 18 12:50:58 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-fca11e7d-a24d-4684-9e4f-e98351264b70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=226739951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.226739951 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.113621152 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 72199142 ps |
| CPU time | 10.99 seconds |
| Started | Feb 18 12:49:56 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-ca6ee44b-db6e-431a-8c32-59675c2f6b68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113621152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.113621152 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3665858482 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 79374850 ps |
| CPU time | 1.57 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:01 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-bfb3ab08-f513-4211-8b94-efa147ce2150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665858482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3665858482 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.890089462 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 54885933 ps |
| CPU time | 1.46 seconds |
| Started | Feb 18 12:49:57 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-43098b99-380a-4a89-86c0-a47157784cb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=890089462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.890089462 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.20855222 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3727267096 ps |
| CPU time | 6.46 seconds |
| Started | Feb 18 12:49:53 PM PST 24 |
| Finished | Feb 18 12:50:05 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-be5fa8f0-642a-42e0-bbd3-930bae982fc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=20855222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.20855222 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.4157349007 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 4929533811 ps |
| CPU time | 7.34 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:07 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-fef362c3-d883-4ab2-8421-1078f4160313 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4157349007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4157349007 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.431609056 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 26686592 ps |
| CPU time | 1.08 seconds |
| Started | Feb 18 12:49:56 PM PST 24 |
| Finished | Feb 18 12:50:03 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-a525cb5f-ca79-4f24-870b-f273de37fac3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431609056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.431609056 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2273367538 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1840339349 ps |
| CPU time | 30.7 seconds |
| Started | Feb 18 12:49:54 PM PST 24 |
| Finished | Feb 18 12:50:31 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-7d2317d0-36cc-44ad-8a1f-57bc42d92183 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273367538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2273367538 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2334181371 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 87720859 ps |
| CPU time | 1.96 seconds |
| Started | Feb 18 12:50:02 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-c2fbb004-e1c4-428a-959e-49d40ce84718 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334181371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2334181371 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.833176470 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 112811110 ps |
| CPU time | 35.99 seconds |
| Started | Feb 18 12:49:52 PM PST 24 |
| Finished | Feb 18 12:50:34 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-083d1bc0-3244-4f62-8112-2d8bf91e0520 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833176470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand _reset.833176470 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3940728429 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8011651614 ps |
| CPU time | 184.47 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:53:20 PM PST 24 |
| Peak memory | 208432 kb |
| Host | smart-e7337422-16b3-4b2c-aabc-41911acaaccc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940728429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3940728429 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3525354387 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 428831770 ps |
| CPU time | 6.48 seconds |
| Started | Feb 18 12:49:56 PM PST 24 |
| Finished | Feb 18 12:50:09 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-b76fa886-ed8a-4d88-8bc6-1eb69c4460d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3525354387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3525354387 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3574682257 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1529991169 ps |
| CPU time | 21.39 seconds |
| Started | Feb 18 12:49:58 PM PST 24 |
| Finished | Feb 18 12:50:26 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-dfd18500-2893-419b-99b7-74bca5a32454 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3574682257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3574682257 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3351998332 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 193798969119 ps |
| CPU time | 223.48 seconds |
| Started | Feb 18 12:49:59 PM PST 24 |
| Finished | Feb 18 12:53:49 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-fbc7b492-42d8-481c-ad60-739ebdb0da05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3351998332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3351998332 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.245562069 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 40201820 ps |
| CPU time | 4.57 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-cbe787a8-3e0a-4642-9b25-8510c83065b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245562069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.245562069 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2696050808 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 458389338 ps |
| CPU time | 7.09 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-18a308fc-04fc-4ece-b1c9-6c633fe9f3bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2696050808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2696050808 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3726739010 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 202875094 ps |
| CPU time | 6.59 seconds |
| Started | Feb 18 12:50:03 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-c05a21b5-9131-4fb7-847d-a53950ff0a9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3726739010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3726739010 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2051085601 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 31610539217 ps |
| CPU time | 157.48 seconds |
| Started | Feb 18 12:50:05 PM PST 24 |
| Finished | Feb 18 12:52:50 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-c1ab09a8-ca4b-4b6e-b8a7-3b0e41efdeac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051085601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2051085601 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1745728552 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 22007180360 ps |
| CPU time | 77.51 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:51:34 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-ef555e49-765d-434d-b8f8-d33dfeaa8f70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1745728552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1745728552 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1003825502 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 96379603 ps |
| CPU time | 6.01 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:13 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-01b21ff9-70cc-4633-a326-32d7582cdbd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003825502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1003825502 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.2569151945 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1054688265 ps |
| CPU time | 12.81 seconds |
| Started | Feb 18 12:49:59 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-d16d942e-7e42-439d-b3c3-5e3199ddf16d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2569151945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2569151945 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.332504815 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 43952642 ps |
| CPU time | 1.39 seconds |
| Started | Feb 18 12:50:03 PM PST 24 |
| Finished | Feb 18 12:50:12 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-b8590c5e-ab2d-4aef-88b1-518b1789d6b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332504815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.332504815 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2279739350 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2874325981 ps |
| CPU time | 10.76 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-88e7d6bb-04fd-4fe7-b6ee-bd442e46b6e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279739350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2279739350 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1995617690 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3171744713 ps |
| CPU time | 13.75 seconds |
| Started | Feb 18 12:49:59 PM PST 24 |
| Finished | Feb 18 12:50:19 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-1aa6ef9a-a0f4-485b-8d20-fa6f1c8d4f7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1995617690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1995617690 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1955380289 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 8581810 ps |
| CPU time | 1.23 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:10 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-b0191110-0680-4090-b29e-85ef7b3b2a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955380289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1955380289 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2910165204 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5618230923 ps |
| CPU time | 60.06 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-05931ffb-d3e2-48a0-ac53-2d9bd990c7b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910165204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2910165204 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.4040928773 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2917489754 ps |
| CPU time | 28.32 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-734dde11-f937-47d1-a279-3bf2dd5d1305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040928773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4040928773 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3070364893 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5551202400 ps |
| CPU time | 127.96 seconds |
| Started | Feb 18 12:50:03 PM PST 24 |
| Finished | Feb 18 12:52:18 PM PST 24 |
| Peak memory | 208352 kb |
| Host | smart-6be12550-ccf3-4361-961c-5fb1724c136b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070364893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3070364893 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.312542281 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 508543283 ps |
| CPU time | 9.97 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:17 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-d9d38e15-a37f-4bdd-805e-f17513401993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312542281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.312542281 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3913120074 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1260293997 ps |
| CPU time | 15.35 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:23 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-47c17c91-b8ec-418d-a7a7-fe47b197e859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3913120074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3913120074 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4054139624 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 230043562 ps |
| CPU time | 3.53 seconds |
| Started | Feb 18 12:49:59 PM PST 24 |
| Finished | Feb 18 12:50:09 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-95647e17-677c-4363-910a-e05c4663cc67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054139624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4054139624 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.576683745 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 730195366 ps |
| CPU time | 2.59 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:10 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-1689f75f-761b-4e01-8125-e98773cc4669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576683745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.576683745 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3042599658 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 673987253 ps |
| CPU time | 14.4 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:21 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-30b0da5d-bc1c-4c24-aed1-70806bacbb00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3042599658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3042599658 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1494501387 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 28822715869 ps |
| CPU time | 129.92 seconds |
| Started | Feb 18 12:49:58 PM PST 24 |
| Finished | Feb 18 12:52:14 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-771d42d7-cba2-41a0-9578-41c2e02e3fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494501387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1494501387 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.835230462 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 14842136638 ps |
| CPU time | 101.49 seconds |
| Started | Feb 18 12:50:03 PM PST 24 |
| Finished | Feb 18 12:51:52 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-1a1b2938-70d4-4fa4-b016-dc3b529f499f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=835230462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.835230462 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2881177388 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 32932578 ps |
| CPU time | 2.18 seconds |
| Started | Feb 18 12:50:05 PM PST 24 |
| Finished | Feb 18 12:50:15 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-07608dba-5702-4b44-a355-8b6e30f6ff5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881177388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2881177388 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.4274863807 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1281109324 ps |
| CPU time | 5.64 seconds |
| Started | Feb 18 12:50:01 PM PST 24 |
| Finished | Feb 18 12:50:14 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-0de85232-0158-4998-a881-198d04e80bae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4274863807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4274863807 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.3032744042 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20619259 ps |
| CPU time | 1.16 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-02d7d32c-ce3b-492e-843c-eebd5faec5ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3032744042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3032744042 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4173377184 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1756248329 ps |
| CPU time | 9.3 seconds |
| Started | Feb 18 12:50:03 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-099b084e-3cbb-430d-9ea6-3cec13240e5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173377184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4173377184 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1191217161 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1302539741 ps |
| CPU time | 8.59 seconds |
| Started | Feb 18 12:50:04 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-6fb0c108-b93b-45db-bb63-b540ec4bae17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1191217161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1191217161 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.451647568 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 32711854 ps |
| CPU time | 1.07 seconds |
| Started | Feb 18 12:50:00 PM PST 24 |
| Finished | Feb 18 12:50:08 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-fbf42939-cab4-4240-9bc2-1ce5683cb606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451647568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.451647568 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3789167880 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1149548500 ps |
| CPU time | 15.24 seconds |
| Started | Feb 18 12:49:59 PM PST 24 |
| Finished | Feb 18 12:50:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-9cf99f44-a80c-4906-8b1b-edddfa975e5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3789167880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3789167880 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2445519147 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 304893978 ps |
| CPU time | 23.21 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-0abaf594-0d02-4d32-a897-e0451ec823cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2445519147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2445519147 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1117859368 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 181378869 ps |
| CPU time | 8.06 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-cb80e313-6612-4ded-8711-e68fc23676f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117859368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1117859368 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3285435379 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 461742944 ps |
| CPU time | 34.1 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 203540 kb |
| Host | smart-4df657bc-429f-442d-b20d-d712c88f5eb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3285435379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3285435379 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1638512369 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1793856844 ps |
| CPU time | 12.03 seconds |
| Started | Feb 18 12:50:02 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-95498281-bb16-4985-af0c-da3c91f98a83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1638512369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1638512369 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1815156924 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 240885858 ps |
| CPU time | 2.46 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-979e7f5f-793c-49df-acfb-3c1bea606d01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815156924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1815156924 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3684910854 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 43391756638 ps |
| CPU time | 112.39 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:52:12 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-c6374ecf-6dff-4715-bdcf-9465fa052ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3684910854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3684910854 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2660969248 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 48407544 ps |
| CPU time | 4.2 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-09cc51d3-b9da-4422-8401-5f2de0faf38c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2660969248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2660969248 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.667624987 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 126830880 ps |
| CPU time | 2.84 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-f39deaed-fd3e-4eed-b4ea-20e537043a46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=667624987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.667624987 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3483579624 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 20141186 ps |
| CPU time | 2.71 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-bf971933-81e6-4403-81c5-4a4b934f2beb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3483579624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3483579624 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1229042274 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 144579335213 ps |
| CPU time | 129.66 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:52:28 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-04414a75-9021-4cb5-b7cc-aae4864e5314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229042274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1229042274 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3275201038 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5648013978 ps |
| CPU time | 40.9 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-9967868a-3ecf-4f35-991b-81ea25518310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3275201038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3275201038 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.328331648 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 192383939 ps |
| CPU time | 3.49 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:50:21 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-e5ad4f0b-6b44-467d-b63c-915855f1d1e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328331648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.328331648 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.876935812 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 22666317 ps |
| CPU time | 2.51 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-e6f23c54-ec4f-4fb7-b85c-bfbc11ffae46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=876935812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.876935812 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.3005557521 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 98737623 ps |
| CPU time | 1.36 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:17 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-64a59fdc-991c-4283-81fc-50340ea46be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005557521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3005557521 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1193561873 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4546933631 ps |
| CPU time | 10.09 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-382ddd43-5999-48ed-b961-eb6e2491d130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193561873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1193561873 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3307894021 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1732043122 ps |
| CPU time | 7.57 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:26 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-24a3a362-e995-4244-a929-034564d5189f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3307894021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3307894021 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.491494847 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 9296750 ps |
| CPU time | 1.24 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-211d5b22-8480-4106-abd0-cb994029a523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491494847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.491494847 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.946437144 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 416478364 ps |
| CPU time | 27.83 seconds |
| Started | Feb 18 12:50:05 PM PST 24 |
| Finished | Feb 18 12:50:41 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-74cd5e77-33ab-4445-a28a-11f34da471a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946437144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.946437144 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2072105724 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 119882102 ps |
| CPU time | 9.62 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:26 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-a78e6395-5d16-4694-bbcb-0db88d42e084 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2072105724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2072105724 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3821879581 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 20768072865 ps |
| CPU time | 365.66 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:56:23 PM PST 24 |
| Peak memory | 207292 kb |
| Host | smart-26a10dc0-c1c3-4ee6-9a51-636f6d3fc691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3821879581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3821879581 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3070985307 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 794888459 ps |
| CPU time | 87.68 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:51:44 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-fe8b1f02-07e6-4faf-8bc2-6a197c2fb7cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070985307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3070985307 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2522429938 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 70722247 ps |
| CPU time | 3.58 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-fc77d1d5-c329-4bde-b55a-334bbca99f38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522429938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2522429938 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3658481047 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 511824381 ps |
| CPU time | 7.55 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-1e8382ef-285d-4bc1-b07f-7decd413ec7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3658481047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3658481047 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1324804630 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 26793394980 ps |
| CPU time | 189.76 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:53:29 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-6a430d53-5187-467b-8e21-5dc58ac793a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1324804630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1324804630 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2739092452 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 173361505 ps |
| CPU time | 3.4 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-0efa5d7f-26f8-4c1f-aae0-5d8ffe4dcf6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2739092452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2739092452 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3812424356 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1984644227 ps |
| CPU time | 11.36 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-b5344dd7-6a3e-44a3-8a2f-d9173b1b1567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3812424356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3812424356 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.3390406023 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 185568877 ps |
| CPU time | 3.74 seconds |
| Started | Feb 18 12:50:06 PM PST 24 |
| Finished | Feb 18 12:50:17 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-a54ad290-2b2f-49a3-a7c4-46caaa356f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390406023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3390406023 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1519563976 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2187001724 ps |
| CPU time | 14.69 seconds |
| Started | Feb 18 12:50:08 PM PST 24 |
| Finished | Feb 18 12:50:31 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c0ac3493-ddcc-4696-8115-af8509c5711f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1519563976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1519563976 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.572394918 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 49557222 ps |
| CPU time | 1.82 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-26466355-1581-4dd4-beca-9047422f410d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572394918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.572394918 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2187458722 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 6108576820 ps |
| CPU time | 9.99 seconds |
| Started | Feb 18 12:50:05 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-8573b9cf-3769-47a6-bcaa-cd6ed874bfcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187458722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2187458722 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1781299898 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 8569747 ps |
| CPU time | 1.28 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:50:18 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-82fdaa3c-1355-4405-ad24-35df7140e104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1781299898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1781299898 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1557491350 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2587204672 ps |
| CPU time | 5.61 seconds |
| Started | Feb 18 12:50:07 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-e5582d72-8d35-4578-abbf-02ecd1d392a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557491350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1557491350 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1056485547 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2357400084 ps |
| CPU time | 11.05 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:50:29 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-cefea76a-3ce2-4f9c-b679-2f1e593397c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1056485547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1056485547 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3045015588 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 9111129 ps |
| CPU time | 1.01 seconds |
| Started | Feb 18 12:50:09 PM PST 24 |
| Finished | Feb 18 12:50:19 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-d6168844-0518-4bb4-9ce2-14df16edaea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045015588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3045015588 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3034095278 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 27899271554 ps |
| CPU time | 91.62 seconds |
| Started | Feb 18 12:50:14 PM PST 24 |
| Finished | Feb 18 12:51:51 PM PST 24 |
| Peak memory | 204660 kb |
| Host | smart-995059e5-ee5e-4973-abd8-20e498cef838 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034095278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3034095278 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2340384142 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 719571633 ps |
| CPU time | 11.79 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:30 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-69990246-4f84-42f0-bea1-55e05819418c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340384142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2340384142 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2489471165 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 15958730826 ps |
| CPU time | 219.74 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:53:59 PM PST 24 |
| Peak memory | 208328 kb |
| Host | smart-a51bec73-2786-4c12-a54d-de4ea734e519 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2489471165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2489471165 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.291045197 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1230439183 ps |
| CPU time | 103.45 seconds |
| Started | Feb 18 12:50:32 PM PST 24 |
| Finished | Feb 18 12:52:17 PM PST 24 |
| Peak memory | 204772 kb |
| Host | smart-b2bec162-a036-46dd-bf70-8bda2d6bdefe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291045197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res et_error.291045197 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1677433979 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 380027453 ps |
| CPU time | 7.23 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-f20053ab-cd8f-45cf-aa85-ed1da41d7b63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1677433979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1677433979 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.187543054 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 63981724 ps |
| CPU time | 8.27 seconds |
| Started | Feb 18 12:50:13 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-05ed061c-1d92-4295-a5c4-c5a996ce7bfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=187543054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.187543054 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1262721891 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 32832386 ps |
| CPU time | 3.63 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d3264084-2c86-4164-bf29-e181f04af134 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262721891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1262721891 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2337473426 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 186327461 ps |
| CPU time | 5.3 seconds |
| Started | Feb 18 12:50:32 PM PST 24 |
| Finished | Feb 18 12:50:39 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-d7c22767-c6c5-4176-9acc-cda53e9a6327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337473426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2337473426 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2497165669 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2760670530 ps |
| CPU time | 16.94 seconds |
| Started | Feb 18 12:50:32 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-0f6e57a4-edc7-4017-9c87-3418957ea1bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2497165669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2497165669 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3359798513 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 40423744978 ps |
| CPU time | 132.22 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:52:42 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-94249a30-9471-4d6e-8d5c-6b8902d4be37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359798513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3359798513 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.108490729 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 11760923561 ps |
| CPU time | 85.13 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:51:44 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-a0f812e4-8d87-478b-8d9c-04241d09c3c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=108490729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.108490729 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1448528791 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 92497690 ps |
| CPU time | 10.35 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:29 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-d7390983-4686-413d-a1af-c0aaaac9ff3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448528791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1448528791 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.4076083163 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 886212238 ps |
| CPU time | 5.99 seconds |
| Started | Feb 18 12:50:14 PM PST 24 |
| Finished | Feb 18 12:50:26 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3729a0d8-f481-4a50-9c25-04a1a9f85fb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4076083163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4076083163 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1355181506 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 302327209 ps |
| CPU time | 1.47 seconds |
| Started | Feb 18 12:50:32 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-c85e6e1a-2186-4bbf-b4c9-8c9e9f3e385b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1355181506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1355181506 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.469230306 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 6521589019 ps |
| CPU time | 7.41 seconds |
| Started | Feb 18 12:50:16 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-14dca6a2-5f9b-46d4-82ec-fb612b8d13ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=469230306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.469230306 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2824050867 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2316686750 ps |
| CPU time | 7.69 seconds |
| Started | Feb 18 12:50:13 PM PST 24 |
| Finished | Feb 18 12:50:27 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-324356ba-3e26-408c-b6bf-c496f0aa1ed4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2824050867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2824050867 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2005960916 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 10997111 ps |
| CPU time | 1.11 seconds |
| Started | Feb 18 12:50:14 PM PST 24 |
| Finished | Feb 18 12:50:21 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-f0b531e1-894c-4078-be1c-3cf8bea7d271 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005960916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2005960916 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1828420521 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 111229569 ps |
| CPU time | 11.8 seconds |
| Started | Feb 18 12:50:15 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-eb0a0018-f442-4b48-823d-7ac3d8b95afa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1828420521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1828420521 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3071757630 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7206444265 ps |
| CPU time | 58.04 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:51:17 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-79e180bd-c2d8-4137-9196-4064dc70fe86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3071757630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3071757630 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3056736945 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5882052679 ps |
| CPU time | 103.57 seconds |
| Started | Feb 18 12:50:33 PM PST 24 |
| Finished | Feb 18 12:52:18 PM PST 24 |
| Peak memory | 206264 kb |
| Host | smart-7e91738b-8a1c-48cf-bf7c-a42871941b05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056736945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.3056736945 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.940750093 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1022718404 ps |
| CPU time | 18.4 seconds |
| Started | Feb 18 12:50:20 PM PST 24 |
| Finished | Feb 18 12:50:40 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-47597e81-ab99-44e3-a63b-797bbbb3384e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=940750093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.940750093 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1940197305 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 29275497 ps |
| CPU time | 1.21 seconds |
| Started | Feb 18 12:50:24 PM PST 24 |
| Finished | Feb 18 12:50:26 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-7b56ca6b-7926-4575-8f60-2845eabffc7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940197305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1940197305 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2250043176 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 34764619 ps |
| CPU time | 3.39 seconds |
| Started | Feb 18 12:50:22 PM PST 24 |
| Finished | Feb 18 12:50:27 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-b83f8f1f-d6a0-47be-bfd6-a00e485d2109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250043176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2250043176 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3858602845 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1676167687 ps |
| CPU time | 16.47 seconds |
| Started | Feb 18 12:50:15 PM PST 24 |
| Finished | Feb 18 12:50:37 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-75f5ce80-2765-4df6-991e-be771f2280e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3858602845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3858602845 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.778462705 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 17748996681 ps |
| CPU time | 81.7 seconds |
| Started | Feb 18 12:50:12 PM PST 24 |
| Finished | Feb 18 12:51:41 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-13111ccb-97e8-4db8-9b1b-ddd6aef59fb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=778462705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.778462705 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.958636604 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 15649523696 ps |
| CPU time | 67.13 seconds |
| Started | Feb 18 12:50:15 PM PST 24 |
| Finished | Feb 18 12:51:27 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-410ecca0-6d9d-4192-b8ec-9c447b6802dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=958636604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.958636604 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1028254062 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 180618606 ps |
| CPU time | 6.93 seconds |
| Started | Feb 18 12:50:17 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-d70ab04d-0d0e-4253-8c2b-ebf846dc1726 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028254062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1028254062 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.3914625464 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3783008304 ps |
| CPU time | 8.41 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:50:37 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-a09677e5-9aa0-4bc9-98e1-29e3126b8e77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3914625464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3914625464 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1893819572 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 9866793 ps |
| CPU time | 1.38 seconds |
| Started | Feb 18 12:50:13 PM PST 24 |
| Finished | Feb 18 12:50:21 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c669e62c-7d6d-4494-8933-b58ec31460cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1893819572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1893819572 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3249743299 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3567222241 ps |
| CPU time | 7.23 seconds |
| Started | Feb 18 12:50:10 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-a6ff6187-c777-458f-a631-d666e272e778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249743299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3249743299 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3843500068 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1365681569 ps |
| CPU time | 9.52 seconds |
| Started | Feb 18 12:50:33 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-02edd9a0-d139-4609-b992-15f2b6674505 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3843500068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3843500068 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1915540135 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 32297732 ps |
| CPU time | 1.16 seconds |
| Started | Feb 18 12:50:11 PM PST 24 |
| Finished | Feb 18 12:50:20 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-58b45485-c866-4b03-9f85-3fa2a1a95c1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915540135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1915540135 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1279493517 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 378884104 ps |
| CPU time | 11.88 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:50:41 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-1f88dc45-1284-45d1-a1d6-3b8f9219a7bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279493517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1279493517 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3011571069 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 756764563 ps |
| CPU time | 21.6 seconds |
| Started | Feb 18 12:50:22 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-3fc31054-f11e-4ebd-a7e6-899cacdd4ad9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3011571069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3011571069 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3194320100 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 495967096 ps |
| CPU time | 98.65 seconds |
| Started | Feb 18 12:50:18 PM PST 24 |
| Finished | Feb 18 12:51:59 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-fb398944-a11d-4779-9eca-a327fe3c8451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3194320100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3194320100 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1492958433 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 299607471 ps |
| CPU time | 19.98 seconds |
| Started | Feb 18 12:50:20 PM PST 24 |
| Finished | Feb 18 12:50:41 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-ec82f941-1aaf-4059-b0ff-8502a02b6661 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492958433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1492958433 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1132007913 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2634534760 ps |
| CPU time | 5.67 seconds |
| Started | Feb 18 12:50:22 PM PST 24 |
| Finished | Feb 18 12:50:29 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-cef646f9-4c5e-4649-91d3-9856c95affd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1132007913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1132007913 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3191334849 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 215152993 ps |
| CPU time | 12.41 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-6f9b4141-7c30-4f2f-ab01-f29bee604a50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191334849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3191334849 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2001831748 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 254168666654 ps |
| CPU time | 292.86 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:53:09 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-36a55e19-de33-47a1-81fd-ce7a15fe9c4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2001831748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2001831748 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3219117659 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1009438576 ps |
| CPU time | 9.68 seconds |
| Started | Feb 18 12:48:08 PM PST 24 |
| Finished | Feb 18 12:48:28 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-c87f1c6c-29e0-4bc8-9b38-6b76b24af8e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3219117659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3219117659 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.1485108937 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 78682482 ps |
| CPU time | 7.55 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:28 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-f0cbd766-dc67-45de-9989-0ed9b8ea8d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485108937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1485108937 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2154031337 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 26667696420 ps |
| CPU time | 58.03 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:49:13 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-cb71c54a-6097-4e19-8bae-fee491545b42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154031337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2154031337 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1306963945 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 27612801308 ps |
| CPU time | 93.1 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:49:50 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-623f8dde-31ea-4e8f-be1e-54d9e8481b68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1306963945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1306963945 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3750037141 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 53769744 ps |
| CPU time | 8.02 seconds |
| Started | Feb 18 12:48:04 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-8d9708e9-a522-4fd4-935f-b8f01c1f73b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750037141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3750037141 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.918092662 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1983438898 ps |
| CPU time | 10.25 seconds |
| Started | Feb 18 12:48:03 PM PST 24 |
| Finished | Feb 18 12:48:25 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-a5c98ea9-2fc9-4e79-bd6f-31f47430079f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918092662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.918092662 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.1690624671 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 13481766 ps |
| CPU time | 1.34 seconds |
| Started | Feb 18 12:48:03 PM PST 24 |
| Finished | Feb 18 12:48:16 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-b610b060-5ec7-445a-b870-e6d2698c7b05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690624671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1690624671 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.851546708 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6937651809 ps |
| CPU time | 11.82 seconds |
| Started | Feb 18 12:48:06 PM PST 24 |
| Finished | Feb 18 12:48:29 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-0ddfc454-ecf9-45b3-a8e1-0770e959a774 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=851546708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.851546708 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2100050608 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1677160498 ps |
| CPU time | 7.84 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-835d7367-4ac8-4757-9770-0a7a1297b72d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2100050608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2100050608 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1315139089 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 9409978 ps |
| CPU time | 1.26 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:48:17 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-72d00e04-a385-45bd-832d-382ace0fc2d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315139089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1315139089 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1658435099 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 263837577 ps |
| CPU time | 26.17 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:45 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-8273f231-f2be-4465-947b-1a0c1fc7ff7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658435099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1658435099 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2979657304 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 312615422 ps |
| CPU time | 36.69 seconds |
| Started | Feb 18 12:48:08 PM PST 24 |
| Finished | Feb 18 12:48:55 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-b8962305-bd48-4d12-a9ef-f3fe952a8227 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979657304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2979657304 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2107317151 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4739415661 ps |
| CPU time | 112.65 seconds |
| Started | Feb 18 12:48:05 PM PST 24 |
| Finished | Feb 18 12:50:09 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-e02a7915-a1dc-496a-89cd-e06ae0c31916 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2107317151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2107317151 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.185255712 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 407703240 ps |
| CPU time | 44.49 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:49:04 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-cdd8eb4b-e27e-4eba-bc6c-f590499fda54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=185255712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.185255712 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2374705654 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21149061 ps |
| CPU time | 2.86 seconds |
| Started | Feb 18 12:48:15 PM PST 24 |
| Finished | Feb 18 12:48:24 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-6dd26f43-a0f9-485d-8776-32ea999a3ab9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2374705654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2374705654 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1515306577 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 39258112 ps |
| CPU time | 8.24 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-6cfd5b45-9fe0-4280-bdf7-3b027e57e8a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515306577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1515306577 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2239857639 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 138967333551 ps |
| CPU time | 146.44 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:52:54 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-a172ae63-27e7-4540-acb1-ef8d64fb7534 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2239857639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2239857639 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3725773821 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 430115700 ps |
| CPU time | 7.52 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:50:37 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-58413a9c-3251-4b4a-ac7d-de7e4e515156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3725773821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3725773821 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.408150177 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 905997637 ps |
| CPU time | 16.2 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:43 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-57828cae-75c5-42f3-9686-042ee3fc6787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=408150177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.408150177 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3192645833 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 939899406 ps |
| CPU time | 11.58 seconds |
| Started | Feb 18 12:50:33 PM PST 24 |
| Finished | Feb 18 12:50:46 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-43fb5033-3681-4423-bdf3-8d84480ad99a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3192645833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3192645833 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.646928888 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 47411158105 ps |
| CPU time | 110.15 seconds |
| Started | Feb 18 12:50:19 PM PST 24 |
| Finished | Feb 18 12:52:11 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-88af5d5c-7d94-4f97-942f-fdce3ed821b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=646928888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.646928888 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2072212285 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 10695886223 ps |
| CPU time | 74.85 seconds |
| Started | Feb 18 12:50:24 PM PST 24 |
| Finished | Feb 18 12:51:40 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-2f14fe47-e500-480f-9064-ee2ba69d9a9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2072212285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2072212285 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1560323771 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 30900906 ps |
| CPU time | 3.99 seconds |
| Started | Feb 18 12:50:18 PM PST 24 |
| Finished | Feb 18 12:50:25 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-59da2539-1287-47e8-a7c4-13746c8a3a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560323771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1560323771 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.960136558 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 354666503 ps |
| CPU time | 4.4 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-b8d00d99-86af-45d6-bf6a-a745d0258d34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960136558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.960136558 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1463168571 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 52812816 ps |
| CPU time | 1.36 seconds |
| Started | Feb 18 12:50:19 PM PST 24 |
| Finished | Feb 18 12:50:22 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-d3249b52-832d-4103-8d68-f7ea1632d40d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1463168571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1463168571 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.568654087 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 9621369540 ps |
| CPU time | 8.44 seconds |
| Started | Feb 18 12:50:23 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-ac90469a-bea0-4866-bf4f-cc0092505af1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=568654087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.568654087 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.544963562 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 931896091 ps |
| CPU time | 6.76 seconds |
| Started | Feb 18 12:50:24 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-6eadb49b-99ea-477c-b15f-bfe596324423 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=544963562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.544963562 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.596733764 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 9571288 ps |
| CPU time | 1.24 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-65e867a2-e073-424b-8c2e-631cc72abf3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596733764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.596733764 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2539826138 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5372979457 ps |
| CPU time | 46.58 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:51:13 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-74be973d-3b7c-411a-981a-a1b2120ce8d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539826138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2539826138 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3967023517 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 856504094 ps |
| CPU time | 44.16 seconds |
| Started | Feb 18 12:50:28 PM PST 24 |
| Finished | Feb 18 12:51:14 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-ddcfcc86-9cab-48a6-906f-0cb12faebc27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967023517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3967023517 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4169025792 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 281106851 ps |
| CPU time | 40.93 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:51:10 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-06c5df08-ed1d-4a00-b3cc-ae8737c1c24d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4169025792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.4169025792 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1812110484 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1865019064 ps |
| CPU time | 58.26 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:51:25 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-05989eb2-82a0-4565-a0cc-4e4a14db834a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1812110484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1812110484 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1922199704 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 69569257 ps |
| CPU time | 4.67 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-197d550e-d8eb-448f-816c-bc801eeb7d28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1922199704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1922199704 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.503749650 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 312515463 ps |
| CPU time | 5.63 seconds |
| Started | Feb 18 12:50:34 PM PST 24 |
| Finished | Feb 18 12:50:41 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-81f1f301-e8c3-4fb2-ab1a-c3c2d9d11d24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503749650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.503749650 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3331466407 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 69907340959 ps |
| CPU time | 278.9 seconds |
| Started | Feb 18 12:50:34 PM PST 24 |
| Finished | Feb 18 12:55:14 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-2cda0a19-2972-457f-93ec-693683cf156e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3331466407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3331466407 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.808596400 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 533683671 ps |
| CPU time | 7.44 seconds |
| Started | Feb 18 12:50:38 PM PST 24 |
| Finished | Feb 18 12:50:48 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ec0e8060-cde4-4ee0-a4e8-075c443eec1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808596400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.808596400 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1293565217 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 818977549 ps |
| CPU time | 6.43 seconds |
| Started | Feb 18 12:50:33 PM PST 24 |
| Finished | Feb 18 12:50:41 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-a4f32418-2690-492b-8faf-59446fd5af96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1293565217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1293565217 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2021715479 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 814861299 ps |
| CPU time | 13.32 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-7d936034-5d77-4f3b-9712-508ad645d72d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2021715479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2021715479 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3588274128 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 88313648827 ps |
| CPU time | 83.79 seconds |
| Started | Feb 18 12:50:26 PM PST 24 |
| Finished | Feb 18 12:51:51 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-d9ea1eba-737c-4641-b88d-24500aac082c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588274128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3588274128 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3970121275 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 24390675896 ps |
| CPU time | 114.81 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:52:34 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-470a104b-c367-4270-8b40-6f4f4d3e5f1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3970121275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3970121275 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3569631560 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 315968523 ps |
| CPU time | 6.25 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-55438aa9-e099-4a88-b467-7a5ce7ed9094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569631560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3569631560 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2556768851 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 48309648 ps |
| CPU time | 2.48 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:50:40 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-1d19697e-0d83-4ca0-b2a7-bac9bb325a73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2556768851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2556768851 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3265316749 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9724294 ps |
| CPU time | 1.24 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-84240758-4348-4b83-b131-d1d6d986325d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265316749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3265316749 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.765997687 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 9151271044 ps |
| CPU time | 7.35 seconds |
| Started | Feb 18 12:50:27 PM PST 24 |
| Finished | Feb 18 12:50:36 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-78cc49da-b93b-45b8-adf3-eb8d429612db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=765997687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.765997687 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2354598464 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2202079348 ps |
| CPU time | 7.69 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:35 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-b216e3c1-694e-4fe6-9ee8-310bd894dfef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2354598464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2354598464 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3971493346 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 9267187 ps |
| CPU time | 1.34 seconds |
| Started | Feb 18 12:50:25 PM PST 24 |
| Finished | Feb 18 12:50:28 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-fabf020b-2e28-4b42-9a17-2399d5049ec7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971493346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3971493346 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.14161753 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 433183178 ps |
| CPU time | 21.33 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-1c23abf2-0744-4716-aaed-6413b7022aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=14161753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.14161753 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.964620372 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 102218661 ps |
| CPU time | 13.59 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-549eab40-7167-4977-b7c8-4a4a8f304933 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=964620372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.964620372 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2971269824 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 641694366 ps |
| CPU time | 72.7 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:51:52 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-968cc15f-e903-45d7-b0d2-b339fdb59fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971269824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2971269824 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2850667205 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4122540872 ps |
| CPU time | 71.57 seconds |
| Started | Feb 18 12:50:34 PM PST 24 |
| Finished | Feb 18 12:51:47 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-0b993400-7639-4161-aa6e-e9dd0c66707e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850667205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2850667205 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3287762077 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 427758324 ps |
| CPU time | 7.84 seconds |
| Started | Feb 18 12:50:35 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-968dc95a-f245-471e-94ca-bfce16ba1a2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3287762077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3287762077 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2323175067 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1296890203 ps |
| CPU time | 19.66 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-029f802d-8124-49f6-b9b5-f8bbef2a448e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323175067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2323175067 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1540470034 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 25526864394 ps |
| CPU time | 178.48 seconds |
| Started | Feb 18 12:50:40 PM PST 24 |
| Finished | Feb 18 12:53:40 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-ff5c86ea-0438-4fd9-b013-0f065df60209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1540470034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.1540470034 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4009670637 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1164005851 ps |
| CPU time | 11.05 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-2f866ead-d3b1-491c-81d7-2cfe8ea877ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4009670637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4009670637 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.4238994990 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 574997929 ps |
| CPU time | 9.76 seconds |
| Started | Feb 18 12:50:38 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-a3a41156-2c73-409d-9b8b-a259274bd32c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4238994990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4238994990 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.3514852481 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 536183512 ps |
| CPU time | 9.41 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:50:47 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b967762a-3fcd-4da0-9924-309786f1953a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3514852481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3514852481 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1831585469 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5990884316 ps |
| CPU time | 31.7 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:51:09 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-2aa5912e-2e2a-4c50-af10-6a934bb41014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1831585469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1831585469 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.999749187 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 52463827 ps |
| CPU time | 3.82 seconds |
| Started | Feb 18 12:50:35 PM PST 24 |
| Finished | Feb 18 12:50:40 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-ad4bcc4f-cfdd-4ab1-bdcf-84304abcaf63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999749187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.999749187 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3052435856 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 314629525 ps |
| CPU time | 3.93 seconds |
| Started | Feb 18 12:50:32 PM PST 24 |
| Finished | Feb 18 12:50:38 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-2175b39a-9e5c-4a11-9e38-2b3ae075a1c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3052435856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3052435856 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.4060813868 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 45245533 ps |
| CPU time | 1.37 seconds |
| Started | Feb 18 12:50:38 PM PST 24 |
| Finished | Feb 18 12:50:42 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-315e76ee-04f8-4aa0-9fda-c5907492c304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060813868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4060813868 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2480384123 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3200959957 ps |
| CPU time | 11.79 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-1e249d02-877a-46cf-bfbe-5f1e7379ceba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480384123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2480384123 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1652571375 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 985205758 ps |
| CPU time | 6.56 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-0f666b54-8ed5-45eb-9b2d-9c458bd31a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1652571375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1652571375 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4085318116 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 10242678 ps |
| CPU time | 1.09 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:50:40 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-bf094694-39aa-47b3-8e14-c58aae9f7120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085318116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4085318116 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4028695775 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2075969715 ps |
| CPU time | 61.81 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:51:40 PM PST 24 |
| Peak memory | 206208 kb |
| Host | smart-66b82427-8b52-4dbc-9c2a-ab0a940a7fda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4028695775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4028695775 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2327047051 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 44470632 ps |
| CPU time | 3.62 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:46 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-60813ed7-9513-4437-b6ac-e009045916f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327047051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2327047051 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3990729988 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 521726098 ps |
| CPU time | 50.69 seconds |
| Started | Feb 18 12:50:37 PM PST 24 |
| Finished | Feb 18 12:51:30 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-e444976e-4859-45b6-995c-d573e50b26f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3990729988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3990729988 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1717923808 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 209449066 ps |
| CPU time | 29.96 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:51:17 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-6716e674-a31e-47cb-8d47-e043f1b380a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1717923808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1717923808 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2694678300 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 419093610 ps |
| CPU time | 7.67 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-f03f7961-94e7-4a5f-a268-f54afb53f186 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694678300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2694678300 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.767604140 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 13131167 ps |
| CPU time | 2.22 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:50:52 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-755b8c5d-a5a6-4110-8716-7426921a789d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=767604140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.767604140 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3054210447 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8265024259 ps |
| CPU time | 41.62 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:51:24 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-0a33c7dd-7b2f-490a-ba60-d76ba867d158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3054210447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3054210447 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2560333988 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 96188008 ps |
| CPU time | 1.64 seconds |
| Started | Feb 18 12:50:40 PM PST 24 |
| Finished | Feb 18 12:50:43 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-cddde375-dcc0-4a44-8a52-8373cf487172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2560333988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2560333988 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3534861573 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 761610418 ps |
| CPU time | 11.96 seconds |
| Started | Feb 18 12:50:47 PM PST 24 |
| Finished | Feb 18 12:51:01 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-9bf5f595-ff9e-4f23-9a83-60bf32fb1177 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534861573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3534861573 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3518358993 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 239116189 ps |
| CPU time | 3.58 seconds |
| Started | Feb 18 12:50:38 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-40317015-fdfb-4bc8-8fcb-8c33c62ae519 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3518358993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3518358993 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2113757821 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 72368935942 ps |
| CPU time | 176.09 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:53:38 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-f526d221-378e-4af3-8f08-19b91c9b2c85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113757821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2113757821 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3568145312 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 16793847059 ps |
| CPU time | 83.55 seconds |
| Started | Feb 18 12:50:36 PM PST 24 |
| Finished | Feb 18 12:52:01 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-decf57cd-0e00-46bd-a09d-19d186df8878 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3568145312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3568145312 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2307184152 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 57300991 ps |
| CPU time | 3.48 seconds |
| Started | Feb 18 12:50:40 PM PST 24 |
| Finished | Feb 18 12:50:45 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-54f32a3c-0742-43d9-aa12-670191982043 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307184152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2307184152 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.2614797936 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 973450615 ps |
| CPU time | 7.99 seconds |
| Started | Feb 18 12:50:45 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-d30405e4-93e1-49e9-8a04-a2bd5e701188 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2614797936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2614797936 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3056263408 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 53347024 ps |
| CPU time | 1.25 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-f973782a-fc88-455f-b583-5b1c316edcdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056263408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3056263408 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1367450458 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4839289450 ps |
| CPU time | 10.07 seconds |
| Started | Feb 18 12:50:42 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-abf5c9fe-bdbc-41a9-8536-4db5caff8150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367450458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1367450458 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3562734073 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 7642341633 ps |
| CPU time | 9 seconds |
| Started | Feb 18 12:50:38 PM PST 24 |
| Finished | Feb 18 12:50:49 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-2c63da0c-721a-448a-a006-7c73c6370a5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3562734073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3562734073 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3312800135 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11022499 ps |
| CPU time | 1.18 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-aac59993-377a-43e4-86a2-984b616b5c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312800135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3312800135 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1496490338 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 719783094 ps |
| CPU time | 11.81 seconds |
| Started | Feb 18 12:50:45 PM PST 24 |
| Finished | Feb 18 12:51:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-a2a08bed-135a-4378-a336-51841dc6981d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496490338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1496490338 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1755410780 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 101849408 ps |
| CPU time | 9.6 seconds |
| Started | Feb 18 12:50:42 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-faf9f295-d36f-4438-b15c-a855f77f683f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1755410780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1755410780 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2646625866 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 6184801748 ps |
| CPU time | 75.84 seconds |
| Started | Feb 18 12:50:42 PM PST 24 |
| Finished | Feb 18 12:51:59 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-30379243-0c93-422b-996a-b94d9ad58211 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646625866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2646625866 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1346711011 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 92929610 ps |
| CPU time | 22.89 seconds |
| Started | Feb 18 12:50:39 PM PST 24 |
| Finished | Feb 18 12:51:05 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-95b2b529-2ee5-412c-a279-e19409cc5ff1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1346711011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1346711011 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.4090234196 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 220016861 ps |
| CPU time | 3.37 seconds |
| Started | Feb 18 12:50:43 PM PST 24 |
| Finished | Feb 18 12:50:48 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-d143bbd1-0da0-453e-bcce-c1f3edb82c6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090234196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4090234196 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3969827703 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 262795010 ps |
| CPU time | 6.41 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-cbb6be2f-6e70-4423-b37d-75807beffa7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969827703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3969827703 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.48017976 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 117057972589 ps |
| CPU time | 170.56 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:53:40 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-3819b357-d80d-46d8-95b8-bb488f3ec568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=48017976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow _rsp.48017976 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.886499040 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 68091478 ps |
| CPU time | 3.33 seconds |
| Started | Feb 18 12:50:43 PM PST 24 |
| Finished | Feb 18 12:50:49 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-31800730-fe35-4c5e-9f41-c5dcc7c2ce1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=886499040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.886499040 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.4127585036 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 179564480 ps |
| CPU time | 8.56 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:50:58 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-f0cf763a-1bfe-418a-90c4-102f9d40a0ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127585036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4127585036 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.798815197 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1388445753 ps |
| CPU time | 10.56 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:54 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-77a27f3a-a391-4325-85a5-f1fe5606cb6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798815197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.798815197 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.694495537 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 25767980891 ps |
| CPU time | 63.84 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:51:57 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-9ed53f5f-9ede-4e88-ba58-7eb0a28b094e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=694495537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.694495537 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1901003688 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 18092828385 ps |
| CPU time | 111.87 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:52:41 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-c83bf6ca-a32b-4df0-b976-8a41def8cba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1901003688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1901003688 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3725669595 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 45092124 ps |
| CPU time | 2.8 seconds |
| Started | Feb 18 12:50:43 PM PST 24 |
| Finished | Feb 18 12:50:48 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-5e0597c6-2b05-41ed-8446-23b739a1e973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725669595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3725669595 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1510273139 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 499540830 ps |
| CPU time | 6.75 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-0c1e7e69-447d-4274-91b0-f6548902bcaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1510273139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1510273139 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3831256254 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 91727102 ps |
| CPU time | 1.47 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:44 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-04b5010c-f097-4452-b090-2b2d87e2b2c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3831256254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3831256254 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.4066376680 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6418884622 ps |
| CPU time | 11.17 seconds |
| Started | Feb 18 12:50:41 PM PST 24 |
| Finished | Feb 18 12:50:54 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-016eea6c-4d20-41a0-ac98-64989b879889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066376680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.4066376680 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3880533899 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 742332835 ps |
| CPU time | 4.99 seconds |
| Started | Feb 18 12:50:39 PM PST 24 |
| Finished | Feb 18 12:50:46 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-316d7cc0-abc7-4970-93c1-a7d14324ee97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3880533899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3880533899 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4159271646 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 23197504 ps |
| CPU time | 1.27 seconds |
| Started | Feb 18 12:50:35 PM PST 24 |
| Finished | Feb 18 12:50:38 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-20684034-25ff-487a-a7c0-6403499e91ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159271646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4159271646 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.358358193 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 254012523 ps |
| CPU time | 1.65 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:50:51 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-7e15a684-fc5f-481a-a65e-15cb885e7fa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=358358193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.358358193 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1484897245 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1422287034 ps |
| CPU time | 12.24 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-10bc19ba-0176-43f7-bced-78379388373a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484897245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1484897245 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4284129886 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 17288449592 ps |
| CPU time | 178.38 seconds |
| Started | Feb 18 12:50:45 PM PST 24 |
| Finished | Feb 18 12:53:46 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-eebc826a-1642-4e9c-a4bd-ccd72566b336 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4284129886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.4284129886 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.954174098 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 682271794 ps |
| CPU time | 108.39 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:52:41 PM PST 24 |
| Peak memory | 207128 kb |
| Host | smart-2f5c5d03-de98-4181-9d06-6cb1f7c8398b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=954174098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.954174098 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2221836834 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 36930834 ps |
| CPU time | 2.26 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:50:52 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-0a7937f9-7741-4671-9894-aa2cc50d3e3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221836834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2221836834 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2709431426 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 36472706 ps |
| CPU time | 5.34 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-48ffb2a8-6322-41a7-b920-56f99fa1bda4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2709431426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2709431426 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3236801760 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 73780418343 ps |
| CPU time | 306.38 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:55:53 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-6fb523cc-84e3-4add-8486-cb5725b28438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3236801760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3236801760 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.918588184 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 10291073 ps |
| CPU time | 1.15 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-202ef238-5fba-4c6d-b987-66f5549d718a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918588184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.918588184 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2980382278 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 47873094 ps |
| CPU time | 3.94 seconds |
| Started | Feb 18 12:50:47 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-46d12d3b-10e7-4a7f-9383-91111936924a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2980382278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2980382278 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.2149766019 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 148695072 ps |
| CPU time | 3.69 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-b5dada51-04e2-49c3-8e10-64f3f52949b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149766019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2149766019 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1084428402 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 82971084498 ps |
| CPU time | 154.92 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:53:24 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ca306074-17c3-4a27-b705-514b7b435e50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084428402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1084428402 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.768367491 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 33386976683 ps |
| CPU time | 53.25 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:51:42 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-85eb299c-a6cd-4836-b900-995ca694529d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=768367491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.768367491 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3523057601 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 85930239 ps |
| CPU time | 5.71 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-d06123a5-e9c1-42f3-bd7a-024fff203b4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523057601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3523057601 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.85382127 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 49985051 ps |
| CPU time | 5.93 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-41d4ec09-6c82-44c4-a45c-b9511ff1ef35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85382127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.85382127 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2386184988 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 13996328 ps |
| CPU time | 1.03 seconds |
| Started | Feb 18 12:50:47 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-20c9e039-80ae-4bb4-85f4-e5209eeabee9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2386184988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2386184988 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1102171427 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 8171525810 ps |
| CPU time | 12.13 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:51:05 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-ebadd6c2-71a2-4c12-817f-ee80d3db5795 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102171427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1102171427 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.207421864 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 6832883902 ps |
| CPU time | 12.77 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-5c1b9c6c-2463-4ff0-8118-8ecdf77e89e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=207421864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.207421864 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.586834687 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 8389273 ps |
| CPU time | 1.18 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-0e45992c-e7a6-4069-aa73-42bfb38cfe50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586834687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.586834687 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1714615622 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5636638080 ps |
| CPU time | 56.28 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:51:43 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-c0cc418f-ef34-4d76-b872-2b24c39d0d14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714615622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1714615622 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1838940587 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2630198668 ps |
| CPU time | 39.54 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:51:25 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-80a77f1c-a5a7-4da7-a0ce-058a7f7a1636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1838940587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1838940587 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1599998739 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 13286830477 ps |
| CPU time | 138.01 seconds |
| Started | Feb 18 12:50:44 PM PST 24 |
| Finished | Feb 18 12:53:05 PM PST 24 |
| Peak memory | 206476 kb |
| Host | smart-a89fa8dd-ff5c-407d-9bf0-c181edbc48e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1599998739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1599998739 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3565655846 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1058391981 ps |
| CPU time | 45.31 seconds |
| Started | Feb 18 12:50:48 PM PST 24 |
| Finished | Feb 18 12:51:35 PM PST 24 |
| Peak memory | 204356 kb |
| Host | smart-93986cc1-8b6a-4fc8-b988-950d63211989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3565655846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3565655846 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.4211234431 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 41998172 ps |
| CPU time | 4.41 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-d73ae659-04bd-4127-a719-38f03f5f6ceb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4211234431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4211234431 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3644268431 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 37760123 ps |
| CPU time | 2.26 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:50:58 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-c3dc20af-3207-4d69-9573-eb4f305c31ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644268431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3644268431 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2995840873 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 130121244 ps |
| CPU time | 6.59 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:10 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-709b17f0-3fd1-4d2d-a4bd-20dd1ea579c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2995840873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2995840873 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1129027551 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 149434553 ps |
| CPU time | 3.62 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-fe8ff115-9ca1-4366-9e9e-052dc0ac7a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129027551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1129027551 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.55339899 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 44723756 ps |
| CPU time | 3.12 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:50:58 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-ac91b8c9-b5b0-49d4-b822-5579f22f8747 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=55339899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.55339899 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2623694679 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 54876114941 ps |
| CPU time | 146.57 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:53:20 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-6e1dd848-1433-4849-9373-6e6ad1526439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623694679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2623694679 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3273757095 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5762004692 ps |
| CPU time | 41.19 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:51:35 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-30b54410-de16-4384-94d9-ecf07a4f8b3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3273757095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3273757095 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3448948801 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 113533285 ps |
| CPU time | 3.31 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:50:58 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-54ae6f6a-2c07-417d-b10b-4595692021f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448948801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3448948801 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2396839294 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1211709710 ps |
| CPU time | 13.32 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:51:07 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-1dbd17a2-6755-41fe-9b05-3998c98db8d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2396839294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2396839294 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.1055258186 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 45807961 ps |
| CPU time | 1.48 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:50:55 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-d79029db-21eb-4009-a390-455a1a72f33b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055258186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1055258186 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1282560473 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1550386753 ps |
| CPU time | 7.38 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:51:00 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-4e9015fc-49b2-44ad-824c-e7116d580ca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282560473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1282560473 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1322898348 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1322666541 ps |
| CPU time | 9.23 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:51:04 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-f158c0c6-3521-4100-9f3d-3d6a14acc456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1322898348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1322898348 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3931047673 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 20701607 ps |
| CPU time | 1.42 seconds |
| Started | Feb 18 12:50:46 PM PST 24 |
| Finished | Feb 18 12:50:50 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-60bee9e6-b34d-470b-9de6-9c1c59db5b3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931047673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3931047673 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3538316839 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 11049054904 ps |
| CPU time | 46.84 seconds |
| Started | Feb 18 12:50:49 PM PST 24 |
| Finished | Feb 18 12:51:39 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-f4d03972-f475-4bcc-ac4b-714c67f7275e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538316839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3538316839 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.110274215 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 420343591 ps |
| CPU time | 20.99 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:51:17 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-e8864546-3dd3-4538-bee6-ba6b8df7d085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=110274215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.110274215 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.743782085 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 299610905 ps |
| CPU time | 49 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:51:43 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-091b76e7-9ba4-4915-a694-6636b729ec7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=743782085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.743782085 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2328797075 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 225833709 ps |
| CPU time | 37.01 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:41 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-291edd79-ebb2-449f-b2f1-b982cf5cfff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2328797075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2328797075 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.3581196759 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 137986403 ps |
| CPU time | 2.71 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-71ef02fd-f6a0-4515-8cc6-20563a3bc5fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3581196759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3581196759 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1507972493 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 139023205 ps |
| CPU time | 7.4 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:51:02 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-cc5cbbe9-c2d6-425a-8ab0-0178e36eab28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507972493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1507972493 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2347077920 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 14119398538 ps |
| CPU time | 98.67 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:52:32 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-770514e2-1da9-43c2-b0a3-682d768bf5ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2347077920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2347077920 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2035207899 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 46531331 ps |
| CPU time | 3.01 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:07 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-386dce99-8bac-44ee-b7bd-473dffc2de0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2035207899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2035207899 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.230215381 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 91123864 ps |
| CPU time | 6.45 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:51:01 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-942ba013-d36e-47f1-a104-2876a8425419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230215381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.230215381 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2218920399 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 287837728 ps |
| CPU time | 4.59 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-556afc0a-f6c7-445b-9630-a817a3f3e2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2218920399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2218920399 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1847927176 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 17356495052 ps |
| CPU time | 60.85 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:51:56 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-25484b7e-cd37-4a31-8259-0e812fa68d7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847927176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1847927176 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2703844818 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 16578423278 ps |
| CPU time | 59.71 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:51:55 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-8359a341-a01c-45d8-9fc6-12287bc74432 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2703844818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2703844818 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.4180124433 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 81208112 ps |
| CPU time | 5 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:51:00 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-2ce94dc4-f8b4-4000-80bd-e22093369c57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180124433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4180124433 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3142471043 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3266437363 ps |
| CPU time | 7.38 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:11 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-7e554d4e-3cef-421f-bb91-d3d794c6cfae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142471043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3142471043 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.1573180269 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 100518958 ps |
| CPU time | 1.54 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:50:55 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-5ed5b326-7689-4b03-af21-20dfe0b9c3e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573180269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1573180269 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1084764877 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3514939760 ps |
| CPU time | 7.47 seconds |
| Started | Feb 18 12:50:49 PM PST 24 |
| Finished | Feb 18 12:50:59 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-3585e0f6-570a-4cac-aca3-33944c31657f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084764877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1084764877 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3957707387 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1137256350 ps |
| CPU time | 7 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:51:01 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-5dfb9d8b-8d5d-4ab0-8922-d6c01650400a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3957707387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3957707387 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.656368516 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 9539067 ps |
| CPU time | 1.39 seconds |
| Started | Feb 18 12:50:49 PM PST 24 |
| Finished | Feb 18 12:50:53 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-39ce47aa-62ab-47b3-9a15-aed7e1f54476 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656368516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.656368516 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1301437832 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 213947505 ps |
| CPU time | 2.23 seconds |
| Started | Feb 18 12:50:52 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-72de4fc4-6189-40b4-8d6a-f6cc529c401c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301437832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1301437832 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2270466045 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 152543488 ps |
| CPU time | 9.01 seconds |
| Started | Feb 18 12:50:51 PM PST 24 |
| Finished | Feb 18 12:51:03 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-6ebd73c5-a44b-42c0-a7c2-1856691209c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2270466045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2270466045 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1736048542 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 5709743222 ps |
| CPU time | 121.34 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:52:54 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-36d4897b-dc30-4e97-aa4d-a86d3cadf79d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1736048542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1736048542 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2145920709 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 803630461 ps |
| CPU time | 155.66 seconds |
| Started | Feb 18 12:50:50 PM PST 24 |
| Finished | Feb 18 12:53:28 PM PST 24 |
| Peak memory | 208904 kb |
| Host | smart-dd365737-fa37-4953-9256-119b6a899faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2145920709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2145920709 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3401987180 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 440524440 ps |
| CPU time | 3.8 seconds |
| Started | Feb 18 12:50:49 PM PST 24 |
| Finished | Feb 18 12:50:56 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-749bb0c0-8c97-4f13-beaa-7f41dc9fa136 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3401987180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3401987180 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.77821806 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 911311866 ps |
| CPU time | 7.55 seconds |
| Started | Feb 18 12:50:59 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-83e343cc-c921-4819-b459-5177af5bdd6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=77821806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.77821806 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2018111680 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 74618322077 ps |
| CPU time | 297.66 seconds |
| Started | Feb 18 12:50:58 PM PST 24 |
| Finished | Feb 18 12:55:57 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-0f6698ef-6151-49a4-8fd5-6b407a6b4c0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2018111680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2018111680 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1054500306 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 481221870 ps |
| CPU time | 5 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:06 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-43d80ce6-d7d1-416f-92ed-211e3fa2060a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1054500306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1054500306 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.2755258290 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 502170852 ps |
| CPU time | 8.5 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:12 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-daf1ed25-cd39-4a6d-b74b-8b13dcb090ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2755258290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2755258290 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.596081337 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 64286607 ps |
| CPU time | 10.41 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:14 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-158ef8e6-add8-4cff-ae3f-15480ec92a7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=596081337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.596081337 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2847265359 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 221976184420 ps |
| CPU time | 117.89 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:53:03 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-2f0b8682-20df-4be6-81e9-c57dad96a0d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847265359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2847265359 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.712584540 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 48083327214 ps |
| CPU time | 109.98 seconds |
| Started | Feb 18 12:50:57 PM PST 24 |
| Finished | Feb 18 12:52:49 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-5b8bc8e4-d93d-4b66-bc30-e2e6be68675e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=712584540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.712584540 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.4259729221 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 82519048 ps |
| CPU time | 6.97 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:12 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-5a522cb1-b363-46c2-9e29-b72c63706657 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259729221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4259729221 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1424454435 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 82462542 ps |
| CPU time | 2.55 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:04 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-ab4db00a-0099-47c1-bab4-ba180e6f8faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1424454435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1424454435 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.492637711 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 275142042 ps |
| CPU time | 1.64 seconds |
| Started | Feb 18 12:50:53 PM PST 24 |
| Finished | Feb 18 12:50:57 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-a79cb40e-3c00-497d-9bb3-72de32358180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=492637711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.492637711 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1516964065 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1793257823 ps |
| CPU time | 8.18 seconds |
| Started | Feb 18 12:50:56 PM PST 24 |
| Finished | Feb 18 12:51:06 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-0b75551f-e0a7-424e-aaf3-ad6aed5195e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516964065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1516964065 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3818817145 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 857657445 ps |
| CPU time | 6.23 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:09 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-61578dad-8833-4704-8fcd-bcadc436b950 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3818817145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3818817145 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2668683590 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 10461782 ps |
| CPU time | 1.48 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:03 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-dab85e68-b235-42b1-a4c2-a810e9436b71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668683590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2668683590 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1158947303 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1900004143 ps |
| CPU time | 16.27 seconds |
| Started | Feb 18 12:50:58 PM PST 24 |
| Finished | Feb 18 12:51:15 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-4d24c194-1f0d-47b6-9f09-b9b44cd2a5ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1158947303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1158947303 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1733248897 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 914268246 ps |
| CPU time | 37.42 seconds |
| Started | Feb 18 12:50:59 PM PST 24 |
| Finished | Feb 18 12:51:38 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-32849094-4666-4ede-b091-284e7095fde9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1733248897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1733248897 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1302393874 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2599328327 ps |
| CPU time | 67.58 seconds |
| Started | Feb 18 12:50:59 PM PST 24 |
| Finished | Feb 18 12:52:08 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-5426c8bd-6883-4674-8f27-c11e28d73049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302393874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1302393874 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2961488940 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 980875501 ps |
| CPU time | 10.82 seconds |
| Started | Feb 18 12:50:59 PM PST 24 |
| Finished | Feb 18 12:51:11 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-d8ff132b-1a4f-4698-9a8b-465f026e6c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2961488940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2961488940 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1514160756 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 34585307 ps |
| CPU time | 4.95 seconds |
| Started | Feb 18 12:50:58 PM PST 24 |
| Finished | Feb 18 12:51:04 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-e44d6a35-15b4-494d-9733-8f3af1b9c347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514160756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1514160756 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2304312660 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 35355480823 ps |
| CPU time | 270.6 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:55:32 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-ca7c1be5-9800-4c69-9d32-d877a5d50f41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2304312660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2304312660 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2880379182 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 413494269 ps |
| CPU time | 9.51 seconds |
| Started | Feb 18 12:50:56 PM PST 24 |
| Finished | Feb 18 12:51:07 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-82de86a4-50ba-4535-b52e-828f2a33f805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2880379182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2880379182 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.702393429 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 28016305 ps |
| CPU time | 2.23 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:04 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-5c24be2c-640d-4763-9289-66d7be23088b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702393429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.702393429 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.578986614 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 186252631 ps |
| CPU time | 5.53 seconds |
| Started | Feb 18 12:50:57 PM PST 24 |
| Finished | Feb 18 12:51:04 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-dd35d875-1069-41a4-bfe3-88d20d82a1bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=578986614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.578986614 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2103686758 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 30385592977 ps |
| CPU time | 143.19 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:53:25 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-9c31daed-5647-4566-8c1c-a89345518863 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103686758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2103686758 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2633649993 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 13310773294 ps |
| CPU time | 42.6 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:45 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-445da554-e3a1-48cd-9736-1069c61d1c85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2633649993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2633649993 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1167910488 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 96131760 ps |
| CPU time | 5.27 seconds |
| Started | Feb 18 12:51:01 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-72abb997-0f27-4891-8d73-87573d1dfe88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167910488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1167910488 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1080990536 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 754801804 ps |
| CPU time | 9.59 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:14 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-353134db-52cc-431e-8f8b-b4c3dd1e6870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1080990536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1080990536 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1448017169 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 89001925 ps |
| CPU time | 1.38 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:03 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-3dbcc9bb-2bdc-4668-8422-de9432661552 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1448017169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1448017169 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.140841721 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7290066423 ps |
| CPU time | 12.78 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:14 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-0d690cbd-cb49-4396-b287-60ab2ab0e084 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=140841721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.140841721 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3002601582 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 989586223 ps |
| CPU time | 6.68 seconds |
| Started | Feb 18 12:50:57 PM PST 24 |
| Finished | Feb 18 12:51:05 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-b68b115c-d945-42b8-877c-9360ff6bd2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3002601582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3002601582 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3650657492 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 10019065 ps |
| CPU time | 1.11 seconds |
| Started | Feb 18 12:51:03 PM PST 24 |
| Finished | Feb 18 12:51:06 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-be0ee783-3e9a-48b1-b80a-92cf4195d524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650657492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3650657492 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1883599910 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 790504278 ps |
| CPU time | 35.88 seconds |
| Started | Feb 18 12:51:04 PM PST 24 |
| Finished | Feb 18 12:51:41 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-20bc68fe-1022-4a6e-94c7-aea56c9fa488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1883599910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1883599910 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.61422792 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5877294888 ps |
| CPU time | 100.76 seconds |
| Started | Feb 18 12:51:09 PM PST 24 |
| Finished | Feb 18 12:52:51 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-1b0a6eec-fb23-46a6-9846-7f3e7ff8193d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61422792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.61422792 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4254464745 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 318266788 ps |
| CPU time | 24.86 seconds |
| Started | Feb 18 12:51:02 PM PST 24 |
| Finished | Feb 18 12:51:28 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-9a4dfc99-5b0c-4c83-829e-0904b4e15b77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4254464745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.4254464745 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.879351189 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4025776808 ps |
| CPU time | 71.91 seconds |
| Started | Feb 18 12:51:08 PM PST 24 |
| Finished | Feb 18 12:52:22 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-5252d6d7-0e5e-4c11-8bed-13050bf995c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=879351189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.879351189 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2026708686 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 60958068 ps |
| CPU time | 8.12 seconds |
| Started | Feb 18 12:51:00 PM PST 24 |
| Finished | Feb 18 12:51:09 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-00a88d48-abaf-4342-ae1b-4ff1472c9989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2026708686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2026708686 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.962074916 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1574951048 ps |
| CPU time | 21.02 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:41 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-f224fc11-8a33-47fb-af18-09fd18e9295c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=962074916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.962074916 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2788138151 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 103201919121 ps |
| CPU time | 334.01 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:53:57 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-376e5147-2d01-4488-98c5-0a41545cdfee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2788138151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2788138151 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1381580458 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 39999534 ps |
| CPU time | 3.22 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-8dc2fe4e-3346-42c0-bfd8-9b4fe48527a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1381580458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1381580458 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3699839185 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1275693285 ps |
| CPU time | 3.38 seconds |
| Started | Feb 18 12:48:20 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-48a819ba-4ff5-4d49-b84e-33bb06dbc4d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3699839185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3699839185 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.1489962281 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 114149258 ps |
| CPU time | 7.4 seconds |
| Started | Feb 18 12:48:19 PM PST 24 |
| Finished | Feb 18 12:48:29 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-428a7493-d91b-4c6b-ac76-196b47816051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1489962281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1489962281 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4227859882 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 69239813595 ps |
| CPU time | 140.27 seconds |
| Started | Feb 18 12:48:12 PM PST 24 |
| Finished | Feb 18 12:50:39 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-a75406f3-b8f0-4a3b-8bb9-d43886825c22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227859882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4227859882 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3297000480 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 6401379630 ps |
| CPU time | 43.8 seconds |
| Started | Feb 18 12:48:12 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-8c7f9257-051a-442b-93a7-de53d6ad62e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3297000480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3297000480 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3438607586 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 103795621 ps |
| CPU time | 5.62 seconds |
| Started | Feb 18 12:48:13 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-8963eaf9-f28f-41dd-8a28-87db89b8b4a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438607586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3438607586 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2942773573 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2614757088 ps |
| CPU time | 5.12 seconds |
| Started | Feb 18 12:48:10 PM PST 24 |
| Finished | Feb 18 12:48:24 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-c2b382e4-dfe5-47f4-8ce6-26b278f50ca9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2942773573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2942773573 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2971687667 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 75182676 ps |
| CPU time | 1.55 seconds |
| Started | Feb 18 12:48:18 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-eb0c5988-cc7d-40b3-8411-1abc1b1064df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971687667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2971687667 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1814378911 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 4404361913 ps |
| CPU time | 9.27 seconds |
| Started | Feb 18 12:48:14 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-11f42bbf-20db-406b-bda7-b11cd4a28ae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814378911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1814378911 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2591243008 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1794710901 ps |
| CPU time | 4.97 seconds |
| Started | Feb 18 12:48:14 PM PST 24 |
| Finished | Feb 18 12:48:25 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-a52a83de-674a-4ca7-8e52-12aa2342a95a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2591243008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2591243008 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3979775341 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 12136818 ps |
| CPU time | 1.25 seconds |
| Started | Feb 18 12:48:16 PM PST 24 |
| Finished | Feb 18 12:48:22 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-9249626b-a3ae-4928-b5b4-7faf17aad364 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979775341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3979775341 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3349103844 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 225656224 ps |
| CPU time | 22.28 seconds |
| Started | Feb 18 12:48:14 PM PST 24 |
| Finished | Feb 18 12:48:43 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-2dc908b9-0c0d-46a5-af50-33f80157d548 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3349103844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3349103844 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2936858966 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 740010511 ps |
| CPU time | 28.25 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:48:52 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-b2bc008f-3455-43c1-a5b4-21a32efbd2f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2936858966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2936858966 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2042261109 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 37645791 ps |
| CPU time | 3.46 seconds |
| Started | Feb 18 12:48:19 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-4ee2194a-3768-47b2-8af9-ad8234eb2dc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2042261109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2042261109 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.227218905 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 598483819 ps |
| CPU time | 91.48 seconds |
| Started | Feb 18 12:48:18 PM PST 24 |
| Finished | Feb 18 12:49:53 PM PST 24 |
| Peak memory | 204976 kb |
| Host | smart-d5b8493d-40a8-462e-8844-33856b656fa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=227218905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.227218905 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1834740371 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 324067185 ps |
| CPU time | 7.92 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:48:31 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-8d84b7d2-09ba-43dc-a6f8-846f6f68f4f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834740371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1834740371 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.575921010 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 600722546 ps |
| CPU time | 12.61 seconds |
| Started | Feb 18 12:48:19 PM PST 24 |
| Finished | Feb 18 12:48:35 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-787fa2a1-a969-4a7f-b912-5af46c929ff7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575921010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.575921010 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3185659684 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 231758488143 ps |
| CPU time | 348.53 seconds |
| Started | Feb 18 12:48:23 PM PST 24 |
| Finished | Feb 18 12:54:14 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-21974861-ed42-46ef-8ec3-5ebd7e1b4124 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3185659684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3185659684 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.522065463 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 50256568 ps |
| CPU time | 1.84 seconds |
| Started | Feb 18 12:48:22 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-50821952-9cfd-41f0-908c-5bd0ef7e7e0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=522065463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.522065463 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.837962720 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 269960170 ps |
| CPU time | 4.55 seconds |
| Started | Feb 18 12:48:20 PM PST 24 |
| Finished | Feb 18 12:48:27 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-7496f540-9b53-4b58-8560-132e28032c0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837962720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.837962720 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.917964811 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 25373306 ps |
| CPU time | 2.77 seconds |
| Started | Feb 18 12:48:12 PM PST 24 |
| Finished | Feb 18 12:48:22 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-94e39006-6a99-4ac0-94b9-1bae223f56f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=917964811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.917964811 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1931601353 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 38402288157 ps |
| CPU time | 133.18 seconds |
| Started | Feb 18 12:48:11 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-43f47cfe-8348-4a38-aad3-a6258f22ca37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931601353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1931601353 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.4166935249 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 39277055369 ps |
| CPU time | 80.91 seconds |
| Started | Feb 18 12:48:24 PM PST 24 |
| Finished | Feb 18 12:49:47 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-6ba86259-21af-4da5-a4f9-72879fc1f712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4166935249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4166935249 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3736128061 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 201914093 ps |
| CPU time | 9.03 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:48:32 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-15045853-fc2d-48f7-8887-956d22fce089 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736128061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3736128061 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.2790847567 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 45628747 ps |
| CPU time | 3.68 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:48:27 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-7c4bb66b-06a7-459a-9b24-20304fa5431f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790847567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2790847567 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3912414071 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 72438501 ps |
| CPU time | 1.63 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:20 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-338f5e41-e0b7-465b-9810-94eecc12427e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3912414071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3912414071 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1366881041 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2451389856 ps |
| CPU time | 9.41 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:28 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-061901e0-99b9-4492-aec5-3270c8529b66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366881041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1366881041 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1172710817 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1360723553 ps |
| CPU time | 10.15 seconds |
| Started | Feb 18 12:48:09 PM PST 24 |
| Finished | Feb 18 12:48:28 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-7cd0e409-8700-4a12-a41d-4d5dd227dfa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1172710817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1172710817 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1292191869 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 10940846 ps |
| CPU time | 1.18 seconds |
| Started | Feb 18 12:48:11 PM PST 24 |
| Finished | Feb 18 12:48:20 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-11d0383c-1f2f-4654-87a9-88f9a644178b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292191869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1292191869 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1115298913 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 110815605 ps |
| CPU time | 2.09 seconds |
| Started | Feb 18 12:48:25 PM PST 24 |
| Finished | Feb 18 12:48:29 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-49b1bd44-6743-4b06-82fa-4cbc0d0ef6ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115298913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1115298913 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.621118102 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 8263254213 ps |
| CPU time | 57.2 seconds |
| Started | Feb 18 12:48:21 PM PST 24 |
| Finished | Feb 18 12:49:21 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-3d9d384c-f36e-49b2-b1d4-956db2457e4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=621118102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.621118102 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1744451096 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 741763912 ps |
| CPU time | 105 seconds |
| Started | Feb 18 12:48:19 PM PST 24 |
| Finished | Feb 18 12:50:08 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-6e51a149-2b33-4153-9535-db74617a74a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1744451096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1744451096 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2920031393 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2358918139 ps |
| CPU time | 8.2 seconds |
| Started | Feb 18 12:48:22 PM PST 24 |
| Finished | Feb 18 12:48:32 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-c9222181-c4ae-402b-9698-c7575112f538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920031393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2920031393 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2130920619 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 72335444 ps |
| CPU time | 1.7 seconds |
| Started | Feb 18 12:48:33 PM PST 24 |
| Finished | Feb 18 12:48:36 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3274965a-37ce-4a21-9928-6ba6a11c46f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2130920619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2130920619 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2001690984 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20637806212 ps |
| CPU time | 126.57 seconds |
| Started | Feb 18 12:48:24 PM PST 24 |
| Finished | Feb 18 12:50:33 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-d01ab9d2-a126-4f1a-8996-234966c3df25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2001690984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2001690984 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.830830797 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 27198070 ps |
| CPU time | 2.74 seconds |
| Started | Feb 18 12:48:30 PM PST 24 |
| Finished | Feb 18 12:48:35 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-95fd46ef-9fc2-40b7-8346-463459ea121a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830830797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.830830797 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2457221674 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 14513664 ps |
| CPU time | 1.82 seconds |
| Started | Feb 18 12:48:31 PM PST 24 |
| Finished | Feb 18 12:48:35 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-661bbd53-1d7b-4eee-9c45-00953cbe3e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2457221674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2457221674 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.3446515164 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 144327626 ps |
| CPU time | 5.5 seconds |
| Started | Feb 18 12:48:23 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-d5c28cad-19aa-4b9e-873e-24e1c8c97ce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446515164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3446515164 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2601638920 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 142417362522 ps |
| CPU time | 134.82 seconds |
| Started | Feb 18 12:48:29 PM PST 24 |
| Finished | Feb 18 12:50:46 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-a29a67ae-34f2-4d36-a84c-fccf442dc77a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601638920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2601638920 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2154636560 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3887942866 ps |
| CPU time | 13.23 seconds |
| Started | Feb 18 12:48:26 PM PST 24 |
| Finished | Feb 18 12:48:42 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-785f30b3-f3f9-4696-988c-59a70571a93b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2154636560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2154636560 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.4282187222 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 42446579 ps |
| CPU time | 5.28 seconds |
| Started | Feb 18 12:48:23 PM PST 24 |
| Finished | Feb 18 12:48:30 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-f20722b5-474f-4c43-adb9-cc7782c1c072 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282187222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4282187222 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1041590758 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 617380702 ps |
| CPU time | 4.3 seconds |
| Started | Feb 18 12:48:33 PM PST 24 |
| Finished | Feb 18 12:48:39 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-22f784b2-95eb-4fd8-a883-905b44999a4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1041590758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1041590758 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.4225144600 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 354860615 ps |
| CPU time | 1.45 seconds |
| Started | Feb 18 12:48:23 PM PST 24 |
| Finished | Feb 18 12:48:26 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-58da465c-26b8-48b8-b8e0-3ec4a4431f26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4225144600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4225144600 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2502425460 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3964689593 ps |
| CPU time | 8.72 seconds |
| Started | Feb 18 12:48:20 PM PST 24 |
| Finished | Feb 18 12:48:31 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-28ddd1b8-d5cd-4e80-aa07-1c04e9c3fc98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502425460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2502425460 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1080384768 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 919056677 ps |
| CPU time | 7.44 seconds |
| Started | Feb 18 12:48:22 PM PST 24 |
| Finished | Feb 18 12:48:32 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-61dc3739-4f7e-474c-903e-df5d618a7369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1080384768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1080384768 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2755033386 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 24772355 ps |
| CPU time | 1.11 seconds |
| Started | Feb 18 12:48:19 PM PST 24 |
| Finished | Feb 18 12:48:23 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-1a542b22-8680-4ea9-abee-7e30d6a55ab9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755033386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2755033386 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1242884482 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1070544714 ps |
| CPU time | 50.23 seconds |
| Started | Feb 18 12:48:29 PM PST 24 |
| Finished | Feb 18 12:49:22 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-024a9c1d-34ba-44ce-8d55-32826634ed14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242884482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1242884482 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2977470639 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 858395410 ps |
| CPU time | 12.72 seconds |
| Started | Feb 18 12:48:25 PM PST 24 |
| Finished | Feb 18 12:48:40 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-a7e7690f-e880-4b6c-a53a-df155064f9ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2977470639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2977470639 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2336700221 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 717169378 ps |
| CPU time | 122.05 seconds |
| Started | Feb 18 12:48:28 PM PST 24 |
| Finished | Feb 18 12:50:32 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-15919d52-b597-4706-a78c-0cda2c91a7e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336700221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.2336700221 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1525251109 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 36862402 ps |
| CPU time | 6.91 seconds |
| Started | Feb 18 12:48:29 PM PST 24 |
| Finished | Feb 18 12:48:38 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-ed74a493-611b-4eb8-9290-56af4dd2058f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1525251109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1525251109 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2960548357 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 22333713 ps |
| CPU time | 1.24 seconds |
| Started | Feb 18 12:48:30 PM PST 24 |
| Finished | Feb 18 12:48:34 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-bde37e34-c8a7-4481-abd8-073597202e07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2960548357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2960548357 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3926002883 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 10601857 ps |
| CPU time | 1.46 seconds |
| Started | Feb 18 12:48:29 PM PST 24 |
| Finished | Feb 18 12:48:33 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-033d5f02-8fac-41e6-a5c4-1124e1d1ea46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926002883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3926002883 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2649141553 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 40321332 ps |
| CPU time | 2.67 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:36 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-aa953d13-85f1-4c4d-8421-bcd06e917742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649141553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2649141553 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2690034718 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 45598545 ps |
| CPU time | 2.99 seconds |
| Started | Feb 18 12:48:30 PM PST 24 |
| Finished | Feb 18 12:48:35 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-16481536-de5d-45d3-adcc-c60cc1dc7e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2690034718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2690034718 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.693169068 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 470930116 ps |
| CPU time | 3.12 seconds |
| Started | Feb 18 12:48:25 PM PST 24 |
| Finished | Feb 18 12:48:31 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-0627283c-795c-42ea-b7e5-e169a630c75e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693169068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.693169068 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.276988875 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 143383462874 ps |
| CPU time | 159.58 seconds |
| Started | Feb 18 12:48:26 PM PST 24 |
| Finished | Feb 18 12:51:08 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-9daac440-8520-4f5a-9257-856220249a2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=276988875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.276988875 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.17203112 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 17185184295 ps |
| CPU time | 98.44 seconds |
| Started | Feb 18 12:48:26 PM PST 24 |
| Finished | Feb 18 12:50:07 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-59e443ab-e123-4951-b571-9d0104f581c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=17203112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.17203112 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.729146679 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9599586 ps |
| CPU time | 1.2 seconds |
| Started | Feb 18 12:48:28 PM PST 24 |
| Finished | Feb 18 12:48:31 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-78543c66-378c-4f42-a3ef-aedf29ef1f99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729146679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.729146679 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2702822855 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 34132493 ps |
| CPU time | 3.5 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:37 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-938a29cc-3671-415a-89ce-34b5fa2d9803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702822855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2702822855 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.643926288 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 10141044 ps |
| CPU time | 1.2 seconds |
| Started | Feb 18 12:48:26 PM PST 24 |
| Finished | Feb 18 12:48:29 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-4990a5fe-33f6-4a81-b814-7d57f4000570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=643926288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.643926288 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3533181652 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 20476970563 ps |
| CPU time | 12.46 seconds |
| Started | Feb 18 12:48:24 PM PST 24 |
| Finished | Feb 18 12:48:38 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-d5e6a8d4-2df0-496a-b417-9b874ebc11ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533181652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3533181652 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2461318079 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 9727984171 ps |
| CPU time | 8.92 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:48:43 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-c70a3d6c-5315-4932-b011-6c50f688446c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2461318079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2461318079 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2902778162 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 43439506 ps |
| CPU time | 1.32 seconds |
| Started | Feb 18 12:48:27 PM PST 24 |
| Finished | Feb 18 12:48:31 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-10dae272-aa47-4bff-848b-067ae190daeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902778162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2902778162 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1756188484 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 502320944 ps |
| CPU time | 47.16 seconds |
| Started | Feb 18 12:48:27 PM PST 24 |
| Finished | Feb 18 12:49:17 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-0535c375-007b-4e84-ad80-478e74f9c1bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1756188484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1756188484 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2206357176 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 427389591 ps |
| CPU time | 28.48 seconds |
| Started | Feb 18 12:48:32 PM PST 24 |
| Finished | Feb 18 12:49:03 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-6ab547f2-6adc-48aa-bb8a-de1cc1cc866c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2206357176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2206357176 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3754686773 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 597123408 ps |
| CPU time | 61.15 seconds |
| Started | Feb 18 12:48:28 PM PST 24 |
| Finished | Feb 18 12:49:31 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-995142da-c081-412e-9d7f-1aaa072f036b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754686773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3754686773 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1114154444 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2514857095 ps |
| CPU time | 191.34 seconds |
| Started | Feb 18 12:48:31 PM PST 24 |
| Finished | Feb 18 12:51:44 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-7af4816f-679f-4137-a4fe-45c82d407d36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1114154444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1114154444 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3434108628 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 123799074 ps |
| CPU time | 7.78 seconds |
| Started | Feb 18 12:48:27 PM PST 24 |
| Finished | Feb 18 12:48:37 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-da34a4de-62cf-482e-8091-6ccdc2800290 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3434108628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3434108628 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1806373851 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2917466619 ps |
| CPU time | 18.04 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:48:56 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-df9ff18a-f2ec-4f10-8b29-d7796c935244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1806373851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1806373851 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2032853305 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4250247198 ps |
| CPU time | 20.9 seconds |
| Started | Feb 18 12:48:44 PM PST 24 |
| Finished | Feb 18 12:49:07 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-1a432dfe-35f1-41c8-9d13-3c3aae789962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2032853305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2032853305 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4220118699 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 207055854 ps |
| CPU time | 5.1 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:47 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-ca15357b-1029-4e3b-a717-237c9ac7aa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220118699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4220118699 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1136508265 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 36994120 ps |
| CPU time | 4.06 seconds |
| Started | Feb 18 12:48:37 PM PST 24 |
| Finished | Feb 18 12:48:42 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-25c369c2-6da6-4d79-a212-7786324fd998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1136508265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1136508265 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.4199630018 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 167632933 ps |
| CPU time | 8.99 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:51 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-0834b7b3-6102-4ac9-a1b2-70fe5a2a6826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4199630018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.4199630018 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1521301155 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 28896051414 ps |
| CPU time | 49.98 seconds |
| Started | Feb 18 12:48:31 PM PST 24 |
| Finished | Feb 18 12:49:23 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-0419d20e-ef7a-4eb5-b5e8-14aa3fb2bfaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521301155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1521301155 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.553179143 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 21954485877 ps |
| CPU time | 77.08 seconds |
| Started | Feb 18 12:48:44 PM PST 24 |
| Finished | Feb 18 12:50:04 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-32797868-e2ce-480f-bfa9-a088107961be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=553179143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.553179143 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.200953187 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 77947053 ps |
| CPU time | 2.98 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:48:45 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-72f06f23-1784-4096-9637-a8d07c392b15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200953187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.200953187 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3515696843 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 101027212 ps |
| CPU time | 6.18 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:48:44 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-e9f76615-295d-4291-b79a-643b468cdb96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3515696843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3515696843 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.2486255181 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 105713371 ps |
| CPU time | 1.51 seconds |
| Started | Feb 18 12:48:28 PM PST 24 |
| Finished | Feb 18 12:48:32 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-f3097ae6-e790-4e1a-be86-86e74a004800 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2486255181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2486255181 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2091732095 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1815748139 ps |
| CPU time | 8.77 seconds |
| Started | Feb 18 12:48:36 PM PST 24 |
| Finished | Feb 18 12:48:47 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-911b51b5-7224-4011-81a6-ff73721f0478 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091732095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2091732095 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2314632426 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1192812886 ps |
| CPU time | 7.46 seconds |
| Started | Feb 18 12:48:33 PM PST 24 |
| Finished | Feb 18 12:48:42 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-1f44ec43-f5f0-4f6c-9480-932d000595d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2314632426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2314632426 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1305009290 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 10191264 ps |
| CPU time | 1.08 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:48:45 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3301ad82-1d48-4804-9ceb-91f226aee5be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305009290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1305009290 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3868139043 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 23492797624 ps |
| CPU time | 60.88 seconds |
| Started | Feb 18 12:48:40 PM PST 24 |
| Finished | Feb 18 12:49:42 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-f2a96b1b-f29f-4440-ad0c-9909e426714e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3868139043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3868139043 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4016697363 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 95798596 ps |
| CPU time | 9.56 seconds |
| Started | Feb 18 12:48:38 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-77b61bda-b602-42b3-a138-1a387b651107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016697363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4016697363 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1667471418 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 688969698 ps |
| CPU time | 114.37 seconds |
| Started | Feb 18 12:48:42 PM PST 24 |
| Finished | Feb 18 12:50:39 PM PST 24 |
| Peak memory | 206192 kb |
| Host | smart-89ebff41-e012-401a-b0b5-e4d0b9a8afca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1667471418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1667471418 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2471136463 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5173625572 ps |
| CPU time | 72.01 seconds |
| Started | Feb 18 12:48:41 PM PST 24 |
| Finished | Feb 18 12:49:55 PM PST 24 |
| Peak memory | 205672 kb |
| Host | smart-d16b6936-4d5c-4758-be08-f56ac3d753e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2471136463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2471136463 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1994091568 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 359505639 ps |
| CPU time | 4.13 seconds |
| Started | Feb 18 12:48:43 PM PST 24 |
| Finished | Feb 18 12:48:49 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-f5444c1b-bd0e-4513-8b48-4eed5bdd640c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1994091568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1994091568 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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