Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 450 1 T2 4 T3 5 T14 2
all_values[1] 446 1 T2 2 T3 7 T14 5
all_values[2] 417 1 T2 4 T3 2 T14 1
all_values[3] 410 1 T2 6 T3 3 T14 1
all_values[4] 447 1 T2 6 T3 6 T14 5
all_values[5] 438 1 T2 7 T3 4 T14 2
all_values[6] 397 1 T2 6 T3 3 T14 3
all_values[7] 426 1 T2 1 T3 3 T14 3
all_values[8] 411 1 T2 5 T3 2 T14 3
all_values[9] 447 1 T2 6 T3 5 T14 2
all_values[10] 450 1 T2 9 T3 1 T14 2
all_values[11] 430 1 T2 4 T3 2 T14 1
all_values[12] 421 1 T2 4 T3 9 T15 10
all_values[13] 449 1 T2 3 T3 5 T14 4
all_values[14] 426 1 T2 9 T3 3 T14 1
all_values[15] 443 1 T2 11 T3 3 T14 3
all_values[16] 426 1 T2 5 T3 4 T14 2
all_values[17] 417 1 T2 11 T3 4 T14 1
all_values[18] 462 1 T2 11 T3 5 T14 3
all_values[19] 441 1 T2 7 T3 6 T14 3
all_values[20] 429 1 T2 6 T3 5 T14 3
all_values[21] 418 1 T2 4 T3 8 T14 2
all_values[22] 445 1 T2 10 T3 5 T14 6
all_values[23] 443 1 T2 8 T3 9 T14 2
all_values[24] 392 1 T2 11 T3 3 T14 1
all_values[25] 421 1 T2 10 T3 4 T14 1
all_values[26] 446 1 T2 9 T3 2 T14 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%