| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.32 | 100.00 | 95.90 | 100.00 | 100.00 | 100.00 | 100.00 |
| T758 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.962465633 | Feb 21 01:15:25 PM PST 24 | Feb 21 01:16:26 PM PST 24 | 19879723010 ps | ||
| T33 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4165851001 | Feb 21 01:15:08 PM PST 24 | Feb 21 01:15:17 PM PST 24 | 4244914232 ps | ||
| T759 | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.4068904522 | Feb 21 01:17:23 PM PST 24 | Feb 21 01:17:39 PM PST 24 | 2256058100 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.593700868 | Feb 21 01:18:15 PM PST 24 | Feb 21 01:19:02 PM PST 24 | 55236128498 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/48.xbar_random.1601131591 | Feb 21 01:18:07 PM PST 24 | Feb 21 01:18:10 PM PST 24 | 156394127 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1242157562 | Feb 21 01:17:39 PM PST 24 | Feb 21 01:17:47 PM PST 24 | 656836619 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.79968344 | Feb 21 01:15:51 PM PST 24 | Feb 21 01:17:06 PM PST 24 | 5427809180 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3181936168 | Feb 21 01:15:23 PM PST 24 | Feb 21 01:15:26 PM PST 24 | 20291104 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3108811419 | Feb 21 01:16:05 PM PST 24 | Feb 21 01:16:08 PM PST 24 | 41110270 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.273557944 | Feb 21 01:17:01 PM PST 24 | Feb 21 01:17:03 PM PST 24 | 12733317 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4068995248 | Feb 21 01:17:08 PM PST 24 | Feb 21 01:17:17 PM PST 24 | 2640681720 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3434654462 | Feb 21 01:15:04 PM PST 24 | Feb 21 01:15:55 PM PST 24 | 3626587568 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3411539361 | Feb 21 01:17:03 PM PST 24 | Feb 21 01:17:05 PM PST 24 | 8661901 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/44.xbar_random.370267822 | Feb 21 01:18:04 PM PST 24 | Feb 21 01:18:10 PM PST 24 | 240744757 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4035004377 | Feb 21 01:17:05 PM PST 24 | Feb 21 01:17:39 PM PST 24 | 2724075922 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1699566146 | Feb 21 01:16:02 PM PST 24 | Feb 21 01:17:18 PM PST 24 | 2822257805 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.774456224 | Feb 21 01:15:38 PM PST 24 | Feb 21 01:15:48 PM PST 24 | 420147570 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2308267890 | Feb 21 01:16:38 PM PST 24 | Feb 21 01:16:45 PM PST 24 | 2740850102 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1450602639 | Feb 21 01:16:16 PM PST 24 | Feb 21 01:16:25 PM PST 24 | 355027787 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1235576996 | Feb 21 01:16:00 PM PST 24 | Feb 21 01:16:13 PM PST 24 | 1046686762 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1928377428 | Feb 21 01:17:00 PM PST 24 | Feb 21 01:17:03 PM PST 24 | 30426868 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.4154141464 | Feb 21 01:14:54 PM PST 24 | Feb 21 01:14:56 PM PST 24 | 101763858 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/7.xbar_random.4172264498 | Feb 21 01:15:28 PM PST 24 | Feb 21 01:15:31 PM PST 24 | 143932568 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2573963603 | Feb 21 01:17:48 PM PST 24 | Feb 21 01:19:13 PM PST 24 | 22419380269 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2239482292 | Feb 21 01:16:00 PM PST 24 | Feb 21 01:16:02 PM PST 24 | 295194158 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1814036369 | Feb 21 01:17:55 PM PST 24 | Feb 21 01:17:58 PM PST 24 | 220564046 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1913597968 | Feb 21 01:18:17 PM PST 24 | Feb 21 01:18:59 PM PST 24 | 11135747265 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.594105784 | Feb 21 01:17:20 PM PST 24 | Feb 21 01:17:23 PM PST 24 | 13621203 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1968087979 | Feb 21 01:18:13 PM PST 24 | Feb 21 01:18:34 PM PST 24 | 168349797 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/24.xbar_error_random.948452394 | Feb 21 01:16:43 PM PST 24 | Feb 21 01:16:47 PM PST 24 | 44932208 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1097376471 | Feb 21 01:15:31 PM PST 24 | Feb 21 01:16:17 PM PST 24 | 4036508888 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/45.xbar_random.3329253519 | Feb 21 01:18:01 PM PST 24 | Feb 21 01:18:15 PM PST 24 | 1181888044 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1570341152 | Feb 21 01:17:05 PM PST 24 | Feb 21 01:17:16 PM PST 24 | 104702355 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2520235057 | Feb 21 01:18:00 PM PST 24 | Feb 21 01:18:10 PM PST 24 | 2170697724 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1151007362 | Feb 21 01:17:16 PM PST 24 | Feb 21 01:17:59 PM PST 24 | 3822507203 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2188856877 | Feb 21 01:14:55 PM PST 24 | Feb 21 01:15:05 PM PST 24 | 743530825 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3808697224 | Feb 21 01:18:00 PM PST 24 | Feb 21 01:18:58 PM PST 24 | 761802059 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3851035827 | Feb 21 01:17:38 PM PST 24 | Feb 21 01:18:18 PM PST 24 | 9007879524 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1464888703 | Feb 21 01:15:53 PM PST 24 | Feb 21 01:16:14 PM PST 24 | 126959232 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/32.xbar_random.3099339059 | Feb 21 01:17:08 PM PST 24 | Feb 21 01:17:15 PM PST 24 | 320920472 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3541791641 | Feb 21 01:17:32 PM PST 24 | Feb 21 01:18:18 PM PST 24 | 8143302739 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.306228663 | Feb 21 01:17:13 PM PST 24 | Feb 21 01:17:19 PM PST 24 | 2720410341 ps | ||
| T34 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3699793795 | Feb 21 01:15:50 PM PST 24 | Feb 21 01:15:58 PM PST 24 | 1629236299 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.81263852 | Feb 21 01:16:00 PM PST 24 | Feb 21 01:17:18 PM PST 24 | 30068434810 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3546016728 | Feb 21 01:17:24 PM PST 24 | Feb 21 01:17:26 PM PST 24 | 11179467 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1710641081 | Feb 21 01:17:12 PM PST 24 | Feb 21 01:19:34 PM PST 24 | 12580850140 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/33.xbar_random.3507212207 | Feb 21 01:17:14 PM PST 24 | Feb 21 01:17:24 PM PST 24 | 159912229 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1685896247 | Feb 21 01:15:49 PM PST 24 | Feb 21 01:15:51 PM PST 24 | 44866072 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2431746605 | Feb 21 01:15:09 PM PST 24 | Feb 21 01:16:44 PM PST 24 | 39253116436 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1212843066 | Feb 21 01:17:48 PM PST 24 | Feb 21 01:20:50 PM PST 24 | 64831552889 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.569713179 | Feb 21 01:17:04 PM PST 24 | Feb 21 01:17:17 PM PST 24 | 2656157367 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3075061661 | Feb 21 01:17:16 PM PST 24 | Feb 21 01:18:14 PM PST 24 | 30144931697 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4226710808 | Feb 21 01:15:57 PM PST 24 | Feb 21 01:16:39 PM PST 24 | 547184392 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2357694028 | Feb 21 01:15:17 PM PST 24 | Feb 21 01:16:09 PM PST 24 | 2517676212 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2556185171 | Feb 21 01:16:59 PM PST 24 | Feb 21 01:17:07 PM PST 24 | 171980840 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3103015869 | Feb 21 01:15:57 PM PST 24 | Feb 21 01:16:00 PM PST 24 | 75571207 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2805146443 | Feb 21 01:15:08 PM PST 24 | Feb 21 01:15:14 PM PST 24 | 71615450 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1023938476 | Feb 21 01:15:57 PM PST 24 | Feb 21 01:15:59 PM PST 24 | 13580375 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/38.xbar_random.818987256 | Feb 21 01:17:38 PM PST 24 | Feb 21 01:17:43 PM PST 24 | 41873100 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2681154326 | Feb 21 01:17:14 PM PST 24 | Feb 21 01:17:15 PM PST 24 | 9406873 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3723507180 | Feb 21 01:15:27 PM PST 24 | Feb 21 01:15:32 PM PST 24 | 29266402 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3849306770 | Feb 21 01:15:16 PM PST 24 | Feb 21 01:15:21 PM PST 24 | 558570855 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1356742361 | Feb 21 01:16:13 PM PST 24 | Feb 21 01:16:14 PM PST 24 | 19267043 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1254283691 | Feb 21 01:16:05 PM PST 24 | Feb 21 01:16:07 PM PST 24 | 10101952 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2015225150 | Feb 21 01:15:53 PM PST 24 | Feb 21 01:16:03 PM PST 24 | 137438901 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3831770516 | Feb 21 01:15:30 PM PST 24 | Feb 21 01:17:52 PM PST 24 | 31526597459 ps | ||
| T147 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2789616128 | Feb 21 01:16:36 PM PST 24 | Feb 21 01:22:00 PM PST 24 | 99261335830 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2575831388 | Feb 21 01:17:17 PM PST 24 | Feb 21 01:17:22 PM PST 24 | 145483388 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.249599614 | Feb 21 01:16:44 PM PST 24 | Feb 21 01:16:54 PM PST 24 | 59073989 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3267831764 | Feb 21 01:17:10 PM PST 24 | Feb 21 01:19:07 PM PST 24 | 35963157974 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.665563941 | Feb 21 01:16:00 PM PST 24 | Feb 21 01:16:07 PM PST 24 | 1179793938 ps | ||
| T188 | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2182166527 | Feb 21 01:17:11 PM PST 24 | Feb 21 01:18:45 PM PST 24 | 30397530007 ps | ||
| T148 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3350184543 | Feb 21 01:17:47 PM PST 24 | Feb 21 01:18:06 PM PST 24 | 3432605469 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.362850248 | Feb 21 01:16:00 PM PST 24 | Feb 21 01:18:01 PM PST 24 | 24108112879 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.175255318 | Feb 21 01:17:32 PM PST 24 | Feb 21 01:17:37 PM PST 24 | 87723728 ps | ||
| T169 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1019876024 | Feb 21 01:15:57 PM PST 24 | Feb 21 01:19:38 PM PST 24 | 17254193557 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4000845013 | Feb 21 01:17:11 PM PST 24 | Feb 21 01:17:17 PM PST 24 | 65340225 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1428615487 | Feb 21 01:15:58 PM PST 24 | Feb 21 01:16:00 PM PST 24 | 9275640 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1858026556 | Feb 21 01:15:58 PM PST 24 | Feb 21 01:16:03 PM PST 24 | 82054928 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2093134154 | Feb 21 01:16:10 PM PST 24 | Feb 21 01:16:21 PM PST 24 | 1078836491 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1795516280 | Feb 21 01:17:52 PM PST 24 | Feb 21 01:18:01 PM PST 24 | 2071657256 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3076823071 | Feb 21 01:15:51 PM PST 24 | Feb 21 01:17:44 PM PST 24 | 13651190086 ps | ||
| T8 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3523087789 | Feb 21 01:17:38 PM PST 24 | Feb 21 01:18:55 PM PST 24 | 1308921921 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2830705861 | Feb 21 01:15:02 PM PST 24 | Feb 21 01:15:05 PM PST 24 | 25810798 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3516223826 | Feb 21 01:18:14 PM PST 24 | Feb 21 01:18:26 PM PST 24 | 80232902 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3052479198 | Feb 21 01:14:53 PM PST 24 | Feb 21 01:14:55 PM PST 24 | 21058787 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2004626966 | Feb 21 01:15:50 PM PST 24 | Feb 21 01:16:30 PM PST 24 | 2981753790 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3501762539 | Feb 21 01:15:45 PM PST 24 | Feb 21 01:15:50 PM PST 24 | 1131070324 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3704473637 | Feb 21 01:18:11 PM PST 24 | Feb 21 01:18:21 PM PST 24 | 2738064692 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2778692666 | Feb 21 01:17:08 PM PST 24 | Feb 21 01:18:35 PM PST 24 | 100557333951 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1585931487 | Feb 21 01:16:15 PM PST 24 | Feb 21 01:16:22 PM PST 24 | 345747275 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.2360550434 | Feb 21 01:15:07 PM PST 24 | Feb 21 01:15:11 PM PST 24 | 535122918 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3774824155 | Feb 21 01:16:04 PM PST 24 | Feb 21 01:16:16 PM PST 24 | 48297776 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1799288612 | Feb 21 01:17:04 PM PST 24 | Feb 21 01:17:17 PM PST 24 | 2443353143 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2830594060 | Feb 21 01:18:09 PM PST 24 | Feb 21 01:18:18 PM PST 24 | 866309315 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2802393170 | Feb 21 01:17:00 PM PST 24 | Feb 21 01:19:21 PM PST 24 | 251820657140 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1352808150 | Feb 21 01:17:22 PM PST 24 | Feb 21 01:18:50 PM PST 24 | 17623221096 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1420768864 | Feb 21 01:17:02 PM PST 24 | Feb 21 01:18:27 PM PST 24 | 2301892331 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.511974934 | Feb 21 01:15:04 PM PST 24 | Feb 21 01:17:03 PM PST 24 | 4498998566 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2844663505 | Feb 21 01:16:56 PM PST 24 | Feb 21 01:17:00 PM PST 24 | 43083126 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1006683661 | Feb 21 01:17:07 PM PST 24 | Feb 21 01:19:00 PM PST 24 | 29474801677 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1215033970 | Feb 21 01:15:51 PM PST 24 | Feb 21 01:18:18 PM PST 24 | 1230672845 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3586304149 | Feb 21 01:15:17 PM PST 24 | Feb 21 01:15:19 PM PST 24 | 17421325 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/32.xbar_same_source.3428896716 | Feb 21 01:17:13 PM PST 24 | Feb 21 01:17:22 PM PST 24 | 2857567389 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1246440625 | Feb 21 01:17:24 PM PST 24 | Feb 21 01:17:35 PM PST 24 | 1202073699 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.4137717711 | Feb 21 01:16:56 PM PST 24 | Feb 21 01:17:05 PM PST 24 | 2163160869 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.181008955 | Feb 21 01:17:56 PM PST 24 | Feb 21 01:17:58 PM PST 24 | 9210776 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4026335982 | Feb 21 01:17:48 PM PST 24 | Feb 21 01:19:52 PM PST 24 | 22351162289 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1690708972 | Feb 21 01:15:47 PM PST 24 | Feb 21 01:18:07 PM PST 24 | 819515361 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4231698683 | Feb 21 01:17:16 PM PST 24 | Feb 21 01:17:26 PM PST 24 | 1750979203 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2453328930 | Feb 21 01:15:26 PM PST 24 | Feb 21 01:15:31 PM PST 24 | 28688080 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.289986273 | Feb 21 01:17:38 PM PST 24 | Feb 21 01:19:12 PM PST 24 | 903179460 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.803075911 | Feb 21 01:17:22 PM PST 24 | Feb 21 01:17:28 PM PST 24 | 303173464 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1764580892 | Feb 21 01:15:19 PM PST 24 | Feb 21 01:19:46 PM PST 24 | 46312842264 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3715971675 | Feb 21 01:15:46 PM PST 24 | Feb 21 01:16:22 PM PST 24 | 6579096965 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.285723329 | Feb 21 01:15:28 PM PST 24 | Feb 21 01:15:36 PM PST 24 | 110954167 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/14.xbar_random.1799183998 | Feb 21 01:15:58 PM PST 24 | Feb 21 01:16:08 PM PST 24 | 626428608 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2188023811 | Feb 21 01:16:43 PM PST 24 | Feb 21 01:16:52 PM PST 24 | 751745033 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.332089590 | Feb 21 01:16:01 PM PST 24 | Feb 21 01:16:05 PM PST 24 | 38325509 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3487333652 | Feb 21 01:15:53 PM PST 24 | Feb 21 01:16:43 PM PST 24 | 11073424231 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2794414860 | Feb 21 01:17:11 PM PST 24 | Feb 21 01:17:38 PM PST 24 | 426242908 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.4178847781 | Feb 21 01:17:46 PM PST 24 | Feb 21 01:20:44 PM PST 24 | 53875148430 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3220382374 | Feb 21 01:15:50 PM PST 24 | Feb 21 01:16:53 PM PST 24 | 5311787975 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1687696909 | Feb 21 01:18:09 PM PST 24 | Feb 21 01:18:19 PM PST 24 | 116839010 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1184601139 | Feb 21 01:15:43 PM PST 24 | Feb 21 01:15:48 PM PST 24 | 305627231 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1587309117 | Feb 21 01:15:17 PM PST 24 | Feb 21 01:15:22 PM PST 24 | 231227248 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1794347159 | Feb 21 01:16:44 PM PST 24 | Feb 21 01:16:57 PM PST 24 | 513406734 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3612418275 | Feb 21 01:15:50 PM PST 24 | Feb 21 01:15:52 PM PST 24 | 63067397 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2517725147 | Feb 21 01:16:48 PM PST 24 | Feb 21 01:16:57 PM PST 24 | 344966725 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.697416313 | Feb 21 01:17:04 PM PST 24 | Feb 21 01:17:53 PM PST 24 | 574295055 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/25.xbar_error_random.3532499828 | Feb 21 01:17:00 PM PST 24 | Feb 21 01:17:02 PM PST 24 | 11807703 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2106965713 | Feb 21 01:16:10 PM PST 24 | Feb 21 01:16:17 PM PST 24 | 95803012 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.772284097 | Feb 21 01:17:55 PM PST 24 | Feb 21 01:17:56 PM PST 24 | 12478947 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.447343899 | Feb 21 01:16:05 PM PST 24 | Feb 21 01:16:50 PM PST 24 | 8653759146 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/2.xbar_same_source.1829871677 | Feb 21 01:15:10 PM PST 24 | Feb 21 01:15:14 PM PST 24 | 60277380 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1397524231 | Feb 21 01:15:40 PM PST 24 | Feb 21 01:15:53 PM PST 24 | 8005479415 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.332166074 | Feb 21 01:17:11 PM PST 24 | Feb 21 01:17:13 PM PST 24 | 60887168 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2052354982 | Feb 21 01:17:59 PM PST 24 | Feb 21 01:18:07 PM PST 24 | 4977506165 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2819827601 | Feb 21 01:17:04 PM PST 24 | Feb 21 01:17:07 PM PST 24 | 8614273 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2566363811 | Feb 21 01:18:00 PM PST 24 | Feb 21 01:19:40 PM PST 24 | 2991365500 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/17.xbar_random.1304591183 | Feb 21 01:16:05 PM PST 24 | Feb 21 01:16:13 PM PST 24 | 2088132824 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1951291141 | Feb 21 01:16:30 PM PST 24 | Feb 21 01:16:35 PM PST 24 | 109404036 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2310217919 | Feb 21 01:18:03 PM PST 24 | Feb 21 01:18:13 PM PST 24 | 1187457931 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3335548313 | Feb 21 01:18:10 PM PST 24 | Feb 21 01:18:13 PM PST 24 | 17128574 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1076942911 | Feb 21 01:15:54 PM PST 24 | Feb 21 01:17:05 PM PST 24 | 77260729305 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4096831815 | Feb 21 01:17:52 PM PST 24 | Feb 21 01:17:56 PM PST 24 | 51362103 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.456828925 | Feb 21 01:17:12 PM PST 24 | Feb 21 01:17:25 PM PST 24 | 1078985599 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2268429415 | Feb 21 01:16:46 PM PST 24 | Feb 21 01:19:19 PM PST 24 | 32388523879 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.111706386 | Feb 21 01:15:39 PM PST 24 | Feb 21 01:15:48 PM PST 24 | 2399841654 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1420631255 | Feb 21 01:16:05 PM PST 24 | Feb 21 01:16:14 PM PST 24 | 322340389 ps |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.635728663 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2900273650 ps |
| CPU time | 132.2 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:18:31 PM PST 24 |
| Peak memory | 206888 kb |
| Host | smart-45db952d-126c-47af-b5f8-d837ff7a9475 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635728663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.635728663 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.358296816 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 79015877653 ps |
| CPU time | 327.27 seconds |
| Started | Feb 21 01:15:45 PM PST 24 |
| Finished | Feb 21 01:21:13 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-c9a0c270-04ac-481a-9bef-08d8d5058c2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=358296816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.358296816 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3668354228 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 71947355651 ps |
| CPU time | 295.72 seconds |
| Started | Feb 21 01:17:45 PM PST 24 |
| Finished | Feb 21 01:22:41 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-2dad5a1f-1d9d-4c75-b5b2-4aaec4593a2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3668354228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3668354228 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.644221568 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 157236235940 ps |
| CPU time | 299 seconds |
| Started | Feb 21 01:17:58 PM PST 24 |
| Finished | Feb 21 01:22:57 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-3be6038c-bb9e-46db-98e5-dc8ef87e673b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=644221568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.644221568 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.488598336 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 45252117441 ps |
| CPU time | 287.18 seconds |
| Started | Feb 21 01:16:59 PM PST 24 |
| Finished | Feb 21 01:21:47 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-8dabd23a-2628-4c4a-b0ad-520112df9060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=488598336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.488598336 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2970634289 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1910388902 ps |
| CPU time | 13.38 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:11 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-0ede6b0b-7864-424b-aca6-6e1772b28a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970634289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.2970634289 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3904780036 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 54270203635 ps |
| CPU time | 247.79 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:22:23 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-5934e7f3-7c99-4930-b1a8-3fe7d593470a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3904780036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.3904780036 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.312404597 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 84918225433 ps |
| CPU time | 287.7 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:22:00 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-3dad9d63-c374-451f-b0d5-1b178879a207 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=312404597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.312404597 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1442592658 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 113869517 ps |
| CPU time | 6.13 seconds |
| Started | Feb 21 01:15:08 PM PST 24 |
| Finished | Feb 21 01:15:15 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-a3d625bf-d5ce-429b-bea0-789824d04814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442592658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1442592658 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3147875785 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 72697287225 ps |
| CPU time | 65.14 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:19:10 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-a2ec0a2d-e4cb-4073-9610-b695f7615323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147875785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3147875785 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2310674088 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 35775753234 ps |
| CPU time | 256.11 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:20:15 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-333b395a-2caa-496a-837e-f4fc7850986e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2310674088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2310674088 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4075836030 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 185256956868 ps |
| CPU time | 291.08 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:21:56 PM PST 24 |
| Peak memory | 204012 kb |
| Host | smart-39708126-fdff-49ff-a8b4-27a47808dbaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4075836030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.4075836030 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.592973509 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1120356751 ps |
| CPU time | 141.53 seconds |
| Started | Feb 21 01:15:05 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-9eb4348e-0338-43ec-8883-56482c676cee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=592973509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.592973509 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3523087789 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1308921921 ps |
| CPU time | 76.02 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:18:55 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-fd5bb3d6-71cd-46b7-b815-9ed8a3a01e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3523087789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3523087789 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2338992015 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 722501055 ps |
| CPU time | 64.32 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 205688 kb |
| Host | smart-245dcf33-b6f5-47bc-a23e-099978ff4712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2338992015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.2338992015 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3188764988 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3124088399 ps |
| CPU time | 101.51 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:17:10 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-86e661bb-62c7-431c-ab0f-ef48c5a3411e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3188764988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.3188764988 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.3922072463 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 789554481 ps |
| CPU time | 11.3 seconds |
| Started | Feb 21 01:14:57 PM PST 24 |
| Finished | Feb 21 01:15:09 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-f09b9279-8b34-4aea-a2e1-68fe74be2814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922072463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3922072463 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3355267428 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 116638363242 ps |
| CPU time | 366.56 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:23:07 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-0e4e47ef-eb71-475c-a64f-9d10de2e17c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3355267428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.3355267428 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.175478962 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2283834558 ps |
| CPU time | 77.55 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 206640 kb |
| Host | smart-16ab5a63-3871-436d-909b-55b9f64b87aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175478962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.175478962 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2169537207 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 11391467130 ps |
| CPU time | 91.38 seconds |
| Started | Feb 21 01:15:22 PM PST 24 |
| Finished | Feb 21 01:16:54 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-2daf1a82-3d3d-4389-b4c0-a0b5a920e247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2169537207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2169537207 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1644937601 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 437861104 ps |
| CPU time | 58.46 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 203988 kb |
| Host | smart-fc950f22-8d3a-4571-ae17-0961504ce1c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1644937601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1644937601 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3264743134 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4848127657 ps |
| CPU time | 41.02 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:47 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-23dd77f6-15e9-4c93-a6e3-c660a15827da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3264743134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3264743134 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3053673761 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8686805853 ps |
| CPU time | 156.26 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:18:29 PM PST 24 |
| Peak memory | 207656 kb |
| Host | smart-79e738a8-d251-49b1-84f6-1b12f7112dcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3053673761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3053673761 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3404883574 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 206902246 ps |
| CPU time | 2.7 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:07 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-ae5d4c61-dbcb-405e-9a8e-c4f194d572e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3404883574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3404883574 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2811028096 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 46057783752 ps |
| CPU time | 305.15 seconds |
| Started | Feb 21 01:15:01 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-45cd7074-ce28-4a6f-afcd-dc6d761bcb3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2811028096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2811028096 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1772443800 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 102374005 ps |
| CPU time | 7.15 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-1119b841-bd07-4c65-9a90-8577d4a2ba96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1772443800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1772443800 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2014717215 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 48499805 ps |
| CPU time | 5.71 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-20ad882c-61e1-4474-81f7-d02ec361df38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014717215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2014717215 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.4156659792 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 621603167 ps |
| CPU time | 8.24 seconds |
| Started | Feb 21 01:14:54 PM PST 24 |
| Finished | Feb 21 01:15:03 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-b69f25a5-7616-4560-a939-a61fcaa21c64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156659792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4156659792 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3208164253 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 174758816270 ps |
| CPU time | 189.05 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:18:14 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-7b86958b-beef-46b7-b334-feecac0f2125 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208164253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3208164253 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.515252196 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 29997395195 ps |
| CPU time | 93.42 seconds |
| Started | Feb 21 01:15:03 PM PST 24 |
| Finished | Feb 21 01:16:36 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-09bb1359-ad28-44b6-b72b-aac6fa9ae2dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=515252196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.515252196 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2510773907 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 59456499 ps |
| CPU time | 7.09 seconds |
| Started | Feb 21 01:14:57 PM PST 24 |
| Finished | Feb 21 01:15:04 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-ff79c3a7-180e-49ad-822d-deb805b50e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510773907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2510773907 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2188856877 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 743530825 ps |
| CPU time | 9.45 seconds |
| Started | Feb 21 01:14:55 PM PST 24 |
| Finished | Feb 21 01:15:05 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-96e57835-3270-46d4-8b2d-4033930292fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2188856877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2188856877 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.2948702183 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 133624197 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:06 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-f9658381-8647-4f42-b489-570dc169c5ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2948702183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2948702183 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.349675430 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5476885847 ps |
| CPU time | 8.57 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:13 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-62f65ba4-f5a3-4219-b634-f34f553a91f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=349675430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.349675430 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1734656399 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 566643617 ps |
| CPU time | 4.77 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:10 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-50ae9a34-aace-4a27-9e80-3d6654b66d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1734656399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1734656399 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3052479198 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 21058787 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 01:14:53 PM PST 24 |
| Finished | Feb 21 01:14:55 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e1f572f1-7991-4725-9465-e6307e235a2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052479198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3052479198 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2202083567 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 686317360 ps |
| CPU time | 12.12 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:17 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-ecf190fd-dc88-4bb7-aba9-b139f75d7716 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2202083567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2202083567 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4071050047 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 4388373626 ps |
| CPU time | 70.37 seconds |
| Started | Feb 21 01:15:07 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-63bb25d3-1af7-437a-be9b-8ceb0ed56131 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4071050047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4071050047 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3744851327 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 858837591 ps |
| CPU time | 51.75 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:15:50 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-495155d9-df0e-477d-910b-8373854555af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3744851327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3744851327 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.4171971648 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6223368247 ps |
| CPU time | 119.82 seconds |
| Started | Feb 21 01:14:54 PM PST 24 |
| Finished | Feb 21 01:16:55 PM PST 24 |
| Peak memory | 206876 kb |
| Host | smart-382eff9f-bb0e-4937-850b-e600fd4f2c90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4171971648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.4171971648 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.968715805 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 397729907 ps |
| CPU time | 5.9 seconds |
| Started | Feb 21 01:14:57 PM PST 24 |
| Finished | Feb 21 01:15:03 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-bb99cbbf-465c-4bdc-ab8d-508811d7ce13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=968715805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.968715805 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2382888722 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 30262055 ps |
| CPU time | 5.98 seconds |
| Started | Feb 21 01:14:56 PM PST 24 |
| Finished | Feb 21 01:15:03 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-4868ebcc-624a-4867-a6b5-b48aaceec56a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2382888722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2382888722 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3278711262 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 21861921499 ps |
| CPU time | 168.07 seconds |
| Started | Feb 21 01:15:03 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-fa9fadd4-aca3-4ea9-a8e8-6ea0f7cf5e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3278711262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3278711262 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.4154141464 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 101763858 ps |
| CPU time | 1.71 seconds |
| Started | Feb 21 01:14:54 PM PST 24 |
| Finished | Feb 21 01:14:56 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-3bcea3c4-4815-4a1d-817d-f4cee25b6992 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4154141464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.4154141464 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.4086444922 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5763556382 ps |
| CPU time | 12.15 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:15:10 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-f645d8ab-8083-4577-af7a-3e29aa63d435 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4086444922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4086444922 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.4004658368 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 362245204514 ps |
| CPU time | 184.45 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:18:10 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-9caa1d22-9acb-42bf-adb9-6670743fe7b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004658368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4004658368 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.412420568 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 106017907904 ps |
| CPU time | 122.7 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-3c2a80a2-3ea7-47bc-b8a9-647fffe96c71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=412420568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.412420568 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.954852303 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 53188506 ps |
| CPU time | 4.35 seconds |
| Started | Feb 21 01:15:02 PM PST 24 |
| Finished | Feb 21 01:15:07 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-331f206a-94bc-4b2d-aa94-04b4a21132ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954852303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.954852303 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.1819329687 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 218604465 ps |
| CPU time | 2.16 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:15:08 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-94645d1a-4258-49e8-929b-ee3871920799 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1819329687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1819329687 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.795576179 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 173715861 ps |
| CPU time | 1.35 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:14:59 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-2c407581-11ab-412f-ac95-40cc3d66e2ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=795576179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.795576179 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.4120907535 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2412949787 ps |
| CPU time | 9.51 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:15:08 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-be0bc84d-65b1-4bbf-9595-05e62b314592 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120907535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.4120907535 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1999881621 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1391303229 ps |
| CPU time | 5.64 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:10 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-125f9c6a-a82a-4370-a1eb-befcedcaa7d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1999881621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1999881621 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2948594575 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 10028319 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 01:14:56 PM PST 24 |
| Finished | Feb 21 01:14:57 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-6a6c1456-998f-49df-a4bb-849c4fa0ff3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948594575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2948594575 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3347047562 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1167431648 ps |
| CPU time | 22.93 seconds |
| Started | Feb 21 01:15:07 PM PST 24 |
| Finished | Feb 21 01:15:30 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-a64dee7f-0fe7-40c7-ac45-483e6fc75f3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347047562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3347047562 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2316912678 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 133888407 ps |
| CPU time | 11.34 seconds |
| Started | Feb 21 01:15:00 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-1f0967f1-0053-4eb8-a980-1b6cccbd2627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2316912678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2316912678 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.511974934 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4498998566 ps |
| CPU time | 118.87 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:17:03 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-21137510-42a5-414c-957b-33ae739b45ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=511974934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.511974934 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.520526877 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 60094152 ps |
| CPU time | 4.57 seconds |
| Started | Feb 21 01:15:03 PM PST 24 |
| Finished | Feb 21 01:15:08 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-d4079ea1-8fa6-4d46-be33-3e37b420b19f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=520526877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.520526877 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2388788913 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 83449560 ps |
| CPU time | 1.89 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:01 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-594e4ddf-3b22-41eb-a226-9779107e4876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388788913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2388788913 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.8345502 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 4098863675 ps |
| CPU time | 28.35 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-679ad3db-6abd-4a56-90c3-ea52add6d5a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=8345502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.8345502 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1370208083 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 67214614 ps |
| CPU time | 1.76 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:15:54 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-d987528e-6da5-4c3d-a63e-55ea9dcb1d8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1370208083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1370208083 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2572736480 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 278699947 ps |
| CPU time | 6.04 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:12 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-d518c55f-c15d-483e-b721-74c88cf3b83f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2572736480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2572736480 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.3471840820 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 131231240 ps |
| CPU time | 7.16 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-b1985f1e-6d27-47cd-9c43-1a2cd20c6789 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3471840820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3471840820 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3269035571 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 14869129648 ps |
| CPU time | 36.09 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:37 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-22f45a40-e521-4f9c-b530-1c765b2a7de0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269035571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3269035571 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3063238850 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 12624608744 ps |
| CPU time | 60.89 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:59 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-be5c87db-b5d4-4a7c-b3e8-65995179ca33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3063238850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3063238850 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2015225150 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 137438901 ps |
| CPU time | 9.39 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:16:03 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-280b6ea5-45f7-4b20-9819-41b540479586 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015225150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2015225150 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3853914871 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 20388572 ps |
| CPU time | 1.88 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:15:59 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-94e47f8f-ccb8-4a49-bfb8-e035d01e0834 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3853914871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3853914871 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.1471935749 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 74630902 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:15:58 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-d9bc276c-8190-490f-beee-2b8deeae670a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1471935749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1471935749 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1285176641 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2555438264 ps |
| CPU time | 10.49 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-5308228c-e156-4c9a-ad33-ac448616234c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285176641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1285176641 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.285682500 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1076272776 ps |
| CPU time | 6.05 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:04 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-d697b422-5cc4-4160-90e8-9b52553cc5ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=285682500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.285682500 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1428615487 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 9275640 ps |
| CPU time | 1.4 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f7d8ec91-a6a6-4257-a80a-9721d7dd3347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428615487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1428615487 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2004626966 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2981753790 ps |
| CPU time | 39.26 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:16:30 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-d2ef7bda-4656-4100-af6b-ba4c64aec6f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2004626966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2004626966 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.475167585 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 523809291 ps |
| CPU time | 24.01 seconds |
| Started | Feb 21 01:15:56 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-d290f702-29aa-4df6-ba68-a8ba7a976075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=475167585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.475167585 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1284883103 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3218062446 ps |
| CPU time | 75.02 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:17:08 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-c493c305-57c0-4924-a98f-4b1baf57ee4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1284883103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1284883103 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3505088500 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 209859199 ps |
| CPU time | 14.47 seconds |
| Started | Feb 21 01:15:56 PM PST 24 |
| Finished | Feb 21 01:16:12 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-fa1033da-e858-47d5-ae16-9bd7b6ecdafc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3505088500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3505088500 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2518582838 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 33949777 ps |
| CPU time | 4.12 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a9d64ecb-4df6-478e-9244-1c1037f8d3ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2518582838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2518582838 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2654135641 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1082229988 ps |
| CPU time | 12.75 seconds |
| Started | Feb 21 01:15:45 PM PST 24 |
| Finished | Feb 21 01:15:58 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-da59f871-4eff-457f-bf83-e6afdb781ad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2654135641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2654135641 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3715971675 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 6579096965 ps |
| CPU time | 35.3 seconds |
| Started | Feb 21 01:15:46 PM PST 24 |
| Finished | Feb 21 01:16:22 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-7292dd1f-af16-4bb6-b105-1384efa9ba96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3715971675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3715971675 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2557775072 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 666830919 ps |
| CPU time | 9.11 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:16:04 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-18f81829-8bcc-4673-afe5-e9168c6aee0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2557775072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2557775072 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2482448582 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1164750921 ps |
| CPU time | 4.87 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-55559c84-2ad3-470f-81cf-b77c90705311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2482448582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2482448582 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1241461694 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 111928545 ps |
| CPU time | 2.5 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:15:55 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-0296e0f3-304c-4108-9287-f249cbe37413 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241461694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1241461694 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.399922561 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 39727206039 ps |
| CPU time | 96.69 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:17:38 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-d523093e-b463-48a4-aaa6-d839c3756915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=399922561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.399922561 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3329464311 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 66517619255 ps |
| CPU time | 138.14 seconds |
| Started | Feb 21 01:16:08 PM PST 24 |
| Finished | Feb 21 01:18:26 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-ccd48927-e05a-40b5-b9bb-6bf552fbe24f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3329464311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3329464311 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2391413132 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 32990200 ps |
| CPU time | 3.36 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-e08d8796-9ae9-4d3c-b443-412062a5420e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391413132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2391413132 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3846291216 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 79571124 ps |
| CPU time | 2.76 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:15:53 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a3df7371-c36a-4aaa-9d44-f377281ad16f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3846291216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3846291216 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3612418275 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 63067397 ps |
| CPU time | 1.65 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-e0e43136-651e-4ecb-8b45-04652319b8a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3612418275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3612418275 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3560068377 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 12106562795 ps |
| CPU time | 10.4 seconds |
| Started | Feb 21 01:15:47 PM PST 24 |
| Finished | Feb 21 01:15:59 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-da9ddf9f-5111-45a2-a746-c571f8006080 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560068377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3560068377 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1438793773 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2672763335 ps |
| CPU time | 8.17 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:16:01 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-47976431-e7fd-4438-8ad5-0cf3ef4695ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1438793773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1438793773 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.607951268 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 12126480 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:15:54 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-f6251c50-371d-4984-826c-7cc6e58b2e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607951268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.607951268 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2490135610 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 5245125070 ps |
| CPU time | 46.43 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:16:43 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-20bbb67a-e429-45d9-b46c-e1787bfb54b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2490135610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2490135610 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1443119748 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1842408861 ps |
| CPU time | 30.33 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:16:25 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-fc4e6d17-7593-49b6-b8d0-13d154d67347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443119748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1443119748 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.642106562 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1322971092 ps |
| CPU time | 224.76 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:19:42 PM PST 24 |
| Peak memory | 208504 kb |
| Host | smart-6a42394c-9828-4594-8159-44fd622eadfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642106562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.642106562 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1790963102 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 9494147 ps |
| CPU time | 1.65 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-e1c99724-c0c9-43cc-ad18-a3d750e3b3c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1790963102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1790963102 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2432434679 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 274657606 ps |
| CPU time | 4.2 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:15:58 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-7423826d-f218-47a1-8133-d582ebd63bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2432434679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2432434679 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.516351871 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 905493574 ps |
| CPU time | 15.37 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-8479cdf0-61ac-428d-8530-412ecb79047e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=516351871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.516351871 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2564594372 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 53809458884 ps |
| CPU time | 290.86 seconds |
| Started | Feb 21 01:15:49 PM PST 24 |
| Finished | Feb 21 01:20:41 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-4bb6c14d-21dd-45b8-b487-a8520df64d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2564594372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2564594372 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1949834636 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 211409379 ps |
| CPU time | 5.33 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:16:01 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-b2ffc0f4-ad49-4d19-b5b7-b6cc066a34f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949834636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1949834636 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1853440701 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1564032027 ps |
| CPU time | 6.99 seconds |
| Started | Feb 21 01:16:07 PM PST 24 |
| Finished | Feb 21 01:16:15 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-7c8b9a50-a9db-476b-a4f5-612345803698 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853440701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1853440701 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.1725961774 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 303175804 ps |
| CPU time | 6.16 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-ca267e74-6383-4c46-99ca-177e6dba1ecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1725961774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1725961774 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1076942911 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 77260729305 ps |
| CPU time | 69.34 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-a4fba5c8-30f1-4e37-9975-ca5de0a34f07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076942911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1076942911 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3487333652 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 11073424231 ps |
| CPU time | 49.77 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:16:43 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-8bae5c03-5c26-41f1-a1ec-a5fb013075a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3487333652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3487333652 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3513170105 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 86012009 ps |
| CPU time | 7.97 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:16:10 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-7ea1ef11-71e5-4bc7-9a0b-e9f4732198d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513170105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3513170105 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.3501150004 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 34112424 ps |
| CPU time | 1.77 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-c628fae4-6a7e-4ba4-b2d2-d9fff82bde9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501150004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3501150004 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1023938476 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 13580375 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:15:59 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-b381bb16-407c-4c21-9d64-c89662e6c6d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1023938476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1023938476 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.68502235 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6974086780 ps |
| CPU time | 12.36 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-b818b497-8538-4626-b256-b3ed9bb75ab9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=68502235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.68502235 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1278811728 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 950481505 ps |
| CPU time | 6.22 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:15:59 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-727ba185-7999-4009-a5c6-32dcbae4a383 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1278811728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1278811728 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1518040869 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 10305823 ps |
| CPU time | 1.2 seconds |
| Started | Feb 21 01:15:56 PM PST 24 |
| Finished | Feb 21 01:15:58 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-016b6209-6113-43ae-873f-32156f300158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518040869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1518040869 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.296831553 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1321436260 ps |
| CPU time | 17.37 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-511816c0-936d-4e9b-9382-d9474b60452c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=296831553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.296831553 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.79968344 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5427809180 ps |
| CPU time | 73.47 seconds |
| Started | Feb 21 01:15:51 PM PST 24 |
| Finished | Feb 21 01:17:06 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-7b241e42-9178-4b92-9818-87b4026ed7ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=79968344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.79968344 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1690708972 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 819515361 ps |
| CPU time | 138.47 seconds |
| Started | Feb 21 01:15:47 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 206172 kb |
| Host | smart-1810301f-269f-48ec-9191-0aa8d7968db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690708972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1690708972 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1707585708 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 817983864 ps |
| CPU time | 63.19 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:16:51 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-1ad06159-c1a1-4b3f-acca-95e89db8273f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707585708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1707585708 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1685896247 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 44866072 ps |
| CPU time | 1.54 seconds |
| Started | Feb 21 01:15:49 PM PST 24 |
| Finished | Feb 21 01:15:51 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-368a6b52-af68-403b-8aa7-39bb2da3888c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1685896247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1685896247 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.283193444 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 30676237 ps |
| CPU time | 4.45 seconds |
| Started | Feb 21 01:15:56 PM PST 24 |
| Finished | Feb 21 01:16:02 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-cf853dcb-13fa-4134-9291-8af1627f3380 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283193444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.283193444 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1858026556 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 82054928 ps |
| CPU time | 4.55 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:03 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-147926e3-a170-41b7-819f-d32d1b4bd081 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1858026556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1858026556 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3378433572 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 467951277 ps |
| CPU time | 3.26 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:16:04 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-7db3248f-7d37-4641-9058-117efc55e783 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378433572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3378433572 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.2000559874 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 430473933 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-944dd47a-3bbf-4cb0-ba21-fb64f4b888d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000559874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2000559874 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.4126985382 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 19620191950 ps |
| CPU time | 91.81 seconds |
| Started | Feb 21 01:16:07 PM PST 24 |
| Finished | Feb 21 01:17:40 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-e2590adc-bc29-4869-ad71-358ea3dfb921 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126985382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4126985382 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.362850248 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 24108112879 ps |
| CPU time | 119.53 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-400eb906-51a3-468c-8b58-6e9674275824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=362850248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.362850248 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2247930877 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 143653207 ps |
| CPU time | 7.66 seconds |
| Started | Feb 21 01:16:08 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-4a0b8bcf-b639-4d17-b02f-8516a9eea0ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247930877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2247930877 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.82499555 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 105444687 ps |
| CPU time | 2.06 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-07868c9d-6f00-4cd5-a1c8-47c836fa4f31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=82499555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.82499555 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.958582075 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 43950062 ps |
| CPU time | 1.35 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:15:57 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-c0d34d32-e0fc-47b1-8d0a-65cbbda66347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958582075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.958582075 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3699793795 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1629236299 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:15:58 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-127e7b76-61b9-4f55-9cb3-a7d740c8d978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699793795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3699793795 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.665563941 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1179793938 ps |
| CPU time | 5.62 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-4c016526-d6d6-49aa-b989-9b174316c25d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=665563941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.665563941 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2580412588 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 29109297 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:02 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-770011cd-44fe-4300-9d83-ea4ad1800669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580412588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2580412588 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3533752357 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 205672268 ps |
| CPU time | 15.56 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-a88348af-3ba3-45ab-ac3e-93a103949acd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3533752357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3533752357 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4226710808 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 547184392 ps |
| CPU time | 40.8 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:39 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-9321f33a-34b7-470e-abfb-6dac84fa258a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4226710808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4226710808 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1464888703 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 126959232 ps |
| CPU time | 19.64 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-12fd8861-5a8a-4980-9e26-4cce42d9274f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1464888703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1464888703 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3769373197 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 44838021 ps |
| CPU time | 3.46 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:01 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-decdbba5-401a-4874-a6fe-93ac51ccdcf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769373197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3769373197 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1442660948 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 171358251 ps |
| CPU time | 8.94 seconds |
| Started | Feb 21 01:16:08 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-bf94bab1-bfea-430f-82c1-a8d22b45a893 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1442660948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1442660948 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1040763860 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 81323609431 ps |
| CPU time | 339.86 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:21:42 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-36be088e-4294-48a4-9238-85df8a4fc660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1040763860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1040763860 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2151012309 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 408609836 ps |
| CPU time | 6.97 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-a19ae1b6-dcf9-432a-8cba-e63eff5b2321 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2151012309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2151012309 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2239482292 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 295194158 ps |
| CPU time | 1.79 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:02 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-3dfce7e6-d45b-44f3-a9c0-33b75ba4a42c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2239482292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2239482292 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1799183998 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 626428608 ps |
| CPU time | 9.91 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-83779542-3470-44bf-8ff6-a0a164e45e0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799183998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1799183998 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.81263852 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 30068434810 ps |
| CPU time | 78 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-d252173f-c976-4379-badf-3cb6d1dc5b96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=81263852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.81263852 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2563535604 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4501955504 ps |
| CPU time | 22.18 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:16:19 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-b67d9c15-d213-43de-ac8c-f085132402ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2563535604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2563535604 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3589008006 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 143047720 ps |
| CPU time | 4.1 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:03 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-d2fe8958-c2bb-4d6b-b7c5-2c3e39314834 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589008006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3589008006 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.2993838544 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1488447744 ps |
| CPU time | 13.8 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:12 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-34b64c4d-66cd-48e0-87e5-f7e9b366c203 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993838544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2993838544 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3103015869 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 75571207 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-a39f01b5-6d10-4278-a5c8-9059f468c1b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103015869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3103015869 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2044281583 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 8585017786 ps |
| CPU time | 11.01 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-249ea40f-6aa7-4f2f-a4ef-1c43d26cb425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044281583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2044281583 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.666102787 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1868295421 ps |
| CPU time | 6.15 seconds |
| Started | Feb 21 01:15:59 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-7b480544-c9b5-4b06-a5f8-42499a031562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=666102787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.666102787 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.99299751 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 11456968 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:15:54 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-7baff894-a9b3-45c4-9be7-77a3bd5c05d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99299751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.99299751 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3281049152 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2190597549 ps |
| CPU time | 17.78 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-48140c74-836d-49ca-a71c-a5c172f51468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281049152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3281049152 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3457582427 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 218200293 ps |
| CPU time | 2.81 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:04 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-8e778b70-ef17-4c1a-9bb4-dd5fe891120e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3457582427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3457582427 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1019876024 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 17254193557 ps |
| CPU time | 220.21 seconds |
| Started | Feb 21 01:15:57 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 205528 kb |
| Host | smart-71d3b299-e27a-4350-9e78-db0786c8be9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1019876024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1019876024 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3125238916 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2326467158 ps |
| CPU time | 57.33 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:58 PM PST 24 |
| Peak memory | 206576 kb |
| Host | smart-af369b64-94aa-4b7d-afb6-52a3635a418e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3125238916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.3125238916 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2878600591 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 760567886 ps |
| CPU time | 13.3 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-329e3ec3-fba5-42b8-b9d4-76164c25ce41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878600591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2878600591 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.332089590 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 38325509 ps |
| CPU time | 3.46 seconds |
| Started | Feb 21 01:16:01 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-95d632c6-839f-4e3e-8461-f5f96beff9a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332089590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.332089590 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.4268787142 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 45683545549 ps |
| CPU time | 313.27 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:21:19 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-8b1ce090-d1d3-4f72-8ae8-7c1710e10712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4268787142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.4268787142 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2106965713 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 95803012 ps |
| CPU time | 6.14 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a9f4b7e7-56da-4482-bae0-370111d82ca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2106965713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2106965713 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2093134154 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1078836491 ps |
| CPU time | 10.79 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-6e66cd69-cc3b-443b-9680-f7b71957afb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093134154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2093134154 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.313626097 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 948566925 ps |
| CPU time | 11.78 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:22 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-fab7ceeb-813a-4530-a000-7a843cfaace4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313626097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.313626097 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1466984453 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15283919717 ps |
| CPU time | 73.76 seconds |
| Started | Feb 21 01:16:09 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-31a2e95c-780f-4ba2-ae0c-a6bce4ff0a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466984453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1466984453 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.998054582 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 36647123122 ps |
| CPU time | 117.52 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-b7fec503-23a5-44ce-a392-816781264afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=998054582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.998054582 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.682430018 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 64103968 ps |
| CPU time | 4.68 seconds |
| Started | Feb 21 01:16:08 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-5eb637a8-b8f9-42ec-9015-efe6f8b71508 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682430018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.682430018 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.4061924593 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4734500240 ps |
| CPU time | 11.42 seconds |
| Started | Feb 21 01:15:59 PM PST 24 |
| Finished | Feb 21 01:16:11 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-fe390889-3259-42f7-933e-48f6e9e122d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061924593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4061924593 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.4216562720 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 51094666 ps |
| CPU time | 1.43 seconds |
| Started | Feb 21 01:15:59 PM PST 24 |
| Finished | Feb 21 01:16:01 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-928c1e30-63c5-4f8a-a16a-1e3beb499137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4216562720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4216562720 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1819507797 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1430720306 ps |
| CPU time | 6.31 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-2d91891b-3513-4ee6-a22e-00eb569f4586 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819507797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1819507797 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4033809553 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 798426637 ps |
| CPU time | 5.35 seconds |
| Started | Feb 21 01:15:58 PM PST 24 |
| Finished | Feb 21 01:16:03 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-db763d6a-9f15-43e3-ae51-72c5af668d68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4033809553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4033809553 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2800319270 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 9435766 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-a21e0218-8283-4d60-9a96-ecf9dc20dc02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800319270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2800319270 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.32060360 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 115731967 ps |
| CPU time | 13.17 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:24 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-639d4950-ddb0-4d7b-ae02-dfdf24bca002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=32060360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.32060360 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3831969953 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 461234537 ps |
| CPU time | 36.49 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:16:40 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-004da6de-2764-4b9d-86e9-fd8948f8d6af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3831969953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3831969953 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1947687595 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 503911839 ps |
| CPU time | 63.92 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-52543f43-dfd7-42ae-9068-59f49593d0b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1947687595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.1947687595 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1897152406 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 903029799 ps |
| CPU time | 109.93 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 206940 kb |
| Host | smart-d1b42460-9a18-4230-9cbd-c79ea2573cb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897152406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1897152406 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1619186621 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3266964116 ps |
| CPU time | 11.5 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-afec18ff-0406-4499-aea9-2317ead2ce66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1619186621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1619186621 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2135947309 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2055690155 ps |
| CPU time | 19.01 seconds |
| Started | Feb 21 01:16:07 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-c60e27f7-9fdb-421b-bc38-8ae7c5066eeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135947309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2135947309 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3432989253 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 153336151821 ps |
| CPU time | 394.85 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:22:41 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-882d92cd-c4f7-4728-bf26-f2a94aef7ae4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3432989253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3432989253 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4231754445 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 263697194 ps |
| CPU time | 5.61 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:11 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-bf62f50e-4a0b-48f5-a49b-dbe985b12e45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4231754445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.4231754445 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3742169028 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 618585062 ps |
| CPU time | 6.55 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-4c167105-4292-46b6-9f81-d6caabd9af06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3742169028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3742169028 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.3737561412 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 19207801 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:06 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-db426365-ddaf-444f-b320-0d6cc59f68fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3737561412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3737561412 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2064164680 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 19298013536 ps |
| CPU time | 78.13 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-283dd66a-a5b9-48b5-9d9a-8394432e7053 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064164680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2064164680 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2405170074 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 39626584100 ps |
| CPU time | 137.37 seconds |
| Started | Feb 21 01:16:02 PM PST 24 |
| Finished | Feb 21 01:18:20 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-503be266-28af-4ca7-8148-7b3b0227693c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2405170074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2405170074 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3300122816 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 38505234 ps |
| CPU time | 6.44 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:12 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-5f1ad693-d072-4c8a-9ace-0aaa2853f3cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300122816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3300122816 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2946511300 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 30866717 ps |
| CPU time | 2.82 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-78f22122-3c94-41c6-bdc4-dfe08fe79631 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2946511300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2946511300 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.714119590 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 48609943 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-f4a09b40-8969-41c4-90dd-a39795cbdd7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=714119590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.714119590 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2310282609 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3426122451 ps |
| CPU time | 9.58 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-43eb5346-4c43-4de8-a985-07f4c18e18b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310282609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2310282609 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.445171803 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4739112145 ps |
| CPU time | 12.29 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-321f6f66-a890-4112-a183-d41531fd1642 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=445171803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.445171803 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1254283691 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 10101952 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-5908645c-770f-439d-be51-67d62627a261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254283691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1254283691 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2366388837 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 162246693 ps |
| CPU time | 8.51 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-3bad71bb-994c-4813-84d2-1382732f91e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2366388837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2366388837 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1105023235 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 67889762 ps |
| CPU time | 4.26 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-5f5af455-b5fd-4e05-b505-b1120ee823da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1105023235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1105023235 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.254097559 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 258432973 ps |
| CPU time | 40.67 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:46 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-a2cfa8c2-920d-43c7-91e3-03e5e3373603 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=254097559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.254097559 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1909757827 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1641746884 ps |
| CPU time | 75.71 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:17:19 PM PST 24 |
| Peak memory | 206204 kb |
| Host | smart-69528456-2dcd-4d9a-a13b-55deb35192c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909757827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1909757827 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1241457726 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 832634130 ps |
| CPU time | 11.36 seconds |
| Started | Feb 21 01:16:02 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-93c80149-317b-4e1d-8304-aefaeae73e27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241457726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1241457726 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1420631255 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 322340389 ps |
| CPU time | 7.67 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-edbbffb5-d814-4066-927f-db18afcc308d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420631255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1420631255 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2208778472 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 16938928366 ps |
| CPU time | 40.56 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:47 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-adf730f2-d740-4efa-9569-d02985d8f538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2208778472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2208778472 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.73247068 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 68735965 ps |
| CPU time | 6.02 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:11 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-b6daaff4-5314-49c7-90e5-b65d7a36d938 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=73247068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.73247068 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3108811419 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 41110270 ps |
| CPU time | 2.76 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-a2e68d8a-9f0e-428c-a4b6-4225dc069f72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3108811419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3108811419 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.1304591183 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2088132824 ps |
| CPU time | 7.83 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-dba05daa-bf9a-4e11-ba6f-766f124efcf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1304591183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1304591183 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.270627542 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 44636637674 ps |
| CPU time | 196.84 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:19:21 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-85022091-4ca0-4f0f-ae93-e5e0d24fe5a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=270627542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.270627542 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3387312214 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 11118421875 ps |
| CPU time | 30.65 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:36 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-488f0284-f7ca-4b04-a189-1ac4df0c1392 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3387312214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3387312214 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3169652290 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 50322958 ps |
| CPU time | 5.47 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:11 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-4b35bee1-103d-4721-bc95-98175e1841da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169652290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3169652290 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.2261935211 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1807165995 ps |
| CPU time | 10.99 seconds |
| Started | Feb 21 01:16:07 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-29a7f0f1-9585-4759-8262-2f51541e5ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261935211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2261935211 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1498530835 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 51178094 ps |
| CPU time | 1.6 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-bcc32ff3-b758-4e88-887a-15169d9abe0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498530835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1498530835 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1291693789 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 7310825479 ps |
| CPU time | 11.36 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-f7f7b6c4-bf22-4899-b190-cbc88f4393ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291693789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1291693789 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2674725163 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1002402848 ps |
| CPU time | 5.15 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:11 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f4a83770-1e3b-4322-8b87-73158d5a2485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2674725163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2674725163 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3201602645 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 9236097 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-c9c62d1e-3a86-418c-8fa9-25325fe58606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201602645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3201602645 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.4101263552 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4815118597 ps |
| CPU time | 76.03 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-cf3eefda-8c9a-4a6d-aa65-a3da4e73537f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4101263552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4101263552 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.447343899 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 8653759146 ps |
| CPU time | 44.78 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:16:50 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-68adf46f-d522-4389-9c98-d2dfd662dd2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=447343899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.447343899 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3774824155 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 48297776 ps |
| CPU time | 10.9 seconds |
| Started | Feb 21 01:16:04 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-77bbaf6f-8949-4d95-b7ea-49461ae09705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3774824155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3774824155 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1699566146 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2822257805 ps |
| CPU time | 75.87 seconds |
| Started | Feb 21 01:16:02 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-0de99144-a956-43c1-8dfe-0afbdec5780c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699566146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1699566146 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2893346719 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 40531403 ps |
| CPU time | 3.37 seconds |
| Started | Feb 21 01:16:03 PM PST 24 |
| Finished | Feb 21 01:16:06 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-8bfeb1b8-0339-42c4-a9e7-261e7b4fe1f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2893346719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2893346719 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2863658659 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1091311221 ps |
| CPU time | 13.24 seconds |
| Started | Feb 21 01:16:09 PM PST 24 |
| Finished | Feb 21 01:16:23 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-543b0a18-7e5b-4cc4-a678-a3a51b5263da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2863658659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2863658659 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3899383947 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 21969908903 ps |
| CPU time | 173.41 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-69135808-1377-40f7-ac02-c94d3b92f7f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3899383947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3899383947 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1870573996 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 95412341 ps |
| CPU time | 6.31 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-938312b9-2ec5-4386-abae-e98d71db1bdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1870573996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1870573996 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.2886181847 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 26528809 ps |
| CPU time | 2.67 seconds |
| Started | Feb 21 01:16:02 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-af7e937b-70c8-4794-bf79-6f118a5b2d67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2886181847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2886181847 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.152148516 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 636696734 ps |
| CPU time | 9.22 seconds |
| Started | Feb 21 01:16:09 PM PST 24 |
| Finished | Feb 21 01:16:19 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-a1dec9b4-2fe0-4ad5-9fb3-7fb224cfdc34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152148516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.152148516 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.336681015 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 26383167942 ps |
| CPU time | 88.1 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-848c2930-9e77-4cab-b42e-22a1c0727b0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=336681015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.336681015 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3384458414 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 76333098394 ps |
| CPU time | 158.24 seconds |
| Started | Feb 21 01:16:09 PM PST 24 |
| Finished | Feb 21 01:18:48 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-b681f42f-75ad-4a4b-b4e8-2693f4a93a37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3384458414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3384458414 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1477320445 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 25097602 ps |
| CPU time | 2.3 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-5ce438c7-86f2-4723-b32b-9790c2759c89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477320445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1477320445 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1676104941 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 11538299 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-75306955-4070-4654-8da5-aa870ee91fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1676104941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1676104941 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.3984319937 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 102324814 ps |
| CPU time | 1.59 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-1c09c265-4fa9-4a08-84c5-19c5b95983db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984319937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3984319937 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3630188267 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1296308198 ps |
| CPU time | 6.7 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-06ab2023-f9fa-4e58-9899-0dd5d7175561 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630188267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3630188267 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4279881951 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 973173462 ps |
| CPU time | 6.14 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-36b944bc-295e-4244-9ec9-1b25189281dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4279881951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4279881951 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1749374105 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 8320549 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-f9e8d8d5-db55-42a8-9a47-9b3d755d38f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749374105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1749374105 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1967651569 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 337677321 ps |
| CPU time | 20.44 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:30 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-4a1504e6-7b23-4b36-8813-eb27ea3f8f37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1967651569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1967651569 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2872559408 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 11572067297 ps |
| CPU time | 61.59 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-8c9e97fd-6c75-448d-b475-14d2f3fd8972 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872559408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2872559408 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.34378339 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 7553594 ps |
| CPU time | 4.49 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c0710f20-4882-40ea-9836-577c8be030e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=34378339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_ reset.34378339 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.368448747 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 235020099 ps |
| CPU time | 33.61 seconds |
| Started | Feb 21 01:16:02 PM PST 24 |
| Finished | Feb 21 01:16:36 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-30f39918-d1e4-45b6-9e92-8d90adcd68f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=368448747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.368448747 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.915492343 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 57224310 ps |
| CPU time | 6.24 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-01b41418-6a97-4be0-920c-22bfeecdd1ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915492343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.915492343 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3655536484 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4488304491 ps |
| CPU time | 21.25 seconds |
| Started | Feb 21 01:16:07 PM PST 24 |
| Finished | Feb 21 01:16:28 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-deae29e9-8f9d-475f-a5c5-7abd59089e70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3655536484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3655536484 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2547003132 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 55480395559 ps |
| CPU time | 211.46 seconds |
| Started | Feb 21 01:16:05 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-fc470ae6-30c4-4819-b1d0-5b5df719d753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2547003132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2547003132 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1573115454 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 750505391 ps |
| CPU time | 8.37 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-53c192ac-5b80-48e1-8bc0-6403420b0a69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573115454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1573115454 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.3538922158 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 78806131 ps |
| CPU time | 6.59 seconds |
| Started | Feb 21 01:16:06 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ede85d84-5ac9-4f59-8912-f5d1b913be04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538922158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3538922158 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2354656615 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6008740177 ps |
| CPU time | 14.72 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:28 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-a0bb96a8-53af-431e-98b9-d5c048ca450d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354656615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2354656615 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.225294626 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 96451660353 ps |
| CPU time | 101.42 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:17:42 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-3b18116c-43b7-4d9b-9884-4b45facea49e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=225294626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.225294626 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.129411915 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13191575904 ps |
| CPU time | 91.84 seconds |
| Started | Feb 21 01:16:10 PM PST 24 |
| Finished | Feb 21 01:17:42 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-0d053de3-cfcf-444e-9d6a-7c3f9069d587 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=129411915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.129411915 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.659249984 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 37908258 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 01:16:11 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-d9214377-7e7c-4ad8-938c-bdf76982c7c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659249984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.659249984 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1502902170 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2575641007 ps |
| CPU time | 11.96 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-c714245a-c940-4b0b-a4c0-bba5c5cf58b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1502902170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1502902170 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3291919197 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 131858578 ps |
| CPU time | 1.35 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:15 PM PST 24 |
| Peak memory | 202056 kb |
| Host | smart-560e7844-a03d-4c89-bd85-6ae104efb7fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3291919197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3291919197 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1570527293 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2496171138 ps |
| CPU time | 11.2 seconds |
| Started | Feb 21 01:16:11 PM PST 24 |
| Finished | Feb 21 01:16:22 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-51f1ed94-031d-4122-ba13-38b38f93f742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570527293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1570527293 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3401119090 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2198442694 ps |
| CPU time | 5.73 seconds |
| Started | Feb 21 01:16:11 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-7a5f9e21-2dcb-4486-8555-76ca56f1ddc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3401119090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3401119090 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.729917772 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 16182565 ps |
| CPU time | 1.29 seconds |
| Started | Feb 21 01:16:11 PM PST 24 |
| Finished | Feb 21 01:16:12 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-047697d9-4b4f-4945-b3f2-5959b5605e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729917772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.729917772 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1111532592 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 617913035 ps |
| CPU time | 23.74 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:16:41 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-f2800d1b-07ec-4e90-be89-ff7aaaefe1a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1111532592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1111532592 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4123398367 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 11068376978 ps |
| CPU time | 44.39 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:17:01 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-361b6cfc-940d-4e03-92df-f77441c72f72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4123398367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4123398367 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3822015817 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1218541143 ps |
| CPU time | 153.86 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 208116 kb |
| Host | smart-6859e02f-036f-45e6-8a25-543ad8b00529 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822015817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3822015817 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3295914889 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 166380595 ps |
| CPU time | 3.31 seconds |
| Started | Feb 21 01:16:17 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-a5a48f38-31a2-45f6-86aa-5d3bd89f589b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295914889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3295914889 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3387142119 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 560082635 ps |
| CPU time | 6.68 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:15:05 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-cac05697-e2b1-48cb-9137-c37e6818969c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3387142119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3387142119 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1979466367 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3273592493 ps |
| CPU time | 20.27 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:15:27 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-a731ad55-ed61-4504-baf5-3f8b3969b132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1979466367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1979466367 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2830705861 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 25810798 ps |
| CPU time | 2.65 seconds |
| Started | Feb 21 01:15:02 PM PST 24 |
| Finished | Feb 21 01:15:05 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-e5638e86-db0a-468e-8d99-c8fbf4b0101a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830705861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2830705861 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2359857851 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 128598143 ps |
| CPU time | 2.65 seconds |
| Started | Feb 21 01:15:09 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-8b0ae266-060f-432b-b279-803c88413d52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2359857851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2359857851 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1395788474 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 57240004 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:15:08 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-9995cf00-ff4e-40b0-85c0-55a08e5cfc8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1395788474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1395788474 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3120790496 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 25244957406 ps |
| CPU time | 91.68 seconds |
| Started | Feb 21 01:14:56 PM PST 24 |
| Finished | Feb 21 01:16:28 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-294b33ef-e00e-43f4-8370-4c2a070b352a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120790496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3120790496 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4111454267 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 26833027665 ps |
| CPU time | 178.76 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-266fb407-a279-4ad6-8d2a-c93842bf97d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4111454267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4111454267 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2246431910 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 75668978 ps |
| CPU time | 4.47 seconds |
| Started | Feb 21 01:15:09 PM PST 24 |
| Finished | Feb 21 01:15:13 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-29794a28-a2e8-4263-ad80-c4593bb8f083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246431910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2246431910 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.1829871677 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 60277380 ps |
| CPU time | 3.5 seconds |
| Started | Feb 21 01:15:10 PM PST 24 |
| Finished | Feb 21 01:15:14 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-a9835c1f-3e79-4ac6-888f-ac1163a84eeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829871677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1829871677 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.4132297604 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 46302832 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 01:14:58 PM PST 24 |
| Finished | Feb 21 01:15:00 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-801c9d3c-9f9e-4541-a272-7e20ff72abae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4132297604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4132297604 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2147241475 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2885233593 ps |
| CPU time | 9.21 seconds |
| Started | Feb 21 01:15:06 PM PST 24 |
| Finished | Feb 21 01:15:16 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-fe03f57b-3f62-46b2-a3f7-947763d4aab1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147241475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2147241475 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1285151828 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1057214754 ps |
| CPU time | 7.26 seconds |
| Started | Feb 21 01:15:05 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-4a9e511f-9795-4ec4-8af7-bda74e1562a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1285151828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1285151828 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1720356560 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 13668527 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:05 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-a73a1598-b773-4d9a-8431-5a25f7a79488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720356560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1720356560 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.4294789359 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 8573276367 ps |
| CPU time | 107.32 seconds |
| Started | Feb 21 01:15:07 PM PST 24 |
| Finished | Feb 21 01:16:55 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-85f162ae-278f-4335-a43d-dde078d5fc70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4294789359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4294789359 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3434654462 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3626587568 ps |
| CPU time | 51.33 seconds |
| Started | Feb 21 01:15:04 PM PST 24 |
| Finished | Feb 21 01:15:55 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-331f8f72-63ed-4d54-830f-de70e938cfe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3434654462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3434654462 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.498293077 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 360285392 ps |
| CPU time | 29.43 seconds |
| Started | Feb 21 01:14:57 PM PST 24 |
| Finished | Feb 21 01:15:27 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-e3b5d738-4769-4ae8-8afb-8c29ad1fc3c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=498293077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_ reset.498293077 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2688121409 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 135530390 ps |
| CPU time | 18.37 seconds |
| Started | Feb 21 01:15:05 PM PST 24 |
| Finished | Feb 21 01:15:24 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-64921c86-057c-4a58-8ba4-5954b11ca165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688121409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.2688121409 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2805146443 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 71615450 ps |
| CPU time | 5.72 seconds |
| Started | Feb 21 01:15:08 PM PST 24 |
| Finished | Feb 21 01:15:14 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-37cbbd70-3c8e-46d7-b151-491592e10403 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2805146443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2805146443 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2482551591 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 174251457 ps |
| CPU time | 7.32 seconds |
| Started | Feb 21 01:16:28 PM PST 24 |
| Finished | Feb 21 01:16:36 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-a59215db-95b3-4731-aa38-1fafef0eedad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2482551591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2482551591 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.873175718 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 14424328641 ps |
| CPU time | 49.61 seconds |
| Started | Feb 21 01:16:24 PM PST 24 |
| Finished | Feb 21 01:17:14 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-81e4f559-94fd-4a81-8581-eaa0cf8bc259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=873175718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.873175718 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1585931487 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 345747275 ps |
| CPU time | 5.97 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:16:22 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-6bd8d086-5201-41ac-a5cc-0b84dbe8359f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1585931487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1585931487 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.1559250455 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 60449940 ps |
| CPU time | 7.6 seconds |
| Started | Feb 21 01:16:20 PM PST 24 |
| Finished | Feb 21 01:16:28 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-fd6e673c-c46c-4a8a-9c38-6da09c13a805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1559250455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1559250455 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.977194432 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 50111480 ps |
| CPU time | 5.33 seconds |
| Started | Feb 21 01:16:23 PM PST 24 |
| Finished | Feb 21 01:16:29 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-56898e56-0e1f-4495-883c-a31fddba14ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977194432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.977194432 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4191290101 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 49915169662 ps |
| CPU time | 67.42 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-27367cdc-a8b4-48a5-a773-fd77afdbf7b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191290101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4191290101 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.4003583571 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 113851511230 ps |
| CPU time | 104.07 seconds |
| Started | Feb 21 01:16:26 PM PST 24 |
| Finished | Feb 21 01:18:11 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-339dfc40-14bb-438f-bad1-180151ac1015 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4003583571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4003583571 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2632690860 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 103276337 ps |
| CPU time | 6.87 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-7ed50466-bf59-4a12-beba-b9ebda0bfe03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632690860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2632690860 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1870007534 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 92415752 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 01:16:24 PM PST 24 |
| Finished | Feb 21 01:16:29 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-9bd6883d-b258-412f-a239-99a4830c10b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1870007534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1870007534 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.1081873334 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 11767330 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-ee2cad6c-5d1f-4821-85af-51f85b3f5128 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081873334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1081873334 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1036184714 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1069444068 ps |
| CPU time | 5.7 seconds |
| Started | Feb 21 01:16:12 PM PST 24 |
| Finished | Feb 21 01:16:19 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-ae42cf1b-873f-4b8e-8303-b1c94616860d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036184714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1036184714 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1404718424 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4389650909 ps |
| CPU time | 7.78 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-aeca55b0-9b58-48bd-8024-3a1153ee1251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1404718424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1404718424 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3351416403 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 12857628 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:16:20 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-39eb8c01-886a-4c8b-8178-5358acfef24a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351416403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3351416403 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1902678308 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 669056098 ps |
| CPU time | 19.14 seconds |
| Started | Feb 21 01:16:23 PM PST 24 |
| Finished | Feb 21 01:16:42 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-f985b733-11e0-4a4b-af65-7eb51924461d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902678308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1902678308 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2782094844 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1985086478 ps |
| CPU time | 22.38 seconds |
| Started | Feb 21 01:16:14 PM PST 24 |
| Finished | Feb 21 01:16:37 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-baf9cd06-b722-49a2-b1a1-ebc283a0f3c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782094844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2782094844 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.302129000 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 331289854 ps |
| CPU time | 36.24 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:16:55 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-7497b14d-7664-4330-9ae0-6e4da3bdf341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302129000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.302129000 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1485965630 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 6655709391 ps |
| CPU time | 82.7 seconds |
| Started | Feb 21 01:16:23 PM PST 24 |
| Finished | Feb 21 01:17:46 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-fb5a507b-5960-42d5-92c1-c40ba4d1d7fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485965630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1485965630 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1450602639 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 355027787 ps |
| CPU time | 7.55 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:16:25 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-67fdbf3a-888a-4cf9-96ad-18f2825b9726 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450602639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1450602639 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.84031232 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1656008769 ps |
| CPU time | 8.96 seconds |
| Started | Feb 21 01:16:17 PM PST 24 |
| Finished | Feb 21 01:16:27 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-ccef6379-a4c9-46c5-a166-280a54797350 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=84031232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.84031232 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3759931938 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 35056004359 ps |
| CPU time | 71.35 seconds |
| Started | Feb 21 01:16:20 PM PST 24 |
| Finished | Feb 21 01:17:32 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-db168cbc-154b-46d2-9176-9aacf4a95c70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3759931938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3759931938 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3769423762 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 615194191 ps |
| CPU time | 3.12 seconds |
| Started | Feb 21 01:16:19 PM PST 24 |
| Finished | Feb 21 01:16:23 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-6b076bff-1d07-428f-95dc-6a7c85860244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769423762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3769423762 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.3122418688 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4078383058 ps |
| CPU time | 10.89 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:25 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-30273ea3-d23f-435a-b545-212015916097 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3122418688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3122418688 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.945723717 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 20231003 ps |
| CPU time | 2.28 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-014998b0-5b56-4f8d-b31c-beadcfeb0520 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945723717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.945723717 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1516969753 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 27268183520 ps |
| CPU time | 97.22 seconds |
| Started | Feb 21 01:16:14 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 202896 kb |
| Host | smart-b0e05625-5c77-41c5-9cab-129cbf59e5f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516969753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1516969753 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3333810048 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 11544608529 ps |
| CPU time | 54.39 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-6fed99c7-07b2-4a97-8b27-04dbe523df45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3333810048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3333810048 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1206305478 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 63613532 ps |
| CPU time | 4.03 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-3feb3a38-64df-40c5-9ce1-e06e6f703545 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206305478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1206305478 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2540844419 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 38981042 ps |
| CPU time | 2.86 seconds |
| Started | Feb 21 01:16:17 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-b9ea4a17-f759-4eda-a235-d21ed7d22697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2540844419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2540844419 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2895908216 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 68805859 ps |
| CPU time | 1.57 seconds |
| Started | Feb 21 01:16:14 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-4b332ec2-440f-4525-b72a-41608a1dc7ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895908216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2895908216 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2993990113 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5562885817 ps |
| CPU time | 6.79 seconds |
| Started | Feb 21 01:16:17 PM PST 24 |
| Finished | Feb 21 01:16:25 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-78564f03-a3de-4522-bc46-97327dcdd8ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993990113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2993990113 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1660558559 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 811853908 ps |
| CPU time | 5.42 seconds |
| Started | Feb 21 01:16:26 PM PST 24 |
| Finished | Feb 21 01:16:32 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-ae5d9ef9-53b8-45dc-97d4-5ae01302757c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1660558559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1660558559 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1356742361 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 19267043 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 01:16:13 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-6610deb1-d351-41c7-bf9c-f7628ea1efb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356742361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1356742361 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.409105911 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1657090826 ps |
| CPU time | 28.23 seconds |
| Started | Feb 21 01:16:24 PM PST 24 |
| Finished | Feb 21 01:16:53 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-3e2f0cbe-a093-4f21-b9d9-fb504fc5896a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409105911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.409105911 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1563854047 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 931184141 ps |
| CPU time | 15.47 seconds |
| Started | Feb 21 01:16:16 PM PST 24 |
| Finished | Feb 21 01:16:33 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-5fbed5cd-3a17-412f-bc6e-5dc110aa1dee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563854047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1563854047 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2945145087 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 6431872432 ps |
| CPU time | 104.22 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 206132 kb |
| Host | smart-77293fa5-a59f-489f-bff3-50800543a14f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2945145087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2945145087 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3117444738 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 127842481 ps |
| CPU time | 6.29 seconds |
| Started | Feb 21 01:16:19 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-594723df-4c27-4f39-b584-4f732db6f4c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3117444738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3117444738 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3264814901 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 103320205 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 01:16:42 PM PST 24 |
| Finished | Feb 21 01:16:44 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-c36aa368-bb6c-4e80-88a3-487ab794701b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3264814901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3264814901 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2246517189 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 21718273044 ps |
| CPU time | 48.15 seconds |
| Started | Feb 21 01:16:39 PM PST 24 |
| Finished | Feb 21 01:17:28 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-e89a9c16-94a4-47f0-a79e-6cf699f05516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2246517189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2246517189 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2308267890 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 2740850102 ps |
| CPU time | 6.2 seconds |
| Started | Feb 21 01:16:38 PM PST 24 |
| Finished | Feb 21 01:16:45 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-1bcc95af-b20d-4eed-91cd-e73fe5195695 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2308267890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2308267890 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.1555048698 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 46919012 ps |
| CPU time | 5.48 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:49 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-9d16c60a-340c-49ed-b610-aafda2b4f1ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555048698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1555048698 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.4266766283 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1921960672 ps |
| CPU time | 10.86 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:55 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-60198edf-9b46-43fb-9953-20aa8feb9278 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266766283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.4266766283 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1361929058 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 41019885369 ps |
| CPU time | 188.5 seconds |
| Started | Feb 21 01:16:45 PM PST 24 |
| Finished | Feb 21 01:19:53 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-60c4ffbf-2671-45f1-a526-730956448197 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361929058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1361929058 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3305491876 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 31237931158 ps |
| CPU time | 163.82 seconds |
| Started | Feb 21 01:16:46 PM PST 24 |
| Finished | Feb 21 01:19:30 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-4636410a-6c4e-4d68-9016-d7064d76d002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3305491876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3305491876 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1951291141 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 109404036 ps |
| CPU time | 4.62 seconds |
| Started | Feb 21 01:16:30 PM PST 24 |
| Finished | Feb 21 01:16:35 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-89295def-6060-43b7-87b7-2dc2788b80d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951291141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1951291141 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1725525503 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1682726567 ps |
| CPU time | 10.23 seconds |
| Started | Feb 21 01:16:46 PM PST 24 |
| Finished | Feb 21 01:16:56 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-5620e34c-a995-40aa-8306-7f58cfb15c0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1725525503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1725525503 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1834425076 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 20378413 ps |
| CPU time | 1.35 seconds |
| Started | Feb 21 01:16:18 PM PST 24 |
| Finished | Feb 21 01:16:21 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-e1269dd1-d02b-4c15-98bc-5f2801b97283 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834425076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1834425076 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2077478972 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2264257415 ps |
| CPU time | 10.3 seconds |
| Started | Feb 21 01:16:22 PM PST 24 |
| Finished | Feb 21 01:16:33 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-cef1ea76-63d2-4c93-a966-ae4758da4456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077478972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2077478972 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.60936764 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1151656341 ps |
| CPU time | 7.34 seconds |
| Started | Feb 21 01:16:19 PM PST 24 |
| Finished | Feb 21 01:16:27 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-f04bc30b-0fe4-4895-bc68-cca9fb6070a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=60936764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.60936764 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1689396382 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 10420505 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:16:15 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-2255a84a-fd69-4c73-93fb-1d9b9aba153a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689396382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1689396382 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2811901877 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 9104095684 ps |
| CPU time | 70.48 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-e26dc70a-a2e1-4bde-928d-8893444836e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811901877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2811901877 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2385812410 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 266928411 ps |
| CPU time | 24.03 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:17:01 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-49d36dae-eb34-45fa-8cdd-9d01ecd01067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385812410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2385812410 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3967870346 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 876512465 ps |
| CPU time | 113.18 seconds |
| Started | Feb 21 01:16:27 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-55f3061a-da29-45e4-9a62-a9613a946045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967870346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3967870346 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1051940273 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 16339584042 ps |
| CPU time | 67.96 seconds |
| Started | Feb 21 01:16:32 PM PST 24 |
| Finished | Feb 21 01:17:41 PM PST 24 |
| Peak memory | 207036 kb |
| Host | smart-021c7e4c-3b08-447f-a009-fe9ae44c2516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1051940273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1051940273 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1985292900 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 511052630 ps |
| CPU time | 6.61 seconds |
| Started | Feb 21 01:16:42 PM PST 24 |
| Finished | Feb 21 01:16:49 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-110be043-98e1-48c1-9704-2e1c803c6013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1985292900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1985292900 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3703203994 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 842504576 ps |
| CPU time | 10.52 seconds |
| Started | Feb 21 01:16:28 PM PST 24 |
| Finished | Feb 21 01:16:39 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-4a4f4157-e1c3-49d6-a412-65d35e46a166 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3703203994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3703203994 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2789616128 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 99261335830 ps |
| CPU time | 323.09 seconds |
| Started | Feb 21 01:16:36 PM PST 24 |
| Finished | Feb 21 01:22:00 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-0d43d327-6d50-44f0-a6cc-6c954ca654cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2789616128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2789616128 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.526229000 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 60923778 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:16:39 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-ec81c570-db34-4ba4-aa1a-2690aa4152be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=526229000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.526229000 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.1747091844 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 179878352 ps |
| CPU time | 2.63 seconds |
| Started | Feb 21 01:16:41 PM PST 24 |
| Finished | Feb 21 01:16:44 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-f8961af6-3032-496d-95a5-65a53c802d09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1747091844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1747091844 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.2148301166 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1288161554 ps |
| CPU time | 17.08 seconds |
| Started | Feb 21 01:16:28 PM PST 24 |
| Finished | Feb 21 01:16:46 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-57734f76-b285-41e7-9809-766554c86075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2148301166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2148301166 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2268429415 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 32388523879 ps |
| CPU time | 152.62 seconds |
| Started | Feb 21 01:16:46 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-dbe9b4a9-09be-4f17-9204-b2803e37fe6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268429415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2268429415 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.4241319627 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3457296873 ps |
| CPU time | 24.6 seconds |
| Started | Feb 21 01:16:32 PM PST 24 |
| Finished | Feb 21 01:16:58 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-107cb53b-130c-42f3-bd14-d797979bdb69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4241319627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4241319627 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.481610296 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 59428848 ps |
| CPU time | 7.4 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:16:45 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-ad47563b-3eb3-4828-a1da-ab68798553a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481610296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.481610296 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.758685011 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 49416196 ps |
| CPU time | 5.87 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:16:44 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-77953987-66d0-4cf5-b84e-a70ac1496bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=758685011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.758685011 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3667492488 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 9595532 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 01:16:46 PM PST 24 |
| Finished | Feb 21 01:16:47 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-d6f2e6b6-2f4b-4d79-a5ab-78e6369c2db9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667492488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3667492488 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.788872471 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2959275352 ps |
| CPU time | 11.7 seconds |
| Started | Feb 21 01:16:37 PM PST 24 |
| Finished | Feb 21 01:16:50 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-5d555b20-3cbf-4c2a-b53b-9b8290a5328c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=788872471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.788872471 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1651563590 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 10148960132 ps |
| CPU time | 14.89 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:58 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-b40a7e82-3518-4243-b2a6-87e925ae357d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1651563590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1651563590 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2545838935 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 11128534 ps |
| CPU time | 1.17 seconds |
| Started | Feb 21 01:16:31 PM PST 24 |
| Finished | Feb 21 01:16:33 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-a807f189-3b0e-4d47-b62e-fc94f2c2c9b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545838935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2545838935 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.4247434786 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1256868258 ps |
| CPU time | 14.35 seconds |
| Started | Feb 21 01:16:42 PM PST 24 |
| Finished | Feb 21 01:16:57 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-64cb6d4d-cc52-4da2-8500-6c4ae0cc2384 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247434786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4247434786 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.4248878572 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 9868420441 ps |
| CPU time | 80.34 seconds |
| Started | Feb 21 01:16:45 PM PST 24 |
| Finished | Feb 21 01:18:06 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-821a4a1e-e91c-44dd-9c37-35e9f6895aa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4248878572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4248878572 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.249599614 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 59073989 ps |
| CPU time | 9.62 seconds |
| Started | Feb 21 01:16:44 PM PST 24 |
| Finished | Feb 21 01:16:54 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-88d94be0-6335-4224-9b14-d25a5dc30680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=249599614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.249599614 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.620971030 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2954735327 ps |
| CPU time | 54.79 seconds |
| Started | Feb 21 01:16:38 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-690521b9-0a4e-4945-bcf8-08005960796a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=620971030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.620971030 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2188023811 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 751745033 ps |
| CPU time | 8.12 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:52 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-ec33dd7c-23d4-4a7f-a23a-52ef4295f9c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2188023811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2188023811 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1794347159 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 513406734 ps |
| CPU time | 12.63 seconds |
| Started | Feb 21 01:16:44 PM PST 24 |
| Finished | Feb 21 01:16:57 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-568b3e0b-7597-4133-9686-f58ea23f891f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1794347159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1794347159 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.233975383 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 138567216409 ps |
| CPU time | 310.89 seconds |
| Started | Feb 21 01:16:47 PM PST 24 |
| Finished | Feb 21 01:21:59 PM PST 24 |
| Peak memory | 204028 kb |
| Host | smart-fa4f2aa6-c2b9-4788-874e-49c43de09469 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=233975383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.233975383 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4223395449 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 125635396 ps |
| CPU time | 2.26 seconds |
| Started | Feb 21 01:16:59 PM PST 24 |
| Finished | Feb 21 01:17:02 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-5b6d8c36-131b-446a-b61e-1093f4be3bf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4223395449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4223395449 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.948452394 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 44932208 ps |
| CPU time | 3.82 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:47 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-71caebd8-f662-47fc-bf0a-f0c3dd52038a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=948452394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.948452394 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1619676876 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 740303023 ps |
| CPU time | 10.58 seconds |
| Started | Feb 21 01:16:41 PM PST 24 |
| Finished | Feb 21 01:16:53 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-a2f5a066-8b89-47d6-be03-9580e72e1565 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1619676876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1619676876 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1635861996 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 9689008831 ps |
| CPU time | 49.35 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:17:33 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-044e1c31-cae0-4bdf-98c5-1b2392af2d74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635861996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1635861996 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2829568783 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 14499854272 ps |
| CPU time | 105.09 seconds |
| Started | Feb 21 01:16:29 PM PST 24 |
| Finished | Feb 21 01:18:14 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-5467373f-c32b-4702-bf0f-c87af94f0971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2829568783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2829568783 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1583762180 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 87482188 ps |
| CPU time | 5.72 seconds |
| Started | Feb 21 01:16:44 PM PST 24 |
| Finished | Feb 21 01:16:50 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-b0a0677c-fe18-4461-94e8-14b603549272 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583762180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1583762180 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3233310073 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 35406704 ps |
| CPU time | 2.82 seconds |
| Started | Feb 21 01:16:45 PM PST 24 |
| Finished | Feb 21 01:16:48 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-06ea04fb-18d8-40d8-bf96-47206f223dbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3233310073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3233310073 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.470332317 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 9655848 ps |
| CPU time | 1 seconds |
| Started | Feb 21 01:16:43 PM PST 24 |
| Finished | Feb 21 01:16:44 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-1ff988f9-1dee-4b8a-8c7a-a9a90a30659d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=470332317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.470332317 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1173653064 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 10440481106 ps |
| CPU time | 9.75 seconds |
| Started | Feb 21 01:16:46 PM PST 24 |
| Finished | Feb 21 01:16:56 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-ecca9906-0201-451b-986c-4ac1e7a1666d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173653064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1173653064 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2741235824 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2536033086 ps |
| CPU time | 10.94 seconds |
| Started | Feb 21 01:16:44 PM PST 24 |
| Finished | Feb 21 01:16:55 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-108e36bf-25fa-477c-bfb7-1491d8edc7af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2741235824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2741235824 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.810029232 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 10237379 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:16:32 PM PST 24 |
| Finished | Feb 21 01:16:33 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-ed09140b-e7c1-40c0-8fdc-c370ea165f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810029232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.810029232 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2517725147 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 344966725 ps |
| CPU time | 7.85 seconds |
| Started | Feb 21 01:16:48 PM PST 24 |
| Finished | Feb 21 01:16:57 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-a3c41a42-0e58-414a-804f-213ed0ea714f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517725147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2517725147 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.4226003859 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 31973023891 ps |
| CPU time | 67.53 seconds |
| Started | Feb 21 01:16:55 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-cee5bddc-f788-4e23-9735-37b004f587b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4226003859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4226003859 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3032769695 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 627709140 ps |
| CPU time | 126.97 seconds |
| Started | Feb 21 01:16:56 PM PST 24 |
| Finished | Feb 21 01:19:04 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-3d4997be-1a3f-45d6-bab8-77ab437100e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3032769695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3032769695 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3025186868 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 535259606 ps |
| CPU time | 9.01 seconds |
| Started | Feb 21 01:16:30 PM PST 24 |
| Finished | Feb 21 01:16:40 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e2079379-02b1-4ae9-a0c3-eb36e63e014b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025186868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3025186868 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1628336685 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1759768235 ps |
| CPU time | 13.04 seconds |
| Started | Feb 21 01:16:50 PM PST 24 |
| Finished | Feb 21 01:17:04 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-d8a0b6f3-dcbb-45c9-a463-dcc62d317569 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628336685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1628336685 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1069149835 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 122740493 ps |
| CPU time | 2.4 seconds |
| Started | Feb 21 01:16:55 PM PST 24 |
| Finished | Feb 21 01:16:58 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-5036c942-04fe-4248-b998-a2a1489e40a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1069149835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1069149835 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.3532499828 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 11807703 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:02 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-b42aeed3-b7f9-4011-8928-28bb96f5d691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3532499828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3532499828 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.871409607 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1937615106 ps |
| CPU time | 11.49 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-aef89007-9a2c-4a9f-9284-90425d87236c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=871409607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.871409607 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1356343131 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 26840202155 ps |
| CPU time | 109.57 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-2e7ba2e0-e3a2-4d3f-a740-88f26419e395 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356343131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1356343131 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1433561066 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 17799670563 ps |
| CPU time | 106.23 seconds |
| Started | Feb 21 01:16:56 PM PST 24 |
| Finished | Feb 21 01:18:43 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-42dfe0e8-1454-43c9-8df7-7188ae0eedf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1433561066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1433561066 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2844663505 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 43083126 ps |
| CPU time | 3.46 seconds |
| Started | Feb 21 01:16:56 PM PST 24 |
| Finished | Feb 21 01:17:00 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-768dd859-0546-4559-b7de-1d7dc9b1de8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844663505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2844663505 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3062385225 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2380558265 ps |
| CPU time | 7.53 seconds |
| Started | Feb 21 01:16:54 PM PST 24 |
| Finished | Feb 21 01:17:02 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-3c6881fa-5ef5-4e39-bf10-ab29cd5d6e6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062385225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3062385225 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1338613384 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 139182356 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-af018ac6-308e-453c-8a4c-502033917f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1338613384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1338613384 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2523703816 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3043691460 ps |
| CPU time | 8.61 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-e65e015c-1894-49e0-915b-b6cacf07a174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523703816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2523703816 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.968948410 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9530787610 ps |
| CPU time | 11.84 seconds |
| Started | Feb 21 01:16:55 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-0d24cd23-d2d3-4db2-8ddc-35925d092dc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=968948410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.968948410 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.273557944 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 12733317 ps |
| CPU time | 1.27 seconds |
| Started | Feb 21 01:17:01 PM PST 24 |
| Finished | Feb 21 01:17:03 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-87c9c4c3-6a17-4e6c-afcc-0615ff09ec70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273557944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.273557944 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2803019384 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 4794955929 ps |
| CPU time | 37.06 seconds |
| Started | Feb 21 01:16:57 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-270894fd-7361-4af5-8b28-2ac059dfef46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2803019384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2803019384 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3674360612 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 139973549 ps |
| CPU time | 10.94 seconds |
| Started | Feb 21 01:16:57 PM PST 24 |
| Finished | Feb 21 01:17:08 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-2dc2e50e-db1f-4e24-8f8e-87c87ef1f000 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674360612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3674360612 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3316495377 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9919481692 ps |
| CPU time | 191.02 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-434d5110-431b-46fc-a813-718b823d0127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316495377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.3316495377 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2552774208 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7800388 ps |
| CPU time | 4.66 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-e06138b0-d8da-426c-9b7a-72a7b45c3054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552774208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.2552774208 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.831784145 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 778893257 ps |
| CPU time | 9.03 seconds |
| Started | Feb 21 01:16:57 PM PST 24 |
| Finished | Feb 21 01:17:06 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b5d72a77-bb5d-468f-b3e9-d3053583df73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831784145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.831784145 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3552933941 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 48048822 ps |
| CPU time | 1.8 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:08 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-1f491a53-4704-4a6d-bea8-b042ccf7bb9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3552933941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3552933941 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3873435920 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1282110943 ps |
| CPU time | 3.04 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-e7fee575-bca0-44f0-a52d-88769391c928 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3873435920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3873435920 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1843872445 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 48305238 ps |
| CPU time | 3.31 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:04 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f21e90f3-b007-48b6-9c1e-40483b851507 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1843872445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1843872445 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.690801743 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 437774020 ps |
| CPU time | 6.77 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-245d0cd7-e538-4dc6-96e0-1cb922d34906 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690801743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.690801743 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3992373939 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 45120050733 ps |
| CPU time | 165.55 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:19:46 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-95562a2b-011f-47bf-86bc-126e58b70457 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992373939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3992373939 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.714473879 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 15758305204 ps |
| CPU time | 96.78 seconds |
| Started | Feb 21 01:16:55 PM PST 24 |
| Finished | Feb 21 01:18:32 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-5bd3b15d-1be4-4db8-8a65-f655c450bcf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=714473879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.714473879 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.4106461561 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 46387493 ps |
| CPU time | 6.06 seconds |
| Started | Feb 21 01:16:50 PM PST 24 |
| Finished | Feb 21 01:16:56 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-81d13939-a770-4706-a0a7-be52e0f89bce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106461561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.4106461561 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3468854487 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1565641520 ps |
| CPU time | 8.71 seconds |
| Started | Feb 21 01:16:56 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-159d3d72-3444-450a-bbc7-8c850aebeaf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3468854487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3468854487 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.940104566 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 33328831 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 01:16:50 PM PST 24 |
| Finished | Feb 21 01:16:52 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-616a49cb-35b2-4841-b942-78da8cd456a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=940104566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.940104566 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.4137717711 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2163160869 ps |
| CPU time | 8.22 seconds |
| Started | Feb 21 01:16:56 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-7d76863c-21ae-48d9-a2dd-e23fbbb6194f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137717711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.4137717711 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.175089147 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 668028738 ps |
| CPU time | 5.98 seconds |
| Started | Feb 21 01:16:57 PM PST 24 |
| Finished | Feb 21 01:17:03 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-e481787d-2a8f-4198-b100-a8cbe5aae7ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=175089147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.175089147 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2496006918 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 8666309 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:16:49 PM PST 24 |
| Finished | Feb 21 01:16:50 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-aba15c3f-770a-4a87-b7f4-67eb0b051d51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496006918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2496006918 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2803976329 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3680883891 ps |
| CPU time | 31.25 seconds |
| Started | Feb 21 01:17:01 PM PST 24 |
| Finished | Feb 21 01:17:33 PM PST 24 |
| Peak memory | 202896 kb |
| Host | smart-fed71633-0100-4c52-a07e-6d53ecb9a65e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2803976329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2803976329 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1341889416 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2172305762 ps |
| CPU time | 117.07 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:19:02 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-2404ff9d-ca7f-4d35-8b56-861a16e2257f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1341889416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1341889416 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.517283956 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 141327404 ps |
| CPU time | 11.73 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-371fde86-0d5e-4d59-bdd2-21304ef8d365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=517283956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.517283956 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3732399953 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 152356621 ps |
| CPU time | 5.74 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-89847430-12b8-48b6-8987-637a363650e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3732399953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3732399953 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.167564693 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 180410765 ps |
| CPU time | 3.98 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-a696f738-9133-4bc1-92f3-ba75d40012d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=167564693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.167564693 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.524608509 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 12474851281 ps |
| CPU time | 78.69 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:18:23 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-a64cbb9e-9252-4959-b989-8330f5c36731 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=524608509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.524608509 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4000845013 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 65340225 ps |
| CPU time | 5.88 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-687da94f-7836-4b60-be23-54b30ee22e9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000845013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.4000845013 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.1218961532 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 33525582 ps |
| CPU time | 3.74 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-5544aa79-746e-4aa0-a85a-0a58df55e991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1218961532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1218961532 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.799176747 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 62940175 ps |
| CPU time | 7.11 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:10 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-52b71f88-ba12-4aa1-ae8f-096f7a0a951e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=799176747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.799176747 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2802393170 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 251820657140 ps |
| CPU time | 140.6 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:19:21 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-eeec9563-9e78-473e-83d2-57533d3fdd50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802393170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2802393170 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2778692666 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 100557333951 ps |
| CPU time | 85.94 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:18:35 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-1efe7da5-be3e-452c-8da3-11746238ff3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2778692666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2778692666 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2556185171 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 171980840 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 01:16:59 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-1c9d3a75-f381-4127-b672-bcd5c6a71f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556185171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2556185171 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.2672256177 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 968902975 ps |
| CPU time | 9.44 seconds |
| Started | Feb 21 01:17:07 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-173e72e0-01bc-4479-a435-68aadafa87fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2672256177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2672256177 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3749720827 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 85121973 ps |
| CPU time | 1.84 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-a972d689-e2d9-4a8c-a838-ec7516f7b177 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3749720827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3749720827 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4208677186 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7440782895 ps |
| CPU time | 8.88 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-20f65f18-01e2-4faa-b781-27b7800d8ced |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208677186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4208677186 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2151090166 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 939776739 ps |
| CPU time | 6.63 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-7aba26f3-54d6-4c92-9525-b6eb02bdcf3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2151090166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2151090166 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2819827601 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 8614273 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-a159e1a7-ce91-4e9b-aa36-7485e27034e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819827601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2819827601 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1681957897 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 13101991974 ps |
| CPU time | 89.12 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:18:40 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-0a56a50c-a454-48cf-81ac-2cc104b7fb8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1681957897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1681957897 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.298872206 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1913458181 ps |
| CPU time | 33.69 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:17:44 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-66f609a6-c6e9-4ea2-9560-e5cdb0950c37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=298872206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.298872206 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2794414860 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 426242908 ps |
| CPU time | 26.94 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:38 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-460385a6-6a68-48e2-aece-3f1643e91b4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2794414860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2794414860 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.179595883 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2899698121 ps |
| CPU time | 61.33 seconds |
| Started | Feb 21 01:17:06 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 204968 kb |
| Host | smart-87c12dab-cc9b-4d95-8143-f3145139e433 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=179595883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.179595883 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3231548465 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 467573461 ps |
| CPU time | 7.58 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-e3176612-1c34-4961-a214-a727b49d3b80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231548465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3231548465 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2645075529 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 52387007 ps |
| CPU time | 7.29 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-29685d99-29d3-402f-9351-28f3b071d0ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2645075529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2645075529 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1602645644 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 32144175 ps |
| CPU time | 3.3 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-9d4b58e7-06b8-4378-b80d-557659ef4121 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1602645644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1602645644 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.1347657056 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 230197526 ps |
| CPU time | 3.84 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:10 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-cf562b51-7141-4dd6-9b7e-c140ae63ffaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1347657056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1347657056 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.1868589600 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 582437570 ps |
| CPU time | 7.69 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-825a1ab7-09f6-494c-addd-3e345129ed1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868589600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1868589600 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3681621536 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 156692312438 ps |
| CPU time | 171.08 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:20:05 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-e4a2c3eb-4478-484c-a7db-e44ec1267466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681621536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3681621536 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2685049077 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 24394997855 ps |
| CPU time | 146.8 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:19:30 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-d342c58e-a9e6-4ea8-ac74-be72073ccedc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2685049077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2685049077 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2118548741 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 59234669 ps |
| CPU time | 4.72 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:19 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-e99b28cb-dec2-48be-b10c-f4f6dccc6906 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118548741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2118548741 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1096385337 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 970921550 ps |
| CPU time | 4.81 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-e9d49b38-6ed8-4c75-98ef-48de1238ec8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1096385337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1096385337 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2385304852 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 11882625 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:08 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-bc15432d-6dff-4675-82b5-f0f57f609680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385304852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2385304852 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2239596872 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2896676824 ps |
| CPU time | 9.7 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-ad220531-791e-471d-a197-733742340321 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239596872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2239596872 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.844523081 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 4977705082 ps |
| CPU time | 8.2 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-52395589-3f18-4d4a-a53d-7f5d2a7c1d5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=844523081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.844523081 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1432392185 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 9859266 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-0a1c6188-aaeb-4458-925c-e36d04b01452 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432392185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1432392185 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.313797002 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2981800240 ps |
| CPU time | 49.79 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:54 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-2e33c167-f567-438b-939e-a3c420d2d951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313797002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.313797002 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2325901876 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 675309180 ps |
| CPU time | 9.88 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-ebf0d4ea-6456-4543-8e16-5a225b13bd0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325901876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2325901876 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1570341152 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 104702355 ps |
| CPU time | 9.25 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-60c9cad9-5281-4e7b-9bf9-85666b4138ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570341152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1570341152 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.350237929 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 411993903 ps |
| CPU time | 31.48 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-975ae7c0-2741-47ed-ba6d-e87863aca34d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=350237929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.350237929 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3340478290 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 185120354 ps |
| CPU time | 6.19 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-643ddd85-86ff-4b39-8ab5-b7d982992a30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340478290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3340478290 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1573705438 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 498807309 ps |
| CPU time | 5.28 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-af745988-7490-49cc-acd0-4fdb64e06d26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573705438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1573705438 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.723320821 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 72624516672 ps |
| CPU time | 149.95 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:19:31 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-56621883-054e-4c25-bd4a-c79298e1c9a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=723320821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.723320821 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2583130057 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 142255435 ps |
| CPU time | 3.94 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-eec0d581-6d99-4140-8c3f-5cdaf759ac94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2583130057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2583130057 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.2616425846 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 106505580 ps |
| CPU time | 5.96 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-3f9ff7bc-3168-46b9-8c84-d6a63d88364e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2616425846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2616425846 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.4124197382 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 156212614 ps |
| CPU time | 2.07 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-b5587a62-666d-4514-b4d6-618cc76b228c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4124197382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.4124197382 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.583442328 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 50184592219 ps |
| CPU time | 88.98 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:18:45 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-aa71be51-15ca-41ad-8999-1a5203504475 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=583442328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.583442328 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.4126195616 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6662152182 ps |
| CPU time | 43.19 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:57 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-c13f0e01-fa53-472f-b557-fe3bac11cc70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4126195616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4126195616 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3494139037 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 453126558 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-bc0ba70d-ff8e-4488-bc7b-d7a7f41d122b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494139037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3494139037 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3432763643 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1177498708 ps |
| CPU time | 7.35 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:14 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-28a73819-89a8-4754-a2a6-38aa32da66e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432763643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3432763643 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.858183867 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 146182276 ps |
| CPU time | 1.45 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202088 kb |
| Host | smart-51aa3ef8-ca29-4cf0-b29d-04e56e0a9c98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858183867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.858183867 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.520134057 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2391501467 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-ede89c14-1421-4cad-bdf7-a83e784b360b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=520134057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.520134057 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4168571904 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1371987797 ps |
| CPU time | 9.96 seconds |
| Started | Feb 21 01:17:07 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-7d8a44db-2683-47e2-b5ce-e467c28fffbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4168571904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4168571904 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1924470149 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 8427720 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-5380a4fe-3bce-45ad-951b-ea18cbb9d189 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924470149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1924470149 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4035004377 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2724075922 ps |
| CPU time | 32.54 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:39 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-0f156e03-8da2-4488-8b58-3df8be73edd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4035004377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4035004377 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2808726833 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 331120775 ps |
| CPU time | 32.36 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:37 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-422c49df-7059-4cea-b0fc-8fb0bc013f25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2808726833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2808726833 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2050858982 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 11772446027 ps |
| CPU time | 120.38 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-911afb0b-d8f7-48b1-8e89-9f9e54bfa06d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050858982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2050858982 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.549088862 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3218714905 ps |
| CPU time | 22.42 seconds |
| Started | Feb 21 01:17:09 PM PST 24 |
| Finished | Feb 21 01:17:32 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-2834418a-b9bf-4474-b6c2-b3a02964fe96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=549088862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.549088862 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.4254217473 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 382271745 ps |
| CPU time | 6.89 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:10 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-fd094e62-1aea-4c7b-a7f8-b6b17ab07d8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4254217473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4254217473 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3438305040 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 27724999 ps |
| CPU time | 5.01 seconds |
| Started | Feb 21 01:15:07 PM PST 24 |
| Finished | Feb 21 01:15:12 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-204b02a9-255e-428f-a9e9-61eb3f29bf89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3438305040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3438305040 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1764580892 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 46312842264 ps |
| CPU time | 266.62 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:19:46 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-7f9d9e70-90ba-4610-bd4e-a151d499216a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1764580892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1764580892 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1487583943 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1251703477 ps |
| CPU time | 6.86 seconds |
| Started | Feb 21 01:15:10 PM PST 24 |
| Finished | Feb 21 01:15:18 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-f47e1ebd-2061-4e41-91d4-ebb0e90ce249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487583943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1487583943 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.201480332 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2544770811 ps |
| CPU time | 14.04 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:15:33 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-5c5697d7-8327-4396-aa4a-161aeb3db4f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=201480332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.201480332 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3101556936 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 75321916 ps |
| CPU time | 6.22 seconds |
| Started | Feb 21 01:15:08 PM PST 24 |
| Finished | Feb 21 01:15:14 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-14f7e929-50e6-4530-b97d-7c314e5e0742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101556936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3101556936 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2431746605 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 39253116436 ps |
| CPU time | 94.59 seconds |
| Started | Feb 21 01:15:09 PM PST 24 |
| Finished | Feb 21 01:16:44 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-379655ce-4a45-44a9-b82a-f4798eae27eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431746605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2431746605 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.877388988 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 5291098828 ps |
| CPU time | 32.93 seconds |
| Started | Feb 21 01:15:09 PM PST 24 |
| Finished | Feb 21 01:15:42 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-31e53c5f-b5d2-4b2d-a4d5-d2bd584a7050 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=877388988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.877388988 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.2360550434 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 535122918 ps |
| CPU time | 3.12 seconds |
| Started | Feb 21 01:15:07 PM PST 24 |
| Finished | Feb 21 01:15:11 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-68b41395-7b5c-4a3a-9560-875a782e4875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2360550434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2360550434 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2038027009 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 10086827 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 01:15:11 PM PST 24 |
| Finished | Feb 21 01:15:13 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-5c5045dc-f680-4897-9f63-07edec6e0999 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2038027009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2038027009 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4165851001 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4244914232 ps |
| CPU time | 8.4 seconds |
| Started | Feb 21 01:15:08 PM PST 24 |
| Finished | Feb 21 01:15:17 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-0a5b9d7d-e3c0-405b-8ddf-f29da09fd178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165851001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4165851001 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1003150506 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1084632958 ps |
| CPU time | 7.91 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:15:27 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-215a3967-e20e-450b-b9d8-32bacd950e3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1003150506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1003150506 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.454358178 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 9664479 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:15:10 PM PST 24 |
| Finished | Feb 21 01:15:11 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-afbd2e5d-405c-449a-ab3a-8c2661a3c04a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454358178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.454358178 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3437140891 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3151911183 ps |
| CPU time | 27.52 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:15:47 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-8ac129d4-eea0-4403-91b0-7f30070ec346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437140891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3437140891 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.687511001 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4120397674 ps |
| CPU time | 20.32 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:15:38 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-448d2065-3219-4d43-84f0-8d9925aa00a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=687511001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.687511001 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2357694028 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2517676212 ps |
| CPU time | 51.79 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-f06b0312-7a10-4ef9-8413-8d8cbf27c553 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357694028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2357694028 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.918083951 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4854593915 ps |
| CPU time | 61.13 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-b2b13e63-61b9-4b61-8086-397f8a9e978e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918083951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.918083951 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1919178333 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2892891202 ps |
| CPU time | 10.52 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:15:29 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-1f3a1fff-7858-4e8d-9a4d-c68428b5e1fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1919178333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1919178333 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.222573610 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 465465241 ps |
| CPU time | 8.87 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-05d1469a-d619-4c20-9b95-f3d860dfb954 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=222573610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.222573610 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2288407410 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 18379553060 ps |
| CPU time | 102.3 seconds |
| Started | Feb 21 01:17:06 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-c091257e-30a8-4c61-861a-0927d7e49a40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2288407410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2288407410 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3003544576 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 532168460 ps |
| CPU time | 6.24 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-714a491f-2cee-42e9-bcce-6e32e7f4c368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003544576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3003544576 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.1082511760 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 102713716 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:02 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-03cc7d3c-6094-463c-869d-7a996bd856f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1082511760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1082511760 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2242866913 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2117353480 ps |
| CPU time | 11.75 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-0968be86-70fd-46f6-8519-02ad3cd0e978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2242866913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2242866913 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1006683661 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 29474801677 ps |
| CPU time | 111.79 seconds |
| Started | Feb 21 01:17:07 PM PST 24 |
| Finished | Feb 21 01:19:00 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-23d61a7d-8997-482f-ae8c-9eff085ada54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006683661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1006683661 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.81091055 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 13306157214 ps |
| CPU time | 59.04 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-ea90ef40-49aa-470f-8c6a-889b4bfdae91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=81091055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.81091055 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1308832013 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 65530257 ps |
| CPU time | 9.09 seconds |
| Started | Feb 21 01:17:05 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-171c6c99-2808-4f98-8548-8d60beca5fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308832013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1308832013 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1928377428 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 30426868 ps |
| CPU time | 2.94 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:17:03 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-7cd998a7-9b13-4a1d-86b5-2993571571e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1928377428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1928377428 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3411539361 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 8661901 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:05 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-36307ff1-3d2b-4e7c-872a-4077998b9094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3411539361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3411539361 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4068995248 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2640681720 ps |
| CPU time | 7.9 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-32f70caf-032b-4cf4-96d9-aab37260a102 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068995248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4068995248 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.4277500402 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 888880333 ps |
| CPU time | 6.61 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:11 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-3a9bcc45-3a60-4c32-90e6-c7522765891f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4277500402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4277500402 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.927725594 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 8459236 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:10 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-32fb4bf5-5f1f-435b-a1fe-a49e231356c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927725594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.927725594 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.697416313 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 574295055 ps |
| CPU time | 46.94 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-a317a405-f4b1-4c2c-be2e-9c8f31e1b4fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=697416313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.697416313 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2411226797 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 11528800324 ps |
| CPU time | 82.97 seconds |
| Started | Feb 21 01:17:00 PM PST 24 |
| Finished | Feb 21 01:18:24 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-e47a35cb-9d20-4d84-a183-6445f57dc1e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2411226797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2411226797 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1420768864 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2301892331 ps |
| CPU time | 84.29 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:18:27 PM PST 24 |
| Peak memory | 205240 kb |
| Host | smart-430504f7-83ae-48ba-8b89-6f077c0e57fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420768864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.1420768864 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.173313659 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 342342875 ps |
| CPU time | 27.04 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:36 PM PST 24 |
| Peak memory | 203012 kb |
| Host | smart-5ae6f59e-fcbc-4bc9-8d59-d083a1d4091c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173313659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.173313659 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1081083076 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 120934766 ps |
| CPU time | 1.67 seconds |
| Started | Feb 21 01:17:06 PM PST 24 |
| Finished | Feb 21 01:17:09 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-38c55451-59b6-4558-8d4a-b1597738bc6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081083076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1081083076 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2247385763 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 677818464 ps |
| CPU time | 13.6 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:18 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-6c4381d7-70a3-4bab-8a43-6a643b0dfb9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247385763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2247385763 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2292433525 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 62767279109 ps |
| CPU time | 309.71 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:22:14 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-3efe606d-7112-4013-93b1-c9a3ea91ba6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2292433525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2292433525 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.702467972 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 401565802 ps |
| CPU time | 6.82 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-9ca7b99f-48e7-40fe-82af-0a02c4770f06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702467972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.702467972 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.2781536578 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 72937494 ps |
| CPU time | 8.87 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-20de1bb5-2f5c-4642-b6aa-d1efc4b5ba20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781536578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2781536578 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2784757743 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 450187885 ps |
| CPU time | 4.02 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:08 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-49413ca5-a59f-42cc-b6aa-ecd2fc8b1db9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784757743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2784757743 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3267831764 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 35963157974 ps |
| CPU time | 116 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-4fa1a345-0ce5-4fe6-b607-04c8a7531c59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267831764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3267831764 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3519254354 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2174541612 ps |
| CPU time | 16.51 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-c7fe8d34-35f4-4e55-88ae-aee5ef48a337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3519254354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3519254354 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1032806850 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 608021379 ps |
| CPU time | 7.79 seconds |
| Started | Feb 21 01:17:06 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-b7553086-5526-4ac5-b4bf-c8893d4c4f0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032806850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1032806850 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1484727553 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 19694771 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 01:17:01 PM PST 24 |
| Finished | Feb 21 01:17:04 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-a3566837-39b8-40ff-8b58-88ce7d67f7fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484727553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1484727553 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2365546676 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 103943586 ps |
| CPU time | 1.86 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-1d2c23fb-2cc3-404d-a4a6-398a3365ce4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2365546676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2365546676 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.569713179 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2656157367 ps |
| CPU time | 11.68 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-25ddf73a-5200-4602-a4e9-3562de67202e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=569713179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.569713179 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2296374859 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1148558944 ps |
| CPU time | 6.93 seconds |
| Started | Feb 21 01:17:03 PM PST 24 |
| Finished | Feb 21 01:17:11 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-29f44390-03cb-42bb-9699-886fae008439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2296374859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2296374859 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2922406171 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 18822908 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:17:02 PM PST 24 |
| Finished | Feb 21 01:17:04 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-26c03599-d7ee-4cca-9cf9-46a594fe1b62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922406171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2922406171 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.4268610387 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 599639137 ps |
| CPU time | 16.72 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-4ca78cae-e76e-4eb8-a198-07042ff96c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268610387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.4268610387 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4112263303 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1045814802 ps |
| CPU time | 14.85 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-ba55ba2d-d8b5-4b9b-9ff7-ce2efa96a077 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112263303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4112263303 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.681813449 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 616096314 ps |
| CPU time | 83.28 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:18:28 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-ebff6f38-e736-4ac3-9896-d38a9297622a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681813449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand _reset.681813449 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1799288612 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2443353143 ps |
| CPU time | 11.02 seconds |
| Started | Feb 21 01:17:04 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-fbeaf3f6-5804-42f4-a83d-96f6aa57a416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799288612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1799288612 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.456828925 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1078985599 ps |
| CPU time | 13.05 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:25 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-9d8a9d4e-087b-4e88-b356-a51dc61825c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456828925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.456828925 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.862006785 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 158350560 ps |
| CPU time | 1.82 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:11 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-b5378cc6-b03b-433e-83b5-23f0add1a2cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=862006785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.862006785 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3490214727 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 14723917 ps |
| CPU time | 1.56 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-bf735783-73cc-4e77-b2ba-151a6549b50e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3490214727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3490214727 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.3099339059 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 320920472 ps |
| CPU time | 5.83 seconds |
| Started | Feb 21 01:17:08 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-2399cc82-7aaf-4362-805e-97574ab95af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3099339059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3099339059 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2692421093 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 24215572114 ps |
| CPU time | 49.76 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:18:00 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-1f7d8357-e909-4461-b0ea-58f57b4bc2a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692421093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2692421093 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2182166527 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 30397530007 ps |
| CPU time | 93.06 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:18:45 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-8287b853-e59c-4a61-91ba-43f105bdb47b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2182166527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2182166527 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2591016093 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 14891596 ps |
| CPU time | 1.27 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b4a2c86b-8b2e-45c6-bdc0-1f4423786f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591016093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2591016093 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.3428896716 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2857567389 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-f9826913-bc0c-4dc9-8c7b-d2bf25be446b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3428896716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3428896716 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.1763975781 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 9415504 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:14 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-b44f543f-f8cb-4e4a-8237-cd2b92729057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1763975781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1763975781 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2951089833 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3186734014 ps |
| CPU time | 11.73 seconds |
| Started | Feb 21 01:17:09 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-0c8b051c-aabb-462f-acaa-d19218303334 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951089833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2951089833 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2403591988 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2705608377 ps |
| CPU time | 4.7 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:19 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-823b1aeb-7b7e-4dd5-b7dc-f707515051d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2403591988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2403591988 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2573629800 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 10544922 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:17:11 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-05861957-9531-483b-b8ca-fb0888a0c58d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573629800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2573629800 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2299001917 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7228840019 ps |
| CPU time | 87.13 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:18:41 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-e4a5f60b-497a-48b3-8ea6-a95913f5892d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299001917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2299001917 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3075061661 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 30144931697 ps |
| CPU time | 57.83 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:18:14 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-67981e6c-0023-4c32-9872-44d0c8ea41e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075061661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3075061661 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1447753922 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 13741670810 ps |
| CPU time | 105.07 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:18:55 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-6ff9ea65-ca49-4ec5-b784-698c07eb4dde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447753922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.1447753922 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4118996431 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 339320076 ps |
| CPU time | 51.58 seconds |
| Started | Feb 21 01:17:09 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-ad0a6276-4272-413a-8666-872fcf1ccf27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4118996431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.4118996431 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.674719440 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 43961806 ps |
| CPU time | 1.45 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-19228a46-4360-4335-ae22-f9ac80697572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674719440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.674719440 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.131611860 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1688246892 ps |
| CPU time | 18.63 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:30 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-d8b7892e-d730-4e2e-a2b1-7aa68fafe2c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131611860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.131611860 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2227620588 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 31154638152 ps |
| CPU time | 235.81 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:21:08 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-4d095fc8-10de-4986-824c-43a89b70cb1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2227620588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2227620588 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2299870225 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1111701483 ps |
| CPU time | 11.44 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:25 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-1695680f-2b27-494b-8dbf-2b2c5f546b93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299870225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2299870225 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.461464165 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 19875585 ps |
| CPU time | 2.21 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c9b7d803-7a12-4da1-90fb-d8c1f326f96e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461464165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.461464165 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.3507212207 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 159912229 ps |
| CPU time | 8.95 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-9cbddd80-f311-47ff-a77e-18555233b3ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507212207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3507212207 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1646701058 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 29617945592 ps |
| CPU time | 50.07 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:18:04 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-ac8f9080-e78c-4e52-8116-5d556de85e7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646701058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1646701058 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3424945498 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 34456722789 ps |
| CPU time | 121.27 seconds |
| Started | Feb 21 01:17:10 PM PST 24 |
| Finished | Feb 21 01:19:12 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-9f200d00-46b8-4519-9cf0-6b4fe9a93638 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3424945498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3424945498 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.485078394 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 11714543 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-504c03bf-21b8-43a2-a1a4-924808e001fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485078394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.485078394 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.4176077897 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1153349011 ps |
| CPU time | 4.11 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-2319d2c7-8043-4179-b081-0d2e8bf8ba9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176077897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4176077897 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.4190752799 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 10573196 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-8b4e09de-89b8-4475-81db-5bc91011338e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4190752799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4190752799 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2159644695 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2620929842 ps |
| CPU time | 9.26 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:25 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-95d2123e-8a7e-4848-9e02-b891a6b3a576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159644695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2159644695 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.540151827 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2144114601 ps |
| CPU time | 6.99 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-e568cc66-b19f-4571-accc-50a09643d6b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=540151827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.540151827 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4123024216 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 14374562 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:16 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-5eb86ccf-2501-44ad-ab33-c0bad80fd611 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123024216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4123024216 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.655502195 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 364521719 ps |
| CPU time | 14.39 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-2a99777e-1ae4-4166-8476-bb06f55022ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=655502195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.655502195 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3653072021 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 7773919650 ps |
| CPU time | 79.87 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:18:34 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-53de3ef8-4be9-4d1f-86ae-79b5f5e8cbba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653072021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3653072021 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3258650620 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 666811268 ps |
| CPU time | 96.93 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:18:53 PM PST 24 |
| Peak memory | 206924 kb |
| Host | smart-c3f164a0-5b87-4944-b6ed-ed8949481a9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258650620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3258650620 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1710641081 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 12580850140 ps |
| CPU time | 141.75 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:19:34 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-93951e81-1a9c-494b-a26b-e2b69523f17e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1710641081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.1710641081 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2848889119 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1208253653 ps |
| CPU time | 12.12 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:26 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-296163a3-21c3-4cd8-bc57-58a81279999b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2848889119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2848889119 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2938140607 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 241552247 ps |
| CPU time | 2.68 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-547bfe92-92ba-4407-a0c9-407ccd483a72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2938140607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2938140607 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2440431486 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 9486495019 ps |
| CPU time | 60.63 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:18:15 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-8aff59b0-0d39-4553-ace5-3742c669a646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2440431486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.2440431486 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1089023748 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1426735030 ps |
| CPU time | 6.65 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-054375ae-fd36-4fe0-8773-7c7d3ec95c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089023748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1089023748 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.4248268901 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 494821266 ps |
| CPU time | 4.61 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-87772251-857f-46e8-96ac-cee47fc94ea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4248268901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4248268901 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2158261836 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 41605947 ps |
| CPU time | 1.68 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-c6df026f-ac76-4256-af7e-3ce9f97077ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2158261836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2158261836 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.639545800 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 26629743402 ps |
| CPU time | 64.81 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-d86db043-9278-476c-a2cb-b84b71095494 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=639545800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.639545800 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1710791805 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 14175134346 ps |
| CPU time | 76.78 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:18:32 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-69b379f5-dc60-4a1f-bf45-e6a1bb305e3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1710791805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1710791805 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2002646897 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 113589597 ps |
| CPU time | 5.2 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-2d2094c2-64ee-48d7-9504-442fac3af28c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002646897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2002646897 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.3543499783 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 508715474 ps |
| CPU time | 7.56 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-94c408f2-03f7-49a0-87b5-cf051aacdd2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3543499783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3543499783 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1592535780 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 74540169 ps |
| CPU time | 1.57 seconds |
| Started | Feb 21 01:17:12 PM PST 24 |
| Finished | Feb 21 01:17:14 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-3eec0f1a-34a5-4902-85db-6fccad66b93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1592535780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1592535780 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3718771875 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3837776867 ps |
| CPU time | 6.98 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:19 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-e539cf64-ee52-428d-a400-3dabeb1ed157 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718771875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3718771875 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.306228663 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2720410341 ps |
| CPU time | 4.86 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:19 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-2bb9a711-ca65-45a8-890a-e4c19da67c3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=306228663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.306228663 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2681154326 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9406873 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:17:15 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-2dc99831-885f-43ce-9371-bd05c64f4bed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681154326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2681154326 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2132048726 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1015159175 ps |
| CPU time | 43.5 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:17:57 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-92069d12-febb-4426-8e25-facd9be4cc1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2132048726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2132048726 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1951856693 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 253266213 ps |
| CPU time | 12.67 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:30 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-adf95539-db19-45a6-bd22-e580f7169df8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951856693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1951856693 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1208354261 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 13480221158 ps |
| CPU time | 94.27 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-e509de96-ea1a-4acb-8b24-0ba91eb739b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208354261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1208354261 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2399747935 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2817980300 ps |
| CPU time | 113.62 seconds |
| Started | Feb 21 01:17:14 PM PST 24 |
| Finished | Feb 21 01:19:08 PM PST 24 |
| Peak memory | 206348 kb |
| Host | smart-d69671ef-2e14-42bf-89c8-fd6b95bd9719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399747935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2399747935 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.332166074 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 60887168 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 01:17:11 PM PST 24 |
| Finished | Feb 21 01:17:13 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-04cdcb38-6d65-43aa-9131-cbdb76556fb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332166074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.332166074 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1630694316 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 318682996 ps |
| CPU time | 6.81 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:28 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-458986c7-3d6b-40ff-a2e2-d38b0e3cdeb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1630694316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1630694316 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.915534933 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 64795829540 ps |
| CPU time | 163.22 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:20:02 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-a3fd1e1a-1768-48a9-aed3-a9a692ebe3c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=915534933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.915534933 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2927735574 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1607816372 ps |
| CPU time | 9.08 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-508d6f6b-33eb-4653-a2fc-1009019d64d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2927735574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2927735574 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2575831388 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 145483388 ps |
| CPU time | 3.98 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 201964 kb |
| Host | smart-069621d3-e219-4c70-a017-8e6485925108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2575831388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2575831388 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3776989731 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 83806634 ps |
| CPU time | 4.22 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-e5aadcff-c06b-4dcb-9e2d-85fb205667f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3776989731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3776989731 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.623100702 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 52561493480 ps |
| CPU time | 147.58 seconds |
| Started | Feb 21 01:17:46 PM PST 24 |
| Finished | Feb 21 01:20:14 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-a49c0038-b83d-440b-8f8e-58d8845e24af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=623100702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.623100702 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1866025280 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10026564543 ps |
| CPU time | 47.85 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-6774ed0d-bdbe-427a-ab5d-f2b1efa25e64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1866025280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1866025280 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3423114359 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 26463910 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-433551cd-4aa8-42c6-87fd-ab40407ea3ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423114359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3423114359 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1202954055 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 28713110 ps |
| CPU time | 2.73 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-198d217e-1213-4a54-bdca-971105f98d95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202954055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1202954055 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.314574154 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 38526352 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 01:17:25 PM PST 24 |
| Finished | Feb 21 01:17:26 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-944d03db-b458-4c86-80a5-5c927eb4f716 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=314574154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.314574154 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4231698683 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1750979203 ps |
| CPU time | 8.85 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:26 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-52fb26d8-f97b-4fd7-8ae1-050fca32faa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231698683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4231698683 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1270718982 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 690669392 ps |
| CPU time | 5.69 seconds |
| Started | Feb 21 01:17:17 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-edd27dc3-8ab0-47ec-9c08-712d6e6df570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1270718982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1270718982 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4220032207 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 28536174 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-2372392e-2f59-4be0-a5c4-9519471d4f66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220032207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4220032207 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1151007362 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3822507203 ps |
| CPU time | 42.43 seconds |
| Started | Feb 21 01:17:16 PM PST 24 |
| Finished | Feb 21 01:17:59 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-e9f95a41-5130-444a-8e60-e01e59836375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1151007362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1151007362 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.398381183 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2522649548 ps |
| CPU time | 15.72 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:31 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-83d28b59-0175-4a1a-b741-d7dac0c31ec0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398381183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.398381183 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3704692675 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2216464911 ps |
| CPU time | 67.64 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:18:29 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-1d134bf4-891d-49c0-bf70-fba1723974c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3704692675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.3704692675 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2695480666 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 437471582 ps |
| CPU time | 69.03 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:18:24 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-22b16f74-143c-4551-b517-ec1fd1dcaa62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2695480666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2695480666 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2406836245 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 173853403 ps |
| CPU time | 3.88 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-d655c11d-5af9-4c15-9b38-9d2fd3000799 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2406836245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2406836245 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2408409345 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 94807970 ps |
| CPU time | 14.64 seconds |
| Started | Feb 21 01:17:22 PM PST 24 |
| Finished | Feb 21 01:17:38 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-c5ee2969-69a2-475e-a9d3-360e8ce06f1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408409345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2408409345 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.710318976 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 76634126323 ps |
| CPU time | 298.02 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:22:18 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-b8e9dc26-046d-4e0d-b6b6-951d49052bf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=710318976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.710318976 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1699210323 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3135490027 ps |
| CPU time | 9.02 seconds |
| Started | Feb 21 01:17:25 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-94e380f5-4f89-4e28-b262-cc573394e80e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699210323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1699210323 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.3324162791 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 48357049 ps |
| CPU time | 3.93 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:17:24 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-0a531022-0dc7-4786-af4e-717fd4d73afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3324162791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3324162791 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.765285738 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2621908634 ps |
| CPU time | 9.7 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:31 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-a8e235cd-62e3-439f-be9b-46b139f2a55a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=765285738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.765285738 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.4210696139 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 25180908839 ps |
| CPU time | 82.23 seconds |
| Started | Feb 21 01:17:13 PM PST 24 |
| Finished | Feb 21 01:18:36 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-6aef9095-d0ea-45c1-865f-e3e960691583 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210696139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4210696139 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3179972469 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 88483963540 ps |
| CPU time | 103.18 seconds |
| Started | Feb 21 01:17:21 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-95e0e4ec-15d0-4248-9491-8415242a878b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3179972469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3179972469 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.123456909 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 103562880 ps |
| CPU time | 4.78 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:25 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-c55203df-9602-488b-b2db-a6ae6c01725a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123456909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.123456909 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.376362214 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1739415106 ps |
| CPU time | 9.88 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:31 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-a16fb141-05ee-41e1-a9ff-3ec1800370cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=376362214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.376362214 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.255779039 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 43251753 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:17 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-426fe3dc-e98a-464d-8954-1ebb45ec0157 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=255779039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.255779039 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.296534111 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5342331927 ps |
| CPU time | 14.68 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:30 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-8826b4c2-f310-41ea-a9d6-58d91bb2f15e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=296534111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.296534111 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3177766992 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1463398767 ps |
| CPU time | 6.95 seconds |
| Started | Feb 21 01:17:15 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-4d61206a-00f2-4442-9e9a-e893128194eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3177766992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3177766992 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.594105784 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 13621203 ps |
| CPU time | 1.27 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:23 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-e7bfdd25-7ae6-4a7c-b9bd-fe573b9afea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594105784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.594105784 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.363292489 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1066509608 ps |
| CPU time | 41.12 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-01a95787-16ea-4c39-82de-fbc15e91d581 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=363292489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.363292489 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3541791641 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 8143302739 ps |
| CPU time | 45.69 seconds |
| Started | Feb 21 01:17:32 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-e017b39d-8555-4dfc-b5ca-e42aa3ab89a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3541791641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3541791641 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1571684120 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 6127541415 ps |
| CPU time | 61.69 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-323e8238-c983-4232-98eb-78963b4dd47d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1571684120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1571684120 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.175255318 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 87723728 ps |
| CPU time | 4.12 seconds |
| Started | Feb 21 01:17:32 PM PST 24 |
| Finished | Feb 21 01:17:37 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-aa8439ef-86d3-4846-a8db-ee5c96be1824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=175255318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.175255318 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2194828567 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 11762679 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:17:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-fa45f221-abfe-49b6-a9f6-14c3e144f9bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2194828567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2194828567 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.803075911 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 303173464 ps |
| CPU time | 5.02 seconds |
| Started | Feb 21 01:17:22 PM PST 24 |
| Finished | Feb 21 01:17:28 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-028ce1ec-2af6-4d01-b163-ad28ccd6508e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=803075911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.803075911 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1453482778 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 48890853039 ps |
| CPU time | 218.48 seconds |
| Started | Feb 21 01:17:33 PM PST 24 |
| Finished | Feb 21 01:21:13 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-d93fd59f-f9d0-4ff1-b078-0adea7c489c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1453482778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1453482778 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1200499114 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3376662889 ps |
| CPU time | 9.57 seconds |
| Started | Feb 21 01:17:21 PM PST 24 |
| Finished | Feb 21 01:17:32 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-6752787a-3758-4805-ace6-d4ee07a479d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1200499114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1200499114 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3642127480 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 85553971 ps |
| CPU time | 9.24 seconds |
| Started | Feb 21 01:17:27 PM PST 24 |
| Finished | Feb 21 01:17:37 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-e86cabad-7cc3-4701-a5fd-dea78e809a9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3642127480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3642127480 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1366505247 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1176267275 ps |
| CPU time | 14.2 seconds |
| Started | Feb 21 01:17:19 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-2715c3e6-a73e-4ada-a595-f42650caa100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1366505247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1366505247 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3037060172 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 194889388394 ps |
| CPU time | 166.71 seconds |
| Started | Feb 21 01:17:25 PM PST 24 |
| Finished | Feb 21 01:20:13 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-fb309de0-8891-44c1-aedc-f3d6fce2d589 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037060172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3037060172 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1352808150 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 17623221096 ps |
| CPU time | 87.33 seconds |
| Started | Feb 21 01:17:22 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-34b9df5e-00d2-42ff-b06d-8d2ca95a9df2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1352808150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1352808150 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2988538478 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 69151756 ps |
| CPU time | 7.62 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:28 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-9a695038-9a9e-48bb-a468-0606eeda2244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988538478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2988538478 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3313858088 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 320669343 ps |
| CPU time | 4.42 seconds |
| Started | Feb 21 01:17:23 PM PST 24 |
| Finished | Feb 21 01:17:28 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-0c3e91db-3a61-48f1-af23-1abba2432696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3313858088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3313858088 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3427947626 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 8674614 ps |
| CPU time | 1.19 seconds |
| Started | Feb 21 01:17:32 PM PST 24 |
| Finished | Feb 21 01:17:34 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-65f5118b-d028-483e-ab45-1a6ea0c1664d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3427947626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3427947626 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.558595287 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3500063466 ps |
| CPU time | 7.94 seconds |
| Started | Feb 21 01:17:30 PM PST 24 |
| Finished | Feb 21 01:17:38 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-71deea0f-8268-41db-a8a6-9ad64e5c3699 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=558595287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.558595287 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3867984236 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 6703512095 ps |
| CPU time | 9.27 seconds |
| Started | Feb 21 01:17:20 PM PST 24 |
| Finished | Feb 21 01:17:30 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-6d1dd151-8e7d-41e4-b893-94ec12686c83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3867984236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3867984236 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3546016728 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 11179467 ps |
| CPU time | 1.2 seconds |
| Started | Feb 21 01:17:24 PM PST 24 |
| Finished | Feb 21 01:17:26 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-d566fa50-81a8-4188-9fad-f6de38021488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546016728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3546016728 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3292365818 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4652226775 ps |
| CPU time | 85.3 seconds |
| Started | Feb 21 01:17:25 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 205736 kb |
| Host | smart-734ec4e9-e33a-4e47-bc48-5fe7ad04027f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3292365818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3292365818 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.4013500318 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 517808526 ps |
| CPU time | 28.47 seconds |
| Started | Feb 21 01:17:21 PM PST 24 |
| Finished | Feb 21 01:17:51 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-9fe68167-ab04-4e0f-9d6f-da735b9d2962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013500318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4013500318 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.711849333 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2306133697 ps |
| CPU time | 19.06 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-cd28aba5-b67d-40bc-a9e7-5d9930f84567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711849333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.711849333 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3227543977 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 102447923 ps |
| CPU time | 6.55 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:17:46 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-dd61fab4-d8a2-434b-946b-60c0eeddfc35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3227543977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3227543977 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.52843785 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 56681598 ps |
| CPU time | 3.95 seconds |
| Started | Feb 21 01:17:23 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-ecc6fe46-db9a-48f5-a81b-441f66f0efe4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52843785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.52843785 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1460313146 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 62214066309 ps |
| CPU time | 259.51 seconds |
| Started | Feb 21 01:17:21 PM PST 24 |
| Finished | Feb 21 01:21:41 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-a1fa5227-ee0c-4bbc-a193-75a51addd48a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1460313146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1460313146 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.4143005758 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1127560293 ps |
| CPU time | 9.58 seconds |
| Started | Feb 21 01:17:41 PM PST 24 |
| Finished | Feb 21 01:17:51 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-fda6bafc-034e-4337-94f7-b14e8fef3b1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4143005758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.4143005758 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1242157562 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 656836619 ps |
| CPU time | 7.52 seconds |
| Started | Feb 21 01:17:39 PM PST 24 |
| Finished | Feb 21 01:17:47 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-c3dab067-df57-4c4c-8dd7-8d0eecdfbd80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242157562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1242157562 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.818987256 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 41873100 ps |
| CPU time | 3.89 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:17:43 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-80a6c0c4-bf25-41ac-bd89-08fa254d1a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=818987256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.818987256 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3851035827 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 9007879524 ps |
| CPU time | 38.82 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-711631a9-b994-4cd7-aee4-60ab52f3d4a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851035827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3851035827 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.4068904522 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 2256058100 ps |
| CPU time | 14.97 seconds |
| Started | Feb 21 01:17:23 PM PST 24 |
| Finished | Feb 21 01:17:39 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-2f670834-1db6-4709-b9f7-314e16fc7674 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4068904522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.4068904522 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1106358468 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 38175042 ps |
| CPU time | 3.52 seconds |
| Started | Feb 21 01:17:23 PM PST 24 |
| Finished | Feb 21 01:17:27 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-4015c6c8-2da4-4cf8-adcf-15fe57c5eab4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106358468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1106358468 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1246440625 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1202073699 ps |
| CPU time | 10.58 seconds |
| Started | Feb 21 01:17:24 PM PST 24 |
| Finished | Feb 21 01:17:35 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-beb2af0b-af19-4c5e-87f1-f654ad7bd638 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1246440625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1246440625 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.3541227915 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 11577839 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:17:33 PM PST 24 |
| Finished | Feb 21 01:17:35 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-c2dac09e-0deb-459e-9c6b-5391c45ce68b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3541227915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3541227915 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3361896617 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2763281810 ps |
| CPU time | 9.86 seconds |
| Started | Feb 21 01:17:33 PM PST 24 |
| Finished | Feb 21 01:17:43 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-59210061-49b8-429e-844c-d730e8aa88aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361896617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3361896617 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2998808032 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1994931956 ps |
| CPU time | 8.19 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-e6024523-4c92-4ff1-a2b1-c9257c39dbfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2998808032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2998808032 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2106193875 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 11568871 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:17:32 PM PST 24 |
| Finished | Feb 21 01:17:33 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-9ec5d813-526d-4efd-902d-3647465bdff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106193875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2106193875 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2726431777 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 296554740 ps |
| CPU time | 15.37 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-33c41f9d-2981-462a-bffc-16cfd2264bc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2726431777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2726431777 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.999714792 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5583723787 ps |
| CPU time | 79.79 seconds |
| Started | Feb 21 01:17:46 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-fd2bd8d1-5c0a-4c81-a7df-38abe5b593c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=999714792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.999714792 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3389792204 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 957062579 ps |
| CPU time | 145.91 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 207084 kb |
| Host | smart-6c0460a1-e0ad-45e9-979e-440e515d6e41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3389792204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.3389792204 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.289986273 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 903179460 ps |
| CPU time | 92.3 seconds |
| Started | Feb 21 01:17:38 PM PST 24 |
| Finished | Feb 21 01:19:12 PM PST 24 |
| Peak memory | 206968 kb |
| Host | smart-02c8f755-eed8-43d7-b8ec-b305575cc020 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=289986273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res et_error.289986273 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4112153840 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 368626014 ps |
| CPU time | 6.14 seconds |
| Started | Feb 21 01:17:54 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b0ddf6f1-f0ac-4b27-ab8a-c6545d7563f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112153840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4112153840 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2525684340 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2545050922 ps |
| CPU time | 21.78 seconds |
| Started | Feb 21 01:17:36 PM PST 24 |
| Finished | Feb 21 01:17:59 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-f3327d50-7a50-4659-9b00-d9cfa4dcebd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2525684340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2525684340 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.145746855 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 79972591 ps |
| CPU time | 1.72 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:50 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-001d513a-8ce7-4d13-9d56-c9dc332fd35a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=145746855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.145746855 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2925333429 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 285278776 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 01:17:45 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-63ae6f09-a87e-4259-88a3-c317827d55ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925333429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2925333429 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.623229105 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 861484054 ps |
| CPU time | 4.27 seconds |
| Started | Feb 21 01:17:37 PM PST 24 |
| Finished | Feb 21 01:17:43 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-7c8f7cd9-1a35-48e4-847d-ec2a449b657e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=623229105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.623229105 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.4178847781 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 53875148430 ps |
| CPU time | 177.36 seconds |
| Started | Feb 21 01:17:46 PM PST 24 |
| Finished | Feb 21 01:20:44 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-a9c480ae-a910-42c4-9a32-fa6859e64ad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178847781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4178847781 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3490889781 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 20954756088 ps |
| CPU time | 113.72 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:19:41 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-512470de-4407-4a79-985a-6b816498b4b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3490889781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3490889781 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1665310619 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 18539048 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 01:17:56 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-8e6c78a7-d8a2-4891-aedc-7b6c5307e8f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665310619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1665310619 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.488876925 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 101398687 ps |
| CPU time | 2.03 seconds |
| Started | Feb 21 01:17:44 PM PST 24 |
| Finished | Feb 21 01:17:47 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-a4efcaf6-f045-4e41-b1d5-56dfc2da58b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=488876925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.488876925 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2686925178 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 10239345 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:49 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-2c622dba-330c-4458-9b8d-27f8086002c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2686925178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2686925178 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2685888721 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3618894956 ps |
| CPU time | 9.95 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-3c2c0d65-35d3-44c2-9e1f-251ac54962e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685888721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2685888721 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2978367658 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 6823763582 ps |
| CPU time | 7.06 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-2d67f813-7c55-4253-8e90-a495a684443a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2978367658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2978367658 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1310751060 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 9478052 ps |
| CPU time | 1.38 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:17:51 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-d71903ab-f279-4d29-9bd3-9807433e6598 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310751060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1310751060 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3050869462 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 4885229877 ps |
| CPU time | 57.93 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:18:46 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-951b24fb-9a62-4e2d-aac5-b398d61365da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3050869462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3050869462 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3021910837 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7867191662 ps |
| CPU time | 137.06 seconds |
| Started | Feb 21 01:17:37 PM PST 24 |
| Finished | Feb 21 01:19:55 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-cf0812d7-957b-4886-83ca-5cce033b0b2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021910837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3021910837 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1210033091 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 6521506638 ps |
| CPU time | 188.15 seconds |
| Started | Feb 21 01:17:45 PM PST 24 |
| Finished | Feb 21 01:20:54 PM PST 24 |
| Peak memory | 208232 kb |
| Host | smart-4bd34ce5-6e3b-46ff-94da-b91ee399ef28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1210033091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1210033091 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1701652000 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 656182288 ps |
| CPU time | 87.92 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-67852ea9-25fe-4d77-b2bf-faa1a0281a9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1701652000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1701652000 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3697276962 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 37456461 ps |
| CPU time | 4.41 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-b62febe7-a3f2-483e-b299-4633539dc692 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697276962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3697276962 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.65586443 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 617171900 ps |
| CPU time | 5.07 seconds |
| Started | Feb 21 01:15:12 PM PST 24 |
| Finished | Feb 21 01:15:17 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-3f6d6e03-17e2-4b4f-96a8-ee9a49cef46e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=65586443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.65586443 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4087820544 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 105244561503 ps |
| CPU time | 170.64 seconds |
| Started | Feb 21 01:15:05 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-eeb8749c-edde-4d7c-bb02-6e9d79e27946 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4087820544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.4087820544 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3579116938 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 76107152 ps |
| CPU time | 6.55 seconds |
| Started | Feb 21 01:15:24 PM PST 24 |
| Finished | Feb 21 01:15:31 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-c19728a8-2d98-47e3-9734-aea50d245a76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3579116938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3579116938 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3849306770 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 558570855 ps |
| CPU time | 4.63 seconds |
| Started | Feb 21 01:15:16 PM PST 24 |
| Finished | Feb 21 01:15:21 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-3a765794-c073-4de6-bf60-f92800ec66c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3849306770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3849306770 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.724682636 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 140370309 ps |
| CPU time | 8.94 seconds |
| Started | Feb 21 01:15:11 PM PST 24 |
| Finished | Feb 21 01:15:20 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-892aa3c4-f12a-4349-ab80-af9fc91f9915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=724682636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.724682636 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2442333375 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 11664092188 ps |
| CPU time | 48.61 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:16:08 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-87acc066-0572-436b-8864-6fcc7e701407 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442333375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2442333375 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.179419520 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 7287689293 ps |
| CPU time | 49 seconds |
| Started | Feb 21 01:15:11 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202888 kb |
| Host | smart-edd3e943-9a44-4ec8-864d-44d4c21dc1dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=179419520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.179419520 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1587309117 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 231227248 ps |
| CPU time | 4.03 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:15:22 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-d4fcaeea-419c-4bfc-a286-4a7a5fcb4861 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587309117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1587309117 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1391906969 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1466984670 ps |
| CPU time | 10.87 seconds |
| Started | Feb 21 01:15:08 PM PST 24 |
| Finished | Feb 21 01:15:19 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-8750aec0-0762-4a9e-a3a9-493750cfe1cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1391906969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1391906969 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2156924637 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 30919895 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:15:16 PM PST 24 |
| Finished | Feb 21 01:15:18 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-bc780b6a-3c75-49ae-85bb-2f02558b88a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2156924637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2156924637 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2856787565 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2752230482 ps |
| CPU time | 7.3 seconds |
| Started | Feb 21 01:15:09 PM PST 24 |
| Finished | Feb 21 01:15:17 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-658ce91e-22ff-4c3d-8f1b-f68cbcd889a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856787565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2856787565 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3369371580 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4814636298 ps |
| CPU time | 11.29 seconds |
| Started | Feb 21 01:15:11 PM PST 24 |
| Finished | Feb 21 01:15:22 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-af5557e6-0b25-4ebf-9b7c-80bbf75d9f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3369371580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3369371580 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3586304149 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 17421325 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:15:17 PM PST 24 |
| Finished | Feb 21 01:15:19 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-fb04687d-6a94-4c06-9202-b2b774adc501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586304149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3586304149 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.70408277 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 577939414 ps |
| CPU time | 31.79 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-f11f8480-b429-4941-978a-32f077f13ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=70408277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.70408277 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.729379239 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 4279578501 ps |
| CPU time | 37.31 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-81ad1b48-9987-4d0b-ad78-3af4bb2ffd4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=729379239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.729379239 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.596564767 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 89756954 ps |
| CPU time | 18.54 seconds |
| Started | Feb 21 01:15:34 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-9bd2a0ef-cd53-49ba-8e57-9aa17c1c463b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=596564767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.596564767 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2271872071 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 20248562 ps |
| CPU time | 1.93 seconds |
| Started | Feb 21 01:15:19 PM PST 24 |
| Finished | Feb 21 01:15:21 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-1132f1f2-0657-4444-ae63-f260a04d927f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2271872071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2271872071 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3350184543 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3432605469 ps |
| CPU time | 18.64 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:18:06 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-63937ae8-0fd9-4887-b165-ef0083febac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3350184543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3350184543 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2909497662 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 26701139313 ps |
| CPU time | 196.42 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:21:05 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-6d143ac3-a947-4525-b4df-185994940183 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2909497662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2909497662 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4096831815 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 51362103 ps |
| CPU time | 4.18 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-6316926d-d905-4477-a43f-0f9e780cb74e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096831815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4096831815 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.1380712500 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3245598053 ps |
| CPU time | 6.94 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:59 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-1b2b1be9-28b5-478e-8f73-9a1aa6a70d54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380712500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1380712500 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3705476814 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 818924434 ps |
| CPU time | 2.55 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:55 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-42df36ff-2e63-4e56-981d-9348242d1e36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705476814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3705476814 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2473080452 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 35165453002 ps |
| CPU time | 74.51 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-50227580-c7b3-4452-ac47-05058b93dbab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473080452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2473080452 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1300561357 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9021453191 ps |
| CPU time | 67.37 seconds |
| Started | Feb 21 01:17:49 PM PST 24 |
| Finished | Feb 21 01:18:57 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-e838700c-d188-45aa-916e-7d6043f139b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1300561357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1300561357 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3838689077 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 23806528 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 01:17:53 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-d6990782-7138-4b56-9644-095c435f61ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838689077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3838689077 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3411208832 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 25093978 ps |
| CPU time | 1.91 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:17:55 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-0418340c-2c16-4741-ade8-ff17c23bca61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3411208832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3411208832 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2157108267 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 104837494 ps |
| CPU time | 1.38 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-34073d9e-3a8e-49bd-a214-d3fcf47e8c91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2157108267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2157108267 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3432558648 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3920485357 ps |
| CPU time | 7.03 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:55 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-e3c786e5-7491-4011-ae25-ab9e2e9ce1f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432558648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3432558648 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2322526078 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 777264166 ps |
| CPU time | 5.64 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:57 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-3473c957-aa59-491a-85c8-f5afb6f95a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2322526078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2322526078 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3158735072 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 30056035 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-b3fa31ef-da85-42ae-984a-ab727b88f578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158735072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3158735072 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1822003698 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 87422487 ps |
| CPU time | 11.69 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-5b85d609-572c-4cf0-8e05-f3771fc33bc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822003698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1822003698 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.388681573 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 157567403 ps |
| CPU time | 8.96 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:18:00 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-81edc2f7-c122-4d55-83a6-94dee8fb79a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=388681573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.388681573 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.405433315 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 203832830 ps |
| CPU time | 34.54 seconds |
| Started | Feb 21 01:17:53 PM PST 24 |
| Finished | Feb 21 01:18:28 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-8e404dd9-b8a6-422e-bddc-dbe628dc7935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=405433315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.405433315 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1036665616 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 797897099 ps |
| CPU time | 101.29 seconds |
| Started | Feb 21 01:17:49 PM PST 24 |
| Finished | Feb 21 01:19:32 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-6da6280f-44f1-44ad-9664-79dc89a30276 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1036665616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1036665616 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3630962298 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 56163702 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-0104e6e2-36a4-4420-b643-8b594bb0d042 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3630962298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3630962298 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1208644872 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 13765614 ps |
| CPU time | 3.11 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b498b819-57d9-463a-b6fa-b6fff3aa0e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208644872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1208644872 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1874109881 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 26840634967 ps |
| CPU time | 169.24 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:20:42 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-37bc4bf5-b8f7-4950-8945-5d38e5f0495a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1874109881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1874109881 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2747931511 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 30130380 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:17:51 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-83f90447-260a-441f-819a-9641176543c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747931511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2747931511 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3947160217 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1029825115 ps |
| CPU time | 4.45 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-3d4c6802-d243-4598-9011-d6276838a5b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3947160217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3947160217 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.1896992270 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 93577155 ps |
| CPU time | 6.48 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:54 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-0e3b22a8-68fc-48ab-a8f8-a09e5b04708a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1896992270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1896992270 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2573963603 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 22419380269 ps |
| CPU time | 83.81 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:19:13 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-17299617-c2cd-4d8d-889f-c06e08f95085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573963603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2573963603 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1212843066 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 64831552889 ps |
| CPU time | 180.97 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:20:50 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-ba16af4a-0f79-48e1-9b8c-8dca684d21da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1212843066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1212843066 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.744543685 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 77793257 ps |
| CPU time | 3.88 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:54 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-a3fd52a2-2fbd-46e4-800f-38c15f176600 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744543685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.744543685 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.250046915 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 74786888 ps |
| CPU time | 4.38 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:55 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-83dfce21-b9d3-4181-aa23-60e585eb23a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=250046915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.250046915 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2855431393 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11127563 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-4b8ae029-cf95-4f01-bf2b-8cdf381e2375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2855431393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2855431393 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.374734889 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2294079679 ps |
| CPU time | 10.63 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:17:59 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-69b823a5-259c-4fab-9c76-ea5472fa1466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=374734889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.374734889 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3013902424 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3888156330 ps |
| CPU time | 11.47 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:18:00 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-49f8a729-0c77-4ede-818e-67be92263029 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3013902424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3013902424 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1771230627 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7905620 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-2f6864f1-8094-4baf-b22a-9321be332bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771230627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1771230627 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.458753113 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 317811513 ps |
| CPU time | 18.32 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 203552 kb |
| Host | smart-94d89ec2-f0e3-406f-ad3c-c79c82568fc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=458753113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.458753113 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3394407447 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 10997450662 ps |
| CPU time | 59.8 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:18:52 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-495c5dd2-46f2-4d5e-b8a3-db869bb8cd24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394407447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3394407447 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2717623345 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 257416827 ps |
| CPU time | 22.78 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:18:11 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-fb49a114-219a-49e4-9018-e5ab9ee40a6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2717623345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2717623345 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.807322558 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5053994758 ps |
| CPU time | 123.09 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:19:52 PM PST 24 |
| Peak memory | 206580 kb |
| Host | smart-926eb629-86eb-4512-9b73-043531aa6ec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=807322558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.807322558 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3805308528 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 445452272 ps |
| CPU time | 5.73 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-3f0bd28e-bfbf-4d52-a113-bc005d0dfd75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805308528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3805308528 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1100056152 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 98494842 ps |
| CPU time | 12.76 seconds |
| Started | Feb 21 01:17:49 PM PST 24 |
| Finished | Feb 21 01:18:04 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-06b68e3b-35ed-4c77-be3d-7beeb048d28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1100056152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1100056152 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4026335982 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 22351162289 ps |
| CPU time | 123.48 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:19:52 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-8d389941-befd-4ffe-ad46-4aa04af08a90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4026335982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.4026335982 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4269149658 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 62281334 ps |
| CPU time | 3.92 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:05 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-0d50a54d-b925-4349-bff5-9562f00a1918 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4269149658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4269149658 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.3373355065 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 933512201 ps |
| CPU time | 13.6 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-d2cebff0-e7b6-4320-baf1-bd3b6e6e9685 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3373355065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3373355065 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.3218970888 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 72148322 ps |
| CPU time | 8.12 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:59 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-41fe2b7c-9c89-47dd-b7d4-e37f3fdb2169 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3218970888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3218970888 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.4232219282 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 20553714969 ps |
| CPU time | 48.34 seconds |
| Started | Feb 21 01:17:50 PM PST 24 |
| Finished | Feb 21 01:18:40 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-57e8f671-f5b3-4163-997e-18cda46a98b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232219282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4232219282 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2464811119 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 21879712591 ps |
| CPU time | 139.91 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:20:08 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-25c60e80-64dc-4b6d-a40a-50bf835c460c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2464811119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2464811119 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1476305637 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 31528881 ps |
| CPU time | 4.26 seconds |
| Started | Feb 21 01:17:51 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-fedc7d6b-6ddd-4487-9be8-cd0308f3cef5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476305637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1476305637 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.2990697184 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2256008007 ps |
| CPU time | 11.46 seconds |
| Started | Feb 21 01:17:49 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-4171be97-0205-4fd7-869e-5ccf95a543a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990697184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2990697184 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2821168301 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 54349928 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 01:17:47 PM PST 24 |
| Finished | Feb 21 01:17:50 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-4d3dac9e-12ac-4aae-a657-13ef143c6d84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2821168301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2821168301 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1795516280 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2071657256 ps |
| CPU time | 8.07 seconds |
| Started | Feb 21 01:17:52 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-31658589-8e3a-469d-a849-adb80e632779 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795516280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1795516280 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1707584731 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2531284231 ps |
| CPU time | 8.72 seconds |
| Started | Feb 21 01:17:54 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-e6a9a39e-bf78-4dd4-baa6-0ab01df3c831 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1707584731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1707584731 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.618764846 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 11133145 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 01:17:49 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f6432218-1d16-4ee7-948e-d3a1cafd1220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618764846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.618764846 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.3089072690 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2349415940 ps |
| CPU time | 30.02 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:30 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-05c9dac3-a3bc-46a7-885e-f0fddc7f61b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3089072690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3089072690 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.942740049 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5803414971 ps |
| CPU time | 28.8 seconds |
| Started | Feb 21 01:17:54 PM PST 24 |
| Finished | Feb 21 01:18:24 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-6eb4a902-a2af-4635-9fff-afecfe84ad82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=942740049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.942740049 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1598153267 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 460633700 ps |
| CPU time | 54.44 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:52 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-b4730cf1-a56e-443d-b769-dd48b2e7a4db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1598153267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1598153267 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3556063426 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 176321360 ps |
| CPU time | 4.26 seconds |
| Started | Feb 21 01:17:48 PM PST 24 |
| Finished | Feb 21 01:17:53 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-5fc71c1b-9b5e-473a-a328-db5af9ec70c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3556063426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3556063426 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3939204601 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 231112540 ps |
| CPU time | 5.28 seconds |
| Started | Feb 21 01:17:55 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-9d3d386c-36bf-4c07-bd31-43c895c016f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3939204601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3939204601 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.100863536 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 126698561127 ps |
| CPU time | 326.76 seconds |
| Started | Feb 21 01:17:58 PM PST 24 |
| Finished | Feb 21 01:23:26 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-e3bbaf27-f93d-42ee-9173-07e231e28c04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=100863536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.100863536 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2219371376 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 804123879 ps |
| CPU time | 11.7 seconds |
| Started | Feb 21 01:17:56 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-684f19c5-3b83-45db-8526-9d58bd2c3e9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2219371376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2219371376 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.765425376 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 602574365 ps |
| CPU time | 9.95 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-6a882d1a-1060-4508-a32c-a044ad84ce2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=765425376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.765425376 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.333873393 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 287579317 ps |
| CPU time | 3.63 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-b40e374b-3fde-48ca-9989-65b8e0432403 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=333873393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.333873393 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3436179499 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 38052974634 ps |
| CPU time | 71.86 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:19:12 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-28061501-4648-4cea-91aa-54f978dd13c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436179499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3436179499 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1187925156 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 108431890661 ps |
| CPU time | 137.81 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:20:23 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-61bd37ff-7115-4c3e-940a-9689b440fcfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1187925156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1187925156 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.896046389 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 40418235 ps |
| CPU time | 3.36 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-eb9edc40-8ebd-4441-815b-2248c7ac020a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896046389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.896046389 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.438433509 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 732202351 ps |
| CPU time | 6.56 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-3002a9db-3b76-4cda-b16c-62b2c460c176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=438433509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.438433509 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1814036369 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 220564046 ps |
| CPU time | 1.74 seconds |
| Started | Feb 21 01:17:55 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-744289be-8665-4550-abf3-8281ce2347c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814036369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1814036369 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1386509277 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1905725274 ps |
| CPU time | 8.4 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-e1d5f7ac-598a-4a0e-807a-d6833780f317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386509277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1386509277 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2522200951 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3368458319 ps |
| CPU time | 9.27 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-12492e81-d80b-4233-bc12-bdc9f2de432d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2522200951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2522200951 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.772284097 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 12478947 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 01:17:55 PM PST 24 |
| Finished | Feb 21 01:17:56 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-2d75ee80-0af7-4591-80b4-829c227b96ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772284097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.772284097 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2868128430 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 17281912995 ps |
| CPU time | 138.06 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:20:19 PM PST 24 |
| Peak memory | 205156 kb |
| Host | smart-cd16e2fc-5ac3-4db2-96a8-e462f3117671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2868128430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2868128430 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2112149593 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 513699871 ps |
| CPU time | 20.66 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-26eae6de-1552-429e-acfa-7b0057714487 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2112149593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2112149593 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.125352675 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 173902595 ps |
| CPU time | 15.91 seconds |
| Started | Feb 21 01:17:55 PM PST 24 |
| Finished | Feb 21 01:18:11 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-a15fad06-6e28-46d0-b8d2-29712bce01ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=125352675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.125352675 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.325424656 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 100657350 ps |
| CPU time | 6.43 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-c90766a4-22e1-4c30-a4d8-1be81e16bc12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325424656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.325424656 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2919156748 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14900547 ps |
| CPU time | 2.04 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-0be128ad-37a4-45b7-9c1d-04a176f5a4a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2919156748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2919156748 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3919979258 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 352223959 ps |
| CPU time | 2.9 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-38db1b19-dc8d-4c9d-9d44-db9bdd8dcb57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3919979258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3919979258 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3314520426 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 44105094 ps |
| CPU time | 2.83 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-602caf5f-7f27-45ca-ae33-367236cab604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314520426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3314520426 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.585285072 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 409188848 ps |
| CPU time | 4.07 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-218ac260-e29f-477b-8dba-b50e2a919771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=585285072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.585285072 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.370267822 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 240744757 ps |
| CPU time | 5.33 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:10 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-5ee15bd0-6a33-4cf9-95b0-ca306b03164c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370267822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.370267822 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.497195492 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 149279894687 ps |
| CPU time | 133.64 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:20:13 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-ca7d90b0-a285-4b5b-a7e5-b5cc784b3086 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=497195492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.497195492 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1933436352 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 50438705344 ps |
| CPU time | 63.25 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:19:03 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-07cd168e-9b42-4d14-af14-867349f5253a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1933436352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1933436352 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1527705554 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 51382188 ps |
| CPU time | 5.49 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:06 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-54a5735b-c4e6-4ccc-aff1-56e9f3c6fa4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527705554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1527705554 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.520160874 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 845112099 ps |
| CPU time | 11.27 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-b0466203-2931-4354-aa9c-4bafae75c573 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=520160874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.520160874 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.4090571210 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 12297043 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:01 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-08a6ac5c-8a81-4a4e-a277-abd2b165871c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4090571210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4090571210 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1744052281 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 6407544696 ps |
| CPU time | 10.3 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-45916a31-c3cb-44cf-a670-6d3415d7e010 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744052281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1744052281 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2052354982 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4977506165 ps |
| CPU time | 7.88 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-9a63e99c-e719-4ae0-b5e3-f15799efe4e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2052354982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2052354982 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.181008955 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 9210776 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 01:17:56 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-5eb851f6-7857-4f3b-9438-d12698a9c5bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181008955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.181008955 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3872053721 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1963762307 ps |
| CPU time | 22.03 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:26 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-2e5d7733-5b8e-4c9c-bcbd-3eb1d05bf989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872053721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3872053721 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4146294595 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2602737693 ps |
| CPU time | 40.84 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:38 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-f40b42e6-bbb0-4e6d-b1cc-d88a3f5c87c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4146294595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4146294595 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3998149432 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1439612811 ps |
| CPU time | 126.09 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:20:10 PM PST 24 |
| Peak memory | 205752 kb |
| Host | smart-0ff37803-e6c4-4ce3-8862-0c4c4b8bcfb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3998149432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3998149432 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1681045686 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 209890746 ps |
| CPU time | 15.72 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:16 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-2ec74db4-291b-40bf-850c-b78164417734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1681045686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.1681045686 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3801054844 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 31000550 ps |
| CPU time | 3.35 seconds |
| Started | Feb 21 01:17:54 PM PST 24 |
| Finished | Feb 21 01:17:58 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-fc879ad7-76fe-48ce-b883-87343f1dafd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3801054844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3801054844 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3634038728 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 627412885 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-243d9418-9211-4311-9a69-b39530548585 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3634038728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3634038728 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1794353403 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 14800313371 ps |
| CPU time | 56.55 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:57 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-35a7c599-2d5a-422a-a142-f8915f34c75b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1794353403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1794353403 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4145476096 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2764537665 ps |
| CPU time | 9.98 seconds |
| Started | Feb 21 01:17:58 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-3f35c361-5ec6-4785-bf6f-8db0d403f7e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145476096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4145476096 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1865172370 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 60542200 ps |
| CPU time | 6.36 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:06 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-29abc232-a852-4137-adb7-e69223b2a45f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1865172370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1865172370 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3329253519 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1181888044 ps |
| CPU time | 13.31 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:15 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-d3194a1c-f7e0-41c7-ac3a-7ce4cd397689 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329253519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3329253519 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1372490302 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 52132501983 ps |
| CPU time | 81.11 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:19:21 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-b5f03f26-ac1e-4fe0-91cd-094d809ecca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372490302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1372490302 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.648612745 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 13519425392 ps |
| CPU time | 72.24 seconds |
| Started | Feb 21 01:17:58 PM PST 24 |
| Finished | Feb 21 01:19:11 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-dfd04e92-b59e-4806-83cd-3e884b5585d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=648612745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.648612745 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3487620707 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 156343354 ps |
| CPU time | 7.54 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:09 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-ffddcdd0-6421-48a9-9f54-56430c7aa935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487620707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3487620707 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2520235057 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2170697724 ps |
| CPU time | 9.6 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:10 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-4b2cd7a3-f366-427a-8a49-4670f6c4e554 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520235057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2520235057 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.1412227489 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 56854230 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:06 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-82fc7d9e-760e-4f53-b080-7675ab481894 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1412227489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1412227489 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2341714829 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3330798617 ps |
| CPU time | 10 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:14 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-bc474ec5-467b-45e1-aba5-5b7665890de4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341714829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2341714829 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.201891987 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2248472550 ps |
| CPU time | 5.94 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-f32c801d-ad70-4d8e-89e1-5a1dc9954fe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=201891987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.201891987 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1743714638 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 12965285 ps |
| CPU time | 1.29 seconds |
| Started | Feb 21 01:18:01 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 201868 kb |
| Host | smart-86bca36d-3ab7-4cac-b0c1-bf64a445391b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743714638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1743714638 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2233036829 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4671443282 ps |
| CPU time | 77.36 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-c00e30cb-5f9b-41fc-8760-33c96ebc9a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2233036829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2233036829 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1513596900 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 136485562 ps |
| CPU time | 13.81 seconds |
| Started | Feb 21 01:17:57 PM PST 24 |
| Finished | Feb 21 01:18:12 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-b58d4ade-b1cb-4c59-8f6f-ee949862fd28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1513596900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1513596900 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3911892047 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 249369926 ps |
| CPU time | 29.7 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:31 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-653b4a8d-ae86-433d-bb30-63fbe7ad1188 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3911892047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.3911892047 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2566363811 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2991365500 ps |
| CPU time | 98.84 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:19:40 PM PST 24 |
| Peak memory | 205616 kb |
| Host | smart-363c1e72-1219-4100-a8ed-9da2272447d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2566363811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2566363811 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1366022638 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 41334036 ps |
| CPU time | 1.2 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:02 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-ede43fea-7fbb-4021-8ad0-78bc0b7c76f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1366022638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1366022638 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2656789167 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 595311471 ps |
| CPU time | 14.61 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:17 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-0a8be0fe-108e-4ea9-8411-8a47e1c6c361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2656789167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2656789167 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.453271406 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 122578931070 ps |
| CPU time | 178.77 seconds |
| Started | Feb 21 01:17:58 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-46056cbf-b197-4fbd-8a84-6f0445699e8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=453271406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.453271406 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2446969212 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 77119205 ps |
| CPU time | 5.08 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-3bc49e0c-f421-4af2-b04e-cccfe86402bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2446969212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2446969212 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1697229037 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 459130489 ps |
| CPU time | 5.06 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:04 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-ebfd7daa-6ba8-4f41-be7a-df68fc62e881 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697229037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1697229037 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2223215195 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 114272389 ps |
| CPU time | 7.11 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:07 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-872831e7-a9e4-4f42-a7f9-69149446eed8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2223215195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2223215195 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2084031057 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 50884973919 ps |
| CPU time | 140.61 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:20:21 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-268c4c40-c47f-41f0-8498-dc4ec3216ef1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2084031057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2084031057 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.485475340 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 33698787 ps |
| CPU time | 4.38 seconds |
| Started | Feb 21 01:18:07 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-08d24865-d229-4d55-93bc-9ba5e3440a93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485475340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.485475340 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2310217919 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1187457931 ps |
| CPU time | 9.65 seconds |
| Started | Feb 21 01:18:03 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-600f77a9-793c-4bbc-adfd-02ae1c87e5fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2310217919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2310217919 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.4017129913 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 93211370 ps |
| CPU time | 1.61 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-f330e13a-fdf3-48a6-8880-660024eec85e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4017129913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4017129913 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4056288401 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3927162800 ps |
| CPU time | 8.94 seconds |
| Started | Feb 21 01:17:59 PM PST 24 |
| Finished | Feb 21 01:18:08 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-5c2c01d9-6f15-41e8-bb29-5ce19c6716db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056288401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4056288401 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.663956852 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 7727637834 ps |
| CPU time | 8.98 seconds |
| Started | Feb 21 01:18:03 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-299ee41e-4ded-4569-8944-6508559be81f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=663956852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.663956852 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.857362838 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 16831978 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 01:18:03 PM PST 24 |
| Finished | Feb 21 01:18:04 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-3eb78492-b4a6-4006-868d-e4db8f10a60c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857362838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.857362838 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2973526986 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 425796554 ps |
| CPU time | 45.47 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:46 PM PST 24 |
| Peak memory | 203520 kb |
| Host | smart-a5223801-52ed-4a9c-98a8-d67bbe6128f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2973526986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2973526986 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3695868644 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 300918277 ps |
| CPU time | 21.84 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:23 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-b26d743e-8dbf-43af-9752-467d24628ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3695868644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3695868644 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1549330864 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 63960856 ps |
| CPU time | 24.6 seconds |
| Started | Feb 21 01:18:02 PM PST 24 |
| Finished | Feb 21 01:18:27 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-4a615991-5681-4ca5-a43e-dc573a15dbaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1549330864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1549330864 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3808697224 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 761802059 ps |
| CPU time | 57.18 seconds |
| Started | Feb 21 01:18:00 PM PST 24 |
| Finished | Feb 21 01:18:58 PM PST 24 |
| Peak memory | 204976 kb |
| Host | smart-cda41ddd-60c8-4c2e-abe1-3b775d351107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3808697224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.3808697224 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.312114158 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 842144985 ps |
| CPU time | 5.44 seconds |
| Started | Feb 21 01:18:04 PM PST 24 |
| Finished | Feb 21 01:18:10 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-456fc9d0-ff02-4bb1-9a26-33a8b3163077 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312114158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.312114158 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1469532326 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 183202932 ps |
| CPU time | 1.71 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:14 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-eb129bd1-746c-4888-a6d5-e3db0c1a8ea8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1469532326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1469532326 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.575148156 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 21526031361 ps |
| CPU time | 121.47 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:20:13 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-b98098ad-0937-4ac0-a24b-0d7f271107bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=575148156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo w_rsp.575148156 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2830594060 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 866309315 ps |
| CPU time | 6.9 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-16dd3697-f376-476c-88f2-2153617d6c49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830594060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2830594060 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.1265297118 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 114919611 ps |
| CPU time | 3.97 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:17 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-4e337468-715c-484d-abad-cc89a69f0c82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1265297118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1265297118 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3286135776 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 776726849 ps |
| CPU time | 9.9 seconds |
| Started | Feb 21 01:18:07 PM PST 24 |
| Finished | Feb 21 01:18:17 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-177858bb-e0bb-4b10-a5c3-c590714916ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3286135776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3286135776 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.47232397 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 66363317939 ps |
| CPU time | 99.07 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:19:55 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-2f896125-7c35-4d26-970f-7ef0dd8dd722 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=47232397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.47232397 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3317311591 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 53151500033 ps |
| CPU time | 130.05 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:20:26 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-784a2dc3-831c-4fcb-8096-38c6c15a91f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3317311591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3317311591 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.4276374766 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 151253950 ps |
| CPU time | 6.1 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-abcf1af8-16b2-4113-8a75-5dd0540a2167 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276374766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4276374766 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2131407332 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 694805187 ps |
| CPU time | 8.46 seconds |
| Started | Feb 21 01:18:16 PM PST 24 |
| Finished | Feb 21 01:18:25 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-2bb65911-fc6f-42e0-afe2-ef43ee484770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2131407332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2131407332 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.100375497 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 48767362 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-d5e81540-511a-470b-af6d-775022f4d70e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100375497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.100375497 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1827320265 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 9913250352 ps |
| CPU time | 9.9 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:22 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-b2704562-ff06-4a5f-840d-328877b41bfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827320265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1827320265 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3704473637 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2738064692 ps |
| CPU time | 7.68 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-0caa2077-8eee-4f91-b695-d8cf965ffe35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3704473637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3704473637 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3426651811 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 11082647 ps |
| CPU time | 1 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:12 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-6bdb8bc6-0696-4ff4-898a-e1dbde63205f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426651811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3426651811 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1277256590 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 99996496 ps |
| CPU time | 4.93 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-52b29511-0345-476d-80f3-4f7ac3a6e7f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1277256590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1277256590 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1735609384 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4025446399 ps |
| CPU time | 31.62 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:44 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-7b5f940b-d25c-4ddf-9d36-a6096e87c30c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1735609384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1735609384 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1968087979 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 168349797 ps |
| CPU time | 19.73 seconds |
| Started | Feb 21 01:18:13 PM PST 24 |
| Finished | Feb 21 01:18:34 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-a5090b52-c12b-40fa-b5e1-ce4d7fc80318 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1968087979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1968087979 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1109582483 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8636866701 ps |
| CPU time | 25.72 seconds |
| Started | Feb 21 01:18:08 PM PST 24 |
| Finished | Feb 21 01:18:36 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-ac56149b-ac3e-47d2-b031-501356b19af3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1109582483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1109582483 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1305004041 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 147045518 ps |
| CPU time | 6.65 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-d61dd6dc-4bd9-41e0-8da1-5283afdf15ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1305004041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1305004041 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1687696909 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 116839010 ps |
| CPU time | 8.24 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-fce9c22e-7efc-4bfb-870f-5cdbc5b675ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1687696909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1687696909 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3353932658 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 459559461 ps |
| CPU time | 3.55 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:16 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-7b2ac91b-81db-4e61-81bb-f7b7cde1e76d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353932658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3353932658 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.4002715437 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 14517861 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:12 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-afbbbedd-c8f4-4dff-962d-7303dee96889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4002715437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4002715437 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1601131591 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 156394127 ps |
| CPU time | 3.22 seconds |
| Started | Feb 21 01:18:07 PM PST 24 |
| Finished | Feb 21 01:18:10 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-518d88f8-d207-4460-9a28-00351da4d927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1601131591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1601131591 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1394294615 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1640610714 ps |
| CPU time | 8.23 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-e6a6ddf7-b7ba-49e2-93b9-ec46903ad1cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394294615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1394294615 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.626672080 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 21034592899 ps |
| CPU time | 97.3 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:19:54 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-0274bc6c-2e35-400c-9cda-01958958fde1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=626672080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.626672080 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2819616278 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 57262719 ps |
| CPU time | 4.14 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:16 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-01e2c220-8f20-44cb-9b3c-ad1757c1884f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819616278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2819616278 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.588798705 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 311939907 ps |
| CPU time | 2.33 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:15 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-15d278fe-23eb-4a2c-bc20-6566d608741a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588798705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.588798705 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.1174827008 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 72893110 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 01:18:13 PM PST 24 |
| Finished | Feb 21 01:18:16 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-fa34b944-d01f-4ca9-8d78-0ff1ecc331e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1174827008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1174827008 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3873694546 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 6641195479 ps |
| CPU time | 9.06 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-eb4aca74-9bec-4656-9ab8-a42a1a91f778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873694546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3873694546 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3426920551 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1554870760 ps |
| CPU time | 5.94 seconds |
| Started | Feb 21 01:18:08 PM PST 24 |
| Finished | Feb 21 01:18:17 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-13ce17e9-549e-46a2-9083-c342dbb89eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3426920551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3426920551 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1534245663 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 8023391 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 01:18:12 PM PST 24 |
| Finished | Feb 21 01:18:15 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-a3f9c3c5-c2a5-432a-b03b-d48f011d0e95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534245663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1534245663 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3238201673 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 43448483523 ps |
| CPU time | 103.95 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:20:00 PM PST 24 |
| Peak memory | 206108 kb |
| Host | smart-7c990aac-54e9-4969-b16e-466731e3d660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3238201673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3238201673 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1913597968 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 11135747265 ps |
| CPU time | 41.27 seconds |
| Started | Feb 21 01:18:17 PM PST 24 |
| Finished | Feb 21 01:18:59 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-6ccc8961-e353-4cfc-8d24-f78f12f45ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1913597968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1913597968 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3516223826 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 80232902 ps |
| CPU time | 10.28 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-7d9b14bd-8b84-4565-bd9c-5f704c4bf589 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3516223826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3516223826 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.671729170 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 725899896 ps |
| CPU time | 94.16 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:19:46 PM PST 24 |
| Peak memory | 207216 kb |
| Host | smart-cf87a7f6-6556-4ae4-918d-bfd489d42c41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=671729170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_res et_error.671729170 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1278233945 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 315200801 ps |
| CPU time | 9.08 seconds |
| Started | Feb 21 01:18:12 PM PST 24 |
| Finished | Feb 21 01:18:23 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-373deb7e-3617-40ab-b1dd-d864d601e316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1278233945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1278233945 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2538589516 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 130523619 ps |
| CPU time | 8.85 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:24 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-14f945aa-9279-4a0c-964a-427222b16d8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2538589516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2538589516 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.593700868 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 55236128498 ps |
| CPU time | 45.74 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:19:02 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-d9619e5c-f800-4730-aaa7-719dc34aecb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=593700868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo w_rsp.593700868 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.264970751 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 122441567 ps |
| CPU time | 2.01 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-218b3d6e-08d3-427a-aaa7-c6d34467f328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=264970751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.264970751 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.1310875084 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 688497824 ps |
| CPU time | 3.42 seconds |
| Started | Feb 21 01:18:13 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-a76e20c5-b3c2-4f3a-8a6e-50937858bbe9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310875084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1310875084 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1849476626 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 31911214 ps |
| CPU time | 3.55 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:20 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-f9f43ae9-d99c-4195-8b7a-50c6d658ee15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849476626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1849476626 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3495186401 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 23350027784 ps |
| CPU time | 117.69 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:20:13 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-91e67242-aa93-4375-aafe-442dabc93691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495186401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3495186401 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3529999507 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 56901292072 ps |
| CPU time | 103.95 seconds |
| Started | Feb 21 01:18:18 PM PST 24 |
| Finished | Feb 21 01:20:02 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-3439c684-0ffd-4530-b3fb-ebc2102e03b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3529999507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3529999507 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.528389204 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 158663937 ps |
| CPU time | 6.15 seconds |
| Started | Feb 21 01:18:13 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-af4fc5fd-afdc-449a-ae56-69f0e4c8e981 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528389204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.528389204 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1496736275 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2310843056 ps |
| CPU time | 5.07 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:20 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-15d697a9-b880-41d5-84a8-62e2fbfed423 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496736275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1496736275 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1959155136 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 113696573 ps |
| CPU time | 1.4 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-4b81774d-4573-4e47-a5c2-5caac690c7e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1959155136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1959155136 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.616844048 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1920617877 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 01:18:18 PM PST 24 |
| Finished | Feb 21 01:18:25 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-a8e33d7b-9a3f-4b5a-9f02-34d81bfeb69a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=616844048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.616844048 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.425168182 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 961233026 ps |
| CPU time | 6.67 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:23 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-20a475cb-8b62-41f7-a648-1a3b8cfdefca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=425168182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.425168182 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3335548313 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 17128574 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:13 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-689226f4-783f-453b-a3de-bc887b3ba760 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335548313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3335548313 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.4073133109 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 23271809 ps |
| CPU time | 1.96 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-fbc4c44e-a340-4a9f-9223-22242186e68b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073133109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.4073133109 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1295617033 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 12129320 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:17 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-96335725-eb96-4cb4-8730-8abfb8a57524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295617033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1295617033 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1812226891 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8281226874 ps |
| CPU time | 78.82 seconds |
| Started | Feb 21 01:18:19 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 205940 kb |
| Host | smart-f0556ed6-2005-4525-9119-8719846c3296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1812226891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1812226891 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3658000890 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4623724048 ps |
| CPU time | 33.15 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:49 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-c1efa5b1-7d42-4f42-bcd0-b85c3c095b00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3658000890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3658000890 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.267287410 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1172109455 ps |
| CPU time | 9.54 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:25 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ef3de09e-497b-403d-b181-7a4c8ff7c6f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=267287410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.267287410 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1723703023 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 93922360 ps |
| CPU time | 10.57 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:15:38 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-c69d7c61-e9cc-49fb-94e6-ac8cdff68873 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1723703023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1723703023 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.962465633 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19879723010 ps |
| CPU time | 60.57 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:16:26 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-9752c019-f341-4db2-9ef6-9d8598cf3be2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=962465633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.962465633 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.194033553 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 240154619 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 01:15:23 PM PST 24 |
| Finished | Feb 21 01:15:24 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-3a82bca7-bad8-4886-91ba-e66f165c19bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194033553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.194033553 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.424708135 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 198497768 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:15:27 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-813d4993-4dcf-45af-bbe3-44d9328651e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424708135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.424708135 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.61166817 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 895040508 ps |
| CPU time | 14.61 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:15:43 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-4542c374-090f-4861-a4ab-71b65dfd15e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61166817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.61166817 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1743765940 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 29579724320 ps |
| CPU time | 125.77 seconds |
| Started | Feb 21 01:15:29 PM PST 24 |
| Finished | Feb 21 01:17:35 PM PST 24 |
| Peak memory | 202928 kb |
| Host | smart-d850080f-bc61-493d-95a6-012a77cb5e2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743765940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1743765940 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3831770516 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 31526597459 ps |
| CPU time | 141.03 seconds |
| Started | Feb 21 01:15:30 PM PST 24 |
| Finished | Feb 21 01:17:52 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-5787573a-8c7f-4ed8-8d93-57107f14f208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3831770516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3831770516 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.285723329 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 110954167 ps |
| CPU time | 6.93 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:15:36 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-cda7b6b0-4e09-4d7f-83d3-6b7c540d00bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285723329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.285723329 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.3225593981 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2205697956 ps |
| CPU time | 11.62 seconds |
| Started | Feb 21 01:15:29 PM PST 24 |
| Finished | Feb 21 01:15:41 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-e89b0873-71a6-435a-bd06-3939de1fd3ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3225593981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3225593981 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.1488443373 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 64739027 ps |
| CPU time | 1.31 seconds |
| Started | Feb 21 01:15:22 PM PST 24 |
| Finished | Feb 21 01:15:24 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-be58f8c4-57a2-45f5-bfa3-f87c97df526e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488443373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1488443373 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.111706386 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2399841654 ps |
| CPU time | 7.7 seconds |
| Started | Feb 21 01:15:39 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-496a23d8-f046-4d67-94a5-25b0ff6efd3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=111706386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.111706386 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3956490097 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3028782752 ps |
| CPU time | 8.66 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:15:37 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-cff69b53-66df-4dc2-a43b-e4ea3ae1c7ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3956490097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3956490097 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1767583374 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 15501029 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:27 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-b1124a7e-f55c-4275-b370-d6a8db0ffbdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767583374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1767583374 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.646655075 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 110858248 ps |
| CPU time | 14.54 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:41 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-b94d62c8-f016-4ddf-a73e-cdd5b145a3e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=646655075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.646655075 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.842509983 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 261145145 ps |
| CPU time | 26.52 seconds |
| Started | Feb 21 01:15:35 PM PST 24 |
| Finished | Feb 21 01:16:02 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-74e5f893-b647-4197-ab63-ab05c6d6d3ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=842509983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.842509983 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.27308811 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 129093229 ps |
| CPU time | 13.36 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:15:38 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-ff05c6f5-370e-4345-8ff1-ac085851471c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27308811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset _error.27308811 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2453328930 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 28688080 ps |
| CPU time | 4.09 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:31 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-40c5bd20-852f-41d3-ac1d-ab918d2fd1a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2453328930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2453328930 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.649118008 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 905905912 ps |
| CPU time | 7.19 seconds |
| Started | Feb 21 01:15:29 PM PST 24 |
| Finished | Feb 21 01:15:37 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-221a944a-7b96-46ca-b3f2-7ce35d77676c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=649118008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.649118008 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.58153851 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 20744111233 ps |
| CPU time | 160.35 seconds |
| Started | Feb 21 01:15:22 PM PST 24 |
| Finished | Feb 21 01:18:03 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-57773712-9781-4e65-8be8-e460d9552e3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=58153851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.58153851 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4277295561 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 200556345 ps |
| CPU time | 4.46 seconds |
| Started | Feb 21 01:15:29 PM PST 24 |
| Finished | Feb 21 01:15:34 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-b8d2d38f-f424-4671-9204-e88037f1ee9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4277295561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4277295561 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.1836071383 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 285175192 ps |
| CPU time | 5.37 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:15:31 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f814ff20-37e3-450a-bcff-edb83da7cbc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1836071383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1836071383 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1746068014 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 722871919 ps |
| CPU time | 10.39 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:36 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-5e937b89-8463-42cd-97f3-24e10fa94804 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746068014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1746068014 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1815173398 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 37720467476 ps |
| CPU time | 114.42 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:17:22 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-014539d9-1f4c-4fb7-8118-82931ffb7310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815173398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1815173398 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2754072071 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 29318250751 ps |
| CPU time | 105.36 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:17:11 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-49917a65-d5a1-455f-b425-d7cff72f572a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2754072071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2754072071 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.463356153 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 62746611 ps |
| CPU time | 5.71 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:15:33 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-043df182-62ef-4afe-9b5f-c150185861f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463356153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.463356153 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3351796029 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4698005932 ps |
| CPU time | 12.36 seconds |
| Started | Feb 21 01:15:38 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-636fdbc0-89b7-467b-bc2a-edf2f64e8c99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3351796029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3351796029 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3750763810 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 64185673 ps |
| CPU time | 1.74 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:15:29 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-e4d8165a-fc01-4a1f-aafd-163d300a79a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750763810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3750763810 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3752392356 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 6415330954 ps |
| CPU time | 11.51 seconds |
| Started | Feb 21 01:15:25 PM PST 24 |
| Finished | Feb 21 01:15:37 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-30dae55b-89c1-4b5b-ae48-b0cf10079295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752392356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3752392356 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.5825205 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1134460235 ps |
| CPU time | 9.04 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:35 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-6bfff9ed-947f-4bef-bf79-485a1cd0f414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=5825205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.5825205 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4290746443 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10654011 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:15:28 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-1a1219cf-6d29-44c9-b8d0-fe6485eac61e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290746443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4290746443 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1782146470 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 11330229874 ps |
| CPU time | 104.46 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-dbd1c463-4758-484b-8c7a-42436e4fd72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782146470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1782146470 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1097376471 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4036508888 ps |
| CPU time | 45.33 seconds |
| Started | Feb 21 01:15:31 PM PST 24 |
| Finished | Feb 21 01:16:17 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-18896217-63d0-4458-9b06-b7e0948a45e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097376471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1097376471 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4194961250 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5610459490 ps |
| CPU time | 135.46 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:17:44 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-8fab5ccb-a7c2-47a1-a225-97bb444358ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4194961250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.4194961250 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.298972485 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1899707886 ps |
| CPU time | 129.48 seconds |
| Started | Feb 21 01:15:30 PM PST 24 |
| Finished | Feb 21 01:17:39 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-d68e894b-a185-4948-8bb2-e0b97df84b78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=298972485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese t_error.298972485 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3181936168 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 20291104 ps |
| CPU time | 2.57 seconds |
| Started | Feb 21 01:15:23 PM PST 24 |
| Finished | Feb 21 01:15:26 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-bb854e06-5b86-4f0d-b6c4-a74a5f916678 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3181936168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3181936168 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2823760462 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 148887903 ps |
| CPU time | 13.48 seconds |
| Started | Feb 21 01:15:43 PM PST 24 |
| Finished | Feb 21 01:15:57 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-03c1ddd2-9d9e-42b3-9e9f-ebadae184840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823760462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2823760462 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4247753663 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 281716573 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 01:15:42 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-21f57b2b-dec9-454d-954e-5ba1196b59ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247753663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4247753663 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.3080125622 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 64906898 ps |
| CPU time | 1.76 seconds |
| Started | Feb 21 01:15:40 PM PST 24 |
| Finished | Feb 21 01:15:42 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-871ce789-e926-4cc4-bc2c-7b7acdb1155f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080125622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3080125622 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.4172264498 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 143932568 ps |
| CPU time | 2.95 seconds |
| Started | Feb 21 01:15:28 PM PST 24 |
| Finished | Feb 21 01:15:31 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-effe2c90-cd07-466c-9769-78a541ec8203 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172264498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4172264498 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3970523646 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1581069048 ps |
| CPU time | 6.45 seconds |
| Started | Feb 21 01:15:38 PM PST 24 |
| Finished | Feb 21 01:15:46 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-62a1a143-6ab7-401f-8d19-189840b3d4e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970523646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3970523646 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4224528031 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 19442885857 ps |
| CPU time | 44.24 seconds |
| Started | Feb 21 01:15:26 PM PST 24 |
| Finished | Feb 21 01:16:10 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-d2dc859e-3c53-4b6b-bc96-9fd4ccceb8b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4224528031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4224528031 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3723507180 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 29266402 ps |
| CPU time | 4.4 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:15:32 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-cedb46d7-d787-4962-9e71-7242e33fa9e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723507180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3723507180 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2210564951 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 24297462 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 01:15:41 PM PST 24 |
| Finished | Feb 21 01:15:44 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-ecd5cbb2-3dd6-420e-8dc9-709de49765be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2210564951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2210564951 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1102803442 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 12681169 ps |
| CPU time | 1.17 seconds |
| Started | Feb 21 01:15:27 PM PST 24 |
| Finished | Feb 21 01:15:29 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-382fc478-46e3-40e3-8836-f254f68f9a0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102803442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1102803442 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.787343900 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3040336431 ps |
| CPU time | 8.72 seconds |
| Started | Feb 21 01:15:41 PM PST 24 |
| Finished | Feb 21 01:15:50 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-4ef1c0d7-29d5-49cf-9d9b-f13c86b51f8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=787343900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.787343900 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1397524231 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 8005479415 ps |
| CPU time | 12.61 seconds |
| Started | Feb 21 01:15:40 PM PST 24 |
| Finished | Feb 21 01:15:53 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-5cebd1a9-ef68-4617-9192-26cb0c841c84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1397524231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1397524231 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1358276610 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 7760913 ps |
| CPU time | 1.28 seconds |
| Started | Feb 21 01:15:29 PM PST 24 |
| Finished | Feb 21 01:15:30 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-d1a672f9-9877-4f1e-88b4-4d9f4de80fa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358276610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1358276610 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3638226645 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 37156060502 ps |
| CPU time | 106.75 seconds |
| Started | Feb 21 01:15:44 PM PST 24 |
| Finished | Feb 21 01:17:31 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-25fd7a70-9096-43a9-a018-a0530dad8118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3638226645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3638226645 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3330899594 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1744954608 ps |
| CPU time | 28.81 seconds |
| Started | Feb 21 01:15:40 PM PST 24 |
| Finished | Feb 21 01:16:10 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-7f698031-16d0-4b1b-85e8-faab1f78ff6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3330899594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3330899594 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2931170549 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 595781653 ps |
| CPU time | 117.55 seconds |
| Started | Feb 21 01:15:38 PM PST 24 |
| Finished | Feb 21 01:17:37 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-339413ff-71f8-4580-ae22-af76e454006c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931170549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.2931170549 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2487677342 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 920299873 ps |
| CPU time | 69.47 seconds |
| Started | Feb 21 01:15:46 PM PST 24 |
| Finished | Feb 21 01:16:56 PM PST 24 |
| Peak memory | 206232 kb |
| Host | smart-bd0997fc-0f99-47c4-9501-ff98b9b8baa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2487677342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2487677342 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.774456224 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 420147570 ps |
| CPU time | 8.17 seconds |
| Started | Feb 21 01:15:38 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-8ce1ba95-ab93-490b-964a-e2741bd93d5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=774456224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.774456224 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1288429372 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1262989055 ps |
| CPU time | 15.8 seconds |
| Started | Feb 21 01:15:44 PM PST 24 |
| Finished | Feb 21 01:16:00 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-bff8d542-8d03-4ecf-86bf-ae5e00de8e5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1288429372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1288429372 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.534819669 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 23247928679 ps |
| CPU time | 168.09 seconds |
| Started | Feb 21 01:15:43 PM PST 24 |
| Finished | Feb 21 01:18:32 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-d732e617-f830-4019-8b8a-0052e1dfd5d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=534819669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.534819669 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1184601139 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 305627231 ps |
| CPU time | 3.84 seconds |
| Started | Feb 21 01:15:43 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-acd3123d-f26a-4785-9aa3-db0d383dfb57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184601139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1184601139 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.8423399 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 826696033 ps |
| CPU time | 5.07 seconds |
| Started | Feb 21 01:15:41 PM PST 24 |
| Finished | Feb 21 01:15:46 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-86206617-a0aa-43d8-b445-63a56fe12e8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8423399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.8423399 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1058885674 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 73121761 ps |
| CPU time | 1.59 seconds |
| Started | Feb 21 01:15:40 PM PST 24 |
| Finished | Feb 21 01:15:42 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-72c016c6-fe88-4816-9289-14e8a79feb69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1058885674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1058885674 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2011226641 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 16113992571 ps |
| CPU time | 33.11 seconds |
| Started | Feb 21 01:15:42 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-1b9cfbc9-2745-4940-bda8-3e5ff451ef4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011226641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2011226641 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.358957808 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 39729418533 ps |
| CPU time | 45.29 seconds |
| Started | Feb 21 01:15:43 PM PST 24 |
| Finished | Feb 21 01:16:28 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-70ada67b-991a-4ab8-b347-c213d659e510 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=358957808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.358957808 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.4106271755 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 16846373 ps |
| CPU time | 1.74 seconds |
| Started | Feb 21 01:15:41 PM PST 24 |
| Finished | Feb 21 01:15:43 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-cced412c-100a-4f22-8219-450977714933 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106271755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.4106271755 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1990859324 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 104998118 ps |
| CPU time | 1.95 seconds |
| Started | Feb 21 01:15:46 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-87cc8ce8-ef18-4c38-a705-cee2e86a6f80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990859324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1990859324 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1171602029 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 149017112 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 01:15:46 PM PST 24 |
| Finished | Feb 21 01:15:48 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-f62a689c-0255-4ffd-8383-62b965d9df49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171602029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1171602029 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.18280630 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2966866255 ps |
| CPU time | 8.47 seconds |
| Started | Feb 21 01:15:42 PM PST 24 |
| Finished | Feb 21 01:15:51 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-83552a6d-20b5-4e44-ba7b-15b3025c2032 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.18280630 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1648538790 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2007899027 ps |
| CPU time | 10.18 seconds |
| Started | Feb 21 01:15:44 PM PST 24 |
| Finished | Feb 21 01:15:55 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-a4794301-0578-4ce6-a0ef-d1500af5f54f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1648538790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1648538790 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3115637934 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9100043 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:15:44 PM PST 24 |
| Finished | Feb 21 01:15:46 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-cc2fe98b-8f81-47f3-bd18-1d1abeec25ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115637934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3115637934 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1391510407 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 233730580 ps |
| CPU time | 24.87 seconds |
| Started | Feb 21 01:15:43 PM PST 24 |
| Finished | Feb 21 01:16:09 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-29948296-fab6-4230-b890-03ab6ab1fa42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1391510407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1391510407 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2174840426 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 992996979 ps |
| CPU time | 35.03 seconds |
| Started | Feb 21 01:15:47 PM PST 24 |
| Finished | Feb 21 01:16:23 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-d60874aa-4728-4697-b041-008326707af5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174840426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2174840426 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2430218131 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 128700911 ps |
| CPU time | 26.3 seconds |
| Started | Feb 21 01:15:49 PM PST 24 |
| Finished | Feb 21 01:16:16 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-6037b7c6-f6d2-4a79-96e8-853b14a13b6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2430218131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2430218131 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1267505049 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 8578144070 ps |
| CPU time | 107.26 seconds |
| Started | Feb 21 01:15:54 PM PST 24 |
| Finished | Feb 21 01:17:43 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-fd699508-0c1e-430f-a725-0449880da58f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267505049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1267505049 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3501762539 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1131070324 ps |
| CPU time | 4.14 seconds |
| Started | Feb 21 01:15:45 PM PST 24 |
| Finished | Feb 21 01:15:50 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-18da018a-9661-4f6c-a8da-b45936091101 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501762539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3501762539 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.171619758 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1927920474 ps |
| CPU time | 20.47 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:16:18 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-4724d644-f716-4901-bc5b-94a14995afd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171619758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.171619758 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2064275168 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 9906471523 ps |
| CPU time | 78.88 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-253f9a7f-a3a3-4c12-a494-b1353660e50e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2064275168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2064275168 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1446241905 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 72594315 ps |
| CPU time | 2.66 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:04 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-1258d7a0-e5af-41c6-b2e6-2e35644f998f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446241905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1446241905 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1235576996 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1046686762 ps |
| CPU time | 12.33 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:13 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-8194ea88-83c0-4105-9861-183cf89f0381 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235576996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1235576996 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.562300657 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 574484043 ps |
| CPU time | 5.25 seconds |
| Started | Feb 21 01:15:46 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-0c0b554e-b57c-4011-b996-b82eadfd49e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=562300657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.562300657 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.648077631 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 20298885603 ps |
| CPU time | 47.78 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:16:37 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-69895e27-8ed8-4e80-93af-73527e50cf5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=648077631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.648077631 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3076823071 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13651190086 ps |
| CPU time | 111.72 seconds |
| Started | Feb 21 01:15:51 PM PST 24 |
| Finished | Feb 21 01:17:44 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-d3a57cd1-a14e-4c22-82fc-c88dc9dbd236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3076823071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3076823071 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1621302169 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 28390101 ps |
| CPU time | 4.17 seconds |
| Started | Feb 21 01:16:00 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-252d2b66-52b6-4895-ac1f-c14fb9e6ab69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621302169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1621302169 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.4167246795 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1867430008 ps |
| CPU time | 7.74 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:15:56 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-f97c2848-ca98-4c20-a52f-d63249ee9abd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4167246795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4167246795 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.778771359 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 10477227 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:15:52 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-f968023a-67bc-4eba-95b5-a9f627cb584b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=778771359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.778771359 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3806788634 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2202100265 ps |
| CPU time | 8.02 seconds |
| Started | Feb 21 01:15:48 PM PST 24 |
| Finished | Feb 21 01:15:56 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-3e3f7e7a-da65-4419-a056-fb898dda5925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806788634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3806788634 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2970763162 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3193086822 ps |
| CPU time | 9.64 seconds |
| Started | Feb 21 01:15:51 PM PST 24 |
| Finished | Feb 21 01:16:02 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-a6b6ddfd-9d15-4578-a104-de25e75f2b46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2970763162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2970763162 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.787420349 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 10692584 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 01:15:53 PM PST 24 |
| Finished | Feb 21 01:15:56 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-cc250683-11a8-4773-a985-596de261fa40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787420349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.787420349 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3220382374 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5311787975 ps |
| CPU time | 63.2 seconds |
| Started | Feb 21 01:15:50 PM PST 24 |
| Finished | Feb 21 01:16:53 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-89cca15f-c463-4600-83a3-89cb79b29803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220382374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3220382374 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.276166541 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 493135690 ps |
| CPU time | 37.71 seconds |
| Started | Feb 21 01:15:52 PM PST 24 |
| Finished | Feb 21 01:16:31 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-bf630f46-2c1c-456e-9e91-154d4763561d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276166541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.276166541 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.283699004 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1380598599 ps |
| CPU time | 46.42 seconds |
| Started | Feb 21 01:15:55 PM PST 24 |
| Finished | Feb 21 01:16:43 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-9cfdd9f3-1de6-4bd9-83ee-727d3ed76c0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283699004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.283699004 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1215033970 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1230672845 ps |
| CPU time | 145.25 seconds |
| Started | Feb 21 01:15:51 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 206972 kb |
| Host | smart-47957435-80bb-4de3-937e-2d0ee5cd9c88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1215033970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1215033970 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3819181138 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 54217294 ps |
| CPU time | 1.41 seconds |
| Started | Feb 21 01:15:45 PM PST 24 |
| Finished | Feb 21 01:15:47 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-608f4559-3c73-40ee-b34a-cc7a3f86fd42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819181138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3819181138 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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