Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 410 1 T4 1 T18 4 T20 2
all_values[1] 445 1 T2 1 T4 8 T18 2
all_values[2] 414 1 T2 1 T4 4 T18 5
all_values[3] 433 1 T2 1 T4 9 T18 1
all_values[4] 445 1 T2 1 T4 5 T17 1
all_values[5] 404 1 T4 1 T17 1 T18 2
all_values[6] 437 1 T4 4 T18 6 T20 1
all_values[7] 429 1 T2 1 T4 3 T18 4
all_values[8] 397 1 T2 1 T4 3 T17 1
all_values[9] 450 1 T2 2 T4 4 T18 8
all_values[10] 423 1 T4 7 T17 2 T18 8
all_values[11] 401 1 T2 1 T4 4 T17 1
all_values[12] 442 1 T4 4 T17 1 T18 4
all_values[13] 405 1 T2 1 T4 1 T17 1
all_values[14] 416 1 T4 3 T18 5 T20 1
all_values[15] 410 1 T4 5 T17 1 T18 2
all_values[16] 385 1 T2 1 T4 5 T20 4
all_values[17] 424 1 T2 2 T4 6 T17 1
all_values[18] 444 1 T2 1 T4 8 T17 1
all_values[19] 413 1 T4 3 T18 3 T23 1
all_values[20] 400 1 T2 1 T4 5 T18 1
all_values[21] 416 1 T4 4 T17 1 T18 5
all_values[22] 400 1 T2 1 T4 1 T18 5
all_values[23] 440 1 T2 3 T4 1 T18 5
all_values[24] 404 1 T4 10 T18 6 T25 4
all_values[25] 431 1 T4 2 T18 1 T20 2
all_values[26] 445 1 T2 1 T17 1 T18 4

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