Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	430	1			T11	2		T22	1		T34	1
all_values[1]	431	1			T22	1		T34	1		T46	1
all_values[2]	448	1			T34	1		T46	1		T113	7
all_values[3]	409	1			T40	1		T34	1		T46	1
all_values[4]	458	1			T11	1		T19	1		T113	6
all_values[5]	423	1			T22	1		T34	1		T113	4
all_values[6]	479	1			T11	1		T34	1		T46	1
all_values[7]	451	1			T113	4		T61	2		T70	3
all_values[8]	453	1			T11	2		T22	1		T34	1
all_values[9]	400	1			T34	1		T113	7		T70	2
all_values[10]	439	1			T113	9		T48	1		T50	1
all_values[11]	402	1			T11	2		T40	2		T34	2
all_values[12]	452	1			T11	2		T19	1		T113	4
all_values[13]	440	1			T113	4		T48	2		T61	1
all_values[14]	423	1			T34	1		T113	7		T70	1
all_values[15]	445	1			T11	1		T40	1		T34	1
all_values[16]	408	1			T11	1		T113	5		T70	2
all_values[17]	418	1			T11	3		T40	1		T46	2
all_values[18]	402	1			T113	4		T61	2		T70	2
all_values[19]	434	1			T11	1		T34	2		T113	4
all_values[20]	441	1			T19	1		T34	1		T46	2
all_values[21]	411	1			T113	2		T70	3		T50	1
all_values[22]	418	1			T46	1		T113	7		T48	1
all_values[23]	424	1			T11	1		T46	1		T113	2
all_values[24]	447	1			T19	1		T34	1		T46	1
all_values[25]	423	1			T11	1		T40	1		T34	2
all_values[26]	435	1			T11	1		T34	2		T113	3