| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.25 | 100.00 | 95.52 | 100.00 | 100.00 | 100.00 | 100.00 |
| T762 | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3624468808 | Feb 29 12:51:02 PM PST 24 | Feb 29 12:51:06 PM PST 24 | 25002189 ps | ||
| T143 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.502946225 | Feb 29 12:52:19 PM PST 24 | Feb 29 12:53:25 PM PST 24 | 4202925052 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.27484496 | Feb 29 12:49:44 PM PST 24 | Feb 29 12:49:48 PM PST 24 | 151537361 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.836266527 | Feb 29 12:49:45 PM PST 24 | Feb 29 12:49:48 PM PST 24 | 9319081 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3901501311 | Feb 29 12:52:25 PM PST 24 | Feb 29 12:54:06 PM PST 24 | 17590360679 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.144101967 | Feb 29 12:51:25 PM PST 24 | Feb 29 12:52:31 PM PST 24 | 85813929040 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/34.xbar_smoke.4199864537 | Feb 29 12:51:48 PM PST 24 | Feb 29 12:51:50 PM PST 24 | 49071928 ps | ||
| T158 | /workspace/coverage/xbar_build_mode/40.xbar_random.3367618713 | Feb 29 12:52:07 PM PST 24 | Feb 29 12:52:17 PM PST 24 | 710818408 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2866664684 | Feb 29 12:51:26 PM PST 24 | Feb 29 12:51:45 PM PST 24 | 120695056 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.890122758 | Feb 29 12:52:14 PM PST 24 | Feb 29 12:52:55 PM PST 24 | 3771614649 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/36.xbar_error_random.4051216467 | Feb 29 12:51:55 PM PST 24 | Feb 29 12:51:57 PM PST 24 | 16099167 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2893402999 | Feb 29 12:51:58 PM PST 24 | Feb 29 12:53:51 PM PST 24 | 3862874897 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2510040953 | Feb 29 12:49:46 PM PST 24 | Feb 29 12:51:54 PM PST 24 | 29588949461 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2390861033 | Feb 29 12:51:26 PM PST 24 | Feb 29 12:52:07 PM PST 24 | 428974687 ps | ||
| T110 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2697532231 | Feb 29 12:51:59 PM PST 24 | Feb 29 12:53:10 PM PST 24 | 3839793521 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1302454422 | Feb 29 12:50:25 PM PST 24 | Feb 29 12:50:50 PM PST 24 | 258840950 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3395039980 | Feb 29 12:49:58 PM PST 24 | Feb 29 12:50:11 PM PST 24 | 5479276643 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1738718705 | Feb 29 12:50:01 PM PST 24 | Feb 29 12:50:04 PM PST 24 | 7197853 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3668415222 | Feb 29 12:50:58 PM PST 24 | Feb 29 12:51:05 PM PST 24 | 1595076476 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1770040438 | Feb 29 12:52:20 PM PST 24 | Feb 29 12:53:10 PM PST 24 | 706742282 ps | ||
| T128 | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.681351039 | Feb 29 12:51:00 PM PST 24 | Feb 29 12:54:26 PM PST 24 | 66028272277 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/21.xbar_smoke.3165741112 | Feb 29 12:51:24 PM PST 24 | Feb 29 12:51:25 PM PST 24 | 8975507 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3055679298 | Feb 29 12:49:49 PM PST 24 | Feb 29 12:50:52 PM PST 24 | 670765176 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4131371057 | Feb 29 12:50:02 PM PST 24 | Feb 29 12:50:04 PM PST 24 | 11594635 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1874150036 | Feb 29 12:50:58 PM PST 24 | Feb 29 12:51:03 PM PST 24 | 214900243 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.153013472 | Feb 29 12:49:39 PM PST 24 | Feb 29 12:49:44 PM PST 24 | 2513205873 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2463800542 | Feb 29 12:50:17 PM PST 24 | Feb 29 12:53:10 PM PST 24 | 23808695484 ps | ||
| T6 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.494349924 | Feb 29 12:52:00 PM PST 24 | Feb 29 12:53:59 PM PST 24 | 855070272 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4255262500 | Feb 29 12:50:57 PM PST 24 | Feb 29 12:51:39 PM PST 24 | 3215303176 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1733475183 | Feb 29 12:51:53 PM PST 24 | Feb 29 12:51:59 PM PST 24 | 133711324 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2404790420 | Feb 29 12:51:53 PM PST 24 | Feb 29 12:52:13 PM PST 24 | 4980451885 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2564710579 | Feb 29 12:52:16 PM PST 24 | Feb 29 12:52:19 PM PST 24 | 25047987 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3038473594 | Feb 29 12:49:46 PM PST 24 | Feb 29 12:50:21 PM PST 24 | 2634776875 ps | ||
| T198 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.275950176 | Feb 29 12:51:32 PM PST 24 | Feb 29 12:52:40 PM PST 24 | 25991999252 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.684045080 | Feb 29 12:51:37 PM PST 24 | Feb 29 12:51:50 PM PST 24 | 576220273 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1032110323 | Feb 29 12:49:52 PM PST 24 | Feb 29 12:50:03 PM PST 24 | 3205364289 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1789720783 | Feb 29 12:50:11 PM PST 24 | Feb 29 12:51:50 PM PST 24 | 2781982691 ps | ||
| T111 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3546580135 | Feb 29 12:52:14 PM PST 24 | Feb 29 12:57:25 PM PST 24 | 138135728908 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3797936805 | Feb 29 12:51:21 PM PST 24 | Feb 29 12:51:26 PM PST 24 | 536426735 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1059413877 | Feb 29 12:49:45 PM PST 24 | Feb 29 12:50:05 PM PST 24 | 4427305957 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1228168499 | Feb 29 12:51:05 PM PST 24 | Feb 29 12:52:44 PM PST 24 | 5769652822 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.4081339061 | Feb 29 12:52:27 PM PST 24 | Feb 29 12:52:29 PM PST 24 | 240887592 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.864726287 | Feb 29 12:49:47 PM PST 24 | Feb 29 12:49:48 PM PST 24 | 10475227 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/26.xbar_random.2817706655 | Feb 29 12:51:15 PM PST 24 | Feb 29 12:51:25 PM PST 24 | 58234155 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.631622897 | Feb 29 12:51:34 PM PST 24 | Feb 29 12:51:53 PM PST 24 | 1022717540 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3458342031 | Feb 29 12:51:21 PM PST 24 | Feb 29 12:51:30 PM PST 24 | 653065654 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.595951748 | Feb 29 12:51:02 PM PST 24 | Feb 29 12:51:08 PM PST 24 | 49777536 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1924527864 | Feb 29 12:50:12 PM PST 24 | Feb 29 12:50:23 PM PST 24 | 3119523516 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4088236205 | Feb 29 12:52:04 PM PST 24 | Feb 29 12:52:07 PM PST 24 | 158056104 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/34.xbar_random.988543532 | Feb 29 12:51:56 PM PST 24 | Feb 29 12:51:59 PM PST 24 | 29659385 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.262947697 | Feb 29 12:49:44 PM PST 24 | Feb 29 12:49:54 PM PST 24 | 93601399 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.650962190 | Feb 29 12:49:38 PM PST 24 | Feb 29 12:49:49 PM PST 24 | 867895659 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3894202933 | Feb 29 12:51:32 PM PST 24 | Feb 29 12:51:34 PM PST 24 | 157110693 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.99853557 | Feb 29 12:50:45 PM PST 24 | Feb 29 12:51:44 PM PST 24 | 10651179410 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.825281941 | Feb 29 12:52:24 PM PST 24 | Feb 29 12:52:29 PM PST 24 | 796814673 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/47.xbar_random.1089612519 | Feb 29 12:52:18 PM PST 24 | Feb 29 12:52:32 PM PST 24 | 1895764222 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/17.xbar_same_source.2954116512 | Feb 29 12:50:44 PM PST 24 | Feb 29 12:50:50 PM PST 24 | 499839275 ps | ||
| T116 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2219769066 | Feb 29 12:51:29 PM PST 24 | Feb 29 12:51:45 PM PST 24 | 1611977676 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2975219270 | Feb 29 12:50:51 PM PST 24 | Feb 29 12:51:00 PM PST 24 | 5241509158 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2390247743 | Feb 29 12:50:00 PM PST 24 | Feb 29 12:50:03 PM PST 24 | 10807053 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4280058388 | Feb 29 12:51:07 PM PST 24 | Feb 29 12:51:14 PM PST 24 | 1952540137 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3177044508 | Feb 29 12:50:45 PM PST 24 | Feb 29 12:50:48 PM PST 24 | 22095616 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3780884480 | Feb 29 12:49:35 PM PST 24 | Feb 29 12:49:41 PM PST 24 | 54514438 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3085888395 | Feb 29 12:51:12 PM PST 24 | Feb 29 12:51:40 PM PST 24 | 721072396 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/49.xbar_random.572570050 | Feb 29 12:52:26 PM PST 24 | Feb 29 12:52:37 PM PST 24 | 407209658 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/31.xbar_same_source.3661500637 | Feb 29 12:51:29 PM PST 24 | Feb 29 12:51:41 PM PST 24 | 5595165723 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1060060445 | Feb 29 12:50:31 PM PST 24 | Feb 29 12:50:41 PM PST 24 | 2128549466 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/23.xbar_random.3717921030 | Feb 29 12:51:14 PM PST 24 | Feb 29 12:51:16 PM PST 24 | 16587898 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/37.xbar_random.877655265 | Feb 29 12:51:44 PM PST 24 | Feb 29 12:51:47 PM PST 24 | 218354490 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.4222667089 | Feb 29 12:49:57 PM PST 24 | Feb 29 12:50:18 PM PST 24 | 1497189658 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1089827274 | Feb 29 12:51:51 PM PST 24 | Feb 29 12:52:06 PM PST 24 | 3673240014 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.481588968 | Feb 29 12:49:52 PM PST 24 | Feb 29 12:50:43 PM PST 24 | 12299387266 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/29.xbar_random.2140016855 | Feb 29 12:51:33 PM PST 24 | Feb 29 12:51:35 PM PST 24 | 289137387 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.564807450 | Feb 29 12:52:02 PM PST 24 | Feb 29 12:52:53 PM PST 24 | 508613555 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2560076917 | Feb 29 12:50:41 PM PST 24 | Feb 29 12:50:50 PM PST 24 | 2018324036 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.177945029 | Feb 29 12:51:27 PM PST 24 | Feb 29 12:51:37 PM PST 24 | 743496886 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.55479252 | Feb 29 12:51:11 PM PST 24 | Feb 29 12:51:27 PM PST 24 | 398970852 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1254208302 | Feb 29 12:51:45 PM PST 24 | Feb 29 12:51:51 PM PST 24 | 122982441 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2635801321 | Feb 29 12:52:17 PM PST 24 | Feb 29 12:52:34 PM PST 24 | 22068304 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.219458696 | Feb 29 12:51:57 PM PST 24 | Feb 29 12:52:06 PM PST 24 | 559537407 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1555568725 | Feb 29 12:51:05 PM PST 24 | Feb 29 12:52:58 PM PST 24 | 20639733460 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2748092172 | Feb 29 12:52:14 PM PST 24 | Feb 29 12:52:15 PM PST 24 | 8751351 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2546988133 | Feb 29 12:49:54 PM PST 24 | Feb 29 12:50:00 PM PST 24 | 61971492 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1152480557 | Feb 29 12:52:21 PM PST 24 | Feb 29 12:52:33 PM PST 24 | 3697226789 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1402086934 | Feb 29 12:51:04 PM PST 24 | Feb 29 12:51:06 PM PST 24 | 69953128 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3622173798 | Feb 29 12:50:29 PM PST 24 | Feb 29 12:50:35 PM PST 24 | 87136831 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1940042457 | Feb 29 12:50:31 PM PST 24 | Feb 29 12:51:21 PM PST 24 | 574522712 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/38.xbar_random.2751263543 | Feb 29 12:51:48 PM PST 24 | Feb 29 12:51:57 PM PST 24 | 104235698 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.228875901 | Feb 29 12:52:19 PM PST 24 | Feb 29 12:52:25 PM PST 24 | 764017979 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3989985828 | Feb 29 12:51:10 PM PST 24 | Feb 29 12:52:54 PM PST 24 | 21626548159 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.209653893 | Feb 29 12:51:34 PM PST 24 | Feb 29 12:51:41 PM PST 24 | 170071318 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1891795031 | Feb 29 12:49:58 PM PST 24 | Feb 29 12:51:30 PM PST 24 | 31163501227 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.877558192 | Feb 29 12:50:59 PM PST 24 | Feb 29 12:51:27 PM PST 24 | 298072783 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/16.xbar_random.1515795524 | Feb 29 12:50:43 PM PST 24 | Feb 29 12:50:57 PM PST 24 | 4494748028 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3941782639 | Feb 29 12:51:36 PM PST 24 | Feb 29 12:51:40 PM PST 24 | 103757121 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1239658625 | Feb 29 12:50:58 PM PST 24 | Feb 29 12:56:08 PM PST 24 | 58293218970 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1258265945 | Feb 29 12:51:58 PM PST 24 | Feb 29 12:52:04 PM PST 24 | 1749958494 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.4133060138 | Feb 29 12:50:35 PM PST 24 | Feb 29 12:50:53 PM PST 24 | 884975671 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3384803472 | Feb 29 12:50:23 PM PST 24 | Feb 29 12:50:25 PM PST 24 | 8807923 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2315600820 | Feb 29 12:50:59 PM PST 24 | Feb 29 12:51:43 PM PST 24 | 7620549388 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1508999659 | Feb 29 12:51:28 PM PST 24 | Feb 29 12:53:30 PM PST 24 | 19881173076 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3830225460 | Feb 29 12:51:53 PM PST 24 | Feb 29 12:51:55 PM PST 24 | 36008253 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3839226039 | Feb 29 12:51:06 PM PST 24 | Feb 29 12:51:24 PM PST 24 | 2025278417 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2511479359 | Feb 29 12:51:34 PM PST 24 | Feb 29 12:52:48 PM PST 24 | 417136022 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3318748638 | Feb 29 12:51:19 PM PST 24 | Feb 29 12:51:27 PM PST 24 | 4495908668 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1037076269 | Feb 29 12:51:46 PM PST 24 | Feb 29 12:52:12 PM PST 24 | 405326054 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2492736012 | Feb 29 12:51:44 PM PST 24 | Feb 29 12:51:48 PM PST 24 | 29408572 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1326172883 | Feb 29 12:49:36 PM PST 24 | Feb 29 12:49:47 PM PST 24 | 11540068436 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.827096738 | Feb 29 12:50:31 PM PST 24 | Feb 29 12:51:40 PM PST 24 | 11516400525 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/35.xbar_random.4265700331 | Feb 29 12:51:58 PM PST 24 | Feb 29 12:52:00 PM PST 24 | 18321407 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/42.xbar_random.2848311600 | Feb 29 12:52:03 PM PST 24 | Feb 29 12:52:16 PM PST 24 | 5847277886 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/36.xbar_random.1312520359 | Feb 29 12:51:50 PM PST 24 | Feb 29 12:51:53 PM PST 24 | 40763905 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1241247495 | Feb 29 12:51:06 PM PST 24 | Feb 29 12:51:15 PM PST 24 | 1090683807 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/4.xbar_same_source.3408482426 | Feb 29 12:49:42 PM PST 24 | Feb 29 12:49:48 PM PST 24 | 942060950 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3296047904 | Feb 29 12:50:14 PM PST 24 | Feb 29 12:55:14 PM PST 24 | 53284735633 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3378281985 | Feb 29 12:51:33 PM PST 24 | Feb 29 12:51:44 PM PST 24 | 3217525125 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.963448091 | Feb 29 12:50:10 PM PST 24 | Feb 29 12:50:12 PM PST 24 | 105591707 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1861381459 | Feb 29 12:50:45 PM PST 24 | Feb 29 12:51:40 PM PST 24 | 10494684852 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3568245465 | Feb 29 12:51:30 PM PST 24 | Feb 29 12:53:46 PM PST 24 | 11348666361 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1380775223 | Feb 29 12:49:40 PM PST 24 | Feb 29 12:49:50 PM PST 24 | 1850867225 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2316732106 | Feb 29 12:51:47 PM PST 24 | Feb 29 12:56:37 PM PST 24 | 76305679071 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1967026955 | Feb 29 12:52:05 PM PST 24 | Feb 29 12:52:42 PM PST 24 | 226019455 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.292153286 | Feb 29 12:49:23 PM PST 24 | Feb 29 12:49:29 PM PST 24 | 372614212 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1072669418 | Feb 29 12:51:25 PM PST 24 | Feb 29 12:52:17 PM PST 24 | 622629439 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1365780954 | Feb 29 12:51:04 PM PST 24 | Feb 29 12:51:06 PM PST 24 | 17437692 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1316837882 | Feb 29 12:52:09 PM PST 24 | Feb 29 12:52:14 PM PST 24 | 51238733 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/2.xbar_smoke.157419909 | Feb 29 12:49:26 PM PST 24 | Feb 29 12:49:28 PM PST 24 | 153223484 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/48.xbar_random.973438358 | Feb 29 12:52:25 PM PST 24 | Feb 29 12:52:34 PM PST 24 | 1491005005 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.548882894 | Feb 29 12:50:31 PM PST 24 | Feb 29 12:53:36 PM PST 24 | 31481709859 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3219678497 | Feb 29 12:49:55 PM PST 24 | Feb 29 12:49:57 PM PST 24 | 59097318 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4157099716 | Feb 29 12:50:17 PM PST 24 | Feb 29 12:51:46 PM PST 24 | 39251297485 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2864024127 | Feb 29 12:51:53 PM PST 24 | Feb 29 12:52:21 PM PST 24 | 2647417383 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.352981114 | Feb 29 12:52:18 PM PST 24 | Feb 29 12:53:36 PM PST 24 | 7972585135 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/4.xbar_random.3614261919 | Feb 29 12:49:51 PM PST 24 | Feb 29 12:49:55 PM PST 24 | 40870089 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3653320399 | Feb 29 12:50:33 PM PST 24 | Feb 29 12:50:38 PM PST 24 | 368853825 ps | ||
| T120 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.403632212 | Feb 29 12:51:05 PM PST 24 | Feb 29 12:57:02 PM PST 24 | 100326053652 ps | ||
| T142 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3906229914 | Feb 29 12:51:24 PM PST 24 | Feb 29 12:53:24 PM PST 24 | 3127290083 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1293502285 | Feb 29 12:51:28 PM PST 24 | Feb 29 12:52:24 PM PST 24 | 7450233008 ps | ||
| T112 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.628270554 | Feb 29 12:49:23 PM PST 24 | Feb 29 12:54:23 PM PST 24 | 59660172702 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/30.xbar_random.2151924174 | Feb 29 12:51:36 PM PST 24 | Feb 29 12:51:44 PM PST 24 | 921464089 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/22.xbar_same_source.165154571 | Feb 29 12:51:17 PM PST 24 | Feb 29 12:51:22 PM PST 24 | 945978954 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1858541737 | Feb 29 12:51:53 PM PST 24 | Feb 29 12:51:58 PM PST 24 | 265869920 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2920539455 | Feb 29 12:51:25 PM PST 24 | Feb 29 12:51:40 PM PST 24 | 803045068 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3614858135 | Feb 29 12:49:47 PM PST 24 | Feb 29 12:50:43 PM PST 24 | 9272762524 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4003633518 | Feb 29 12:52:11 PM PST 24 | Feb 29 12:52:12 PM PST 24 | 12323508 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3896990783 | Feb 29 12:52:21 PM PST 24 | Feb 29 12:52:23 PM PST 24 | 27359748 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3075445621 | Feb 29 12:50:40 PM PST 24 | Feb 29 12:52:54 PM PST 24 | 21733828863 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2243945106 | Feb 29 12:51:58 PM PST 24 | Feb 29 12:52:03 PM PST 24 | 104981949 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2660885580 | Feb 29 12:50:46 PM PST 24 | Feb 29 12:50:49 PM PST 24 | 191967511 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3741999107 | Feb 29 12:51:38 PM PST 24 | Feb 29 12:53:48 PM PST 24 | 56545170558 ps |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2896608334 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 32753767250 ps |
| CPU time | 142.09 seconds |
| Started | Feb 29 12:50:56 PM PST 24 |
| Finished | Feb 29 12:53:19 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-901dcc4a-27af-4c4a-acb7-ee9714f775b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896608334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2896608334 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2032625530 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 42887467883 ps |
| CPU time | 335.99 seconds |
| Started | Feb 29 12:50:09 PM PST 24 |
| Finished | Feb 29 12:55:46 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-1d106ab9-b405-484f-bcf1-a4bf696219c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2032625530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.2032625530 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2427975187 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 108156763805 ps |
| CPU time | 361.07 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:57:29 PM PST 24 |
| Peak memory | 204656 kb |
| Host | smart-1476152d-5b50-4b2d-9972-ffd280236275 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2427975187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2427975187 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3083219684 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 204149316342 ps |
| CPU time | 348.82 seconds |
| Started | Feb 29 12:52:20 PM PST 24 |
| Finished | Feb 29 12:58:09 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-9953d7d5-c53d-4834-8a76-547e42b3d2e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3083219684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.3083219684 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2635402506 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 148319246268 ps |
| CPU time | 299.67 seconds |
| Started | Feb 29 12:52:24 PM PST 24 |
| Finished | Feb 29 12:57:23 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-e82d3eb3-75c9-4cf4-a654-bf7f908cf9ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2635402506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2635402506 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.4253506883 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2276718802 ps |
| CPU time | 52.75 seconds |
| Started | Feb 29 12:50:29 PM PST 24 |
| Finished | Feb 29 12:51:22 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-e6e42c9a-774f-4b8b-bc6f-5faa63468d38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4253506883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.4253506883 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2961016465 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1589382975 ps |
| CPU time | 21.98 seconds |
| Started | Feb 29 12:51:01 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f195b182-bb0b-49cc-a6fe-ffbbe4e25297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2961016465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2961016465 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.2021245719 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 43022563 ps |
| CPU time | 1.91 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-277b1508-1d2b-4641-8803-0bc1a3fda821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2021245719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2021245719 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3063875561 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 38751770107 ps |
| CPU time | 206.99 seconds |
| Started | Feb 29 12:51:22 PM PST 24 |
| Finished | Feb 29 12:54:50 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-d050ed0c-385f-4bf6-86b3-18b24d4bb098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3063875561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3063875561 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3925761992 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3298243150 ps |
| CPU time | 59.06 seconds |
| Started | Feb 29 12:50:37 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 204180 kb |
| Host | smart-9e11ea36-196a-4f55-a0f7-2fac131a667b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3925761992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3925761992 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2146338639 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 53072071911 ps |
| CPU time | 308.95 seconds |
| Started | Feb 29 12:52:29 PM PST 24 |
| Finished | Feb 29 12:57:38 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-5635a072-1507-4823-b4c8-85703caead21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2146338639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.2146338639 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.807360042 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 175486153 ps |
| CPU time | 30.07 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:50:15 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-5eb16b94-c76c-4b95-8be6-06695b3dd904 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=807360042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_ reset.807360042 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3453836682 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3416955974 ps |
| CPU time | 89.02 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:53:34 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-2f804693-ea69-4026-bdbe-828b68cc8393 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3453836682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3453836682 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.269397611 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 35825453308 ps |
| CPU time | 137.73 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:54:06 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-0091f36d-0e69-43b4-9ce1-d202f801bf7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=269397611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.269397611 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.111193967 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 62671858 ps |
| CPU time | 14.75 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:50:00 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-f4c279e6-bb2f-41f8-97df-19813365156b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=111193967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.111193967 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3437234843 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 470576129 ps |
| CPU time | 85.49 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:53:34 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-129f4201-1306-4f1e-a52f-a19257ab61cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437234843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3437234843 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.474956932 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1166355391 ps |
| CPU time | 120.27 seconds |
| Started | Feb 29 12:50:54 PM PST 24 |
| Finished | Feb 29 12:52:55 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-bcbf6afd-e611-46ca-b6fc-1fcc7451f123 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=474956932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.474956932 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3799144159 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 56599395326 ps |
| CPU time | 325.68 seconds |
| Started | Feb 29 12:49:39 PM PST 24 |
| Finished | Feb 29 12:55:05 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-54627f80-61c8-4514-9cf4-b8e9e3043019 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3799144159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3799144159 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.40861093 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 8362873767 ps |
| CPU time | 101.41 seconds |
| Started | Feb 29 12:50:16 PM PST 24 |
| Finished | Feb 29 12:51:58 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-17db52d4-d0fa-4c3b-94b8-d1b32331d21c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=40861093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_ reset.40861093 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2350863426 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 130831896965 ps |
| CPU time | 397.54 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:58:11 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-4dbdf5e7-6b9c-45fb-ba7a-431eb3c3a598 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2350863426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2350863426 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2242372257 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6194375638 ps |
| CPU time | 36.54 seconds |
| Started | Feb 29 12:50:10 PM PST 24 |
| Finished | Feb 29 12:50:48 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-61a1cea5-fbb7-44fe-9918-76fe4b9004ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2242372257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.2242372257 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3617075965 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 5273957090 ps |
| CPU time | 104.18 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:53:09 PM PST 24 |
| Peak memory | 206532 kb |
| Host | smart-1e15c16d-2256-48d8-aacb-5f3c0d9a947e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3617075965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3617075965 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.600857068 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4542002166 ps |
| CPU time | 162.62 seconds |
| Started | Feb 29 12:49:25 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 208700 kb |
| Host | smart-1b99eddd-6c3f-4c78-a933-3b13987c57d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=600857068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.600857068 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2085731329 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 54018790661 ps |
| CPU time | 184.04 seconds |
| Started | Feb 29 12:49:27 PM PST 24 |
| Finished | Feb 29 12:52:31 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-dfb2aae1-8175-4229-a6e1-d3ee4606982e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2085731329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2085731329 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1393264046 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 656477606 ps |
| CPU time | 2.69 seconds |
| Started | Feb 29 12:50:48 PM PST 24 |
| Finished | Feb 29 12:50:51 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-3c639ec6-0c2a-4b38-ba1b-f2b45370fb45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393264046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1393264046 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3547825554 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 48585302 ps |
| CPU time | 3.84 seconds |
| Started | Feb 29 12:49:23 PM PST 24 |
| Finished | Feb 29 12:49:27 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-30cb1a1a-63bb-4598-9140-42ff401badce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3547825554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3547825554 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.628270554 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 59660172702 ps |
| CPU time | 299.75 seconds |
| Started | Feb 29 12:49:23 PM PST 24 |
| Finished | Feb 29 12:54:23 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-66bffa29-07bb-41f9-baa5-e95cdc22f5da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=628270554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.628270554 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.472084362 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1087618364 ps |
| CPU time | 4.22 seconds |
| Started | Feb 29 12:49:16 PM PST 24 |
| Finished | Feb 29 12:49:20 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-f6cf3bdd-ac87-4af7-bd9d-74b47792e3d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472084362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.472084362 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.3324227731 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 109925395 ps |
| CPU time | 4.49 seconds |
| Started | Feb 29 12:49:20 PM PST 24 |
| Finished | Feb 29 12:49:25 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-474e2fdf-de65-4aac-aeeb-6344faef58b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3324227731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3324227731 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.2503948351 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 258968037 ps |
| CPU time | 3.87 seconds |
| Started | Feb 29 12:49:05 PM PST 24 |
| Finished | Feb 29 12:49:09 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-15324f74-94b6-4ac8-9bf3-47605681f712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2503948351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2503948351 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.552724673 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 29424270080 ps |
| CPU time | 44.85 seconds |
| Started | Feb 29 12:49:17 PM PST 24 |
| Finished | Feb 29 12:50:02 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-256666ba-1fd6-4838-9429-2073c3973b38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=552724673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.552724673 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2117336764 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 21987294547 ps |
| CPU time | 87.21 seconds |
| Started | Feb 29 12:49:20 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-79999af4-0844-4db4-aa2c-30119e364a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2117336764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2117336764 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.685094334 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 46535227 ps |
| CPU time | 2.88 seconds |
| Started | Feb 29 12:48:59 PM PST 24 |
| Finished | Feb 29 12:49:02 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-92b8cfdf-37d2-48b2-8405-09bce1649fb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685094334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.685094334 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.4017009771 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 948660505 ps |
| CPU time | 6.59 seconds |
| Started | Feb 29 12:49:15 PM PST 24 |
| Finished | Feb 29 12:49:21 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-ec748823-8114-44c1-810d-54c55c9d9f14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4017009771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4017009771 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3470477696 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 80103895 ps |
| CPU time | 1.56 seconds |
| Started | Feb 29 12:49:19 PM PST 24 |
| Finished | Feb 29 12:49:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-ea5c462b-436f-4b67-823f-072933b5e8d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3470477696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3470477696 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2644900420 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9345776207 ps |
| CPU time | 7.79 seconds |
| Started | Feb 29 12:49:27 PM PST 24 |
| Finished | Feb 29 12:49:35 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-b014c495-36c2-43a7-a349-c0c752fa6c3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644900420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2644900420 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2834196904 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5979495180 ps |
| CPU time | 9.33 seconds |
| Started | Feb 29 12:49:17 PM PST 24 |
| Finished | Feb 29 12:49:26 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-25fa3476-009a-4c31-9e98-c75a4c3704fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2834196904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2834196904 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3912797677 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 20235254 ps |
| CPU time | 1.25 seconds |
| Started | Feb 29 12:49:30 PM PST 24 |
| Finished | Feb 29 12:49:32 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-69136cb4-9ee6-4cb3-b1fb-04e5c375d85e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912797677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3912797677 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2093359895 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 327867486 ps |
| CPU time | 17.51 seconds |
| Started | Feb 29 12:49:17 PM PST 24 |
| Finished | Feb 29 12:49:35 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-c09ed252-dcb3-4b30-b876-a5c0ac526654 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093359895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2093359895 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3752512505 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 4623054785 ps |
| CPU time | 53.06 seconds |
| Started | Feb 29 12:49:21 PM PST 24 |
| Finished | Feb 29 12:50:14 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-4c2f0ab7-80ad-4a35-b7f9-f9d53ab36095 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752512505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3752512505 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3880728441 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 341614483 ps |
| CPU time | 51.67 seconds |
| Started | Feb 29 12:49:16 PM PST 24 |
| Finished | Feb 29 12:50:08 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-65ffbd58-9944-4cf5-9e3b-786c2395413a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880728441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3880728441 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1705524452 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 749054404 ps |
| CPU time | 54.22 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:50:30 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-363f6787-0905-4f47-bdb8-a7b329839ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1705524452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.1705524452 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3652225973 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 59753724 ps |
| CPU time | 6.3 seconds |
| Started | Feb 29 12:49:22 PM PST 24 |
| Finished | Feb 29 12:49:28 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-fc4a4bd4-c465-4de2-9fff-f46e50bd400e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652225973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3652225973 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1227338706 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 577207883 ps |
| CPU time | 5.62 seconds |
| Started | Feb 29 12:49:32 PM PST 24 |
| Finished | Feb 29 12:49:39 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-956b4d20-cc14-4f16-a121-e23c0c3d6250 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1227338706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1227338706 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1782548537 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 65690533739 ps |
| CPU time | 312.82 seconds |
| Started | Feb 29 12:49:26 PM PST 24 |
| Finished | Feb 29 12:54:39 PM PST 24 |
| Peak memory | 203960 kb |
| Host | smart-ce27b0b1-fe6e-445e-a494-f535e88779f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1782548537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1782548537 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.292153286 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 372614212 ps |
| CPU time | 5.81 seconds |
| Started | Feb 29 12:49:23 PM PST 24 |
| Finished | Feb 29 12:49:29 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-1ba0e413-e14a-4c20-a0f5-82bc8276c93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292153286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.292153286 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.332013515 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 216133560 ps |
| CPU time | 4.96 seconds |
| Started | Feb 29 12:49:20 PM PST 24 |
| Finished | Feb 29 12:49:26 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-5a273e14-52cd-4974-bb58-afc3364341cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332013515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.332013515 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.1926170772 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1149335109 ps |
| CPU time | 15.22 seconds |
| Started | Feb 29 12:49:38 PM PST 24 |
| Finished | Feb 29 12:49:53 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-a074cbf9-a439-43bc-a18c-12faabc18e99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926170772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1926170772 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1163151027 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 238056389884 ps |
| CPU time | 126.57 seconds |
| Started | Feb 29 12:49:41 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-0d9f038a-bef7-4954-866b-85d8f9b8b8ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163151027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1163151027 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1681620263 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 33255859 ps |
| CPU time | 4.66 seconds |
| Started | Feb 29 12:49:14 PM PST 24 |
| Finished | Feb 29 12:49:19 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-6f2e9dde-3c41-4cce-9dea-d3fd383468ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681620263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1681620263 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.409888637 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 27185514 ps |
| CPU time | 3.04 seconds |
| Started | Feb 29 12:49:29 PM PST 24 |
| Finished | Feb 29 12:49:32 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-df0d0a72-e785-444e-850e-c7649c41641a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409888637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.409888637 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1866022166 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 110971975 ps |
| CPU time | 1.3 seconds |
| Started | Feb 29 12:49:28 PM PST 24 |
| Finished | Feb 29 12:49:30 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-52371a35-6dc1-4829-b384-7d9e6822e75d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1866022166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1866022166 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2824132829 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2152669164 ps |
| CPU time | 8.59 seconds |
| Started | Feb 29 12:49:26 PM PST 24 |
| Finished | Feb 29 12:49:34 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-20197c2e-7d11-408e-b92f-ccbfbafc2deb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824132829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2824132829 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.925938729 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1816221063 ps |
| CPU time | 12.22 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:49:47 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-9a951682-251d-43d9-ba37-f271ba9c1e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=925938729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.925938729 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2783183817 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 8308132 ps |
| CPU time | 1.05 seconds |
| Started | Feb 29 12:49:30 PM PST 24 |
| Finished | Feb 29 12:49:31 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-04092fe3-d9a5-4360-a08d-0c86471d167d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783183817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2783183817 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3908855539 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2485927474 ps |
| CPU time | 35.34 seconds |
| Started | Feb 29 12:49:39 PM PST 24 |
| Finished | Feb 29 12:50:15 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-77960f2e-ca6b-48db-8b3e-e84f46d5f95a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3908855539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3908855539 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.334574532 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 290905011 ps |
| CPU time | 12.37 seconds |
| Started | Feb 29 12:49:26 PM PST 24 |
| Finished | Feb 29 12:49:39 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-e68767a2-0e14-4ed0-8a6a-198e832e9510 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=334574532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.334574532 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2635962339 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1316832639 ps |
| CPU time | 66.77 seconds |
| Started | Feb 29 12:49:34 PM PST 24 |
| Finished | Feb 29 12:50:40 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-72b384d8-3cd0-4283-83c3-abe51d21f0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2635962339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.2635962339 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.312363673 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 117230008 ps |
| CPU time | 3.09 seconds |
| Started | Feb 29 12:49:36 PM PST 24 |
| Finished | Feb 29 12:49:39 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-635ddd33-bfbb-40b8-b80b-fb7a96f6c953 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=312363673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.312363673 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.4083128062 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 754253644 ps |
| CPU time | 14.41 seconds |
| Started | Feb 29 12:50:25 PM PST 24 |
| Finished | Feb 29 12:50:39 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-be66f343-2d6b-4c7f-aacb-8fc0fe930c2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4083128062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4083128062 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2651670405 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 114361329300 ps |
| CPU time | 131.6 seconds |
| Started | Feb 29 12:50:12 PM PST 24 |
| Finished | Feb 29 12:52:23 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-4fa4a3b0-73b2-46bc-b963-7028412db477 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2651670405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2651670405 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2145178671 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 64776681 ps |
| CPU time | 3.79 seconds |
| Started | Feb 29 12:50:29 PM PST 24 |
| Finished | Feb 29 12:50:33 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-da9febe7-4b0d-4a15-af0c-a9251647f283 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2145178671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2145178671 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1060060445 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2128549466 ps |
| CPU time | 9.32 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:41 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-a500e670-e92f-4c57-9687-2520c6ad2db3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1060060445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1060060445 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.3725368557 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 359972207 ps |
| CPU time | 4.77 seconds |
| Started | Feb 29 12:50:18 PM PST 24 |
| Finished | Feb 29 12:50:24 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-d866b858-94ce-47ec-b5c0-4177cd338847 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3725368557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3725368557 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3268331625 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 7995906030 ps |
| CPU time | 37.59 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:50:51 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-e3234d23-7b89-40de-bf00-51a4001591ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268331625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3268331625 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3730590871 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 17888495611 ps |
| CPU time | 117.14 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:52:10 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-0aa944ea-3081-4178-9170-d4259601c3f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3730590871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3730590871 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.570461317 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 42144565 ps |
| CPU time | 4.95 seconds |
| Started | Feb 29 12:50:27 PM PST 24 |
| Finished | Feb 29 12:50:32 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-b2c6937a-8a03-4e30-a5a0-36abd8a8bbf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570461317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.570461317 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3612935957 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 176705809 ps |
| CPU time | 5.47 seconds |
| Started | Feb 29 12:50:22 PM PST 24 |
| Finished | Feb 29 12:50:28 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-1110809f-d7ac-4de5-a5ed-c614c242fcc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3612935957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3612935957 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.3514926379 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 45409556 ps |
| CPU time | 1.36 seconds |
| Started | Feb 29 12:50:12 PM PST 24 |
| Finished | Feb 29 12:50:14 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-4aac4d04-89e8-4ff1-86ce-2b2ee84c8919 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3514926379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3514926379 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1924527864 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3119523516 ps |
| CPU time | 10.13 seconds |
| Started | Feb 29 12:50:12 PM PST 24 |
| Finished | Feb 29 12:50:23 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-36627a00-2e46-44bf-b477-0b3532dd5920 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924527864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1924527864 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3122093678 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1362368526 ps |
| CPU time | 7.88 seconds |
| Started | Feb 29 12:50:24 PM PST 24 |
| Finished | Feb 29 12:50:32 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-e2abec3e-5f22-471d-a02e-92d6142da6f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3122093678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3122093678 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3384803472 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 8807923 ps |
| CPU time | 1.26 seconds |
| Started | Feb 29 12:50:23 PM PST 24 |
| Finished | Feb 29 12:50:25 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-13f13eb9-df91-437e-ac3a-438a4a54c63e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384803472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3384803472 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.4026967413 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 7327662316 ps |
| CPU time | 134.43 seconds |
| Started | Feb 29 12:50:27 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 207176 kb |
| Host | smart-ff64f57e-2bfa-4130-883c-dcb603022184 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4026967413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4026967413 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.112566785 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 916339214 ps |
| CPU time | 32.03 seconds |
| Started | Feb 29 12:50:21 PM PST 24 |
| Finished | Feb 29 12:50:53 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-417dd361-60fc-48c4-96a0-e53a7737ef7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=112566785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.112566785 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3657403962 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 211770491 ps |
| CPU time | 51.01 seconds |
| Started | Feb 29 12:50:24 PM PST 24 |
| Finished | Feb 29 12:51:15 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-3a101264-54ca-41d0-9269-237164ec7774 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3657403962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3657403962 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1789720783 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2781982691 ps |
| CPU time | 98.72 seconds |
| Started | Feb 29 12:50:11 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 207612 kb |
| Host | smart-ab41af4c-2855-4446-84e4-c2b6552aaa5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789720783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1789720783 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2180016992 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 877219552 ps |
| CPU time | 9.94 seconds |
| Started | Feb 29 12:50:14 PM PST 24 |
| Finished | Feb 29 12:50:24 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-c17734b1-3094-41c3-9d76-207d43686796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2180016992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2180016992 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1458848537 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 62684521 ps |
| CPU time | 3.05 seconds |
| Started | Feb 29 12:50:20 PM PST 24 |
| Finished | Feb 29 12:50:23 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-c55f0ccf-7d5a-4620-bfa6-10f9190b34be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1458848537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1458848537 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2613633170 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 374022483 ps |
| CPU time | 5.86 seconds |
| Started | Feb 29 12:50:29 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b5a5c930-20f8-45ad-9013-c20c4b34d1c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2613633170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2613633170 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.520855974 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 176681138 ps |
| CPU time | 2.39 seconds |
| Started | Feb 29 12:50:20 PM PST 24 |
| Finished | Feb 29 12:50:23 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-fbeae7a2-88f4-4a67-b3d7-c23ffcbf934c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=520855974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.520855974 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.3293514260 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1160565579 ps |
| CPU time | 8.64 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:16 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-f846d636-9264-408f-be6b-163b48812b8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3293514260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3293514260 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2318820028 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 58360142705 ps |
| CPU time | 86.14 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-801e15e5-52d9-48a4-9ae8-91fe03f6588f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318820028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2318820028 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1793364210 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 46845911533 ps |
| CPU time | 106.06 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:52:18 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-ce8c653b-048a-43a9-8b5f-49278f1dbe22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1793364210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1793364210 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.390890821 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 113835915 ps |
| CPU time | 8.29 seconds |
| Started | Feb 29 12:50:09 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-6fabb7b2-7c2d-4b7f-93b0-857b55457488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390890821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.390890821 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.1948378960 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 56057892 ps |
| CPU time | 5.19 seconds |
| Started | Feb 29 12:50:07 PM PST 24 |
| Finished | Feb 29 12:50:12 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-5592ad60-46be-4c68-945e-7dda86de178f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1948378960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1948378960 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2390247743 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 10807053 ps |
| CPU time | 1.12 seconds |
| Started | Feb 29 12:50:00 PM PST 24 |
| Finished | Feb 29 12:50:03 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-e0ce24c9-c76c-42cf-b931-85ac3cce3cb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390247743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2390247743 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3918704096 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 8384551730 ps |
| CPU time | 7.81 seconds |
| Started | Feb 29 12:50:27 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-eebf4acd-1feb-41be-b1b9-21d0613e527f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918704096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3918704096 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.614636724 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 867239101 ps |
| CPU time | 5.65 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:50:19 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-dbb04944-4f7a-4100-8417-d34797e03d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=614636724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.614636724 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2473845393 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 11356399 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:50:15 PM PST 24 |
| Finished | Feb 29 12:50:16 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-fe65989e-9a4c-41ad-9466-6200d3be86b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473845393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2473845393 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3063623229 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 8859138312 ps |
| CPU time | 95.36 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-e2e74242-112c-4eeb-91de-6a81e2a8ce31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3063623229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3063623229 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2955877191 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 5238655664 ps |
| CPU time | 74.6 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-c1d5536b-4d1e-4d60-bba0-c21b287a2faa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955877191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2955877191 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2824726317 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 114442531 ps |
| CPU time | 13.5 seconds |
| Started | Feb 29 12:50:19 PM PST 24 |
| Finished | Feb 29 12:50:33 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-a1c5b70e-5371-4d4f-95c6-780135d907c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2824726317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2824726317 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3952912216 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 748211805 ps |
| CPU time | 4.14 seconds |
| Started | Feb 29 12:50:24 PM PST 24 |
| Finished | Feb 29 12:50:29 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-71efa110-8f36-4f17-9519-6c7a7e09502b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3952912216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3952912216 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1293775593 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 61562047 ps |
| CPU time | 9.8 seconds |
| Started | Feb 29 12:50:22 PM PST 24 |
| Finished | Feb 29 12:50:32 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-8d5ea295-2b4d-45b1-8fb6-fd7e0d689c64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1293775593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1293775593 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.428342794 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 48706230339 ps |
| CPU time | 337.62 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:56:10 PM PST 24 |
| Peak memory | 204008 kb |
| Host | smart-1242bdbf-c2ae-4dd2-873b-70882cee296a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=428342794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo w_rsp.428342794 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3485713756 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 46776329 ps |
| CPU time | 4.47 seconds |
| Started | Feb 29 12:50:26 PM PST 24 |
| Finished | Feb 29 12:50:30 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-491af535-bdc1-420a-8eb9-20b1f6f54057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3485713756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3485713756 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3820235034 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 60448595 ps |
| CPU time | 2.87 seconds |
| Started | Feb 29 12:50:39 PM PST 24 |
| Finished | Feb 29 12:50:42 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-52c1df22-be4b-4df7-ad36-28f1030fda19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3820235034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3820235034 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.402615965 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 868126420 ps |
| CPU time | 7.23 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:50:46 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-7bc94e26-0e94-49ed-95a3-7f7b1b2006fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=402615965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.402615965 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1565341911 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 16810697829 ps |
| CPU time | 51.88 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:51:28 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-c889dfe6-1498-41e3-8863-69fd849a9584 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565341911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1565341911 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.210337597 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 30739461085 ps |
| CPU time | 92.2 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-acdf93e7-e9cb-49b3-99f9-ebb23e4294c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=210337597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.210337597 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2021453654 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 106114131 ps |
| CPU time | 6.91 seconds |
| Started | Feb 29 12:50:34 PM PST 24 |
| Finished | Feb 29 12:50:41 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-3c151787-6d8c-4b1d-8721-40c9e160e7b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021453654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2021453654 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.3628449665 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 388850486 ps |
| CPU time | 5.26 seconds |
| Started | Feb 29 12:50:40 PM PST 24 |
| Finished | Feb 29 12:50:46 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-97eec080-bef2-468c-8984-8575a24f0e54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628449665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3628449665 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1210532014 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 87059078 ps |
| CPU time | 1.42 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:50:37 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-9e7cabfc-2629-41df-8959-f1913dfae96a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1210532014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1210532014 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3391621136 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5444322535 ps |
| CPU time | 11.5 seconds |
| Started | Feb 29 12:50:47 PM PST 24 |
| Finished | Feb 29 12:50:58 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-65d3bb94-52ba-4654-b2be-c49c8f752280 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391621136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3391621136 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1522213502 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 958583417 ps |
| CPU time | 6.72 seconds |
| Started | Feb 29 12:50:28 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-19e77fbe-1b48-4e9a-93f4-b304efdf5b47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1522213502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1522213502 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2010090238 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 39110013 ps |
| CPU time | 1.29 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:50:33 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-16cb3391-3718-4afb-b8ff-f56170405645 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010090238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2010090238 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1940042457 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 574522712 ps |
| CPU time | 49.8 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 205128 kb |
| Host | smart-e2da5839-9894-4e50-818d-1f0b786cd669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940042457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1940042457 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.292891452 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 333401673 ps |
| CPU time | 26.01 seconds |
| Started | Feb 29 12:50:45 PM PST 24 |
| Finished | Feb 29 12:51:11 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-8a63ef5d-c103-4378-bdad-0b45cd35398a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292891452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.292891452 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1302454422 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 258840950 ps |
| CPU time | 24.94 seconds |
| Started | Feb 29 12:50:25 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-2a2018c1-9541-43f0-b32a-7700a0c97406 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302454422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1302454422 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1837750299 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 873400834 ps |
| CPU time | 5.25 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:42 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-d5e1f2a0-69ce-4c2d-8884-665f41fee6c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1837750299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1837750299 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1687879429 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 47307271 ps |
| CPU time | 7.91 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:50:42 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-057af57a-cb5d-4364-993b-b1849932af4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1687879429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1687879429 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2794354026 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 43586656213 ps |
| CPU time | 185.02 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:53:40 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-92a7be8f-84e9-46a5-9bbc-c00bb7c28e7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2794354026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2794354026 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.398082171 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 383449667 ps |
| CPU time | 4.4 seconds |
| Started | Feb 29 12:50:30 PM PST 24 |
| Finished | Feb 29 12:50:34 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-7479a8e1-0551-40aa-9ce4-59bfbcef6d0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398082171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.398082171 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3008024952 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 7788761 ps |
| CPU time | 1 seconds |
| Started | Feb 29 12:50:45 PM PST 24 |
| Finished | Feb 29 12:50:51 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-e209575d-804b-4fe7-a010-0fe42ac97021 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008024952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3008024952 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.2260486774 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1132072385 ps |
| CPU time | 10.93 seconds |
| Started | Feb 29 12:50:48 PM PST 24 |
| Finished | Feb 29 12:50:59 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-b7d3dedc-77ad-4179-b548-46d4d59869f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2260486774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2260486774 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3852145077 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4823801945 ps |
| CPU time | 24.1 seconds |
| Started | Feb 29 12:50:47 PM PST 24 |
| Finished | Feb 29 12:51:11 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-539c7f16-b7af-4093-9d61-6dde0f1e8da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852145077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3852145077 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4282574418 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 20004402952 ps |
| CPU time | 51.19 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-3f064044-0a60-49c4-954f-bb8c1f19344d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4282574418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4282574418 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3023976157 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 75891795 ps |
| CPU time | 7.32 seconds |
| Started | Feb 29 12:50:41 PM PST 24 |
| Finished | Feb 29 12:50:49 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-3d372fcf-a916-4c6a-bdc8-4bfe31d88a87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023976157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3023976157 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.3146282138 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3909802871 ps |
| CPU time | 12.78 seconds |
| Started | Feb 29 12:50:41 PM PST 24 |
| Finished | Feb 29 12:50:54 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-742c05d0-83b1-4315-a4b1-eaf4f1dcacc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3146282138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3146282138 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1162483581 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 18505551 ps |
| CPU time | 1.14 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:38 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-7967f53e-c067-4c8a-aaec-28a20ff518ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1162483581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1162483581 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3896381050 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 8797160578 ps |
| CPU time | 9.31 seconds |
| Started | Feb 29 12:50:24 PM PST 24 |
| Finished | Feb 29 12:50:33 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-1df37ef1-aec0-4911-9a7d-d2f2499d225f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896381050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3896381050 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.64582934 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 6293309175 ps |
| CPU time | 6.46 seconds |
| Started | Feb 29 12:50:37 PM PST 24 |
| Finished | Feb 29 12:50:44 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-bfce11b5-5931-480b-a4c1-57c8d2e32a75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=64582934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.64582934 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2319705622 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 37860716 ps |
| CPU time | 1.19 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:33 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-5ec18a4f-e016-48ed-8be9-ad44d6d9efbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319705622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2319705622 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.797269540 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1061385224 ps |
| CPU time | 21.17 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:53 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-06c3f84f-a2fb-4a25-8ad3-0077e54106bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797269540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.797269540 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.827096738 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 11516400525 ps |
| CPU time | 68.81 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-bc9fa63f-893d-4aa3-937c-2d225b4b7b6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827096738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.827096738 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1508996544 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 179862371 ps |
| CPU time | 19.84 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:56 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-fab7f8c8-e812-4807-8f95-aee7543d654a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508996544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1508996544 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.917096920 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1848496815 ps |
| CPU time | 68.65 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-e10f8fcc-432a-4407-abc6-d0499956f34b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=917096920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.917096920 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.4251197790 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 14679298 ps |
| CPU time | 1.63 seconds |
| Started | Feb 29 12:50:25 PM PST 24 |
| Finished | Feb 29 12:50:27 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-48bd4afe-1089-4a88-99d0-ea9fbe7ae9fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251197790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4251197790 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3622173798 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 87136831 ps |
| CPU time | 6.17 seconds |
| Started | Feb 29 12:50:29 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-914d7cd1-8e15-4d88-bdf9-fe8e85f7d89e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3622173798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3622173798 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.548882894 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 31481709859 ps |
| CPU time | 185.28 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:53:36 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-7c5c897b-8d85-4588-babf-86faba023523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=548882894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slo w_rsp.548882894 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3653320399 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 368853825 ps |
| CPU time | 5.36 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:50:38 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-c5560b86-c08c-4af3-b6af-610be77f9c53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653320399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3653320399 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3666447714 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 325475440 ps |
| CPU time | 5.01 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:50:40 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-465bcb64-52cb-4e57-9191-a66f6d1df014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3666447714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3666447714 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1849334368 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3482835920 ps |
| CPU time | 12.67 seconds |
| Started | Feb 29 12:50:25 PM PST 24 |
| Finished | Feb 29 12:50:37 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-f19f5d74-d549-43f8-9c08-2b56c970bc2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849334368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1849334368 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1433270777 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5576272305 ps |
| CPU time | 18.88 seconds |
| Started | Feb 29 12:50:29 PM PST 24 |
| Finished | Feb 29 12:50:48 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-f378cb3c-73e7-433c-8897-65fedf75ab2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433270777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1433270777 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1562227947 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14853180496 ps |
| CPU time | 27.27 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:51:04 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f6eea855-1988-48c4-8fff-0188c262db22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1562227947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1562227947 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1365780954 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 17437692 ps |
| CPU time | 1.39 seconds |
| Started | Feb 29 12:51:04 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-e53de34a-54c9-426f-a49e-e8a88c038a6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365780954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1365780954 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.621936085 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 677957323 ps |
| CPU time | 7.16 seconds |
| Started | Feb 29 12:50:25 PM PST 24 |
| Finished | Feb 29 12:50:44 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-0fe13f50-75d5-41c7-be67-fa8e59f5dc0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=621936085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.621936085 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2785231303 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 95025605 ps |
| CPU time | 1.58 seconds |
| Started | Feb 29 12:50:30 PM PST 24 |
| Finished | Feb 29 12:50:32 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-31951ffa-5ca2-456e-8b46-4e1a70236fa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2785231303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2785231303 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.214605148 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2683244992 ps |
| CPU time | 6.54 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:37 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-73a68adb-b3a1-4d42-8f49-158f66af6033 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=214605148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.214605148 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2371449445 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1568404201 ps |
| CPU time | 6.12 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:50:38 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-1c374a0e-c5bc-407c-8b75-0b3a0bb82681 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2371449445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2371449445 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1390296714 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 31815914 ps |
| CPU time | 1.13 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-c75f28f6-dabb-4bbf-bf95-358db7d68f04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390296714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1390296714 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2955316011 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 713401083 ps |
| CPU time | 12.33 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:43 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-3a1b2560-d3f3-4bc4-8d43-d62ea80f8812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955316011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2955316011 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.4133060138 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 884975671 ps |
| CPU time | 17.21 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:50:53 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-552c448a-7f86-44eb-bf8f-b2b87ed0c836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4133060138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4133060138 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3352561045 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1194584953 ps |
| CPU time | 172.63 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:53:28 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-43ff748e-0905-4fd7-82db-3eb62352962d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3352561045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3352561045 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2886135049 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3199667460 ps |
| CPU time | 41.64 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:51:12 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-d7a583e1-e30c-427d-994e-3118510654b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2886135049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2886135049 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2374697805 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2637968803 ps |
| CPU time | 10.42 seconds |
| Started | Feb 29 12:50:34 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-7df97075-3edb-4b66-862f-45dc45c092eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2374697805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2374697805 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2018709057 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 57600217 ps |
| CPU time | 11.6 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:50:46 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-eba0b268-044e-4efb-8cd2-028d4bf4eb0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2018709057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2018709057 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1235984242 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 64043617631 ps |
| CPU time | 324.29 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:55:58 PM PST 24 |
| Peak memory | 205016 kb |
| Host | smart-1e04555c-83fd-4309-bc84-d1b2b9e8d22f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1235984242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1235984242 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2839548458 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 704105224 ps |
| CPU time | 9.84 seconds |
| Started | Feb 29 12:50:31 PM PST 24 |
| Finished | Feb 29 12:50:41 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-ff3ee1bd-ba98-444f-821c-82a68e3d24a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2839548458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2839548458 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.128757859 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 102735410 ps |
| CPU time | 7.13 seconds |
| Started | Feb 29 12:50:19 PM PST 24 |
| Finished | Feb 29 12:50:26 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-6635db4c-1f49-41ed-ba38-e87b87217aa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128757859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.128757859 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.1390888535 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 118809699 ps |
| CPU time | 1.48 seconds |
| Started | Feb 29 12:50:41 PM PST 24 |
| Finished | Feb 29 12:50:43 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-0657e215-4d45-4c85-9060-f9fb1a9f6ff1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1390888535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1390888535 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.4269947331 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 20202187566 ps |
| CPU time | 81.85 seconds |
| Started | Feb 29 12:50:34 PM PST 24 |
| Finished | Feb 29 12:51:56 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-17db28fa-6963-43a9-8257-e20580a2f2ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269947331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4269947331 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1155176129 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 25485015662 ps |
| CPU time | 150.15 seconds |
| Started | Feb 29 12:50:34 PM PST 24 |
| Finished | Feb 29 12:53:04 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-2964b372-933a-40ab-af28-23a7afbaa807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1155176129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1155176129 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2426609903 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 113181697 ps |
| CPU time | 3.89 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:40 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-4ff41d62-df5a-45f9-b433-cfaf90cb60f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426609903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2426609903 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3524873232 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 135724443 ps |
| CPU time | 2.61 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-732fa7a5-d361-4a3b-978c-60dd4b740b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524873232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3524873232 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.779590782 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 49874362 ps |
| CPU time | 1.6 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:50:34 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-4327aa39-5203-4510-8985-e9ce553686ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=779590782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.779590782 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2844360933 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3599408041 ps |
| CPU time | 10.5 seconds |
| Started | Feb 29 12:50:26 PM PST 24 |
| Finished | Feb 29 12:50:37 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-bc7c7c31-b15f-4f91-b03f-33773312009a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844360933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2844360933 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1016997050 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 950131769 ps |
| CPU time | 6.6 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:50:39 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-d1e69928-af08-4456-8665-bab6f3c16e80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1016997050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1016997050 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3915483801 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 25811613 ps |
| CPU time | 1.33 seconds |
| Started | Feb 29 12:50:23 PM PST 24 |
| Finished | Feb 29 12:50:24 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-afc59ebb-b186-4bd5-b054-b9a074f20668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915483801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3915483801 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1630816366 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 273744983 ps |
| CPU time | 6.36 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-65d22544-3a2c-4d13-8fdb-89e10747c989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1630816366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1630816366 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2669575740 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1723114018 ps |
| CPU time | 37.64 seconds |
| Started | Feb 29 12:50:49 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-5b1dbc69-5ef8-4214-9fdc-2aa3673a9ce5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2669575740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2669575740 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3604739863 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2887537977 ps |
| CPU time | 67.94 seconds |
| Started | Feb 29 12:50:51 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-02aa1fbb-e6cb-4e77-9625-d1b739df6f70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3604739863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3604739863 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.577017430 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 309093221 ps |
| CPU time | 25.33 seconds |
| Started | Feb 29 12:50:42 PM PST 24 |
| Finished | Feb 29 12:51:08 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-d8fddabf-485c-4c8d-a5c1-c63f21992f83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=577017430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.577017430 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3663307106 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 98798244 ps |
| CPU time | 7.92 seconds |
| Started | Feb 29 12:50:35 PM PST 24 |
| Finished | Feb 29 12:50:43 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-94884c36-f7f6-4806-87c1-c64b33e5dcc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3663307106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3663307106 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1475379220 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 91722293 ps |
| CPU time | 11.46 seconds |
| Started | Feb 29 12:50:46 PM PST 24 |
| Finished | Feb 29 12:50:58 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-d4669af5-0c6e-406c-b055-c768370d2cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1475379220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1475379220 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.99853557 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 10651179410 ps |
| CPU time | 58.68 seconds |
| Started | Feb 29 12:50:45 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-859a1f86-a499-423b-bfec-e9e994bb337c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=99853557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow _rsp.99853557 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2530057 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1101684873 ps |
| CPU time | 8.53 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:50:47 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c5ce916f-7c1b-4581-9f7c-4ed9847458d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2530057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2530057 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.991587873 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 22540341 ps |
| CPU time | 1.7 seconds |
| Started | Feb 29 12:50:40 PM PST 24 |
| Finished | Feb 29 12:50:42 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-1d87f4cb-a6c6-4db9-bfd1-d6f8c9904e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=991587873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.991587873 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1515795524 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4494748028 ps |
| CPU time | 14.29 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:57 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-9dff615e-6bd0-4911-a4e5-269e351e63a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515795524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1515795524 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1065851094 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 108165114632 ps |
| CPU time | 108.21 seconds |
| Started | Feb 29 12:50:49 PM PST 24 |
| Finished | Feb 29 12:52:38 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-e58b251a-2192-4f11-b01f-0a0d73dad132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065851094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1065851094 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.681351039 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 66028272277 ps |
| CPU time | 205.65 seconds |
| Started | Feb 29 12:51:00 PM PST 24 |
| Finished | Feb 29 12:54:26 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-e7c8f6c0-8483-41aa-a421-a47829feb1ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=681351039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.681351039 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3140861595 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 165717145 ps |
| CPU time | 5.51 seconds |
| Started | Feb 29 12:50:37 PM PST 24 |
| Finished | Feb 29 12:50:44 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-be4f456b-8875-4e9f-885f-25e6d9ff998d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140861595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3140861595 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2758021670 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 977964099 ps |
| CPU time | 10.43 seconds |
| Started | Feb 29 12:50:54 PM PST 24 |
| Finished | Feb 29 12:51:10 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-598a0857-6f85-42bc-a1c8-1f8f892d1fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758021670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2758021670 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2610015273 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 8620110 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:38 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-46db9210-313b-4a99-af49-d16d6c7f531b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610015273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2610015273 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2560076917 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2018324036 ps |
| CPU time | 9.04 seconds |
| Started | Feb 29 12:50:41 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-63d87b04-e5d4-4fc0-b856-c9fd9f136f6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560076917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2560076917 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3030669357 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 664176049 ps |
| CPU time | 5.02 seconds |
| Started | Feb 29 12:50:55 PM PST 24 |
| Finished | Feb 29 12:51:01 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-9d01aa57-3b33-4915-b0d2-73454c2262fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3030669357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3030669357 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.111627091 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9146590 ps |
| CPU time | 1.15 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:44 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-8b5ac647-8f2e-432c-b669-5d9717c39421 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111627091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.111627091 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1655813575 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 15489692092 ps |
| CPU time | 89.64 seconds |
| Started | Feb 29 12:50:33 PM PST 24 |
| Finished | Feb 29 12:52:03 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-fb34398e-052b-474a-bd5c-604eb6b048a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1655813575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1655813575 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.182408753 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 801301949 ps |
| CPU time | 59.79 seconds |
| Started | Feb 29 12:50:40 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-1ee0a1b1-936b-45f0-9300-cbb5dbd7dc0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182408753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.182408753 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2899106757 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7722058452 ps |
| CPU time | 82.16 seconds |
| Started | Feb 29 12:50:46 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-8c0f1f59-999f-4717-8ef3-e46a48ce1c3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899106757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2899106757 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2660885580 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 191967511 ps |
| CPU time | 2.85 seconds |
| Started | Feb 29 12:50:46 PM PST 24 |
| Finished | Feb 29 12:50:49 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-7a1987b2-c32c-410a-94da-df3af761f2c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2660885580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2660885580 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3177044508 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 22095616 ps |
| CPU time | 2.66 seconds |
| Started | Feb 29 12:50:45 PM PST 24 |
| Finished | Feb 29 12:50:48 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-4d31f346-b332-4dbf-99bf-785ef5ef4eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3177044508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3177044508 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2883632761 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 23612351836 ps |
| CPU time | 167.86 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:53:26 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-19085f13-467f-4c4f-887b-146e5a00d98e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2883632761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2883632761 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1432110427 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 658048585 ps |
| CPU time | 8.88 seconds |
| Started | Feb 29 12:50:40 PM PST 24 |
| Finished | Feb 29 12:50:49 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-48d037c4-4f17-4587-97a5-3abf955c7e16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432110427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1432110427 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.164029826 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 79389384 ps |
| CPU time | 1.94 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-1ada953e-2d95-4f52-be21-aafddd8afdd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=164029826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.164029826 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.2541734882 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 67815927 ps |
| CPU time | 7.57 seconds |
| Started | Feb 29 12:50:32 PM PST 24 |
| Finished | Feb 29 12:50:40 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-a1bf9477-53a8-433e-82c9-74481f979e54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2541734882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2541734882 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2783336818 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 33248134558 ps |
| CPU time | 123.86 seconds |
| Started | Feb 29 12:50:37 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-0d416788-ad45-46f4-85ee-5d089f8e8653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783336818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2783336818 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1861381459 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 10494684852 ps |
| CPU time | 54.2 seconds |
| Started | Feb 29 12:50:45 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-164355cc-643a-41b0-b2b9-f7dbcf379383 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1861381459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1861381459 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3624468808 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 25002189 ps |
| CPU time | 2.43 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-ae30a6f4-7f5a-4790-8924-ed8407a94206 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624468808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3624468808 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.2954116512 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 499839275 ps |
| CPU time | 4.95 seconds |
| Started | Feb 29 12:50:44 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-562ff7b1-e691-4510-9c78-50bc220535f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2954116512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2954116512 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.3867044341 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 10717506 ps |
| CPU time | 1.23 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-ac19f603-da66-47f6-9ff9-f9768c419f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3867044341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3867044341 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2262714079 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1722975514 ps |
| CPU time | 8.87 seconds |
| Started | Feb 29 12:50:55 PM PST 24 |
| Finished | Feb 29 12:51:05 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-3d617f72-da43-44d0-90b8-aa22f152f1df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262714079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2262714079 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.4262918896 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2707937133 ps |
| CPU time | 5.76 seconds |
| Started | Feb 29 12:50:39 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-b3aee8e1-d226-4a81-b259-af55cb8ea726 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4262918896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4262918896 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3436363478 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 11968928 ps |
| CPU time | 1.23 seconds |
| Started | Feb 29 12:50:41 PM PST 24 |
| Finished | Feb 29 12:50:48 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-9f8019ad-c0b4-41a5-b930-e3c6153af3ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436363478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3436363478 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2876654708 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4633723965 ps |
| CPU time | 80.77 seconds |
| Started | Feb 29 12:50:37 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-b8c3aca4-17d7-408a-9b97-5b2f4716780f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2876654708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2876654708 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2751355549 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 71101239 ps |
| CPU time | 6.39 seconds |
| Started | Feb 29 12:50:52 PM PST 24 |
| Finished | Feb 29 12:50:59 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-3feb0e97-cbbd-40e3-9486-1fdb8b52e51b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751355549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2751355549 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1789158725 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 200272965 ps |
| CPU time | 14.14 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:51:16 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-3faad163-7f3e-4edc-ae9e-a6d183bbe93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789158725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1789158725 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3075445621 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 21733828863 ps |
| CPU time | 133.51 seconds |
| Started | Feb 29 12:50:40 PM PST 24 |
| Finished | Feb 29 12:52:54 PM PST 24 |
| Peak memory | 207412 kb |
| Host | smart-823c26f9-b4c7-4ab3-b080-6ee7d82a493f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075445621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3075445621 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1874150036 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 214900243 ps |
| CPU time | 4.5 seconds |
| Started | Feb 29 12:50:58 PM PST 24 |
| Finished | Feb 29 12:51:03 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-887f81bb-bc09-472d-8c9b-8d6d2e96ce99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1874150036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1874150036 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2177395779 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 18215614985 ps |
| CPU time | 62.27 seconds |
| Started | Feb 29 12:50:58 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-fa3fc232-0778-43d8-add8-de694404020c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2177395779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.2177395779 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.682904682 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 481136502 ps |
| CPU time | 5.1 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:51:20 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-ef8f6291-0051-40ef-a324-d74cdff32ec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682904682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.682904682 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1088067023 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1006774208 ps |
| CPU time | 11.38 seconds |
| Started | Feb 29 12:50:48 PM PST 24 |
| Finished | Feb 29 12:51:00 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-ac53ad32-6a84-45ef-a9a0-01a45829ce1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1088067023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1088067023 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.4017272727 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 351145584 ps |
| CPU time | 5.96 seconds |
| Started | Feb 29 12:50:44 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-8fe96a9c-e66e-4793-b15c-c48cb40392b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4017272727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4017272727 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.521797189 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 14969929177 ps |
| CPU time | 89.86 seconds |
| Started | Feb 29 12:50:59 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-a64c00cd-248f-4a2c-8e9a-580916f40524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=521797189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.521797189 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2161699599 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 73576540 ps |
| CPU time | 7.79 seconds |
| Started | Feb 29 12:51:09 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-dceb74fd-8620-46a8-9185-e565bc453061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161699599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2161699599 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1595400927 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 539559908 ps |
| CPU time | 3.69 seconds |
| Started | Feb 29 12:51:13 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-45331769-f7b4-41d1-80a9-121ccec3c665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1595400927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1595400927 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.4262146940 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 60451661 ps |
| CPU time | 1.41 seconds |
| Started | Feb 29 12:50:43 PM PST 24 |
| Finished | Feb 29 12:50:44 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-96a7ea83-5fe3-43c6-bd6f-1e84f5420c8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4262146940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.4262146940 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2258909112 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1845282020 ps |
| CPU time | 8.76 seconds |
| Started | Feb 29 12:50:36 PM PST 24 |
| Finished | Feb 29 12:50:45 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-1177b146-e0ad-4037-802b-6aac3b406843 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258909112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2258909112 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1950771436 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3484611221 ps |
| CPU time | 9.21 seconds |
| Started | Feb 29 12:50:56 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-cf981ac0-14db-4a42-b083-1540d65c352f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1950771436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1950771436 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4286889467 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 10673649 ps |
| CPU time | 1.26 seconds |
| Started | Feb 29 12:50:38 PM PST 24 |
| Finished | Feb 29 12:50:40 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-607caa8d-1508-4166-bde8-ebf22e0536a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286889467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4286889467 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1251689815 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 266321972 ps |
| CPU time | 26.13 seconds |
| Started | Feb 29 12:50:46 PM PST 24 |
| Finished | Feb 29 12:51:12 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-7d005a52-c80f-43a0-bc03-9eaf11f68330 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251689815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1251689815 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.4073975765 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 50800456202 ps |
| CPU time | 106.78 seconds |
| Started | Feb 29 12:50:57 PM PST 24 |
| Finished | Feb 29 12:52:44 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-c68dae4a-f3e1-484c-ae1f-c70e9c611933 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073975765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4073975765 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.877558192 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 298072783 ps |
| CPU time | 28.03 seconds |
| Started | Feb 29 12:50:59 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-e8b9bcbd-b933-42f9-8463-d1d2c972f6d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877558192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.877558192 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1221929205 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3195662870 ps |
| CPU time | 171.48 seconds |
| Started | Feb 29 12:50:52 PM PST 24 |
| Finished | Feb 29 12:53:44 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-00d7981d-39fb-49d4-a9de-4008e927c79e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1221929205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1221929205 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1711368495 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 698735417 ps |
| CPU time | 5.63 seconds |
| Started | Feb 29 12:50:52 PM PST 24 |
| Finished | Feb 29 12:50:58 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-314c441d-8768-43fe-8e08-856fedf39e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1711368495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1711368495 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1327606207 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 354883836 ps |
| CPU time | 5.21 seconds |
| Started | Feb 29 12:50:51 PM PST 24 |
| Finished | Feb 29 12:50:57 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-36ee57ec-7e12-4901-9e8f-bcf0658cab35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1327606207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1327606207 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.250158336 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 138555794372 ps |
| CPU time | 125.91 seconds |
| Started | Feb 29 12:50:56 PM PST 24 |
| Finished | Feb 29 12:53:02 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-9492820a-7495-48d2-8fc9-befb32b00576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=250158336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.250158336 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4224264396 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 206291121 ps |
| CPU time | 3.85 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:10 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-8fdb1843-2446-466a-85be-fdec51fd6879 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224264396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4224264396 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.727529271 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2063688636 ps |
| CPU time | 8.36 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:51:11 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-f8c59db1-6581-4f1a-902e-1d517e692964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=727529271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.727529271 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.1359307486 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 16002216 ps |
| CPU time | 1.11 seconds |
| Started | Feb 29 12:50:49 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-fc246950-4d55-44fb-a1d5-3c796cd67b88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359307486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1359307486 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3077149486 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 33216007209 ps |
| CPU time | 120.99 seconds |
| Started | Feb 29 12:50:53 PM PST 24 |
| Finished | Feb 29 12:52:55 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-4e49a181-f84d-4ce4-965d-9f884f746955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077149486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3077149486 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3825891796 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1766401931 ps |
| CPU time | 13.73 seconds |
| Started | Feb 29 12:51:03 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-441f3fe6-5a3a-4502-811d-b879da6aa28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3825891796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3825891796 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3344392356 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 79809384 ps |
| CPU time | 4.86 seconds |
| Started | Feb 29 12:50:57 PM PST 24 |
| Finished | Feb 29 12:51:03 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-937ec903-cd96-4b8e-9907-6fec8cc318ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344392356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3344392356 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1241247495 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1090683807 ps |
| CPU time | 8.75 seconds |
| Started | Feb 29 12:51:06 PM PST 24 |
| Finished | Feb 29 12:51:15 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-d13ae8fd-f45f-48a5-b567-6c61366a56f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241247495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1241247495 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1402086934 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 69953128 ps |
| CPU time | 1.41 seconds |
| Started | Feb 29 12:51:04 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-8cd8e259-7b4a-4c99-addb-655e3be8647e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402086934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1402086934 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1995786181 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2485868550 ps |
| CPU time | 8.89 seconds |
| Started | Feb 29 12:51:12 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-35ebd5d1-e386-4d04-9e21-32921a4f39e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995786181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1995786181 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.155483466 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2280643457 ps |
| CPU time | 8 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:13 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-59d54c4c-7f3e-4a1c-8ba2-288c3c1cf5de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155483466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.155483466 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3298272976 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 10485639 ps |
| CPU time | 1.42 seconds |
| Started | Feb 29 12:51:06 PM PST 24 |
| Finished | Feb 29 12:51:08 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-d2053795-68e0-4efc-a6b0-0c282c373556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298272976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3298272976 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3961059160 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 166885690 ps |
| CPU time | 18.72 seconds |
| Started | Feb 29 12:51:03 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 203184 kb |
| Host | smart-1a44215b-557b-4df0-ad58-19e0e1afbeb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961059160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3961059160 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4255262500 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3215303176 ps |
| CPU time | 40.89 seconds |
| Started | Feb 29 12:50:57 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-179637e4-562b-41d2-b8a8-d67050c36e70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4255262500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4255262500 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3775347697 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 46785822 ps |
| CPU time | 3.63 seconds |
| Started | Feb 29 12:50:57 PM PST 24 |
| Finished | Feb 29 12:51:00 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-a0f8d897-23f8-41c8-a91f-1b4738eab5bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775347697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3775347697 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3616674225 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 273861674 ps |
| CPU time | 4.11 seconds |
| Started | Feb 29 12:50:51 PM PST 24 |
| Finished | Feb 29 12:50:55 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-4937e2c9-5c5b-44bc-b5d3-fb64065184a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616674225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3616674225 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1478362367 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 22369347 ps |
| CPU time | 1.12 seconds |
| Started | Feb 29 12:49:42 PM PST 24 |
| Finished | Feb 29 12:49:43 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-69dcec02-2533-4cec-a08c-d1938d5c1c57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1478362367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1478362367 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3861652806 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 429007259 ps |
| CPU time | 7.43 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:49:51 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-b7dceccb-9a7d-4148-b358-9fe3ebd1efe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861652806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3861652806 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.3855680635 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 272848989 ps |
| CPU time | 1.92 seconds |
| Started | Feb 29 12:49:41 PM PST 24 |
| Finished | Feb 29 12:49:44 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-7a6c83b1-9d27-4f9c-8318-9a7488bf8e0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3855680635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3855680635 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1797200398 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 19313563 ps |
| CPU time | 2.05 seconds |
| Started | Feb 29 12:49:33 PM PST 24 |
| Finished | Feb 29 12:49:35 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-efe5970e-1b5f-4e48-b7c4-2d17413058cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797200398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1797200398 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3064524762 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 51567878617 ps |
| CPU time | 127.37 seconds |
| Started | Feb 29 12:49:23 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-31b6d5ef-2147-4acb-af56-d2fa64694ac7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064524762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3064524762 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2092849953 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3933617157 ps |
| CPU time | 18.11 seconds |
| Started | Feb 29 12:49:37 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-b9018e12-f162-4044-ba84-e067efba6f3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2092849953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2092849953 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2543153655 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 66664373 ps |
| CPU time | 4.08 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-f140328c-6a6e-4843-bd25-827829239f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543153655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2543153655 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.46393066 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 339532449 ps |
| CPU time | 5.58 seconds |
| Started | Feb 29 12:49:31 PM PST 24 |
| Finished | Feb 29 12:49:37 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-c21f2cf8-ca7c-4ade-98c5-35bfb521dc66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46393066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.46393066 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.157419909 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 153223484 ps |
| CPU time | 1.72 seconds |
| Started | Feb 29 12:49:26 PM PST 24 |
| Finished | Feb 29 12:49:28 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-2c9f192b-7b20-4d95-89a6-84465222d682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=157419909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.157419909 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4218890885 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3675171749 ps |
| CPU time | 10.5 seconds |
| Started | Feb 29 12:49:23 PM PST 24 |
| Finished | Feb 29 12:49:33 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-3469c361-7fa7-438f-84fd-114d126e3184 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218890885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4218890885 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.298294921 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 789631029 ps |
| CPU time | 6.37 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:49:42 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-2e11333e-d2ed-4973-99b8-58967d8302a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=298294921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.298294921 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2619341809 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 8823622 ps |
| CPU time | 1.08 seconds |
| Started | Feb 29 12:49:26 PM PST 24 |
| Finished | Feb 29 12:49:28 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-b4806fc2-7389-478e-b27c-fa92c93faab8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619341809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2619341809 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1566434882 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5246650229 ps |
| CPU time | 53.36 seconds |
| Started | Feb 29 12:49:40 PM PST 24 |
| Finished | Feb 29 12:50:34 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-cd4bc974-2f8c-4b35-8bba-fc63a012c78b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1566434882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1566434882 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3734108582 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1456433606 ps |
| CPU time | 20.41 seconds |
| Started | Feb 29 12:49:52 PM PST 24 |
| Finished | Feb 29 12:50:12 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-cf946a87-4fe2-409e-bfe0-c827b0efb7ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3734108582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3734108582 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3516198123 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 66625340 ps |
| CPU time | 22.54 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:50:08 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f8ef8b1f-fac2-4840-929a-276b61fd702f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3516198123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3516198123 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2419842854 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 35862819 ps |
| CPU time | 3.09 seconds |
| Started | Feb 29 12:49:42 PM PST 24 |
| Finished | Feb 29 12:49:45 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-98efc667-abbc-4e60-ab4d-deeb68c36bcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419842854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2419842854 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.403632212 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 100326053652 ps |
| CPU time | 356.03 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:57:02 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-167c98de-4657-465a-a46f-29d8c7ae1ca0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=403632212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.403632212 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1615922182 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 86100855 ps |
| CPU time | 5.83 seconds |
| Started | Feb 29 12:51:18 PM PST 24 |
| Finished | Feb 29 12:51:24 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-6abde917-d1aa-4af5-9178-7aaf06365c6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1615922182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1615922182 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.2645887491 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 854897791 ps |
| CPU time | 6.56 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:51:09 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-5f8b3f9e-b6c1-4f2f-81a6-d9b8a6a9cf9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2645887491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2645887491 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.4234713263 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 54382363 ps |
| CPU time | 8.63 seconds |
| Started | Feb 29 12:51:09 PM PST 24 |
| Finished | Feb 29 12:51:18 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-fce9766a-175a-4414-b2db-5b43b850f1a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234713263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4234713263 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.117618178 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 37508660062 ps |
| CPU time | 62.23 seconds |
| Started | Feb 29 12:50:59 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-8fcb42a7-60ae-419f-b174-98731041b9e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=117618178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.117618178 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1555568725 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 20639733460 ps |
| CPU time | 112.35 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:52:58 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-ea307824-1500-4c0b-9cbb-15dcfa3b8133 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1555568725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1555568725 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.696335848 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 23031145 ps |
| CPU time | 1.88 seconds |
| Started | Feb 29 12:50:59 PM PST 24 |
| Finished | Feb 29 12:51:01 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-e8b7df55-70a8-401a-b25f-c729b53992db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696335848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.696335848 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.774040110 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 562962996 ps |
| CPU time | 7.78 seconds |
| Started | Feb 29 12:50:55 PM PST 24 |
| Finished | Feb 29 12:51:03 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-97b8b700-39a1-401b-a22e-5fc3343c8270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=774040110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.774040110 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2181229190 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 74940621 ps |
| CPU time | 1.73 seconds |
| Started | Feb 29 12:50:48 PM PST 24 |
| Finished | Feb 29 12:50:50 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-ef206c85-24a7-412b-a292-96c39be0a841 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2181229190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2181229190 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3668415222 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1595076476 ps |
| CPU time | 6.16 seconds |
| Started | Feb 29 12:50:58 PM PST 24 |
| Finished | Feb 29 12:51:05 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-76032ab1-82e0-4fdb-972d-88a543ca736f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668415222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3668415222 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1604042810 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2084268352 ps |
| CPU time | 7.05 seconds |
| Started | Feb 29 12:50:56 PM PST 24 |
| Finished | Feb 29 12:51:04 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-e609f395-95fc-47a8-97fb-ecc4fffdb5c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1604042810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1604042810 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3419993341 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8830816 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:50:50 PM PST 24 |
| Finished | Feb 29 12:50:52 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-2e549e1b-6455-4c97-acb2-f2aca5dec21c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419993341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3419993341 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1055362306 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 301437977 ps |
| CPU time | 32.81 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-ccae2dd8-6f6e-4f83-aec9-d76e2ad1aa14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055362306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1055362306 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.802457336 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4543165919 ps |
| CPU time | 86.29 seconds |
| Started | Feb 29 12:51:09 PM PST 24 |
| Finished | Feb 29 12:52:36 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-32cd79da-f4e2-44df-8aa7-6259a9924fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=802457336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.802457336 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2916193618 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 637267475 ps |
| CPU time | 62.58 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:52:06 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-c37c543f-accb-4510-a179-68be6007b756 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2916193618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2916193618 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3141552306 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 724641912 ps |
| CPU time | 86.22 seconds |
| Started | Feb 29 12:51:07 PM PST 24 |
| Finished | Feb 29 12:52:34 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-2273bc52-9dc4-452d-aee8-6565b18c33f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141552306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.3141552306 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3103644008 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 20063266 ps |
| CPU time | 2.64 seconds |
| Started | Feb 29 12:50:50 PM PST 24 |
| Finished | Feb 29 12:50:53 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-86766459-21f4-44b8-94c9-13c99cee15c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103644008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3103644008 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.536639812 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 255896253 ps |
| CPU time | 2.07 seconds |
| Started | Feb 29 12:50:46 PM PST 24 |
| Finished | Feb 29 12:50:49 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-73a76f26-26e9-488a-a89a-185db3c53340 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=536639812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.536639812 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3989985828 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 21626548159 ps |
| CPU time | 104.26 seconds |
| Started | Feb 29 12:51:10 PM PST 24 |
| Finished | Feb 29 12:52:54 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-e0b3461e-66c1-4376-8488-ad2cf863cfce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3989985828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3989985828 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.318755846 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1623240832 ps |
| CPU time | 7.99 seconds |
| Started | Feb 29 12:51:03 PM PST 24 |
| Finished | Feb 29 12:51:13 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-17abe898-0d5f-42ea-90e3-9dbc31b1bf19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=318755846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.318755846 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2135104885 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 112653562 ps |
| CPU time | 5.37 seconds |
| Started | Feb 29 12:51:12 PM PST 24 |
| Finished | Feb 29 12:51:18 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-99d229d1-846d-4c37-b937-4d797d1fa289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135104885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2135104885 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.1626064743 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 201339513 ps |
| CPU time | 3.93 seconds |
| Started | Feb 29 12:51:04 PM PST 24 |
| Finished | Feb 29 12:51:09 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-a651996a-47a5-4274-a7e7-6a49426d8e84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1626064743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1626064743 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4276579707 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4566904636 ps |
| CPU time | 9.86 seconds |
| Started | Feb 29 12:50:55 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-d95f0fdd-796c-4da6-abeb-7d59e2d2a593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276579707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4276579707 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1598480444 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 13166446640 ps |
| CPU time | 75.83 seconds |
| Started | Feb 29 12:51:01 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-22b3abf1-5fe1-4161-8326-572b2daa1ec2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1598480444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1598480444 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3607570861 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 158377114 ps |
| CPU time | 5.51 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:51:26 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-f79ba036-244b-4443-a705-12968d745826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607570861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3607570861 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2110884904 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1105476171 ps |
| CPU time | 13.71 seconds |
| Started | Feb 29 12:51:00 PM PST 24 |
| Finished | Feb 29 12:51:14 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-6082d2fd-b7de-464d-a417-b43bc0936e3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2110884904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2110884904 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.3165741112 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 8975507 ps |
| CPU time | 1.11 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-413769a9-5798-4cdc-b16a-a09e2200a0a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3165741112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3165741112 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1071992887 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13045739580 ps |
| CPU time | 12.12 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-eef90dad-3bb0-4777-b4c5-e353b8ecf97b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071992887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1071992887 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2975219270 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5241509158 ps |
| CPU time | 9.02 seconds |
| Started | Feb 29 12:50:51 PM PST 24 |
| Finished | Feb 29 12:51:00 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-5f2084a0-06ca-4514-a018-fc917d4e07cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2975219270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2975219270 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.4008351931 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 16839880 ps |
| CPU time | 1.11 seconds |
| Started | Feb 29 12:50:52 PM PST 24 |
| Finished | Feb 29 12:50:59 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-07e1f68a-ae98-4cb0-ae1b-9a61b162b3aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008351931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.4008351931 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.55479252 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 398970852 ps |
| CPU time | 16.01 seconds |
| Started | Feb 29 12:51:11 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-91f5c6fd-31cf-4d03-9836-da27a4b48cc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=55479252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.55479252 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1055384104 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 174458127 ps |
| CPU time | 9.24 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-ba114da0-b022-4728-8c0c-53cf3e174f2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055384104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1055384104 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1524975184 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 199029562 ps |
| CPU time | 30.32 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-57c68d83-ae57-42fb-bcc1-34e84aeaade7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1524975184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.1524975184 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3602765357 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5208907436 ps |
| CPU time | 121.13 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:53:28 PM PST 24 |
| Peak memory | 207760 kb |
| Host | smart-25411493-bb1e-45aa-8738-228dca6359b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3602765357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3602765357 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.4257565576 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 193086997 ps |
| CPU time | 5.19 seconds |
| Started | Feb 29 12:50:55 PM PST 24 |
| Finished | Feb 29 12:51:01 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-ad3f2533-a277-496e-8720-d7a13e3337fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257565576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4257565576 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1414195908 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2694930586 ps |
| CPU time | 13.46 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:51:38 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-a279a63b-7c3e-4749-91e3-c66eadd27c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1414195908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1414195908 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3668824478 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 43273412301 ps |
| CPU time | 307.78 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:56:32 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-bc597384-31d6-463c-a0e6-5ea329e6256c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3668824478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3668824478 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1450897595 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 46117632 ps |
| CPU time | 3.94 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-0bb03b56-91a5-4a34-a2b9-ec86145aad8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450897595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1450897595 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.4104177874 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 590198827 ps |
| CPU time | 3.75 seconds |
| Started | Feb 29 12:51:06 PM PST 24 |
| Finished | Feb 29 12:51:10 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-83523d92-cf86-4861-ac5b-3574da5c69dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104177874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.4104177874 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.2108533165 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1901864022 ps |
| CPU time | 12.45 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-022edc34-ffac-45d5-94a1-551392b78ee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2108533165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2108533165 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3990321937 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 32529793654 ps |
| CPU time | 89.63 seconds |
| Started | Feb 29 12:51:09 PM PST 24 |
| Finished | Feb 29 12:52:39 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-c482a8a2-4b12-4bd7-a592-5974ac02933b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990321937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3990321937 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2315600820 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 7620549388 ps |
| CPU time | 43.72 seconds |
| Started | Feb 29 12:50:59 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-b680f3f2-4b83-4408-9f4e-2ad21978c39e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2315600820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2315600820 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.908042591 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 84092795 ps |
| CPU time | 4.77 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:11 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-2ed4d2a6-de2e-4f5c-9bf5-938b6d6203e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908042591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.908042591 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.165154571 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 945978954 ps |
| CPU time | 4.72 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:51:22 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-7c719a42-1f8e-42f6-8a51-ad2d4b707616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=165154571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.165154571 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.3223321821 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 18491087 ps |
| CPU time | 1.02 seconds |
| Started | Feb 29 12:51:08 PM PST 24 |
| Finished | Feb 29 12:51:09 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-df2f515d-a62a-47c4-94b3-9a0a4606a2c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3223321821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3223321821 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4280058388 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1952540137 ps |
| CPU time | 6.96 seconds |
| Started | Feb 29 12:51:07 PM PST 24 |
| Finished | Feb 29 12:51:14 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-c8bb6c56-afb2-42f2-87f1-59a77d387e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280058388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4280058388 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3106872825 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2144967530 ps |
| CPU time | 7.78 seconds |
| Started | Feb 29 12:50:57 PM PST 24 |
| Finished | Feb 29 12:51:05 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-a4f0b21f-bea3-4b42-a440-16a9d9af8f1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3106872825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3106872825 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2859735274 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 9624747 ps |
| CPU time | 1.27 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-113d76e2-9a27-452e-848a-d6fbf2f02ad3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859735274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2859735274 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.4156745685 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2376383800 ps |
| CPU time | 33.14 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-a085a153-0ee9-4783-ad1c-90c4f977f413 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156745685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4156745685 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2560024356 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 423519541 ps |
| CPU time | 35.25 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-b012fe47-8227-4df6-aeb0-e9275a98c210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2560024356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2560024356 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1228168499 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 5769652822 ps |
| CPU time | 98.68 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:52:44 PM PST 24 |
| Peak memory | 205524 kb |
| Host | smart-476e2d03-eabf-4fd5-b855-0b37db2b8c35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228168499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1228168499 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.660570759 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 569060017 ps |
| CPU time | 5.25 seconds |
| Started | Feb 29 12:51:18 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-8a86ba97-2f82-4474-8901-4e822960f3e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660570759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.660570759 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.207444511 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 579004546 ps |
| CPU time | 10.31 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-ad4e90e0-3ba4-41dd-8a09-85e5e8779007 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=207444511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.207444511 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1239658625 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 58293218970 ps |
| CPU time | 309.82 seconds |
| Started | Feb 29 12:50:58 PM PST 24 |
| Finished | Feb 29 12:56:08 PM PST 24 |
| Peak memory | 205164 kb |
| Host | smart-30604246-c58f-4aa6-9810-53fcd83ca33c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1239658625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1239658625 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.595951748 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 49777536 ps |
| CPU time | 5.19 seconds |
| Started | Feb 29 12:51:02 PM PST 24 |
| Finished | Feb 29 12:51:08 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-f07739a3-94cc-42e7-a0aa-bb858fd99f63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=595951748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.595951748 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.833499719 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 44206779 ps |
| CPU time | 4.58 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:51:22 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-ec735e4f-a1a8-434e-8959-dbe2582bff1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833499719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.833499719 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3717921030 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 16587898 ps |
| CPU time | 1.68 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:51:16 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-eab81a77-66f1-4471-affc-66db0106de14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717921030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3717921030 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.476736504 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 157909649236 ps |
| CPU time | 81.81 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:52:43 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-e78f0dae-5096-4624-93ca-95fcccb1afd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=476736504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.476736504 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1767478282 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 146835771035 ps |
| CPU time | 157.98 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:54:02 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-bc49c36c-2ceb-437d-8e00-ae798f2e9828 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1767478282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1767478282 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1339195212 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 46455122 ps |
| CPU time | 3.79 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-1b76e9ff-171f-4647-b7b3-b3b238a0e809 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339195212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1339195212 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3458342031 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 653065654 ps |
| CPU time | 8.82 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-f00b2111-66e4-491c-8c63-5e04bc3e9c44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3458342031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3458342031 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.1035868642 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 126200822 ps |
| CPU time | 1.62 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-95aafda6-044c-470d-abc2-7ee098bfcab7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1035868642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1035868642 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3318748638 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4495908668 ps |
| CPU time | 7.45 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-ee52dbfb-58c7-41c1-a195-44b8eeac4061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318748638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3318748638 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.807884117 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2346886789 ps |
| CPU time | 5.26 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-0b164f30-322d-4411-ac70-a0a461145122 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=807884117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.807884117 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2560642641 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 15499529 ps |
| CPU time | 1.03 seconds |
| Started | Feb 29 12:51:22 PM PST 24 |
| Finished | Feb 29 12:51:24 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-b5443f8c-31cf-497b-ad7c-131d19b91c01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560642641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2560642641 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3839226039 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2025278417 ps |
| CPU time | 18.13 seconds |
| Started | Feb 29 12:51:06 PM PST 24 |
| Finished | Feb 29 12:51:24 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-3e9cc64a-9067-42a9-a47a-85189ace2133 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3839226039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3839226039 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2674795856 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 57479771 ps |
| CPU time | 4.74 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:51:31 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-6e0980a2-ebe2-4f76-a424-d622c25cc4c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674795856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2674795856 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.831078048 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 10161447 ps |
| CPU time | 2.33 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-920396c9-3aae-43e2-9ae0-4dc8184a04a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831078048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.831078048 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1072669418 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 622629439 ps |
| CPU time | 51.77 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-c9f8bc12-2a8f-4e54-b936-a3194ad99a19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1072669418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1072669418 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3913170663 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1071368489 ps |
| CPU time | 7.22 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-6e79fab5-175d-4811-9218-15841a41503e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3913170663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3913170663 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1721957322 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1167643165 ps |
| CPU time | 16.17 seconds |
| Started | Feb 29 12:51:05 PM PST 24 |
| Finished | Feb 29 12:51:22 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-632fe317-82b2-4336-9723-e4f81aff8c37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721957322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1721957322 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.400774219 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 57849329459 ps |
| CPU time | 338.32 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:56:59 PM PST 24 |
| Peak memory | 203960 kb |
| Host | smart-5408e97d-c38f-41d2-81c8-0f7e10983bb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=400774219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.400774219 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2074247722 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 234510467 ps |
| CPU time | 3.23 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:34 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-e0470f64-eb3b-4ec8-a05f-50f5bab18f80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2074247722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2074247722 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.371908969 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 53831186 ps |
| CPU time | 5.96 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-c2f6b63c-b829-40c2-a3ac-2b8192d75102 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371908969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.371908969 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.144101967 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 85813929040 ps |
| CPU time | 65.2 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:52:31 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c848ca72-f543-4426-aaef-86109b6d84b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=144101967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.144101967 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2694617782 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 12157484384 ps |
| CPU time | 67.37 seconds |
| Started | Feb 29 12:51:13 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-5a25fc75-fa42-4d79-85fc-df6e89f4303f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2694617782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2694617782 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1274080174 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 77237786 ps |
| CPU time | 7.6 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:29 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-fdc31a55-58bf-48a0-b9ad-12210e76a1ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274080174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1274080174 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.279339867 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 65137853 ps |
| CPU time | 3.86 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-4944b633-882e-4558-b468-2ee9f834e78a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=279339867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.279339867 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2965796046 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 17064244 ps |
| CPU time | 1.36 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-1fabb465-2176-4b5c-8d98-e6ac0fca91c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2965796046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2965796046 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1387286533 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5198066987 ps |
| CPU time | 9.91 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:26 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-9ecf3c48-693d-48df-bb9d-bafb2bb0a5de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387286533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1387286533 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3786366449 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5369752014 ps |
| CPU time | 6.23 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:51:31 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f85db29c-5b30-4634-abf5-cf79fbc5c3ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3786366449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3786366449 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1521398157 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15505951 ps |
| CPU time | 1.17 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-5b0b84b9-c1c2-4c66-b73c-451b7fe7f4ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521398157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1521398157 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2348920105 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 288124440 ps |
| CPU time | 24.16 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-f71e5117-c814-4459-8a46-8452b996919d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348920105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2348920105 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3085888395 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 721072396 ps |
| CPU time | 28.23 seconds |
| Started | Feb 29 12:51:12 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-03d451d8-2859-4cdc-a980-5548b68e712f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085888395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3085888395 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3387324978 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 287811666 ps |
| CPU time | 50.17 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-6236c119-bb71-4333-887a-3e6d277951c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3387324978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3387324978 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2866664684 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 120695056 ps |
| CPU time | 17.84 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:51:45 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-f0fb8c3e-0d8a-494a-8c41-961aa4e436fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866664684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2866664684 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3784225769 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 772705266 ps |
| CPU time | 11.28 seconds |
| Started | Feb 29 12:51:04 PM PST 24 |
| Finished | Feb 29 12:51:16 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-0cb355b4-8926-4a48-bce3-e2c1c1f024c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3784225769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3784225769 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3040925094 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1628555388 ps |
| CPU time | 17.36 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-7cb64a06-f36a-4501-863e-41c3e0875238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3040925094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3040925094 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1924640839 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 79255322086 ps |
| CPU time | 259.58 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:55:38 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-64b73e17-25a9-4dd9-9113-08f719a94643 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1924640839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.1924640839 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.564126224 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 224737203 ps |
| CPU time | 5.09 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:20 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-3ee0c67d-292f-4dd8-9ff6-f539a38e751e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=564126224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.564126224 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.796023870 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 47524627 ps |
| CPU time | 4.04 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:29 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-2daf075a-322f-45b4-9751-9082a7fc232b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796023870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.796023870 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2898627092 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 382285098 ps |
| CPU time | 4.69 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-ef0939f5-76aa-4f0b-ae22-eb949682e9ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2898627092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2898627092 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.18359591 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 30386358483 ps |
| CPU time | 135.25 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:53:31 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-29f06d53-c07c-4e46-90d6-a8d9aba60b4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=18359591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.18359591 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2444699787 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 22072378164 ps |
| CPU time | 82.01 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:52:43 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-5a796210-dd6b-4134-925e-de2b6b53d319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2444699787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2444699787 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.4225581214 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 23601611 ps |
| CPU time | 1.35 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-29340699-fb72-4999-945c-8f7573657185 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225581214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4225581214 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2510867892 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 29176041 ps |
| CPU time | 1.41 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-486f6a8a-86ca-4b35-ac44-c8cc5c0d04bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510867892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2510867892 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.2674760392 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 65257119 ps |
| CPU time | 1.68 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-de830c78-9171-4fe2-8299-9877d95909d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674760392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2674760392 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3408075806 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1838240094 ps |
| CPU time | 9.01 seconds |
| Started | Feb 29 12:51:16 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-a33b1a1f-7d56-469c-b54e-da4de772f351 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408075806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3408075806 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2014088502 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1389141470 ps |
| CPU time | 7.39 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ff31ce56-255e-40ff-b2ea-76de4cc4f3d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2014088502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2014088502 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1140574386 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 10932872 ps |
| CPU time | 1.1 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-57e2cd57-c42e-4d7a-aab0-41ce59e42404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140574386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1140574386 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.585839315 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2785921564 ps |
| CPU time | 39.58 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:52:06 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-f7c6be7e-423f-4194-a864-5bdbc536df02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=585839315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.585839315 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2149805681 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 387674561 ps |
| CPU time | 11.17 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:51:28 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-e6182bcd-0ebe-41e1-b159-8d659b9001ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149805681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2149805681 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3906229914 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3127290083 ps |
| CPU time | 120.21 seconds |
| Started | Feb 29 12:51:24 PM PST 24 |
| Finished | Feb 29 12:53:24 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-efc7f52a-ec64-49dc-872a-6fac59d44c49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906229914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.3906229914 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1030116854 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5969170933 ps |
| CPU time | 137.31 seconds |
| Started | Feb 29 12:51:14 PM PST 24 |
| Finished | Feb 29 12:53:32 PM PST 24 |
| Peak memory | 206124 kb |
| Host | smart-dcdddf3d-acbc-4485-b3d1-4cd1b0afc4db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1030116854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1030116854 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1003974619 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 45167406 ps |
| CPU time | 2.13 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:51:26 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-b65b25a5-88e7-4a9e-8ee0-4d5b35c7823e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1003974619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1003974619 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3441629016 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 53103279 ps |
| CPU time | 10.02 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-1bb41e9c-e16f-4f7a-a164-f4d9d8fcf9ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3441629016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3441629016 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1496857203 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 286991506 ps |
| CPU time | 4.45 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:34 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-4c2c758a-9649-4214-b64c-f3005e2f62a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496857203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1496857203 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3797936805 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 536426735 ps |
| CPU time | 3.49 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-c9ccfc95-9bab-402a-a6eb-722a5c30c174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797936805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3797936805 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2817706655 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 58234155 ps |
| CPU time | 9.86 seconds |
| Started | Feb 29 12:51:15 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-e7876474-2aa6-433c-83eb-e6f60f96345e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817706655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2817706655 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1385558377 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 12682780422 ps |
| CPU time | 53.28 seconds |
| Started | Feb 29 12:51:17 PM PST 24 |
| Finished | Feb 29 12:52:10 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-4a0f016f-025c-4316-8b51-7062f2bcc5f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385558377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1385558377 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.121176904 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 14907984068 ps |
| CPU time | 84.49 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:52:45 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-3c29305a-c97d-405a-aa2a-fcaac4b9cf9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=121176904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.121176904 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1205172097 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 95699780 ps |
| CPU time | 3.05 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:33 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a275afb8-3365-4ac0-9ddf-a19d74d5e675 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205172097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1205172097 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.4272645691 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2523351629 ps |
| CPU time | 8.15 seconds |
| Started | Feb 29 12:51:16 PM PST 24 |
| Finished | Feb 29 12:51:25 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-5c926601-107a-430b-906e-b84b05182441 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272645691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4272645691 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1386794196 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 27104848 ps |
| CPU time | 1.21 seconds |
| Started | Feb 29 12:51:21 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-fa2dcfc6-6607-458b-a669-8e5ca8990e62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1386794196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1386794196 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3093764195 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 5003988153 ps |
| CPU time | 7.34 seconds |
| Started | Feb 29 12:51:20 PM PST 24 |
| Finished | Feb 29 12:51:28 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-058d519f-1ec3-4b5e-a7b9-eee6d48493c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093764195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3093764195 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3493301482 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3155265125 ps |
| CPU time | 11.46 seconds |
| Started | Feb 29 12:51:19 PM PST 24 |
| Finished | Feb 29 12:51:31 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-4ff01b84-b57d-4e9c-a6cd-304d9ce42a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3493301482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3493301482 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3420757843 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 8139425 ps |
| CPU time | 1.05 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-b19e2f45-eb3c-41f3-8a21-98aaaff86d5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420757843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3420757843 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3810261261 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 919035979 ps |
| CPU time | 77.34 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:52:50 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-6322354c-a65c-47cf-9fc4-95b27341425b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810261261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3810261261 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2920539455 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 803045068 ps |
| CPU time | 15.04 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-efcd0d95-f2c9-4bb1-a867-82243b4651c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920539455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2920539455 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.523729506 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 487728633 ps |
| CPU time | 79.91 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:52:46 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-dbff909a-18bd-4212-b003-93e730507792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=523729506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.523729506 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1333048989 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1095654608 ps |
| CPU time | 69.35 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-a802101f-f5a0-4d93-9028-33d0903a3a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1333048989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1333048989 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1064351881 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 681437647 ps |
| CPU time | 9.04 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-543cba8b-4f51-43df-b5fa-2e101ea1507b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064351881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1064351881 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3531398669 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 103589566 ps |
| CPU time | 9.07 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:51:36 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-bca89308-a2e1-4930-983a-04aea0957ecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531398669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3531398669 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2577295852 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 61044424466 ps |
| CPU time | 270.61 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:56:07 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-3c9c314c-c246-4be9-b774-b17df92834fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2577295852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2577295852 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.464363379 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1492301823 ps |
| CPU time | 12.25 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-d22b1230-9ca5-4320-8db7-c0c946cae88f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464363379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.464363379 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.291105057 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 504411235 ps |
| CPU time | 3.35 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:38 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-a52d8922-3d94-47d0-839b-4ad8f11cbd54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291105057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.291105057 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.1853527336 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 312991179 ps |
| CPU time | 4.09 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:35 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-909b86ad-fd2a-45e7-bd52-1b66b51d9297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853527336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1853527336 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2534801018 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 31788606676 ps |
| CPU time | 135.13 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:53:44 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-83b16551-3840-4c67-891f-ee37e51aa12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534801018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2534801018 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1508999659 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 19881173076 ps |
| CPU time | 120.48 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:53:30 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-578df87f-a279-4baa-8d8b-0c9c0f68a4ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1508999659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1508999659 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.439853770 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 52786703 ps |
| CPU time | 6.19 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:36 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-ab4954e6-f93a-4378-8306-a13c162aae33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439853770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.439853770 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.503026691 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 83418778 ps |
| CPU time | 3.9 seconds |
| Started | Feb 29 12:51:23 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-ed5ad3d0-08bc-4db3-a755-35e2c8ea4182 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503026691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.503026691 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3810014209 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 326048733 ps |
| CPU time | 1.76 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-5b02e6e3-97d6-4583-a9d2-da2c9a1a14f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810014209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3810014209 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1453855810 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1315597964 ps |
| CPU time | 7.27 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:51:34 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-aa93c8d9-6e80-46e5-84e9-331013ab30e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453855810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1453855810 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2407300849 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1803677907 ps |
| CPU time | 9.93 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-016ebae0-15d0-49a0-aa67-79028ce828b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2407300849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2407300849 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1905525735 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 10429684 ps |
| CPU time | 1.04 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-5a7ce305-d49b-447b-a7db-2423e80cf94e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905525735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1905525735 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4096029097 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 222304824 ps |
| CPU time | 19 seconds |
| Started | Feb 29 12:51:42 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-2831707f-4cde-45dc-87b5-e2b14007a1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096029097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4096029097 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1577586559 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1301464142 ps |
| CPU time | 51.98 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-91fe0d18-ce98-492f-9550-ac5bb5d8b338 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577586559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1577586559 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.407537476 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 544592949 ps |
| CPU time | 69.18 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:52:36 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-1703b086-1f32-4edf-9198-d5b94a9b8cf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407537476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.407537476 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.252744492 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 733218301 ps |
| CPU time | 83.09 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:52:53 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-eccd46e0-d431-4540-ba88-ade4532aae35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252744492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.252744492 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3894202933 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 157110693 ps |
| CPU time | 1.97 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:34 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-e3be08a7-4775-45ef-9fc8-22126a234702 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3894202933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3894202933 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2219769066 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1611977676 ps |
| CPU time | 14.59 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-4f0ba15d-3215-4572-842d-b1d42cd61f75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2219769066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2219769066 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.991857755 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 43834672477 ps |
| CPU time | 58.13 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-8ae36e6f-7aa6-4aff-a74a-bfa337a37bad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=991857755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.991857755 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2058603962 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 102020457 ps |
| CPU time | 5.32 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ba9da165-c800-474f-a841-72756b8e846a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2058603962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2058603962 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.1836735586 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1515133119 ps |
| CPU time | 9.51 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-21369254-a97d-41a9-a8c4-05a94ed5dd91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1836735586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1836735586 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.705600312 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 806567319 ps |
| CPU time | 9.79 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:42 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-4466bcb7-f42a-4e79-a280-408d7e35c034 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=705600312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.705600312 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1387818225 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 35443825803 ps |
| CPU time | 149.76 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:53:56 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-3be174fe-0aa4-45bc-9e7d-b709bd2197f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387818225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1387818225 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2214563966 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 80829049901 ps |
| CPU time | 90.79 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:52:56 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-834e1fee-a824-43d4-8d62-091a172723a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2214563966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2214563966 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3319475809 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 90628788 ps |
| CPU time | 6.58 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-dc304773-10d3-463c-8f1c-8a6062446824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319475809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3319475809 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.96784030 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 52375825 ps |
| CPU time | 5.9 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-c2f55a13-7969-4e7c-9a17-840921b9a293 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=96784030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.96784030 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3596672319 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12610078 ps |
| CPU time | 1.29 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:31 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-f454704a-c549-469a-b22e-77756af4594f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3596672319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3596672319 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4231965812 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1681747638 ps |
| CPU time | 6.35 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-63d722e3-226b-46c3-8006-f17f9da6c2cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231965812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4231965812 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1915760489 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2426732501 ps |
| CPU time | 8 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:51:35 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-956420a0-ec3b-4daf-a2b2-affcba0295d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1915760489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1915760489 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1354091009 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 9066594 ps |
| CPU time | 1.17 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:27 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-5722796a-d65b-4bad-bd6a-682a935309ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354091009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1354091009 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2291681769 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3597038709 ps |
| CPU time | 26.82 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:56 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-d4ec8f3b-79d8-47ff-8b3a-4262bd873edc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291681769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2291681769 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2576878608 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 186835968 ps |
| CPU time | 13.83 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-3be3a4b7-78d5-4ef9-9a43-d9c96f509556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2576878608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2576878608 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.763777568 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2942336109 ps |
| CPU time | 141.55 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:54:09 PM PST 24 |
| Peak memory | 207248 kb |
| Host | smart-039d7232-5631-4966-a6a4-c947a85460fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=763777568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.763777568 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3435001764 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 761844589 ps |
| CPU time | 121.69 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:53:32 PM PST 24 |
| Peak memory | 207816 kb |
| Host | smart-c3708e1b-9383-4cb1-b617-f51088e81a48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3435001764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3435001764 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.177945029 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 743496886 ps |
| CPU time | 10.44 seconds |
| Started | Feb 29 12:51:27 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-a53643d0-f947-4cbe-944d-ab88da72a2d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177945029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.177945029 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2555508887 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 250923809 ps |
| CPU time | 5.54 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-2426293b-5802-4f9c-b63b-785a447d6dd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2555508887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2555508887 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2661606674 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 83399682 ps |
| CPU time | 3.32 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:38 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-eca6db92-0836-43c0-b6e8-74e37f0a2cdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2661606674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2661606674 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.2482424515 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 410967318 ps |
| CPU time | 4.23 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:33 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-f20085ca-491d-4e67-a7a1-ce5b7ba4d505 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2482424515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2482424515 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2140016855 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 289137387 ps |
| CPU time | 1.34 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:51:35 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-8af837f5-12e6-4e0b-b154-cc3ef1cb32f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2140016855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2140016855 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.738250886 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 21109038204 ps |
| CPU time | 64.29 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:52:35 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-650f8605-6d55-4fd9-92cc-b5908d2cb662 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=738250886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.738250886 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1293502285 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 7450233008 ps |
| CPU time | 54.02 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-3de3bd1e-bfd0-4e1e-a1e1-d433f3ba257d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1293502285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1293502285 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.4144736474 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 471339692 ps |
| CPU time | 8.64 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:51:42 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-2bc0de6d-025d-48e8-af71-a82699a7bb63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144736474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4144736474 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.561733448 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 49312946 ps |
| CPU time | 4.64 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-565a8bba-c06a-435a-a195-d01be54f170a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561733448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.561733448 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2770947103 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 11053751 ps |
| CPU time | 1.09 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-930ffddc-0db8-464e-a00a-754149120c67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2770947103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2770947103 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3378281985 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3217525125 ps |
| CPU time | 10.88 seconds |
| Started | Feb 29 12:51:33 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-5f74eb4b-9ed5-41bc-8951-c12aa5f25472 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378281985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3378281985 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.207056111 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 669898138 ps |
| CPU time | 5.09 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-f4ae313e-1ca4-4c1f-b71a-b0b0d066c8ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=207056111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.207056111 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2053726726 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 12222294 ps |
| CPU time | 1.03 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:31 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-163893c6-7a48-4b2f-97f6-00cdd451cca4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053726726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2053726726 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2078924809 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 367916984 ps |
| CPU time | 15.35 seconds |
| Started | Feb 29 12:51:38 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-25859541-5389-48b4-8b8a-9f4211e074d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2078924809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2078924809 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1037076269 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 405326054 ps |
| CPU time | 25.85 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-bd7d9f9a-f728-4ab4-b217-09893eadad9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037076269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1037076269 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2390861033 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 428974687 ps |
| CPU time | 40.38 seconds |
| Started | Feb 29 12:51:26 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-5d5398ce-413a-4416-84ed-9628d1694836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390861033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2390861033 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3891727087 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 6495517298 ps |
| CPU time | 158.89 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:54:08 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-b0516c09-a5f9-46f8-8290-d0bce3be8a4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3891727087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3891727087 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.209653893 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 170071318 ps |
| CPU time | 6.44 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-67848695-c9b6-4587-9f0d-bb2a17d01645 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209653893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.209653893 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1059413877 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4427305957 ps |
| CPU time | 19.69 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:50:05 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-3bff83d4-147b-4a6c-8947-4244cdb4d2cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1059413877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1059413877 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.4265722270 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 43675153726 ps |
| CPU time | 200 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:53:05 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-9a0ce57a-af37-4cd5-9fb3-376394281a45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4265722270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.4265722270 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.863676141 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5369200557 ps |
| CPU time | 11.99 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:49:58 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-759dbdca-4b48-4fa5-a248-f2be7be41f65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863676141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.863676141 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.730201943 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 57107641 ps |
| CPU time | 6.56 seconds |
| Started | Feb 29 12:49:37 PM PST 24 |
| Finished | Feb 29 12:49:44 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-18e71c03-99da-4b17-a237-f401743129cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730201943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.730201943 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3013428774 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 564750750 ps |
| CPU time | 7.98 seconds |
| Started | Feb 29 12:49:39 PM PST 24 |
| Finished | Feb 29 12:49:47 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-bed5579d-ec78-4783-94ba-e5237a40f769 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013428774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3013428774 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3894601514 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 23523733419 ps |
| CPU time | 89.56 seconds |
| Started | Feb 29 12:49:36 PM PST 24 |
| Finished | Feb 29 12:51:06 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-747f23fa-6fa6-4cf9-8061-5d7aae09f7c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894601514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3894601514 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.129946520 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6650565941 ps |
| CPU time | 39.39 seconds |
| Started | Feb 29 12:49:41 PM PST 24 |
| Finished | Feb 29 12:50:21 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-689edd0e-a239-4302-b4ef-28026cbbd10d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=129946520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.129946520 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2546988133 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 61971492 ps |
| CPU time | 5.86 seconds |
| Started | Feb 29 12:49:54 PM PST 24 |
| Finished | Feb 29 12:50:00 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-794e5fef-1b10-4621-bf7a-fcc07b2c8e7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546988133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2546988133 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.153013472 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2513205873 ps |
| CPU time | 4.76 seconds |
| Started | Feb 29 12:49:39 PM PST 24 |
| Finished | Feb 29 12:49:44 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-62284cec-30b0-47f0-a958-2f667e99dd30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=153013472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.153013472 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2113616521 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 9559496 ps |
| CPU time | 1.17 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:49:36 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-08ee3a2a-7c52-4971-8a06-a4fbd11850ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2113616521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2113616521 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2326399271 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1396434293 ps |
| CPU time | 7.22 seconds |
| Started | Feb 29 12:49:48 PM PST 24 |
| Finished | Feb 29 12:49:56 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-06e9b84f-76f7-4d30-bb03-15f2b3a7f6a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326399271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2326399271 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4167400519 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 806191852 ps |
| CPU time | 5.26 seconds |
| Started | Feb 29 12:49:41 PM PST 24 |
| Finished | Feb 29 12:49:47 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-7144f44a-8b12-403f-9da5-c2619420e48e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4167400519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4167400519 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3561784392 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 10173007 ps |
| CPU time | 1.38 seconds |
| Started | Feb 29 12:49:48 PM PST 24 |
| Finished | Feb 29 12:49:49 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-f0f8c057-0358-4a4c-9858-5d4c9ca05bf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561784392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3561784392 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.442829702 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8012499719 ps |
| CPU time | 100.58 seconds |
| Started | Feb 29 12:49:36 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 205608 kb |
| Host | smart-fc0fb097-fb90-4a7e-b9ea-093d4ec02c80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=442829702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.442829702 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3038473594 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2634776875 ps |
| CPU time | 34.27 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:50:21 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-f877763d-9252-4b87-b7f2-7019fdea30aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3038473594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3038473594 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.806334886 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 322556114 ps |
| CPU time | 36.17 seconds |
| Started | Feb 29 12:49:42 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 204080 kb |
| Host | smart-5417948e-2f8a-43a1-874b-f43aa98927c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806334886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.806334886 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2029270193 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 274068284 ps |
| CPU time | 5.35 seconds |
| Started | Feb 29 12:49:36 PM PST 24 |
| Finished | Feb 29 12:49:41 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-84f69598-326a-4cab-af38-ef38c0dba308 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2029270193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2029270193 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3554323151 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 328296396 ps |
| CPU time | 4.23 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:36 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-537ef025-a913-4eb6-936e-db6adae6d21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554323151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3554323151 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.287878291 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 190074478 ps |
| CPU time | 3.4 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:33 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-66931915-c835-4447-8887-93306df06c8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=287878291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.287878291 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.811139526 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 42466729 ps |
| CPU time | 4.09 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:36 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3765d3b4-77b9-4eb7-b384-f031d4f9a8a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811139526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.811139526 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2151924174 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 921464089 ps |
| CPU time | 7.68 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-844a67b8-a304-46d4-9077-a48efdd1bf88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2151924174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2151924174 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3358300501 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 58914044683 ps |
| CPU time | 51.6 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:52:37 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-0c288f39-509d-4378-95d1-a8b18cea25ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358300501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3358300501 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1189402964 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4934230015 ps |
| CPU time | 6.54 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-5642bb92-0493-4dbe-bfb6-ef420b79f2c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1189402964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1189402964 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3202850582 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 55991313 ps |
| CPU time | 7.45 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-e3527a68-9e5b-40b5-a296-484144add7c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202850582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3202850582 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3225914487 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 46781354 ps |
| CPU time | 4.49 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-20e15b5c-cb87-48b8-9da6-d222448f1ff3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3225914487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3225914487 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.2901156223 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 335182888 ps |
| CPU time | 1.64 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:28 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-77a84873-ee46-41a6-853b-01c3e5153590 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2901156223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2901156223 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3685417595 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3829827589 ps |
| CPU time | 8.71 seconds |
| Started | Feb 29 12:51:25 PM PST 24 |
| Finished | Feb 29 12:51:35 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-0c0e7cc6-0dd3-4fb5-8f5b-4bbcef7935b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685417595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3685417595 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.493747989 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1219794461 ps |
| CPU time | 5.34 seconds |
| Started | Feb 29 12:51:28 PM PST 24 |
| Finished | Feb 29 12:51:34 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-161dee9e-58e4-46bc-bdd8-8ef3f81abfd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=493747989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.493747989 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3069827466 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 9044856 ps |
| CPU time | 1.15 seconds |
| Started | Feb 29 12:51:22 PM PST 24 |
| Finished | Feb 29 12:51:23 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-481d4f3d-6331-4559-a192-6e5fe315a3e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069827466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3069827466 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.739743977 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 100760129 ps |
| CPU time | 6.11 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:39 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-085c482a-6a7b-4fac-87eb-7c1c81ca7482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739743977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.739743977 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1439279416 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 50516439 ps |
| CPU time | 3.43 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-d83a9e21-450d-4066-bdad-f9a46046f3a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1439279416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1439279416 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2511479359 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 417136022 ps |
| CPU time | 73.62 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:52:48 PM PST 24 |
| Peak memory | 206240 kb |
| Host | smart-5398c23c-4044-45d0-a39a-6bb804899cc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2511479359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2511479359 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.367702028 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2060366496 ps |
| CPU time | 83.74 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:52:59 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-a285b0f9-0aaa-4e4e-8b86-273db385de2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=367702028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.367702028 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.481142875 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 175928573 ps |
| CPU time | 3.93 seconds |
| Started | Feb 29 12:51:39 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-1777cf8b-2b8e-4dbc-8221-8171f7e953e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=481142875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.481142875 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1467590079 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 892025897 ps |
| CPU time | 7.15 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b8497dae-7514-49ee-8b28-2a0b2a93838c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467590079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1467590079 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.275950176 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 25991999252 ps |
| CPU time | 67.22 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:52:40 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-161d200b-4f35-4abb-927b-ffea9f4dbbb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=275950176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.275950176 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2954222358 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 569647829 ps |
| CPU time | 7.91 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:38 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-02486d8d-23b8-419d-a7d5-4a1456a959d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2954222358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2954222358 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.2503789924 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 679449023 ps |
| CPU time | 3.98 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-ef47b4a9-3c2e-4ac9-868a-57e7f4f80280 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2503789924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2503789924 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2125729948 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 24861971 ps |
| CPU time | 1.14 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:32 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-a9e3bc4a-e8bf-47d1-84c2-7d79dfb3879a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2125729948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2125729948 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2202463417 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 43254668046 ps |
| CPU time | 152.29 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:54:07 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-8ac3691c-bda4-4d1a-95a6-0333104db550 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202463417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2202463417 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.465616648 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6720813982 ps |
| CPU time | 25.65 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-6481b630-5c95-4487-bfe2-90292c95912e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=465616648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.465616648 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1554952991 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 73448198 ps |
| CPU time | 4.94 seconds |
| Started | Feb 29 12:51:38 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-6b9d7323-12a3-4359-82be-3efd329d6f4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554952991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1554952991 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.3661500637 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 5595165723 ps |
| CPU time | 11.08 seconds |
| Started | Feb 29 12:51:29 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-54ecbf17-f2ec-4f44-ab5a-53abc5a04bdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661500637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3661500637 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.3251267941 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 262594603 ps |
| CPU time | 1.57 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:35 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-845e2640-28c7-495a-b315-c1f9aad189ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251267941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3251267941 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3339282060 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2795801160 ps |
| CPU time | 10.4 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:45 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-4ed729ef-436c-4991-aaed-01a9098605bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339282060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3339282060 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3356289429 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 975196334 ps |
| CPU time | 6.6 seconds |
| Started | Feb 29 12:51:43 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-07d71c48-b61f-4a40-ae49-38ac81d5d496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3356289429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3356289429 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3876149100 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8151833 ps |
| CPU time | 1.07 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:37 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-4cd0e23f-1039-41d0-ade5-76845d0721b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876149100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3876149100 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.631622897 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1022717540 ps |
| CPU time | 18.41 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-7166b4fb-12c0-45af-a5c1-e2a83787eb7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=631622897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.631622897 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2377011386 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2288391483 ps |
| CPU time | 5.19 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-07620fc5-4067-4725-b92e-9ab8cb363e07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377011386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2377011386 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1043454578 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2589493904 ps |
| CPU time | 35.21 seconds |
| Started | Feb 29 12:51:31 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-075ce8c3-e699-4632-83fa-335060b53c1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1043454578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1043454578 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3568245465 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 11348666361 ps |
| CPU time | 135.13 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:53:46 PM PST 24 |
| Peak memory | 206960 kb |
| Host | smart-3f2f9584-c386-4a04-a12b-e97f6219f290 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3568245465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3568245465 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3895479162 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1855479538 ps |
| CPU time | 10.56 seconds |
| Started | Feb 29 12:51:32 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-c8550fe8-fb38-4be4-9c65-bcec467c6648 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3895479162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3895479162 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2275946071 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 84193758 ps |
| CPU time | 2.98 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-f308b4a4-dd14-469c-bfdf-3fd8c424c492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275946071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2275946071 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3212968032 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 30045150704 ps |
| CPU time | 170.53 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:54:25 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-cdd408c9-ed7b-42b9-958f-e9de4853c7a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3212968032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.3212968032 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3941782639 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 103757121 ps |
| CPU time | 4.2 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-ca21e783-4e8e-4b27-842a-c5c6f61b8127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3941782639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3941782639 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.1809557754 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 52062700 ps |
| CPU time | 4.79 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-3ecad37c-1ed4-4f25-ac62-5034ffc45b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1809557754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1809557754 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.981020602 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 119615668 ps |
| CPU time | 7.45 seconds |
| Started | Feb 29 12:51:37 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ad7cf1f6-a54a-4072-b9e3-48be029d446d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981020602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.981020602 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3830409602 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 20266443534 ps |
| CPU time | 32.85 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:52:09 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-008b1040-f57e-4b39-a894-b33eb4b207f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830409602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3830409602 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3237713211 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 15312287504 ps |
| CPU time | 53.78 seconds |
| Started | Feb 29 12:51:47 PM PST 24 |
| Finished | Feb 29 12:52:41 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-878495f8-191a-4376-bf94-d6bf3a4b1ecb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3237713211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3237713211 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1339592294 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 74170379 ps |
| CPU time | 4.26 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:40 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-1be550e0-9958-4d71-b37c-8e76caaaca86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339592294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1339592294 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.3061908085 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 41997773 ps |
| CPU time | 3.35 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:38 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-2f02379d-bea0-435b-b8a0-0594419a4202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3061908085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3061908085 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3769348154 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 111594461 ps |
| CPU time | 1.82 seconds |
| Started | Feb 29 12:51:43 PM PST 24 |
| Finished | Feb 29 12:51:44 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-938a4f37-d1d0-4ab5-a90a-142e1eec9291 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769348154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3769348154 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1477558502 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4333339631 ps |
| CPU time | 6.4 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:42 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-c4595963-7fdb-4744-9614-bbac04efa37b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477558502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1477558502 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.350717228 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 946027445 ps |
| CPU time | 6.57 seconds |
| Started | Feb 29 12:51:49 PM PST 24 |
| Finished | Feb 29 12:51:56 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-161ef23a-8612-47c8-955e-2c030674f614 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=350717228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.350717228 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2839464040 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 10189289 ps |
| CPU time | 1.17 seconds |
| Started | Feb 29 12:51:34 PM PST 24 |
| Finished | Feb 29 12:51:36 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-e718e8ab-24ec-4475-924e-9ec3cddc5a86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839464040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2839464040 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.740861268 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3835888108 ps |
| CPU time | 17.68 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-48197200-4935-401c-894e-a0fe1a505d56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=740861268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.740861268 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1220241637 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 177598166 ps |
| CPU time | 14.04 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-d2042bb3-5b92-4780-8618-027659dafdcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220241637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1220241637 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3822650819 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1359863517 ps |
| CPU time | 83.4 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:53:10 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-003f41bf-955c-460f-8a33-e7bce9b271ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822650819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3822650819 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.485366436 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 425451476 ps |
| CPU time | 30.82 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-4b987785-761c-4704-b5e2-6c370f443517 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=485366436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res et_error.485366436 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2080580298 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 307017820 ps |
| CPU time | 7.62 seconds |
| Started | Feb 29 12:51:35 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-8cdca2a1-841c-4f8b-b23c-b3194b1e624b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080580298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2080580298 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.684045080 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 576220273 ps |
| CPU time | 13.18 seconds |
| Started | Feb 29 12:51:37 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-db5a2f62-c07a-407e-9b84-3072453037d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=684045080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.684045080 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2316732106 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 76305679071 ps |
| CPU time | 289.72 seconds |
| Started | Feb 29 12:51:47 PM PST 24 |
| Finished | Feb 29 12:56:37 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-236890ed-ffca-47cb-ab12-3bc36ac83673 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2316732106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2316732106 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3910132636 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1445661831 ps |
| CPU time | 4.1 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-faffdc73-ee97-4e17-bbf3-bfbbba9835f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3910132636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3910132636 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2109644859 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 58959996 ps |
| CPU time | 2.31 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-12c56023-2a40-4966-8d64-7f35201c0a6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2109644859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2109644859 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.1201425254 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 656718165 ps |
| CPU time | 9.91 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-a183bb8e-d829-4b20-b0f4-7346ce91c41d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1201425254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1201425254 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3741999107 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 56545170558 ps |
| CPU time | 129.03 seconds |
| Started | Feb 29 12:51:38 PM PST 24 |
| Finished | Feb 29 12:53:48 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-fa9d38f7-a575-4ea4-9be8-8429e4b34e52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741999107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3741999107 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2006330510 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 16512140966 ps |
| CPU time | 116.02 seconds |
| Started | Feb 29 12:51:37 PM PST 24 |
| Finished | Feb 29 12:53:33 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-aa282bd9-0acf-45d7-ae34-09b6e5e83f39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2006330510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2006330510 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1965696484 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 153270298 ps |
| CPU time | 6.37 seconds |
| Started | Feb 29 12:51:38 PM PST 24 |
| Finished | Feb 29 12:51:45 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-ff2250d6-5da2-4739-a2fc-91837d65f2ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965696484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1965696484 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2492736012 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 29408572 ps |
| CPU time | 3.19 seconds |
| Started | Feb 29 12:51:44 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-06ccf103-0741-40f7-bccb-74284ce0ba47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492736012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2492736012 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.4211999609 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 51105509 ps |
| CPU time | 1.46 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-004aeffb-11b0-4a63-86b9-002d46524e5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4211999609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4211999609 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4044599683 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3679816122 ps |
| CPU time | 10.78 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:52:03 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-4c54148f-3333-489e-abd2-1418207be604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044599683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4044599683 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1257333343 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2411449047 ps |
| CPU time | 6.42 seconds |
| Started | Feb 29 12:51:39 PM PST 24 |
| Finished | Feb 29 12:51:46 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-6d15b740-36a8-46a1-b14b-6b4b50b2ad22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1257333343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1257333343 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2996534651 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 9667634 ps |
| CPU time | 1.1 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:46 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-c9545d23-ccdc-48eb-9fde-726e79db0039 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996534651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2996534651 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1935917636 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5336404646 ps |
| CPU time | 21.14 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:52:11 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-2e5edc8f-2981-4eac-b818-db3c3b450963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1935917636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1935917636 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3370688656 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 188720942 ps |
| CPU time | 15.52 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-c42c3320-a30c-47cc-bb3a-22e79247cfb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370688656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3370688656 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3195536018 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2414831596 ps |
| CPU time | 77.44 seconds |
| Started | Feb 29 12:52:04 PM PST 24 |
| Finished | Feb 29 12:53:27 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-10d8e1d8-4cdf-43c8-9ebf-e36bcd4694ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3195536018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3195536018 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2322599925 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 17650658 ps |
| CPU time | 2.17 seconds |
| Started | Feb 29 12:51:55 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-c64b8903-29c5-48e9-a0b1-8bd297a945e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322599925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2322599925 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3850650389 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 260635006 ps |
| CPU time | 5.48 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-54f8ce76-5d7b-4368-93b9-4a56cb0cb6b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3850650389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3850650389 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.940066531 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 535514126 ps |
| CPU time | 8.87 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-d7cca8b7-35e6-4a14-a4a4-71a7b17a678a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=940066531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.940066531 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1258265945 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1749958494 ps |
| CPU time | 5.89 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-a7669e37-6c05-40a4-9e61-41bdd751037c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258265945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1258265945 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.916056699 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1464786857 ps |
| CPU time | 4.05 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-2c82f0bd-3520-4534-8f22-42390789d82c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=916056699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.916056699 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.988543532 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 29659385 ps |
| CPU time | 2.48 seconds |
| Started | Feb 29 12:51:56 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-c02ab36a-6e3f-42bb-a511-049bdcc19c14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=988543532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.988543532 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3959095922 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 55473223324 ps |
| CPU time | 56.38 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:52:45 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-b2f0379c-c658-4b94-b403-02d59035bf88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959095922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3959095922 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.4162556814 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 105003739792 ps |
| CPU time | 102.77 seconds |
| Started | Feb 29 12:51:54 PM PST 24 |
| Finished | Feb 29 12:53:37 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-b6cb56e1-d390-40e8-8656-df0f4cad5e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4162556814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4162556814 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2280825385 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 60422742 ps |
| CPU time | 6.5 seconds |
| Started | Feb 29 12:52:03 PM PST 24 |
| Finished | Feb 29 12:52:10 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-f528c029-7757-471f-bd6e-136298e8cae0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280825385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2280825385 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.173833123 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 65710961 ps |
| CPU time | 3.17 seconds |
| Started | Feb 29 12:52:00 PM PST 24 |
| Finished | Feb 29 12:52:03 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-d9282d0a-7fcb-4f92-87ce-f55486521181 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173833123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.173833123 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.4199864537 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 49071928 ps |
| CPU time | 1.34 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:50 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-0eb17c47-4d2c-4487-8363-4bb38bd6392a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4199864537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4199864537 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2286022960 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2633099219 ps |
| CPU time | 7.38 seconds |
| Started | Feb 29 12:51:44 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-39ee92ed-cf33-4368-b492-67ed20e35731 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286022960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2286022960 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1644568089 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1567971338 ps |
| CPU time | 8.34 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-2ebbdb5b-97bf-4041-8d38-522d4d5dbba2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1644568089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1644568089 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2950703936 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 14024389 ps |
| CPU time | 1.1 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:51:47 PM PST 24 |
| Peak memory | 202104 kb |
| Host | smart-77d9f19a-4d3a-430e-9168-f0bbe6a6219b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950703936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2950703936 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2697532231 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3839793521 ps |
| CPU time | 70.75 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:53:10 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-46946775-af31-4381-a51b-26552ade1991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2697532231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2697532231 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2864024127 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2647417383 ps |
| CPU time | 28.11 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-8d5f423a-41ca-4c1e-943f-1869a8f41921 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864024127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2864024127 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.61111399 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 91178531 ps |
| CPU time | 12.14 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-75cdb3ae-9660-4203-98c3-7b7103057075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61111399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_ reset.61111399 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.276745328 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 10518187318 ps |
| CPU time | 203.6 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:55:14 PM PST 24 |
| Peak memory | 207464 kb |
| Host | smart-03e3086b-55f6-46e9-a3de-306e5d225047 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276745328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.276745328 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3523914023 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 415267291 ps |
| CPU time | 7.19 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-3c767dc7-c4df-4022-af9c-c5bb27f3e6bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3523914023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3523914023 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1372689748 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 923797032 ps |
| CPU time | 18.15 seconds |
| Started | Feb 29 12:51:47 PM PST 24 |
| Finished | Feb 29 12:52:10 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-087c7ad8-6146-40cd-9aa7-86b9d0671e6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1372689748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1372689748 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1921679954 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 105354294 ps |
| CPU time | 4.48 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-806deef5-7839-4953-86c3-df5a4e2799c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1921679954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1921679954 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.3014825552 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 793535186 ps |
| CPU time | 7.86 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-3cdd36af-ec12-4812-af9d-a27e6e89a583 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3014825552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3014825552 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.4265700331 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 18321407 ps |
| CPU time | 1.04 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-88c13303-291b-4ca1-ba7d-a04bc1728f02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4265700331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.4265700331 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.404539891 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 6960135305 ps |
| CPU time | 31.52 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:33 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-4addba3f-8d9c-4cb9-97f5-2468bdd0100b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=404539891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.404539891 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.567339399 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 18816018509 ps |
| CPU time | 115.96 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:53:55 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-c7c74f17-e5c8-4603-bcda-ad8839e46560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=567339399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.567339399 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1254208302 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 122982441 ps |
| CPU time | 5.31 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-9b644b52-5043-443c-a3bf-b1914d08bf79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254208302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1254208302 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1176728876 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 400170630 ps |
| CPU time | 2.81 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:48 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-bb75d72c-62d0-47c5-be36-f086f3987cf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176728876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1176728876 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.4040277494 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 16484487 ps |
| CPU time | 1.09 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:49 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-8226fba5-9b10-4a1a-8b85-cd856bac8519 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040277494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4040277494 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1995764670 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1794739935 ps |
| CPU time | 7.27 seconds |
| Started | Feb 29 12:51:47 PM PST 24 |
| Finished | Feb 29 12:51:54 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-c125caa0-17b3-46c7-9480-ac18394d2a72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995764670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1995764670 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1072727201 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4135754546 ps |
| CPU time | 10.78 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-6b7285e4-648a-4365-83cc-3a216fdaa66a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1072727201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1072727201 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3562465755 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 10595493 ps |
| CPU time | 1.19 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:49 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-e611a53f-a5f0-4534-9b8a-9a61678bdc76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562465755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3562465755 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3847128282 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 568727415 ps |
| CPU time | 60.37 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:59 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-226a993d-782e-4f91-9f27-bd6923ee498a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3847128282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3847128282 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3036642806 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1780631122 ps |
| CPU time | 14.33 seconds |
| Started | Feb 29 12:51:30 PM PST 24 |
| Finished | Feb 29 12:51:45 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-db480349-c577-412d-9c5d-a292f47ecd4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036642806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3036642806 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.156229855 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5603732470 ps |
| CPU time | 151.86 seconds |
| Started | Feb 29 12:51:38 PM PST 24 |
| Finished | Feb 29 12:54:10 PM PST 24 |
| Peak memory | 207444 kb |
| Host | smart-9ea75d54-5956-4cdd-b869-e4ab4954d3b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156229855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.156229855 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3379391491 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6409144886 ps |
| CPU time | 138.21 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:54:06 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-6faa3055-cf6f-459e-8457-451fff1dcc29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379391491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3379391491 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.102650253 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 184170337 ps |
| CPU time | 2.39 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-4a501592-8504-4207-b2d6-afb0439ac24d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=102650253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.102650253 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3635412712 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 170550202 ps |
| CPU time | 7.78 seconds |
| Started | Feb 29 12:51:44 PM PST 24 |
| Finished | Feb 29 12:51:52 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-06c3d849-7095-4723-9718-5ab741182a60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635412712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3635412712 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1616622628 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 15613691712 ps |
| CPU time | 104.79 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:53:41 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-d94dd429-5a6d-406c-b7a9-fae6705e20de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1616622628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1616622628 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4236036861 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 14712865 ps |
| CPU time | 1.56 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:18 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-faeae070-6ba3-4783-a407-115509f12fef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4236036861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4236036861 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.4051216467 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 16099167 ps |
| CPU time | 1.27 seconds |
| Started | Feb 29 12:51:55 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-d83cb55a-0fd1-4af1-a463-59e623d69779 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4051216467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4051216467 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.1312520359 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 40763905 ps |
| CPU time | 2.64 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-fd76b9a0-8eb6-4a2c-850c-2b8d0228e600 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1312520359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1312520359 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.258302990 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 41204960464 ps |
| CPU time | 191.41 seconds |
| Started | Feb 29 12:51:39 PM PST 24 |
| Finished | Feb 29 12:54:51 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-9ff0efdf-49f8-40d8-81a9-91abaf3b225a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=258302990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.258302990 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1745131683 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 13271001856 ps |
| CPU time | 50.82 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-e6efcb3e-fe5d-4f3b-a791-97b1dd895411 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1745131683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1745131683 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.834535902 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 66109314 ps |
| CPU time | 2.91 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-d1701170-01a5-4db7-a7eb-7fc9892a0429 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834535902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.834535902 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.52104445 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 55070432 ps |
| CPU time | 2.01 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:47 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b57ab191-e9bd-4c5b-aad1-c2558e9676e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52104445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.52104445 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2485937632 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 275348154 ps |
| CPU time | 1.5 seconds |
| Started | Feb 29 12:52:03 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-52bab7dd-4f28-4d35-8d9b-c23da8eb238f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2485937632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2485937632 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3462500026 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5028276836 ps |
| CPU time | 9.97 seconds |
| Started | Feb 29 12:52:00 PM PST 24 |
| Finished | Feb 29 12:52:10 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-fad34e62-fa3a-43ff-abc1-e870645864e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462500026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3462500026 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2054071266 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2774015613 ps |
| CPU time | 12.67 seconds |
| Started | Feb 29 12:51:36 PM PST 24 |
| Finished | Feb 29 12:51:49 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-c822644f-930d-4c1f-9835-6fbec453f221 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2054071266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2054071266 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.149984151 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 23151444 ps |
| CPU time | 1.11 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-c7ad4bd6-1897-44bc-ad6e-e4937d852978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149984151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.149984151 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3755569271 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 9332613354 ps |
| CPU time | 72.4 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:53:30 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-8f8d5f4f-9a9f-4519-b4b9-20510a3a2b5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3755569271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3755569271 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3997878153 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 25669822824 ps |
| CPU time | 62.02 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:52:54 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-fdbd1a41-b1ed-491a-a0e1-59de6efd6e86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3997878153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3997878153 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.996356511 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 95738795 ps |
| CPU time | 31.14 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-216d5d98-65e5-487a-ac6f-db6a5daac399 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=996356511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.996356511 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2664288854 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 472983433 ps |
| CPU time | 60.57 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:53:17 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-cb572f70-6923-4033-a672-f813fcfaaaca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664288854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2664288854 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2564710579 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 25047987 ps |
| CPU time | 2.2 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:19 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-2d42351a-e21c-4355-af84-c1397df1ee45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2564710579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2564710579 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2288708903 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 40134801 ps |
| CPU time | 5 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:03 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-79bed214-2240-4527-af64-50afbaf3cb13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288708903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2288708903 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1612544388 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 16339227802 ps |
| CPU time | 110.43 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:53:52 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-f27701b9-6c13-43da-a03e-06a747ca43c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1612544388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1612544388 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.219458696 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 559537407 ps |
| CPU time | 8.96 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:06 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-46bf42db-72fa-4efe-a1ca-2fa6d2a95f96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=219458696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.219458696 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1733475183 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 133711324 ps |
| CPU time | 5.26 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:51:59 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-453b0c6c-a7e6-487c-b8ff-be37df228800 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1733475183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1733475183 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.877655265 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 218354490 ps |
| CPU time | 3 seconds |
| Started | Feb 29 12:51:44 PM PST 24 |
| Finished | Feb 29 12:51:47 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-054e82db-7141-4586-ab70-869967bd4411 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877655265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.877655265 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3569469770 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 77269859724 ps |
| CPU time | 196.06 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:55:13 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-56f264c2-796a-441c-81ad-c5d1c7de2b2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569469770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3569469770 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1980805229 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 91642703544 ps |
| CPU time | 96.44 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:53:28 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-5d115a08-568f-4241-8bfd-a9fc577920d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1980805229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1980805229 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2160566097 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 22562650 ps |
| CPU time | 2.03 seconds |
| Started | Feb 29 12:51:41 PM PST 24 |
| Finished | Feb 29 12:51:43 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-9ae880c0-0d4e-4714-a5a3-326271832541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160566097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2160566097 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.4250417029 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2499258549 ps |
| CPU time | 5.99 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b0c4be5a-d906-42af-ad64-549dd96f041a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4250417029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4250417029 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.4214638418 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 82828884 ps |
| CPU time | 1.47 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-e1e89b46-2978-4004-9d94-c20490efda65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4214638418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.4214638418 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3647380090 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4333110884 ps |
| CPU time | 10.73 seconds |
| Started | Feb 29 12:51:42 PM PST 24 |
| Finished | Feb 29 12:51:53 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-fe485574-0f58-4536-b118-1ad9fe6e692c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647380090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3647380090 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1065412500 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1125932389 ps |
| CPU time | 6.42 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-8dbe9c79-afda-49d7-b156-a7f5e8f7514d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1065412500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1065412500 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3627299883 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 10453717 ps |
| CPU time | 1.23 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-c75f8cf4-2df2-4ee9-b325-8f9c369818d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627299883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3627299883 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.564807450 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 508613555 ps |
| CPU time | 50.18 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:53 PM PST 24 |
| Peak memory | 205600 kb |
| Host | smart-61d62314-bdf8-46d7-9c42-2cfcb51c9a1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=564807450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.564807450 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.181482810 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1789775967 ps |
| CPU time | 27.81 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:52:33 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-fc223022-d2af-4dcd-8f11-7ea464a6f19f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=181482810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.181482810 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3931817998 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 191232259 ps |
| CPU time | 29.45 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:28 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-05f66077-8e7a-4364-a843-6dfc70f28332 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3931817998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3931817998 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1451593460 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 619991472 ps |
| CPU time | 67.11 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:53:15 PM PST 24 |
| Peak memory | 204392 kb |
| Host | smart-611a722c-b177-40fd-a576-743d4069ffd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451593460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1451593460 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3144429126 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 50449457 ps |
| CPU time | 2.88 seconds |
| Started | Feb 29 12:51:49 PM PST 24 |
| Finished | Feb 29 12:51:52 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-7f0b0d72-871c-4051-ba95-800ec909f52f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3144429126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3144429126 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3171576328 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 66956180 ps |
| CPU time | 6.93 seconds |
| Started | Feb 29 12:51:54 PM PST 24 |
| Finished | Feb 29 12:52:01 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-b2042a5f-131d-4850-995f-eff20c625e7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3171576328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3171576328 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.25996159 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 39881210358 ps |
| CPU time | 113.04 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:53:52 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-6026c562-1259-4c7e-94e9-831b756c7115 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=25996159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow _rsp.25996159 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3830225460 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 36008253 ps |
| CPU time | 2.48 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-b02910a3-02db-4916-80a3-2ab44b4927ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3830225460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3830225460 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2545754018 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1072549129 ps |
| CPU time | 11.25 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:22 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-c9feeb08-4d9d-43f2-8ab8-cee5e239daca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545754018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2545754018 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2751263543 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 104235698 ps |
| CPU time | 8.48 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-4a313dbb-d361-47b7-a69d-a6bdbca0a063 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751263543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2751263543 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2404790420 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4980451885 ps |
| CPU time | 19.98 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-a80379e5-ef9f-4775-82e1-90d633d77d74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404790420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2404790420 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2085099258 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 8263119432 ps |
| CPU time | 15.56 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-dc0e0076-3d22-48b1-846f-143c12528801 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2085099258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2085099258 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1381632639 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 131880524 ps |
| CPU time | 6.33 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:51:52 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-6a45d412-29c2-47bc-9e5c-ca700bcc21d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381632639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1381632639 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.708797821 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 257571663 ps |
| CPU time | 2.81 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-15325c59-bfd1-4101-a1d3-0706398fb2bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708797821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.708797821 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1192355020 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 9677527 ps |
| CPU time | 1.22 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:51:52 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-41a7ce12-7656-460d-8701-7309d9dc0352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1192355020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1192355020 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2987929141 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1992545190 ps |
| CPU time | 9.67 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-394d31ca-b6a3-4a4a-8016-4397b7f61daa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987929141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2987929141 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3362959128 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1289731151 ps |
| CPU time | 8.28 seconds |
| Started | Feb 29 12:51:54 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-964bff59-119c-4062-b245-bf4c644f0305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3362959128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3362959128 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3007813944 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 15947644 ps |
| CPU time | 1.18 seconds |
| Started | Feb 29 12:51:54 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-8e4a33ed-e9cb-4852-b6d8-140ae610a759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007813944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3007813944 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2708771033 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 6462695778 ps |
| CPU time | 96.82 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:53:27 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-5595551d-837a-49fc-ad38-15ae43de9fca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2708771033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2708771033 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3498544033 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 4640198984 ps |
| CPU time | 31.8 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-1f52eb00-b13b-4bae-bfab-74bcb348c2b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498544033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3498544033 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2642045325 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1556817886 ps |
| CPU time | 56.99 seconds |
| Started | Feb 29 12:51:50 PM PST 24 |
| Finished | Feb 29 12:52:47 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-3cb5e622-9b8b-4580-b826-f03a90eb2135 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2642045325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2642045325 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2893402999 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3862874897 ps |
| CPU time | 112.22 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:53:51 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-18c4256c-7d8c-4a26-9439-9bc6f9000f76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2893402999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2893402999 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1858541737 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 265869920 ps |
| CPU time | 4.88 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:51:58 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-e69b02fe-40e7-4e02-a2a0-e6a633104b58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1858541737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1858541737 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1199304354 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 59279398 ps |
| CPU time | 9.26 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-84aac980-6ba9-4b06-9fd5-f83bf889182e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1199304354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1199304354 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3546580135 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 138135728908 ps |
| CPU time | 310.66 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:57:25 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-37fb4850-a9d3-4911-9b7d-b61b9b40a851 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3546580135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3546580135 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1432714696 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 506749183 ps |
| CPU time | 5.44 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-bb209dd2-1607-4d50-9975-e0da11ef4d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432714696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1432714696 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3298601721 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 376446721 ps |
| CPU time | 6.33 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-682aa137-c27d-44a8-9225-5e6cb1d0e2fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3298601721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3298601721 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.314981547 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 127312281 ps |
| CPU time | 8.2 seconds |
| Started | Feb 29 12:51:55 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-9485e9e3-8944-4eb7-98d1-9052d4791b43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=314981547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.314981547 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1872461951 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 35815741768 ps |
| CPU time | 157.06 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:54:37 PM PST 24 |
| Peak memory | 202828 kb |
| Host | smart-41c880d5-7da2-402c-9572-e4897b7bcf65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872461951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1872461951 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3197842364 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 107980059170 ps |
| CPU time | 144.8 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:54:41 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-939156c4-cd85-4192-8870-4b2c9d2424f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3197842364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3197842364 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.95415745 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 50108806 ps |
| CPU time | 4.36 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-85f2cfd9-54bb-4942-9c8c-bb78a9264a3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95415745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.95415745 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1004805011 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 107205994 ps |
| CPU time | 3.42 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:22 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-d99127a0-4e96-46f5-88de-cf28707e992b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1004805011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1004805011 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3023046819 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 44009597 ps |
| CPU time | 1.37 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:11 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-2c3938e0-55a7-423f-8fc0-faabede8a1bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3023046819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3023046819 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1031725814 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2661414432 ps |
| CPU time | 11.16 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-1d063aa5-15ca-45a5-95a2-a9324eba6a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031725814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1031725814 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2713746879 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1783312933 ps |
| CPU time | 12.85 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-abc8da2b-1a60-4e99-bd2e-616c34434707 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2713746879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2713746879 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2748092172 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 8751351 ps |
| CPU time | 1 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-2dc875ca-3bba-401b-8936-a99c87df7c3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748092172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2748092172 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3223883616 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4882842104 ps |
| CPU time | 59.2 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:53:07 PM PST 24 |
| Peak memory | 204020 kb |
| Host | smart-2fa4fb56-1115-4fe6-9e01-a7357907ac40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3223883616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3223883616 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2167635237 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 115105903 ps |
| CPU time | 10.81 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-c37d8430-2676-4ef8-8f35-a1419890c3af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167635237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2167635237 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2549360048 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5608131805 ps |
| CPU time | 86.87 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:53:25 PM PST 24 |
| Peak memory | 205036 kb |
| Host | smart-ed99cbb7-dbed-4c3b-9492-d12ba1edbadd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549360048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.2549360048 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2139633696 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 581019713 ps |
| CPU time | 56.43 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:53:10 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-ce348c43-42f2-4f81-9d94-6be7b66b0ed0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2139633696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2139633696 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3832950404 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1002770870 ps |
| CPU time | 10.19 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-fd82a2b3-e539-4316-b2b6-9f03d4a9d0d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3832950404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3832950404 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.529799893 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 53522046 ps |
| CPU time | 1.79 seconds |
| Started | Feb 29 12:49:40 PM PST 24 |
| Finished | Feb 29 12:49:43 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-9c14bdda-10f8-439f-8c3f-4885d08afcca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529799893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.529799893 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1386216522 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 57154689888 ps |
| CPU time | 311.34 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:54:56 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-84a522c9-bef6-4dc2-96d9-08579bfd0559 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1386216522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1386216522 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3780884480 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 54514438 ps |
| CPU time | 6.18 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:49:41 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-5c06680b-9082-4ff4-8e8b-e1dbb7a0d68d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780884480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3780884480 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.650962190 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 867895659 ps |
| CPU time | 11.32 seconds |
| Started | Feb 29 12:49:38 PM PST 24 |
| Finished | Feb 29 12:49:49 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-7d5df140-8d88-4439-973c-2396a5bc0c16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=650962190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.650962190 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3614261919 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 40870089 ps |
| CPU time | 3.97 seconds |
| Started | Feb 29 12:49:51 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-476bc373-b50c-4db3-94cb-099608c5a66a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3614261919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3614261919 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1326172883 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 11540068436 ps |
| CPU time | 11.37 seconds |
| Started | Feb 29 12:49:36 PM PST 24 |
| Finished | Feb 29 12:49:47 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-61f07ac2-1ed2-40b5-90d4-f4b29bd9cb49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326172883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1326172883 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3922076513 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 21270216641 ps |
| CPU time | 155.66 seconds |
| Started | Feb 29 12:49:37 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-5fae1a64-3955-431e-9d9a-1657078ecf62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3922076513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3922076513 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1544314311 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 50751288 ps |
| CPU time | 4.08 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:49:50 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-84cefeba-3b99-4f2e-853a-f8ed79864f9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544314311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1544314311 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.3408482426 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 942060950 ps |
| CPU time | 5.23 seconds |
| Started | Feb 29 12:49:42 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-e5df164d-fa03-4d99-855a-2cd7cf693254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3408482426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3408482426 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3219678497 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 59097318 ps |
| CPU time | 1.6 seconds |
| Started | Feb 29 12:49:55 PM PST 24 |
| Finished | Feb 29 12:49:57 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-c0cb3502-9c57-4067-8ed4-8195e30a62cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3219678497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3219678497 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1380775223 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1850867225 ps |
| CPU time | 8.94 seconds |
| Started | Feb 29 12:49:40 PM PST 24 |
| Finished | Feb 29 12:49:50 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-8acaeb12-1fd5-4d51-866b-377d64f76a27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380775223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1380775223 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1546125670 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2236486472 ps |
| CPU time | 10.8 seconds |
| Started | Feb 29 12:49:49 PM PST 24 |
| Finished | Feb 29 12:49:59 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-82e10716-42a9-4bda-9f30-1929e21228a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1546125670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1546125670 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3705272204 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 10137699 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:49:53 PM PST 24 |
| Finished | Feb 29 12:49:54 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-7ba94a56-dfce-4b75-9f44-6ea38ceb56de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705272204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3705272204 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1131896509 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3110580809 ps |
| CPU time | 24.41 seconds |
| Started | Feb 29 12:49:42 PM PST 24 |
| Finished | Feb 29 12:50:07 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-3270c3c8-935b-4fd5-b961-b30aa24ab7e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1131896509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1131896509 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.262947697 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 93601399 ps |
| CPU time | 9.91 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:49:54 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-338554d0-b4c0-44e1-9b67-55ab9f915afc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=262947697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.262947697 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3055679298 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 670765176 ps |
| CPU time | 63.47 seconds |
| Started | Feb 29 12:49:49 PM PST 24 |
| Finished | Feb 29 12:50:52 PM PST 24 |
| Peak memory | 205152 kb |
| Host | smart-f92e4268-c0eb-45ea-a311-4c25d412451e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3055679298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.3055679298 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1034905482 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1653772442 ps |
| CPU time | 140.85 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:52:08 PM PST 24 |
| Peak memory | 209320 kb |
| Host | smart-493d0c5f-9c64-41cf-b22c-b40e99a85e6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034905482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1034905482 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.920622421 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 431134046 ps |
| CPU time | 3.07 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:50 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-03fa7b3f-bdd5-4bba-8103-9d0f6f0319cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=920622421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.920622421 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4088236205 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 158056104 ps |
| CPU time | 3.03 seconds |
| Started | Feb 29 12:52:04 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-7b48cf1c-d6e9-4a7d-9899-f07e09bda619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4088236205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4088236205 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3295698678 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 10677260448 ps |
| CPU time | 47.76 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:58 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-8a11a085-0598-400b-a5a1-e6354064d0d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3295698678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3295698678 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2724366629 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 106103097 ps |
| CPU time | 4.37 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-3d7e52f6-5325-4304-9408-eecc6167192e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2724366629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2724366629 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.407948053 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 859444423 ps |
| CPU time | 3.51 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:52:27 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-65e8e857-56f9-40d0-b15f-40c850f018cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407948053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.407948053 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3367618713 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 710818408 ps |
| CPU time | 9.35 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-90097f74-4d7a-475a-af0f-846cd89bcb51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3367618713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3367618713 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2978011510 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 44266406582 ps |
| CPU time | 106.49 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:53:49 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-4e66fb54-d97b-48e6-9700-5662efb37439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978011510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2978011510 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2655471045 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 14298645040 ps |
| CPU time | 89.15 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:53:37 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-50789f6a-e499-48a2-9388-f7af3e6e11ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2655471045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2655471045 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.310043851 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 142653609 ps |
| CPU time | 6.24 seconds |
| Started | Feb 29 12:52:06 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-77fd5fae-8772-49a7-9097-8e666e85c752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310043851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.310043851 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3289582674 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1698529635 ps |
| CPU time | 13.61 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-271ce8ef-d603-4d29-8963-f210c5603ee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3289582674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3289582674 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2581375576 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 109072893 ps |
| CPU time | 1.56 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-c93e3801-263a-476d-adf5-ddea4e48373e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581375576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2581375576 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2917681586 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4168151454 ps |
| CPU time | 9.22 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-90cfcb0d-a44e-47cc-8aa6-ec3f05d3a444 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917681586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2917681586 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3287032013 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3953659824 ps |
| CPU time | 14.47 seconds |
| Started | Feb 29 12:52:04 PM PST 24 |
| Finished | Feb 29 12:52:19 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-f3039cf0-e836-4bac-9db3-6fb231eeea23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3287032013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3287032013 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.916198691 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 22369141 ps |
| CPU time | 1.27 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-f1315865-f3e4-483f-ac7c-a17556037759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916198691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.916198691 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1672130396 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 7763381603 ps |
| CPU time | 38.39 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:52:37 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-e3f75707-d912-4230-b2d6-3b6613856aab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1672130396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1672130396 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.890122758 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3771614649 ps |
| CPU time | 40.25 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:55 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-50b34bdb-9595-4c93-9477-2d99c6ebe1e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=890122758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.890122758 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.494349924 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 855070272 ps |
| CPU time | 118.84 seconds |
| Started | Feb 29 12:52:00 PM PST 24 |
| Finished | Feb 29 12:53:59 PM PST 24 |
| Peak memory | 207496 kb |
| Host | smart-608bd1fe-7ec3-4498-986f-f0b2a2b3089a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=494349924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.494349924 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.321338416 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1450042797 ps |
| CPU time | 38.24 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:55 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-5fd63f11-fbea-4f8e-b041-52b8066f1839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=321338416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.321338416 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3952247970 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1038605565 ps |
| CPU time | 8.77 seconds |
| Started | Feb 29 12:51:47 PM PST 24 |
| Finished | Feb 29 12:51:56 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-14adf979-0242-404f-a615-5977bef1a4c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3952247970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3952247970 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1805982432 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 838830317 ps |
| CPU time | 19.6 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:23 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-8bad8c4b-123d-4f82-8a98-e1b82667da66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805982432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1805982432 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2948195967 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 99552946801 ps |
| CPU time | 380.33 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:58:12 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-263c9196-9e5a-4631-8ca2-cd550a13aaf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2948195967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.2948195967 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1981913172 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 312167520 ps |
| CPU time | 5.33 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:25 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-ba0fd9d7-7871-41f6-b458-aaceddcef05f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1981913172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1981913172 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1156334451 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 34882051 ps |
| CPU time | 3.04 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:51:54 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-8eedb2aa-9f32-459c-8615-0b6e7ecc43cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1156334451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1156334451 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2980585127 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 98884956 ps |
| CPU time | 1.49 seconds |
| Started | Feb 29 12:51:49 PM PST 24 |
| Finished | Feb 29 12:51:51 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-d9ee7f98-5536-4612-8e95-7121b46e2044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2980585127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2980585127 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3329237533 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 42074293304 ps |
| CPU time | 65.97 seconds |
| Started | Feb 29 12:52:06 PM PST 24 |
| Finished | Feb 29 12:53:12 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-91d37397-580a-4f83-8e10-f8d084a2a935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329237533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3329237533 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.184784971 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 8357737227 ps |
| CPU time | 46.6 seconds |
| Started | Feb 29 12:51:54 PM PST 24 |
| Finished | Feb 29 12:52:41 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-be93adaa-a6e5-45d4-80e5-45ded2ee6625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=184784971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.184784971 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1503491338 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 289676120 ps |
| CPU time | 6.25 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-48eda395-d9a8-476f-9401-0170ea38a1f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503491338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1503491338 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.4045915518 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3217659674 ps |
| CPU time | 12.49 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:22 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-5a1a4338-4932-4dc5-a095-fdb97e58c5c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4045915518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4045915518 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2878293430 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 131714586 ps |
| CPU time | 1.38 seconds |
| Started | Feb 29 12:51:53 PM PST 24 |
| Finished | Feb 29 12:51:54 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-a6f298a0-e914-418c-bdc4-0a4821350d91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878293430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2878293430 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1689062719 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2319522458 ps |
| CPU time | 7.89 seconds |
| Started | Feb 29 12:51:57 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-26a8614b-4d4b-4036-8a43-fc8a9da5aa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689062719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1689062719 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2885981897 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1504558200 ps |
| CPU time | 9.32 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:52:01 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-0dec9ab8-44ff-46c7-ae7b-dbd20e31a351 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2885981897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2885981897 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4070329736 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14777403 ps |
| CPU time | 1.1 seconds |
| Started | Feb 29 12:51:48 PM PST 24 |
| Finished | Feb 29 12:51:49 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-85495e5e-fb38-49b9-b829-616b81f71b8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070329736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4070329736 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1900722047 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 10922873442 ps |
| CPU time | 72.81 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:53:15 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-d3260cc6-e0b5-499d-9c7a-c2cde6dec782 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1900722047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1900722047 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.860805759 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 10044873 ps |
| CPU time | 1.14 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-e43f0de8-56ac-4a5a-870b-e6e74e8884a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860805759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.860805759 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1227001315 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1148076136 ps |
| CPU time | 57.26 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:52:57 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-32ba2178-6c5a-4303-b8d5-458f72c8f3f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1227001315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1227001315 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2244146092 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1069200471 ps |
| CPU time | 68.85 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:53:01 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-173a2360-f85c-47f9-ba17-b7904fc3d49f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2244146092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2244146092 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.877205429 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 37956337 ps |
| CPU time | 3.38 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-7d0da0ae-e01a-4306-a027-235ac4ee3299 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877205429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.877205429 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2243945106 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 104981949 ps |
| CPU time | 5.23 seconds |
| Started | Feb 29 12:51:58 PM PST 24 |
| Finished | Feb 29 12:52:03 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-391b25a7-c223-44d9-a38a-422b4fee3928 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2243945106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2243945106 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.833671813 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 26447407364 ps |
| CPU time | 139.96 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:54:32 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-394095f0-f464-4be1-ae85-6b6004ed1991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=833671813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.833671813 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3969663152 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 45830162 ps |
| CPU time | 4.39 seconds |
| Started | Feb 29 12:51:46 PM PST 24 |
| Finished | Feb 29 12:51:55 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-410fd2c6-0743-4938-a6f3-238ed9432b5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969663152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3969663152 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.194927910 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 601027386 ps |
| CPU time | 8.27 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-d8449481-5d2e-42a6-9cf0-97b1c69ff130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194927910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.194927910 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.2848311600 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5847277886 ps |
| CPU time | 12.76 seconds |
| Started | Feb 29 12:52:03 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-fa62dbc4-93ad-44d8-979e-f67414f145e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2848311600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2848311600 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3575071481 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 39820048158 ps |
| CPU time | 64.51 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:53:16 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-6091a6dc-d053-4756-87d8-afc626781303 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575071481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3575071481 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2681073806 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 17807453881 ps |
| CPU time | 59.86 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:53:11 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-a53759e9-228b-4f5c-aea9-532596905deb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2681073806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2681073806 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.4202115300 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 107031969 ps |
| CPU time | 7.19 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:09 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-8022f14a-c067-40f6-8093-8fcf36a6ac72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202115300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.4202115300 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3555696732 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 11190912 ps |
| CPU time | 1.34 seconds |
| Started | Feb 29 12:52:02 PM PST 24 |
| Finished | Feb 29 12:52:04 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-33996a83-2e0a-4ee8-96a8-477e8e9c45d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555696732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3555696732 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.850969744 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 169947838 ps |
| CPU time | 1.68 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:52:06 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-79c3e4ad-7d0a-431f-943e-095b7a15c0cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=850969744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.850969744 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.793274187 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5334406168 ps |
| CPU time | 10.05 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:27 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-db2a2f82-3108-4cb6-ade9-0d230d7190ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=793274187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.793274187 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1715923560 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1522347550 ps |
| CPU time | 8.84 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-fd76581b-f963-4d08-b971-bbf01576344e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1715923560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1715923560 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3415485960 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 9060505 ps |
| CPU time | 1.26 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:09 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-4e4c4e99-8bc7-4d6c-98d8-de73d2c3876e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415485960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3415485960 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2359619652 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 542982049 ps |
| CPU time | 19.71 seconds |
| Started | Feb 29 12:52:01 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-bb54d3fa-093b-4f94-9517-fb0d6cbee816 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2359619652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2359619652 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1998202769 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 339730555 ps |
| CPU time | 7.38 seconds |
| Started | Feb 29 12:51:45 PM PST 24 |
| Finished | Feb 29 12:51:58 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-d58dd849-96f0-4552-b6d1-0d5e40c4c79f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1998202769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1998202769 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1429239131 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1770420397 ps |
| CPU time | 85.57 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:53:37 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-57961ecc-dec6-450e-bd90-eabf6eb2c6ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1429239131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1429239131 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.515566861 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 254617514 ps |
| CPU time | 4.34 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-59f807e1-cdad-4a50-8655-46d9b6828aeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=515566861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.515566861 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.813128853 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 496846994 ps |
| CPU time | 10.4 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-c9f3e536-806d-4391-b55e-5981c459b036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=813128853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.813128853 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3677622233 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 47891260181 ps |
| CPU time | 262.26 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:56:34 PM PST 24 |
| Peak memory | 204008 kb |
| Host | smart-00e2b705-ed06-4a0b-9d54-17a684fc480e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3677622233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3677622233 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3160107761 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 223433305 ps |
| CPU time | 3.99 seconds |
| Started | Feb 29 12:52:03 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-5d54385a-fe30-4108-96f6-c46f7fefd3fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160107761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3160107761 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.1165474266 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 62437434 ps |
| CPU time | 1.79 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d2578ffc-bb58-4b6d-82e0-38c76e78625d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1165474266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1165474266 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.2639735861 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 98341013 ps |
| CPU time | 9.59 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-c1594c6b-47cc-4e57-972f-e280440195bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639735861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2639735861 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.4202361750 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 23151955276 ps |
| CPU time | 82.07 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:53:34 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-efd332c3-338c-4249-9bf4-ed7ef86cfd2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202361750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.4202361750 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1089827274 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3673240014 ps |
| CPU time | 14.19 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:52:06 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-9d648e5a-4a50-4b2f-aaa4-f06890651648 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1089827274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1089827274 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.325976445 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 249814311 ps |
| CPU time | 5.72 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-00ba3b2c-e77d-41a6-9034-e7094c87544f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325976445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.325976445 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.3203688642 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 456319153 ps |
| CPU time | 5.18 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-27ee1dfe-e4d8-48c5-b8d6-d89dc3996572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203688642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3203688642 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.2100228542 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 46554297 ps |
| CPU time | 1.23 seconds |
| Started | Feb 29 12:52:04 PM PST 24 |
| Finished | Feb 29 12:52:05 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-78c4cffb-1e38-4021-a456-79762e4b17ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100228542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2100228542 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.912861679 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2115971710 ps |
| CPU time | 9.85 seconds |
| Started | Feb 29 12:51:52 PM PST 24 |
| Finished | Feb 29 12:52:02 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-35274fbb-09fa-446e-bb57-c0fd1e767d28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=912861679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.912861679 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.596469917 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2079791681 ps |
| CPU time | 12.12 seconds |
| Started | Feb 29 12:52:00 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-382ad736-d4c5-4aca-8b74-80bb6c7e1e15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=596469917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.596469917 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4003633518 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 12323508 ps |
| CPU time | 1.08 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-bea763ea-f60e-4ede-a969-91e11d67aa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003633518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4003633518 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.876405531 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1758120619 ps |
| CPU time | 25.35 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:40 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-586a69d0-a0dc-4092-ac92-fe8f482be086 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=876405531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.876405531 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2746587960 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 103131889 ps |
| CPU time | 8.13 seconds |
| Started | Feb 29 12:51:51 PM PST 24 |
| Finished | Feb 29 12:52:00 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-7a5b973f-8664-4297-bf7e-5529ca9d6e5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2746587960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2746587960 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.41851996 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 242457770 ps |
| CPU time | 29.35 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:39 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-8e9d3f3c-8986-48a0-a42d-51cf7aa4aee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41851996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_ reset.41851996 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.993408704 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 77867622 ps |
| CPU time | 2.03 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:18 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-6a95e56d-abc0-4c9d-84bf-f75d9b04f05a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993408704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.993408704 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.4257196783 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 150376627 ps |
| CPU time | 11.08 seconds |
| Started | Feb 29 12:52:13 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-28a0ca38-34cb-4b6a-840e-4ccd3605a19e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257196783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.4257196783 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2031538362 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 103010494949 ps |
| CPU time | 158.87 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:55:00 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-2bd6d088-7e0d-45ba-8d50-45b3a45bb875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2031538362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2031538362 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.855913537 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 443850003 ps |
| CPU time | 4.91 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-4521bbb3-d03c-4058-8656-eb2d03b0be43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=855913537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.855913537 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.4203017175 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 587754694 ps |
| CPU time | 3.98 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-aa7173da-9ea2-445b-8f8b-c8cf7e597675 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203017175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4203017175 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2119407184 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 28599929 ps |
| CPU time | 2.47 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:19 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-c3b62073-c8f5-4924-b6a0-e28e468ed3c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2119407184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2119407184 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2796152429 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 13229542196 ps |
| CPU time | 44.2 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:59 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-ba02cc33-075e-434c-88eb-eefe96432e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796152429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2796152429 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3945657163 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 53735399476 ps |
| CPU time | 109.65 seconds |
| Started | Feb 29 12:52:22 PM PST 24 |
| Finished | Feb 29 12:54:12 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-fb3d6a2d-3dff-4264-838d-53602de40e0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3945657163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3945657163 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1316837882 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 51238733 ps |
| CPU time | 5.32 seconds |
| Started | Feb 29 12:52:09 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-cfaee8aa-17a4-4292-8e88-a92d75caf2b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316837882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1316837882 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.733764654 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 239003808 ps |
| CPU time | 3.67 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-5e34fb45-0422-4e05-897e-a26bf30d1f47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733764654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.733764654 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3138823069 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 12041506 ps |
| CPU time | 1.27 seconds |
| Started | Feb 29 12:51:55 PM PST 24 |
| Finished | Feb 29 12:51:56 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-31667b66-7084-4155-8074-e17242619131 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3138823069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3138823069 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3339351002 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1682001011 ps |
| CPU time | 7.43 seconds |
| Started | Feb 29 12:51:59 PM PST 24 |
| Finished | Feb 29 12:52:07 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-71f0a140-6698-4ea3-a4f9-d6b60847b04c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339351002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3339351002 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2995151770 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 512841802 ps |
| CPU time | 4.59 seconds |
| Started | Feb 29 12:52:30 PM PST 24 |
| Finished | Feb 29 12:52:35 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-0baa9a7d-3124-41c2-a4e8-50baa3e46896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2995151770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2995151770 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3949444935 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 10610458 ps |
| CPU time | 1.14 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-f910d6f9-e612-4d3e-a438-db71be6cc5eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949444935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3949444935 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1967026955 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 226019455 ps |
| CPU time | 31.35 seconds |
| Started | Feb 29 12:52:05 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-8babcdf2-c3e4-4331-8192-1bdc2227e54f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1967026955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1967026955 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3775330614 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4309695997 ps |
| CPU time | 40.25 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:55 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-e9b72a2d-1b66-4d32-8eca-fea654ad31e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775330614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3775330614 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3142369697 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3153666170 ps |
| CPU time | 104.03 seconds |
| Started | Feb 29 12:52:13 PM PST 24 |
| Finished | Feb 29 12:53:58 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-bb236e0a-d940-44f3-bdac-d6783bfde796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142369697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3142369697 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.159154339 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 211037019 ps |
| CPU time | 9.37 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:30 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-3867319b-cc82-4cc8-b98a-be6e74451792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=159154339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.159154339 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3005199687 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 34050821 ps |
| CPU time | 2.81 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:23 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-89c49abc-f7e2-47d8-a611-388cd7f408da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005199687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3005199687 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1045271356 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 48504298 ps |
| CPU time | 9.07 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:52:31 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-de155801-5473-4922-9fa5-ee7b6f6fcf34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1045271356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1045271356 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3901501311 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 17590360679 ps |
| CPU time | 100.6 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:54:06 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-25b4669f-e2f7-40b5-b086-71f3a0621931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3901501311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3901501311 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2985132712 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 424249726 ps |
| CPU time | 7.92 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:28 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-5ea04e6d-c0a6-4d4f-8e3b-5180a1f3208d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2985132712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2985132712 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2260253061 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 17723764 ps |
| CPU time | 1.58 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-5b765f49-726d-4e43-a163-62e2fdba5466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2260253061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2260253061 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.631822937 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 145472208 ps |
| CPU time | 1.44 seconds |
| Started | Feb 29 12:52:29 PM PST 24 |
| Finished | Feb 29 12:52:31 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-6f7ec1dc-2021-43d0-967f-c25c604d1037 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=631822937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.631822937 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3206163306 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 104966205994 ps |
| CPU time | 84.64 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:53:41 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-01df5dcb-146c-45d2-ad4a-2f3b66bbbcbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206163306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3206163306 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2246167724 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2991706801 ps |
| CPU time | 8.84 seconds |
| Started | Feb 29 12:52:33 PM PST 24 |
| Finished | Feb 29 12:52:42 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-c9002ca4-0b2b-4ac0-ae77-9de50e5aef9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2246167724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2246167724 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3890853697 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 33158705 ps |
| CPU time | 3.6 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:11 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-0bb2d92a-5851-42af-8143-ef7ef0f30185 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890853697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3890853697 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.3552445582 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 23070105 ps |
| CPU time | 2.69 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:52:09 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-50536561-ce5d-4b22-b9a9-f7672b98abe9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3552445582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3552445582 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2558783598 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 62123697 ps |
| CPU time | 1.61 seconds |
| Started | Feb 29 12:52:13 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-98142ead-36c8-4d2d-95a8-d215fa7f7214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2558783598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2558783598 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.225793063 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2562455813 ps |
| CPU time | 8.93 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-b0a3f0a1-4067-4415-9ebf-c35ed48fe890 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=225793063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.225793063 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.228875901 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 764017979 ps |
| CPU time | 5.42 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:25 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-e8780367-a820-4d39-9c60-7372fc4cc973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=228875901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.228875901 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3065748764 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 17697048 ps |
| CPU time | 1.27 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-2e458cfc-3dfc-42c2-a8e9-1fefc9ce6150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065748764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3065748764 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.4265256438 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 309530486 ps |
| CPU time | 18.45 seconds |
| Started | Feb 29 12:52:13 PM PST 24 |
| Finished | Feb 29 12:52:32 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-08cf4276-8c3f-422a-bfee-04c6a0592119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4265256438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4265256438 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2611990736 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 378774429 ps |
| CPU time | 39.57 seconds |
| Started | Feb 29 12:52:04 PM PST 24 |
| Finished | Feb 29 12:52:44 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-2524c5b9-b9e7-4c43-80d6-a43be158ceaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2611990736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2611990736 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3034389057 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2504201239 ps |
| CPU time | 103 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:54:06 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-6da7b5e6-5d9b-4f69-8dfd-4cde95f636bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034389057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.3034389057 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3003463404 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 210270522 ps |
| CPU time | 12.64 seconds |
| Started | Feb 29 12:52:32 PM PST 24 |
| Finished | Feb 29 12:52:46 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-912e1d72-5c55-43f4-99e7-fc36301d1d82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003463404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3003463404 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.248246936 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 120991595 ps |
| CPU time | 5.33 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-bc5dd74b-ca0e-40aa-ac61-2e2756ebc3e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=248246936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.248246936 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.682737341 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 115101721 ps |
| CPU time | 9.18 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-f292323a-9573-45a9-be85-07cfb498cdcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682737341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.682737341 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3026545197 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 112198340767 ps |
| CPU time | 270.85 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:56:54 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-eaee607f-e93a-4a0d-b360-9b3a69d7a16c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3026545197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3026545197 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.4174766050 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 939129966 ps |
| CPU time | 9.28 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:28 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-77f815ea-223f-4d2b-b4b0-85fb1d3a6992 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4174766050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.4174766050 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.2606400245 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 31711582 ps |
| CPU time | 1.24 seconds |
| Started | Feb 29 12:52:12 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-9c02f3ec-d290-4ca8-8b96-3e05554258bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2606400245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2606400245 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.1773777532 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 602190971 ps |
| CPU time | 7.69 seconds |
| Started | Feb 29 12:52:13 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-d1bbfa0c-27b3-4354-a5bb-a1574b6f3d4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773777532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1773777532 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3240016322 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 31982407872 ps |
| CPU time | 103.37 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:54:00 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-ce881946-be97-4cee-b7eb-2ed445606f43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240016322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3240016322 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2869207976 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 36943157129 ps |
| CPU time | 123.56 seconds |
| Started | Feb 29 12:52:07 PM PST 24 |
| Finished | Feb 29 12:54:10 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-9522686c-69fa-4055-8f2c-cea365a24cb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2869207976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2869207976 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2456435628 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 27040445 ps |
| CPU time | 3.39 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f4a66559-406d-479b-8904-fecbe709a93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456435628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2456435628 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1507484960 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1860688658 ps |
| CPU time | 7.97 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:52:33 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-2e924ccf-cdb5-491a-a52b-4d4c19b43a6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507484960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1507484960 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.4149573437 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 8773750 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:52:20 PM PST 24 |
| Finished | Feb 29 12:52:21 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-6417768b-3e2f-4b3b-9897-52eeefe65354 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4149573437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4149573437 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2927524365 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 5485428696 ps |
| CPU time | 8.99 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:27 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-33810e56-bd9c-414b-b9c6-f265db65d34b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927524365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2927524365 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4091592652 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2907713731 ps |
| CPU time | 9.31 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-f7b104de-859a-4638-89af-a845deb0aaf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4091592652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4091592652 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.182269025 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 7927828 ps |
| CPU time | 1.08 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-39f9c319-c754-4271-a3ca-27b90d2cb4df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182269025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.182269025 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1152480557 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3697226789 ps |
| CPU time | 11.92 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:52:33 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-11ebb0cc-4028-4441-bd3a-7c34bc6f8688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152480557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1152480557 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1593199481 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1915977497 ps |
| CPU time | 23.15 seconds |
| Started | Feb 29 12:52:20 PM PST 24 |
| Finished | Feb 29 12:52:43 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-1c305398-3e2e-4387-9472-238a9400a141 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593199481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1593199481 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2635801321 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 22068304 ps |
| CPU time | 16.46 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:52:34 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-fe4f0918-0be8-4149-a066-7d9219af817d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2635801321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.2635801321 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3204672330 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 175219009 ps |
| CPU time | 26.69 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:47 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-a2955075-f75c-4a1a-b0cb-709868959ace |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3204672330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.3204672330 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1403187721 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 187734336 ps |
| CPU time | 5.77 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-abb58155-88a2-4ebf-a631-a2461d906cbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403187721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1403187721 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3093015951 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 382212734 ps |
| CPU time | 5.99 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:20 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-2ecc936a-ea43-47fe-a519-b5a2405cadde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093015951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3093015951 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1201908640 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 14600077534 ps |
| CPU time | 24.11 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:40 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-07abd764-cb25-459e-9c8f-095fedc1d67b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1201908640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1201908640 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.363341592 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 568984940 ps |
| CPU time | 7.98 seconds |
| Started | Feb 29 12:52:06 PM PST 24 |
| Finished | Feb 29 12:52:14 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-c5054af9-0149-4384-a4ac-b16f98b51fa2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=363341592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.363341592 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.1400260808 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1255949605 ps |
| CPU time | 14.38 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:33 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-1702ebb0-6d67-45ba-a330-56195e507e97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400260808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1400260808 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.1089612519 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1895764222 ps |
| CPU time | 13.26 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:32 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-8cc476a8-bda4-43eb-847a-8ed6c04362a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089612519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1089612519 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.656095648 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 21737429831 ps |
| CPU time | 89.17 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:53:52 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-7e48a288-ae76-4853-8a50-20336bdba38a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=656095648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.656095648 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.25797665 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 17941239054 ps |
| CPU time | 110.08 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:54:00 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-2bab95f2-585e-4417-807a-8b3d9f1664b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=25797665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.25797665 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3159208042 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 61302919 ps |
| CPU time | 8.53 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-bfbfe594-ed27-4d7e-8a73-c2ce9ad78060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159208042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3159208042 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.693819214 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1617292148 ps |
| CPU time | 9.32 seconds |
| Started | Feb 29 12:52:20 PM PST 24 |
| Finished | Feb 29 12:52:30 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-dc81b1f8-5ee2-48b7-8537-560ee857d808 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693819214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.693819214 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.4081339061 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 240887592 ps |
| CPU time | 1.56 seconds |
| Started | Feb 29 12:52:27 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-1fdb8165-a1fc-4ab6-bbdf-bdeacbc7a6e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4081339061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4081339061 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.10779938 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3144278865 ps |
| CPU time | 8.69 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:52:30 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-85288dac-3dbd-46c4-90cc-5e7308c73722 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=10779938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.10779938 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2262147559 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2457215800 ps |
| CPU time | 8.18 seconds |
| Started | Feb 29 12:52:08 PM PST 24 |
| Finished | Feb 29 12:52:17 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-896ea795-58ef-4533-9a4b-47ac19e0b538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2262147559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2262147559 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2830094253 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 39730480 ps |
| CPU time | 1.21 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:52:19 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-5b421291-46e9-4c8a-9822-555ea22adcb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830094253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2830094253 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.388253017 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2369828157 ps |
| CPU time | 36.64 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:56 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-7a8227a3-9be1-4195-afb2-3b28da07325e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=388253017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.388253017 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3858149370 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 875901882 ps |
| CPU time | 30.92 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:52:52 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-6e63b3f3-b361-44b4-846b-e10179fbaffb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3858149370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3858149370 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2567842881 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4918662576 ps |
| CPU time | 155.34 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:54:55 PM PST 24 |
| Peak memory | 207052 kb |
| Host | smart-eeec16b1-c742-477e-8674-a6b184d91846 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567842881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2567842881 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1762316050 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 223641942 ps |
| CPU time | 12.55 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:52:28 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-ebf75e65-2192-4981-a794-57aa006b2d61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762316050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1762316050 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1015601300 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 914037518 ps |
| CPU time | 12.58 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:52:30 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-968bc9f0-8a09-46b9-9f39-22bb3d32b1ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1015601300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1015601300 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2113731052 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 73608527 ps |
| CPU time | 6.46 seconds |
| Started | Feb 29 12:52:28 PM PST 24 |
| Finished | Feb 29 12:52:35 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-55ab1f39-e250-4294-a3ae-13693d8255b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2113731052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2113731052 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.504151258 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 975805919 ps |
| CPU time | 5.94 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:52:25 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-2ead03ec-ebc5-4f9c-aa61-b7da94a6e00e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=504151258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.504151258 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.726742205 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 367292255 ps |
| CPU time | 4.45 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-880a7dd8-6c69-4b03-9d36-50bf7fde4c53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726742205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.726742205 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.973438358 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1491005005 ps |
| CPU time | 9.13 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:52:34 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-b1576168-86d6-423b-be35-b864b5ea66d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973438358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.973438358 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3237773550 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 34804149585 ps |
| CPU time | 136.21 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:54:31 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-a9bae905-b785-4253-81c7-2bb03cf1c1c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237773550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3237773550 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.735403255 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 49415799749 ps |
| CPU time | 64.56 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:53:28 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-c93ea10a-af93-4e9c-9092-54f39fc178e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=735403255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.735403255 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2123398311 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 21647808 ps |
| CPU time | 1.71 seconds |
| Started | Feb 29 12:52:22 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-2f299d43-a51a-4f14-bb2b-8d86f0f52446 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123398311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2123398311 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3896990783 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 27359748 ps |
| CPU time | 2.09 seconds |
| Started | Feb 29 12:52:21 PM PST 24 |
| Finished | Feb 29 12:52:23 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-9795f664-0036-44a1-9823-08d93cf51fd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3896990783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3896990783 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.4177592558 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 74060397 ps |
| CPU time | 1.43 seconds |
| Started | Feb 29 12:52:11 PM PST 24 |
| Finished | Feb 29 12:52:12 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-cd456fad-315e-444a-b227-d31711130f22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4177592558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.4177592558 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.582318011 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2337441840 ps |
| CPU time | 7.77 seconds |
| Started | Feb 29 12:52:24 PM PST 24 |
| Finished | Feb 29 12:52:32 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-d8fd6977-e585-4e84-8770-b8277458b9a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=582318011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.582318011 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2325339001 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8506228091 ps |
| CPU time | 7.27 seconds |
| Started | Feb 29 12:52:22 PM PST 24 |
| Finished | Feb 29 12:52:30 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-fe1579bf-785d-4def-b798-2a096a1c7a30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2325339001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2325339001 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3362430606 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 7764089 ps |
| CPU time | 1.11 seconds |
| Started | Feb 29 12:52:23 PM PST 24 |
| Finished | Feb 29 12:52:24 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-5ce810b8-776d-42d9-8b0e-5f09024ed99d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362430606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3362430606 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.352981114 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 7972585135 ps |
| CPU time | 76.43 seconds |
| Started | Feb 29 12:52:18 PM PST 24 |
| Finished | Feb 29 12:53:36 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-adbd7c63-6b52-41d0-88c1-df0c489b5b9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=352981114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.352981114 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2734621974 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4576411275 ps |
| CPU time | 74.57 seconds |
| Started | Feb 29 12:52:16 PM PST 24 |
| Finished | Feb 29 12:53:31 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-522ef541-8e79-43b7-85cd-6b056e2a5176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2734621974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2734621974 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2506830256 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 256871791 ps |
| CPU time | 54.72 seconds |
| Started | Feb 29 12:52:26 PM PST 24 |
| Finished | Feb 29 12:53:21 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-338e0343-da3f-4e3d-b63e-8ba6a511dd79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2506830256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2506830256 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1925338370 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 10865806731 ps |
| CPU time | 194.88 seconds |
| Started | Feb 29 12:52:22 PM PST 24 |
| Finished | Feb 29 12:55:37 PM PST 24 |
| Peak memory | 207760 kb |
| Host | smart-06e8d3cf-6e5f-46ff-bf8b-38ba84244682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925338370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1925338370 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.4164253852 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1255100964 ps |
| CPU time | 8.66 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-12377ae2-f10c-4f22-be45-5ffbfacb819f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164253852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4164253852 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.4151509951 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 78354242 ps |
| CPU time | 12.34 seconds |
| Started | Feb 29 12:52:17 PM PST 24 |
| Finished | Feb 29 12:52:35 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-76f806d8-274a-4273-a035-b73ba5880db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4151509951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4151509951 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3021947136 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 830896740 ps |
| CPU time | 10.46 seconds |
| Started | Feb 29 12:52:33 PM PST 24 |
| Finished | Feb 29 12:52:44 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-febffc28-2053-4672-bbe7-c6219dee2576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021947136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3021947136 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.854616018 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 16777537 ps |
| CPU time | 1.84 seconds |
| Started | Feb 29 12:52:24 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-209bd9b5-476f-49d3-a88d-d3fc8437ed0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=854616018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.854616018 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.572570050 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 407209658 ps |
| CPU time | 9.22 seconds |
| Started | Feb 29 12:52:26 PM PST 24 |
| Finished | Feb 29 12:52:37 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-5d2bd09d-da57-4450-832d-b21ffe5332cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572570050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.572570050 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3469565877 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 44194193724 ps |
| CPU time | 60.94 seconds |
| Started | Feb 29 12:52:15 PM PST 24 |
| Finished | Feb 29 12:53:16 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-31d91853-0304-49fb-925c-f4f0181d673b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469565877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3469565877 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.432416192 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 5899328731 ps |
| CPU time | 38.83 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:53:04 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-3ba9f11a-6ec2-4823-8b3c-49651c5a0a7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=432416192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.432416192 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3700945860 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 24172187 ps |
| CPU time | 2.42 seconds |
| Started | Feb 29 12:52:14 PM PST 24 |
| Finished | Feb 29 12:52:16 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-5298c9ad-13ee-4da5-8fc3-278aedeb8540 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700945860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3700945860 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4247243222 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 582938084 ps |
| CPU time | 6.58 seconds |
| Started | Feb 29 12:52:30 PM PST 24 |
| Finished | Feb 29 12:52:37 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-70d16965-b657-4cd5-975e-6e6619d101af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247243222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4247243222 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.190733018 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 68701364 ps |
| CPU time | 1.3 seconds |
| Started | Feb 29 12:52:25 PM PST 24 |
| Finished | Feb 29 12:52:26 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-1db01d83-0568-4d8f-88ad-4d08776ad73f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=190733018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.190733018 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.583668945 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2637894801 ps |
| CPU time | 9.19 seconds |
| Started | Feb 29 12:52:29 PM PST 24 |
| Finished | Feb 29 12:52:38 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-c3e30e75-1e2b-4750-8394-b738e3f01d73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=583668945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.583668945 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.344887853 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 667205006 ps |
| CPU time | 5.24 seconds |
| Started | Feb 29 12:52:10 PM PST 24 |
| Finished | Feb 29 12:52:15 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-9646422c-d4f9-4d25-a7d6-83739f7bb82b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=344887853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.344887853 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3015337172 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10789358 ps |
| CPU time | 1.15 seconds |
| Started | Feb 29 12:52:24 PM PST 24 |
| Finished | Feb 29 12:52:25 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-8bc50c95-2940-4219-8738-c8115035a422 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015337172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3015337172 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.502946225 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4202925052 ps |
| CPU time | 65.42 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:53:25 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-80797b86-0fc4-4c3b-8178-c44e2e2f945a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=502946225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.502946225 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1698593190 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 31239575558 ps |
| CPU time | 132.31 seconds |
| Started | Feb 29 12:52:28 PM PST 24 |
| Finished | Feb 29 12:54:42 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-f1112423-06b4-4aad-9be4-71e7935f985a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1698593190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1698593190 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2560523098 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 9597959 ps |
| CPU time | 2.36 seconds |
| Started | Feb 29 12:52:19 PM PST 24 |
| Finished | Feb 29 12:52:22 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-2e46a1c3-169d-4d12-9e6c-48580eefe1bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2560523098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.2560523098 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1770040438 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 706742282 ps |
| CPU time | 49.55 seconds |
| Started | Feb 29 12:52:20 PM PST 24 |
| Finished | Feb 29 12:53:10 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-22c051bd-c3eb-4d5e-aa1f-35087632f0c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1770040438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1770040438 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.825281941 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 796814673 ps |
| CPU time | 4.61 seconds |
| Started | Feb 29 12:52:24 PM PST 24 |
| Finished | Feb 29 12:52:29 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-c65e4942-9a25-417a-82cd-143a2d552b02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825281941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.825281941 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.4049162092 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 715733575 ps |
| CPU time | 4.54 seconds |
| Started | Feb 29 12:49:48 PM PST 24 |
| Finished | Feb 29 12:49:52 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-70bcc83b-78e6-4707-8fba-d8b3e2a3b9cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049162092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4049162092 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3968487488 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 44488979696 ps |
| CPU time | 108 seconds |
| Started | Feb 29 12:50:03 PM PST 24 |
| Finished | Feb 29 12:51:52 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-431b52e4-f72d-46d4-a234-c5f9f0894a38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3968487488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3968487488 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1208573431 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 421229079 ps |
| CPU time | 7.3 seconds |
| Started | Feb 29 12:49:49 PM PST 24 |
| Finished | Feb 29 12:49:56 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-cdf95dff-0b91-49fa-91c4-035d2ea0ac57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208573431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1208573431 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2348198689 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 935975076 ps |
| CPU time | 10.32 seconds |
| Started | Feb 29 12:49:54 PM PST 24 |
| Finished | Feb 29 12:50:05 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-4a433426-2986-48ec-aec8-830451c99b5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348198689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2348198689 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.437001412 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 146628082 ps |
| CPU time | 5.45 seconds |
| Started | Feb 29 12:49:43 PM PST 24 |
| Finished | Feb 29 12:49:49 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-a5234c0e-a518-4f85-b719-c66c1758e066 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437001412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.437001412 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.426615830 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 30449545586 ps |
| CPU time | 105.74 seconds |
| Started | Feb 29 12:49:35 PM PST 24 |
| Finished | Feb 29 12:51:21 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-2d7603a1-c4e0-4e2b-83e0-039e4b5ff5b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=426615830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.426615830 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1501664614 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 7878427058 ps |
| CPU time | 23.54 seconds |
| Started | Feb 29 12:49:49 PM PST 24 |
| Finished | Feb 29 12:50:13 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-bff2d85f-eb49-45cd-b2f2-ef3b864d54ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1501664614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1501664614 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.130433772 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 55262873 ps |
| CPU time | 7.95 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-d803529b-da5e-4a2d-a982-898f1cfba921 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130433772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.130433772 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.837280979 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 33401552 ps |
| CPU time | 1.86 seconds |
| Started | Feb 29 12:49:51 PM PST 24 |
| Finished | Feb 29 12:49:53 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-9b873808-215e-4f8f-9926-6afa2ea38038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837280979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.837280979 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.270085354 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 15669330 ps |
| CPU time | 1.25 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-a7e74cc5-304c-4f7a-b95f-b5f3cc12d7e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=270085354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.270085354 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1289249080 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 6454835529 ps |
| CPU time | 8.32 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-2ec6849e-efe2-4656-8c6e-673435dba310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289249080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1289249080 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.165453500 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1112743499 ps |
| CPU time | 8.32 seconds |
| Started | Feb 29 12:49:51 PM PST 24 |
| Finished | Feb 29 12:49:59 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-51b03416-3733-41bd-808c-cd0ea25ec3cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=165453500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.165453500 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.836266527 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 9319081 ps |
| CPU time | 1.32 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-b2b8be91-2d71-4b5b-aab6-81d45d637be7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836266527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.836266527 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2330851047 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 225145561 ps |
| CPU time | 3.45 seconds |
| Started | Feb 29 12:49:57 PM PST 24 |
| Finished | Feb 29 12:50:01 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-3b42a877-7066-4a8f-8374-d909e292cdd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2330851047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2330851047 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3879909353 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 27959883370 ps |
| CPU time | 89.67 seconds |
| Started | Feb 29 12:49:54 PM PST 24 |
| Finished | Feb 29 12:51:24 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-ff21473d-034f-4085-9e1f-b7784b02f2cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3879909353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3879909353 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2172554972 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 8083506391 ps |
| CPU time | 113.54 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:51:41 PM PST 24 |
| Peak memory | 207600 kb |
| Host | smart-9ce9b3a9-d165-4bd7-869b-dcb1465c261d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172554972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2172554972 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2128609339 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 12551436134 ps |
| CPU time | 89.29 seconds |
| Started | Feb 29 12:49:49 PM PST 24 |
| Finished | Feb 29 12:51:19 PM PST 24 |
| Peak memory | 206196 kb |
| Host | smart-2203c581-0fb5-486e-9513-bcf3d9a8c0b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128609339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.2128609339 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3222269729 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 12533764 ps |
| CPU time | 1.02 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-9d133c51-9d84-4cad-85a9-f2d20aea9018 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222269729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3222269729 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1399332854 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 43538238 ps |
| CPU time | 5.2 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:52 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a8d6af88-2553-43a1-86f2-0665a26442f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399332854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1399332854 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.421178131 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 42211097937 ps |
| CPU time | 286.27 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:54:33 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-c002f87d-f091-4335-9794-e76fdac297c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=421178131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.421178131 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2729115627 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 858331272 ps |
| CPU time | 8.37 seconds |
| Started | Feb 29 12:49:52 PM PST 24 |
| Finished | Feb 29 12:50:01 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-2002ae0c-a864-4995-985f-887a19365d6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729115627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2729115627 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.3015603380 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 37556641 ps |
| CPU time | 3.16 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:06 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-17d61ed4-78bb-44d5-8ddf-8d0e212f334d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3015603380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3015603380 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.4176478044 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 92938518 ps |
| CPU time | 5.41 seconds |
| Started | Feb 29 12:49:58 PM PST 24 |
| Finished | Feb 29 12:50:04 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-2dca085f-02dc-4baa-b396-079ccb957c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176478044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.4176478044 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.183947586 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 41981285462 ps |
| CPU time | 145.46 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:52:13 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-8b6c67c4-50a3-49bd-85a5-b0760dcb6cd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=183947586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.183947586 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3614858135 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 9272762524 ps |
| CPU time | 56.16 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:50:43 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-a518cbcf-85cb-416b-af15-9cd4f4e283c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3614858135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3614858135 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3662883875 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 26484437 ps |
| CPU time | 3.34 seconds |
| Started | Feb 29 12:49:55 PM PST 24 |
| Finished | Feb 29 12:50:04 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-bda9b86c-61bf-4744-9249-e7c8b2b4437f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662883875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3662883875 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.961772103 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 786416335 ps |
| CPU time | 11.23 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:14 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-74990a39-33c6-4223-8ae7-cbe4703270f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=961772103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.961772103 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.583611776 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 43626344 ps |
| CPU time | 1.46 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-8d73829d-d048-4988-b6b7-ae8c12f4f835 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=583611776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.583611776 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1706795659 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 11847710618 ps |
| CPU time | 10.17 seconds |
| Started | Feb 29 12:49:56 PM PST 24 |
| Finished | Feb 29 12:50:07 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-a3a712cd-8de7-4ae1-b840-e557dc1ebafb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706795659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1706795659 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.4069248799 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2636333332 ps |
| CPU time | 13.34 seconds |
| Started | Feb 29 12:49:55 PM PST 24 |
| Finished | Feb 29 12:50:08 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-5a50c0fe-3581-49c5-8d36-94411b2c55b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4069248799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4069248799 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.864726287 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 10475227 ps |
| CPU time | 1.17 seconds |
| Started | Feb 29 12:49:47 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-ff6adb2e-515a-47c3-a8bc-24b87f58dbf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864726287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.864726287 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1891795031 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 31163501227 ps |
| CPU time | 92.18 seconds |
| Started | Feb 29 12:49:58 PM PST 24 |
| Finished | Feb 29 12:51:30 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-13181c98-e575-4847-acb0-3259234393da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891795031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1891795031 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4007150728 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5311647294 ps |
| CPU time | 54.41 seconds |
| Started | Feb 29 12:50:22 PM PST 24 |
| Finished | Feb 29 12:51:17 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-62592056-1211-41f8-969e-4ceedff18b2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4007150728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4007150728 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2114458558 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6848201328 ps |
| CPU time | 67.51 seconds |
| Started | Feb 29 12:49:56 PM PST 24 |
| Finished | Feb 29 12:51:04 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-83ee02c2-5d0b-40aa-a568-0ffd4b061cde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2114458558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.2114458558 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2793076026 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 180198005 ps |
| CPU time | 24.07 seconds |
| Started | Feb 29 12:50:03 PM PST 24 |
| Finished | Feb 29 12:50:27 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-51159865-9582-488e-8708-53b5199f3823 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2793076026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2793076026 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1008281406 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 529730414 ps |
| CPU time | 10.12 seconds |
| Started | Feb 29 12:50:04 PM PST 24 |
| Finished | Feb 29 12:50:15 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-41c3f3fd-ed71-4ac6-ab96-1eb4b7b0920f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1008281406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1008281406 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.93745452 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1797893445 ps |
| CPU time | 18.12 seconds |
| Started | Feb 29 12:50:00 PM PST 24 |
| Finished | Feb 29 12:50:19 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-fe3ef1d7-7251-4b2f-8f51-fefeca540413 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=93745452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.93745452 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3512269352 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 71615254799 ps |
| CPU time | 71.24 seconds |
| Started | Feb 29 12:49:58 PM PST 24 |
| Finished | Feb 29 12:51:10 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-1c48947a-5984-4377-b79a-b07a96d03174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3512269352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3512269352 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1032110323 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3205364289 ps |
| CPU time | 10.88 seconds |
| Started | Feb 29 12:49:52 PM PST 24 |
| Finished | Feb 29 12:50:03 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-0ae36d6c-1192-427c-9827-40e89fe91b59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032110323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1032110323 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.3485296218 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 122868725 ps |
| CPU time | 5.24 seconds |
| Started | Feb 29 12:49:50 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-3f47fd67-6c79-4da6-82a4-3695f2dd1606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3485296218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3485296218 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.925289901 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 4549198765 ps |
| CPU time | 9.33 seconds |
| Started | Feb 29 12:49:45 PM PST 24 |
| Finished | Feb 29 12:49:55 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-93fbcd64-b86d-410a-9a84-287a5c86d249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=925289901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.925289901 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.481588968 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 12299387266 ps |
| CPU time | 50.97 seconds |
| Started | Feb 29 12:49:52 PM PST 24 |
| Finished | Feb 29 12:50:43 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-5764c84c-8706-4559-88d1-3cf2a8d0fc89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=481588968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.481588968 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3192279253 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 29357605903 ps |
| CPU time | 148.62 seconds |
| Started | Feb 29 12:50:23 PM PST 24 |
| Finished | Feb 29 12:52:52 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-ea8219fd-6b62-4225-b2c8-bee76c128f01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192279253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3192279253 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1733892646 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 18802986 ps |
| CPU time | 1.13 seconds |
| Started | Feb 29 12:50:03 PM PST 24 |
| Finished | Feb 29 12:50:05 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-3f43b039-cf23-4537-847d-5e9ddc5f06d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733892646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1733892646 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2646270055 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1070951400 ps |
| CPU time | 9.21 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:49:56 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-8a96a7b3-b0cd-4247-a051-9b8f073f3dc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646270055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2646270055 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.2760165096 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 14168066 ps |
| CPU time | 1.1 seconds |
| Started | Feb 29 12:49:57 PM PST 24 |
| Finished | Feb 29 12:49:59 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-c0e02c41-d266-40b0-b470-468ec60a9873 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760165096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2760165096 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.938175612 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4748848664 ps |
| CPU time | 10.06 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:13 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-f0cb66b7-2bff-437a-ae6f-fda86244c7cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=938175612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.938175612 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3395039980 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5479276643 ps |
| CPU time | 12.33 seconds |
| Started | Feb 29 12:49:58 PM PST 24 |
| Finished | Feb 29 12:50:11 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-4221907b-2000-4352-aa31-03e794bc0369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3395039980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3395039980 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.4138210540 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 9622889 ps |
| CPU time | 1.15 seconds |
| Started | Feb 29 12:49:52 PM PST 24 |
| Finished | Feb 29 12:49:53 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-7e86afcd-da15-4c93-9df5-0972a3b7b805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138210540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4138210540 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.4291800407 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 255788338 ps |
| CPU time | 34.01 seconds |
| Started | Feb 29 12:50:01 PM PST 24 |
| Finished | Feb 29 12:50:36 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-aa2db63a-61a8-4a08-950e-eb1ebb979112 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4291800407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4291800407 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.859570198 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1040445205 ps |
| CPU time | 33.94 seconds |
| Started | Feb 29 12:50:04 PM PST 24 |
| Finished | Feb 29 12:50:38 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-4024a028-70a3-4a8a-aecb-8eadfcc2d59c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=859570198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.859570198 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1723003409 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 454821801 ps |
| CPU time | 57.68 seconds |
| Started | Feb 29 12:49:48 PM PST 24 |
| Finished | Feb 29 12:50:46 PM PST 24 |
| Peak memory | 204892 kb |
| Host | smart-a30657c7-34ad-432d-ae27-4ebc3a84e8bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1723003409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1723003409 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1738718705 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 7197853 ps |
| CPU time | 1.91 seconds |
| Started | Feb 29 12:50:01 PM PST 24 |
| Finished | Feb 29 12:50:04 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-feef0a44-783f-4975-a498-c8b8888b32f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1738718705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1738718705 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.27484496 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 151537361 ps |
| CPU time | 3.89 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:49:48 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-88f5fa47-18b8-4fa2-8a5d-c15b8b0dcaf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27484496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.27484496 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2610440457 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 48523296 ps |
| CPU time | 6.12 seconds |
| Started | Feb 29 12:50:19 PM PST 24 |
| Finished | Feb 29 12:50:26 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-9c81c85d-80cb-4251-a50c-333cee9c0cad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610440457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2610440457 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1029953979 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 23397940 ps |
| CPU time | 1.86 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:49:49 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-d2f6b300-1493-4754-a215-50eaeddf0e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029953979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1029953979 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.664369684 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 65572396 ps |
| CPU time | 2.99 seconds |
| Started | Feb 29 12:50:28 PM PST 24 |
| Finished | Feb 29 12:50:31 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-36b463fe-718e-4259-b401-f04e07b46981 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=664369684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.664369684 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1183566395 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 354312137 ps |
| CPU time | 2.92 seconds |
| Started | Feb 29 12:49:59 PM PST 24 |
| Finished | Feb 29 12:50:03 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-8c532e51-b475-46b0-8a71-79c2eb8b88fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1183566395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1183566395 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2510040953 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 29588949461 ps |
| CPU time | 127.2 seconds |
| Started | Feb 29 12:49:46 PM PST 24 |
| Finished | Feb 29 12:51:54 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-3ab5ec77-aef6-42af-b4df-4c8065c09681 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510040953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2510040953 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1989186153 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 7393103744 ps |
| CPU time | 59.02 seconds |
| Started | Feb 29 12:50:10 PM PST 24 |
| Finished | Feb 29 12:51:10 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-f1d481c1-06bd-4cb9-b63d-571f003f880c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1989186153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1989186153 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.429020780 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 206827503 ps |
| CPU time | 6.05 seconds |
| Started | Feb 29 12:49:53 PM PST 24 |
| Finished | Feb 29 12:50:00 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f48f547d-7a8f-4a05-ad35-ed5174c047f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429020780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.429020780 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3345893056 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 986978456 ps |
| CPU time | 12.68 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:50:26 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-c4b02ca6-ef7d-4b34-864b-aff41350826e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345893056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3345893056 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3451637640 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 21768414 ps |
| CPU time | 1.13 seconds |
| Started | Feb 29 12:50:00 PM PST 24 |
| Finished | Feb 29 12:50:02 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-e1c76258-833d-42ca-8c83-85db379cb95f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3451637640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3451637640 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3400377949 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 6944245896 ps |
| CPU time | 10.4 seconds |
| Started | Feb 29 12:50:07 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-bc835d97-86a8-4c90-9f78-784088452476 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400377949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3400377949 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3966723444 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1932969949 ps |
| CPU time | 7.85 seconds |
| Started | Feb 29 12:49:48 PM PST 24 |
| Finished | Feb 29 12:49:56 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-f0a7fd0e-28e3-4f08-81ba-e7280e1dfd7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3966723444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3966723444 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3237539959 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 10756316 ps |
| CPU time | 1.15 seconds |
| Started | Feb 29 12:49:44 PM PST 24 |
| Finished | Feb 29 12:49:45 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-f2186ea1-f7e4-44b7-8e13-b62e2f128989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237539959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3237539959 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.4222667089 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1497189658 ps |
| CPU time | 21.43 seconds |
| Started | Feb 29 12:49:57 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-142fbcf4-0632-4c31-b8a7-b5880f31bcd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222667089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4222667089 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2331015506 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2393166226 ps |
| CPU time | 28.49 seconds |
| Started | Feb 29 12:50:00 PM PST 24 |
| Finished | Feb 29 12:50:30 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-5e3c811b-1979-448d-b252-8ce468cd3837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2331015506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2331015506 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2463800542 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 23808695484 ps |
| CPU time | 173.32 seconds |
| Started | Feb 29 12:50:17 PM PST 24 |
| Finished | Feb 29 12:53:10 PM PST 24 |
| Peak memory | 206940 kb |
| Host | smart-38bd2ae5-4483-42fb-acc5-adf32c13c9d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2463800542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2463800542 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3833739251 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 392428262 ps |
| CPU time | 33.96 seconds |
| Started | Feb 29 12:50:07 PM PST 24 |
| Finished | Feb 29 12:50:42 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-21ce8ea5-25cf-4174-81ed-78b2863a1c55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3833739251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3833739251 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.963448091 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 105591707 ps |
| CPU time | 2.12 seconds |
| Started | Feb 29 12:50:10 PM PST 24 |
| Finished | Feb 29 12:50:12 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-ccf3aa02-c912-4369-b2f7-167b501aae28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963448091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.963448091 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.170999711 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 213277425 ps |
| CPU time | 3.99 seconds |
| Started | Feb 29 12:50:14 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-c9f89e5c-5e0c-4537-97d1-cce306ad1e8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=170999711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.170999711 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3296047904 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 53284735633 ps |
| CPU time | 299.4 seconds |
| Started | Feb 29 12:50:14 PM PST 24 |
| Finished | Feb 29 12:55:14 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-3b48138d-2052-40d2-8f5a-dcc3312bb561 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3296047904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.3296047904 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1982536055 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 855296402 ps |
| CPU time | 7.8 seconds |
| Started | Feb 29 12:50:06 PM PST 24 |
| Finished | Feb 29 12:50:14 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-4a3d046d-11d6-49d9-a712-7c71928fefae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1982536055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1982536055 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.2094880435 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 59945694 ps |
| CPU time | 6.84 seconds |
| Started | Feb 29 12:49:58 PM PST 24 |
| Finished | Feb 29 12:50:05 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f00df175-af67-4033-b5cf-938c56af9d2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2094880435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2094880435 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3379172328 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 53559633 ps |
| CPU time | 7.68 seconds |
| Started | Feb 29 12:50:08 PM PST 24 |
| Finished | Feb 29 12:50:16 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-24ab6650-db8f-49be-9ce8-bb19d5fa34d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379172328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3379172328 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1370530326 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2916201496 ps |
| CPU time | 15.01 seconds |
| Started | Feb 29 12:50:04 PM PST 24 |
| Finished | Feb 29 12:50:19 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-0cf6032e-5f47-42af-a89c-5efdc03f489d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370530326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1370530326 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4157099716 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 39251297485 ps |
| CPU time | 88 seconds |
| Started | Feb 29 12:50:17 PM PST 24 |
| Finished | Feb 29 12:51:46 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-bbb1dfa1-43d1-4e1d-a914-f68f851c3310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4157099716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4157099716 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1400237229 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 19241169 ps |
| CPU time | 1.23 seconds |
| Started | Feb 29 12:50:20 PM PST 24 |
| Finished | Feb 29 12:50:21 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-c0171b20-7d6b-4906-b900-b3495ae58116 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400237229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1400237229 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1808316529 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 57401005 ps |
| CPU time | 4.38 seconds |
| Started | Feb 29 12:50:13 PM PST 24 |
| Finished | Feb 29 12:50:18 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-d48e000b-12ca-4081-9900-2b7b96b2a0b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808316529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1808316529 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3652511662 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 11137008 ps |
| CPU time | 1.36 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:04 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-9323252a-1e61-432d-b10d-a9a520b8d9a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652511662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3652511662 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2063747941 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3450696684 ps |
| CPU time | 5.6 seconds |
| Started | Feb 29 12:50:17 PM PST 24 |
| Finished | Feb 29 12:50:23 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-3c7412b4-ff4a-4791-ba39-0cb577496e9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063747941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2063747941 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2954320047 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1934965375 ps |
| CPU time | 7.13 seconds |
| Started | Feb 29 12:50:28 PM PST 24 |
| Finished | Feb 29 12:50:36 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-27b01114-8662-4787-9073-7fab10c447fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2954320047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2954320047 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4131371057 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 11594635 ps |
| CPU time | 1.2 seconds |
| Started | Feb 29 12:50:02 PM PST 24 |
| Finished | Feb 29 12:50:04 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-ca5ce900-3005-4bb0-903f-25af8bec101c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131371057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4131371057 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3605495606 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 124932685 ps |
| CPU time | 14.05 seconds |
| Started | Feb 29 12:50:10 PM PST 24 |
| Finished | Feb 29 12:50:24 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-93b9e638-cbad-4be7-84ce-6e8a4a4baf1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605495606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3605495606 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4095857567 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6781813795 ps |
| CPU time | 90.32 seconds |
| Started | Feb 29 12:50:26 PM PST 24 |
| Finished | Feb 29 12:51:57 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-c8436780-39c8-4e14-a575-7c8ef0e4fdea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4095857567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4095857567 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2781489207 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 289009242 ps |
| CPU time | 27.33 seconds |
| Started | Feb 29 12:50:07 PM PST 24 |
| Finished | Feb 29 12:50:35 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-502b2564-ff2d-4c1d-8bd0-b2d244d7eb34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781489207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2781489207 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.872743142 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 29246385 ps |
| CPU time | 7.33 seconds |
| Started | Feb 29 12:50:15 PM PST 24 |
| Finished | Feb 29 12:50:22 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-8df63ec8-e5e9-488b-8677-7f168e7aabc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872743142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.872743142 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3122053487 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 315019990 ps |
| CPU time | 2.67 seconds |
| Started | Feb 29 12:50:01 PM PST 24 |
| Finished | Feb 29 12:50:05 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-9709728f-1794-46ba-b106-439b89bba560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3122053487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3122053487 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |