Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	489	1			T3	1		T21	1		T24	1
all_values[1]	512	1			T3	1		T36	2		T38	8
all_values[2]	543	1			T3	1		T21	2		T36	1
all_values[3]	504	1			T3	1		T21	1		T36	2
all_values[4]	494	1			T3	1		T24	2		T36	2
all_values[5]	518	1			T21	1		T36	2		T38	4
all_values[6]	496	1			T36	1		T38	7		T118	1
all_values[7]	512	1			T3	1		T21	1		T24	1
all_values[8]	491	1			T18	1		T36	1		T38	6
all_values[9]	521	1			T3	2		T18	1		T21	1
all_values[10]	534	1			T3	1		T18	1		T35	1
all_values[11]	525	1			T3	1		T35	1		T38	7
all_values[12]	546	1			T3	1		T36	2		T38	5
all_values[13]	478	1			T21	1		T24	1		T38	8
all_values[14]	503	1			T35	1		T36	1		T38	12
all_values[15]	493	1			T3	1		T38	9		T44	1
all_values[16]	491	1			T21	1		T24	1		T35	1
all_values[17]	507	1			T35	1		T36	1		T38	12
all_values[18]	525	1			T3	1		T18	1		T24	1
all_values[19]	503	1			T3	1		T21	1		T24	3
all_values[20]	528	1			T21	1		T36	2		T38	4
all_values[21]	506	1			T18	1		T24	1		T36	1
all_values[22]	515	1			T21	1		T36	1		T38	10
all_values[23]	532	1			T36	1		T38	9		T58	1
all_values[24]	520	1			T18	3		T38	13		T118	1
all_values[25]	474	1			T36	1		T38	12		T118	1
all_values[26]	494	1			T3	1		T24	1		T36	3