Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	410	1			T19	1		T170	1		T171	1
all_values[1]	426	1			T170	2		T32	3		T51	1
all_values[2]	412	1			T19	2		T170	3		T171	1
all_values[3]	412	1			T170	2		T171	2		T32	7
all_values[4]	445	1			T19	1		T170	3		T171	2
all_values[5]	412	1			T170	4		T171	1		T32	5
all_values[6]	430	1			T19	2		T170	3		T32	1
all_values[7]	431	1			T170	1		T171	1		T32	3
all_values[8]	409	1			T170	2		T171	1		T32	5
all_values[9]	409	1			T19	1		T170	1		T171	1
all_values[10]	403	1			T19	1		T170	3		T32	4
all_values[11]	403	1			T19	1		T32	5		T174	1
all_values[12]	430	1			T19	2		T170	2		T171	2
all_values[13]	416	1			T170	3		T32	2		T39	1
all_values[14]	441	1			T19	1		T32	4		T34	1
all_values[15]	420	1			T19	1		T170	2		T32	6
all_values[16]	379	1			T19	1		T170	1		T32	2
all_values[17]	425	1			T19	1		T170	2		T171	1
all_values[18]	430	1			T19	2		T170	1		T171	1
all_values[19]	412	1			T170	5		T32	6		T36	1
all_values[20]	425	1			T32	8		T34	1		T51	1
all_values[21]	411	1			T170	3		T32	10		T36	1
all_values[22]	405	1			T170	2		T171	1		T32	5
all_values[23]	399	1			T170	2		T171	1		T32	8
all_values[24]	404	1			T19	2		T170	2		T171	3
all_values[25]	416	1			T170	2		T32	3		T34	1
all_values[26]	411	1			T170	1		T32	7		T61	1