| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.25 | 100.00 | 95.52 | 100.00 | 100.00 | 100.00 | 100.00 |
| T757 | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2014423423 | Mar 05 01:14:53 PM PST 24 | Mar 05 01:16:14 PM PST 24 | 36087021162 ps | ||
| T758 | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3019468045 | Mar 05 01:15:21 PM PST 24 | Mar 05 01:15:33 PM PST 24 | 4589429914 ps | ||
| T759 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3278547911 | Mar 05 01:15:42 PM PST 24 | Mar 05 01:16:27 PM PST 24 | 10110090425 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2671356118 | Mar 05 01:15:55 PM PST 24 | Mar 05 01:15:57 PM PST 24 | 169078395 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3938915218 | Mar 05 01:14:28 PM PST 24 | Mar 05 01:14:46 PM PST 24 | 206579831 ps | ||
| T8 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.130375054 | Mar 05 01:13:01 PM PST 24 | Mar 05 01:13:30 PM PST 24 | 337797097 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2147582169 | Mar 05 01:15:04 PM PST 24 | Mar 05 01:15:06 PM PST 24 | 67920124 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4090463142 | Mar 05 01:14:42 PM PST 24 | Mar 05 01:14:48 PM PST 24 | 1417772521 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3789465969 | Mar 05 01:15:31 PM PST 24 | Mar 05 01:17:52 PM PST 24 | 84753955528 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3232641694 | Mar 05 01:15:53 PM PST 24 | Mar 05 01:15:55 PM PST 24 | 73469622 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2284072035 | Mar 05 01:13:48 PM PST 24 | Mar 05 01:13:53 PM PST 24 | 628301840 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4201511930 | Mar 05 01:16:04 PM PST 24 | Mar 05 01:16:39 PM PST 24 | 9686230769 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/4.xbar_smoke.4070563627 | Mar 05 01:12:28 PM PST 24 | Mar 05 01:12:30 PM PST 24 | 63334039 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1171056030 | Mar 05 01:15:13 PM PST 24 | Mar 05 01:15:22 PM PST 24 | 83168815 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2582710921 | Mar 05 01:15:02 PM PST 24 | Mar 05 01:17:07 PM PST 24 | 9328036687 ps | ||
| T92 | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3371985178 | Mar 05 01:15:03 PM PST 24 | Mar 05 01:17:07 PM PST 24 | 54838863210 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3035166502 | Mar 05 01:14:51 PM PST 24 | Mar 05 01:14:55 PM PST 24 | 15918741 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/49.xbar_error_random.2108982852 | Mar 05 01:16:00 PM PST 24 | Mar 05 01:16:08 PM PST 24 | 467315769 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.117273695 | Mar 05 01:15:16 PM PST 24 | Mar 05 01:16:21 PM PST 24 | 622943277 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3625704168 | Mar 05 01:14:17 PM PST 24 | Mar 05 01:16:40 PM PST 24 | 3550943224 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.46899355 | Mar 05 01:15:44 PM PST 24 | Mar 05 01:16:09 PM PST 24 | 854333361 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3642826216 | Mar 05 01:12:23 PM PST 24 | Mar 05 01:12:32 PM PST 24 | 3895700842 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2528266531 | Mar 05 01:13:36 PM PST 24 | Mar 05 01:14:51 PM PST 24 | 15840431839 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1618601483 | Mar 05 01:14:02 PM PST 24 | Mar 05 01:14:03 PM PST 24 | 14421769 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2702893559 | Mar 05 01:16:07 PM PST 24 | Mar 05 01:17:31 PM PST 24 | 16477383516 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.649829821 | Mar 05 01:15:28 PM PST 24 | Mar 05 01:15:37 PM PST 24 | 4035843097 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2814868673 | Mar 05 01:16:00 PM PST 24 | Mar 05 01:16:11 PM PST 24 | 574303507 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3297332323 | Mar 05 01:14:03 PM PST 24 | Mar 05 01:15:01 PM PST 24 | 261395355 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1543415478 | Mar 05 01:15:02 PM PST 24 | Mar 05 01:15:06 PM PST 24 | 187726195 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.659861369 | Mar 05 01:13:37 PM PST 24 | Mar 05 01:13:46 PM PST 24 | 5480474961 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3810894822 | Mar 05 01:12:10 PM PST 24 | Mar 05 01:12:22 PM PST 24 | 108542195 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/36.xbar_smoke.858630282 | Mar 05 01:15:15 PM PST 24 | Mar 05 01:15:17 PM PST 24 | 50255728 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2368266378 | Mar 05 01:14:08 PM PST 24 | Mar 05 01:14:15 PM PST 24 | 1025569374 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2366922000 | Mar 05 01:16:03 PM PST 24 | Mar 05 01:16:09 PM PST 24 | 42914030 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1675716583 | Mar 05 01:15:26 PM PST 24 | Mar 05 01:15:28 PM PST 24 | 95705157 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.169159051 | Mar 05 01:12:10 PM PST 24 | Mar 05 01:14:28 PM PST 24 | 85307446633 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.781171406 | Mar 05 01:12:37 PM PST 24 | Mar 05 01:12:48 PM PST 24 | 51974322 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.341920654 | Mar 05 01:14:17 PM PST 24 | Mar 05 01:14:35 PM PST 24 | 282064691 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/41.xbar_random.2285148691 | Mar 05 01:15:41 PM PST 24 | Mar 05 01:15:44 PM PST 24 | 23835005 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.984257805 | Mar 05 01:13:49 PM PST 24 | Mar 05 01:13:50 PM PST 24 | 16967685 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/12.xbar_error_random.2232124960 | Mar 05 01:13:32 PM PST 24 | Mar 05 01:13:42 PM PST 24 | 1784044356 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2228646056 | Mar 05 01:15:43 PM PST 24 | Mar 05 01:16:41 PM PST 24 | 26964631524 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.731576905 | Mar 05 01:14:08 PM PST 24 | Mar 05 01:14:21 PM PST 24 | 104289149 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.842252420 | Mar 05 01:16:00 PM PST 24 | Mar 05 01:16:10 PM PST 24 | 1321346777 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.250875761 | Mar 05 01:14:39 PM PST 24 | Mar 05 01:16:21 PM PST 24 | 24353119004 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3855629940 | Mar 05 01:13:02 PM PST 24 | Mar 05 01:13:12 PM PST 24 | 181933532 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/45.xbar_random.3253525979 | Mar 05 01:15:51 PM PST 24 | Mar 05 01:15:59 PM PST 24 | 267981805 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2742157478 | Mar 05 01:13:12 PM PST 24 | Mar 05 01:13:18 PM PST 24 | 369183482 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3507004420 | Mar 05 01:13:20 PM PST 24 | Mar 05 01:13:53 PM PST 24 | 1096427332 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/41.xbar_error_random.4091200677 | Mar 05 01:15:38 PM PST 24 | Mar 05 01:15:42 PM PST 24 | 53953627 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3361815484 | Mar 05 01:14:38 PM PST 24 | Mar 05 01:14:49 PM PST 24 | 1502638961 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3779833503 | Mar 05 01:15:40 PM PST 24 | Mar 05 01:16:23 PM PST 24 | 526604208 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.4047791637 | Mar 05 01:15:31 PM PST 24 | Mar 05 01:15:43 PM PST 24 | 85389077 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1496253951 | Mar 05 01:12:30 PM PST 24 | Mar 05 01:12:32 PM PST 24 | 19913215 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/12.xbar_random.3016186640 | Mar 05 01:13:13 PM PST 24 | Mar 05 01:13:15 PM PST 24 | 18262746 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/30.xbar_error_random.273532705 | Mar 05 01:14:46 PM PST 24 | Mar 05 01:15:01 PM PST 24 | 1023317612 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1458885607 | Mar 05 01:16:03 PM PST 24 | Mar 05 01:16:19 PM PST 24 | 2415992236 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.637343481 | Mar 05 01:14:41 PM PST 24 | Mar 05 01:14:44 PM PST 24 | 21674228 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3112038811 | Mar 05 01:15:39 PM PST 24 | Mar 05 01:18:07 PM PST 24 | 5996582242 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/7.xbar_random.3531844792 | Mar 05 01:12:54 PM PST 24 | Mar 05 01:13:07 PM PST 24 | 503501509 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2206997509 | Mar 05 01:13:35 PM PST 24 | Mar 05 01:13:44 PM PST 24 | 1310253387 ps | ||
| T142 | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3107629525 | Mar 05 01:12:28 PM PST 24 | Mar 05 01:12:38 PM PST 24 | 653470474 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.286386903 | Mar 05 01:13:01 PM PST 24 | Mar 05 01:13:14 PM PST 24 | 4951712568 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.4214326527 | Mar 05 01:15:30 PM PST 24 | Mar 05 01:15:31 PM PST 24 | 12262005 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3535852359 | Mar 05 01:13:01 PM PST 24 | Mar 05 01:13:06 PM PST 24 | 36102390 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.629786179 | Mar 05 01:15:40 PM PST 24 | Mar 05 01:15:52 PM PST 24 | 73887304 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.775915341 | Mar 05 01:12:12 PM PST 24 | Mar 05 01:13:57 PM PST 24 | 54778803244 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.175294760 | Mar 05 01:15:38 PM PST 24 | Mar 05 01:18:08 PM PST 24 | 191521457283 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.742357641 | Mar 05 01:14:33 PM PST 24 | Mar 05 01:14:43 PM PST 24 | 430465896 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3799081728 | Mar 05 01:12:18 PM PST 24 | Mar 05 01:12:19 PM PST 24 | 15771086 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.55332128 | Mar 05 01:13:23 PM PST 24 | Mar 05 01:15:33 PM PST 24 | 554191944 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3862791404 | Mar 05 01:13:57 PM PST 24 | Mar 05 01:13:58 PM PST 24 | 22905708 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/23.xbar_same_source.303528989 | Mar 05 01:14:18 PM PST 24 | Mar 05 01:14:26 PM PST 24 | 749982035 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2311975463 | Mar 05 01:14:08 PM PST 24 | Mar 05 01:14:09 PM PST 24 | 10025367 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1002856162 | Mar 05 01:14:51 PM PST 24 | Mar 05 01:15:04 PM PST 24 | 1242514512 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4115489879 | Mar 05 01:14:52 PM PST 24 | Mar 05 01:14:53 PM PST 24 | 16377759 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2708267763 | Mar 05 01:15:26 PM PST 24 | Mar 05 01:17:53 PM PST 24 | 37594354887 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.598658225 | Mar 05 01:14:29 PM PST 24 | Mar 05 01:17:52 PM PST 24 | 36651878687 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1330047099 | Mar 05 01:13:44 PM PST 24 | Mar 05 01:17:09 PM PST 24 | 16454202453 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1149706488 | Mar 05 01:12:35 PM PST 24 | Mar 05 01:13:18 PM PST 24 | 381925665 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2072468823 | Mar 05 01:13:51 PM PST 24 | Mar 05 01:13:53 PM PST 24 | 11221079 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3944571982 | Mar 05 01:15:19 PM PST 24 | Mar 05 01:15:26 PM PST 24 | 1124300479 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.791045574 | Mar 05 01:14:04 PM PST 24 | Mar 05 01:14:10 PM PST 24 | 248630244 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2940706642 | Mar 05 01:13:45 PM PST 24 | Mar 05 01:13:47 PM PST 24 | 54995680 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2544144841 | Mar 05 01:13:36 PM PST 24 | Mar 05 01:13:43 PM PST 24 | 1200708434 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1531612874 | Mar 05 01:14:31 PM PST 24 | Mar 05 01:16:27 PM PST 24 | 35455189499 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3009687884 | Mar 05 01:12:26 PM PST 24 | Mar 05 01:12:30 PM PST 24 | 889103500 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/18.xbar_same_source.515539032 | Mar 05 01:13:49 PM PST 24 | Mar 05 01:13:55 PM PST 24 | 482538122 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.549718730 | Mar 05 01:14:31 PM PST 24 | Mar 05 01:14:36 PM PST 24 | 100612969 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2368056309 | Mar 05 01:14:34 PM PST 24 | Mar 05 01:15:59 PM PST 24 | 15774755482 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2282868975 | Mar 05 01:15:27 PM PST 24 | Mar 05 01:17:00 PM PST 24 | 659344576 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.363055263 | Mar 05 01:13:02 PM PST 24 | Mar 05 01:13:43 PM PST 24 | 10097087809 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.176859759 | Mar 05 01:15:51 PM PST 24 | Mar 05 01:16:50 PM PST 24 | 11829830009 ps | ||
| T93 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3157482616 | Mar 05 01:15:40 PM PST 24 | Mar 05 01:15:56 PM PST 24 | 1834150707 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3559890789 | Mar 05 01:15:16 PM PST 24 | Mar 05 01:15:18 PM PST 24 | 8772735 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4007791055 | Mar 05 01:13:03 PM PST 24 | Mar 05 01:15:20 PM PST 24 | 6501834131 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3661225044 | Mar 05 01:16:02 PM PST 24 | Mar 05 01:16:10 PM PST 24 | 2950333830 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3496955211 | Mar 05 01:14:43 PM PST 24 | Mar 05 01:14:46 PM PST 24 | 28162774 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2182965650 | Mar 05 01:13:10 PM PST 24 | Mar 05 01:13:20 PM PST 24 | 938587845 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1551173584 | Mar 05 01:13:20 PM PST 24 | Mar 05 01:14:37 PM PST 24 | 24650948012 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.614960584 | Mar 05 01:16:02 PM PST 24 | Mar 05 01:16:04 PM PST 24 | 46325569 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/49.xbar_random.2854724690 | Mar 05 01:16:05 PM PST 24 | Mar 05 01:16:12 PM PST 24 | 76608888 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3337209090 | Mar 05 01:14:52 PM PST 24 | Mar 05 01:14:54 PM PST 24 | 8250852 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3730459326 | Mar 05 01:13:57 PM PST 24 | Mar 05 01:14:02 PM PST 24 | 46622288 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3047640159 | Mar 05 01:12:39 PM PST 24 | Mar 05 01:12:40 PM PST 24 | 8693896 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1726931192 | Mar 05 01:15:25 PM PST 24 | Mar 05 01:15:29 PM PST 24 | 48735447 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3477200345 | Mar 05 01:13:56 PM PST 24 | Mar 05 01:14:05 PM PST 24 | 5666275110 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3461047059 | Mar 05 01:14:08 PM PST 24 | Mar 05 01:16:55 PM PST 24 | 1168425441 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4276918158 | Mar 05 01:12:40 PM PST 24 | Mar 05 01:14:06 PM PST 24 | 5066896686 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2935063502 | Mar 05 01:15:40 PM PST 24 | Mar 05 01:15:44 PM PST 24 | 3960919003 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2961045861 | Mar 05 01:12:29 PM PST 24 | Mar 05 01:12:30 PM PST 24 | 23933131 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.174464150 | Mar 05 01:15:20 PM PST 24 | Mar 05 01:15:21 PM PST 24 | 9307819 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1013928884 | Mar 05 01:13:31 PM PST 24 | Mar 05 01:13:33 PM PST 24 | 44243524 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.939765772 | Mar 05 01:15:43 PM PST 24 | Mar 05 01:15:44 PM PST 24 | 7920719 ps | ||
| T9 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3308375883 | Mar 05 01:15:50 PM PST 24 | Mar 05 01:18:01 PM PST 24 | 3035767632 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.268798569 | Mar 05 01:16:03 PM PST 24 | Mar 05 01:16:06 PM PST 24 | 117008718 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.395273107 | Mar 05 01:13:31 PM PST 24 | Mar 05 01:13:37 PM PST 24 | 112856220 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1411418699 | Mar 05 01:12:39 PM PST 24 | Mar 05 01:12:45 PM PST 24 | 236496310 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.843427088 | Mar 05 01:13:02 PM PST 24 | Mar 05 01:13:09 PM PST 24 | 32081439 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.225181440 | Mar 05 01:14:55 PM PST 24 | Mar 05 01:16:14 PM PST 24 | 484000733 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2304856065 | Mar 05 01:15:22 PM PST 24 | Mar 05 01:15:25 PM PST 24 | 151182281 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2593774754 | Mar 05 01:15:16 PM PST 24 | Mar 05 01:15:19 PM PST 24 | 513208686 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2706650 | Mar 05 01:14:28 PM PST 24 | Mar 05 01:14:29 PM PST 24 | 160420437 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3186082399 | Mar 05 01:13:00 PM PST 24 | Mar 05 01:13:40 PM PST 24 | 356400774 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2308775884 | Mar 05 01:15:02 PM PST 24 | Mar 05 01:15:15 PM PST 24 | 696987415 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/43.xbar_random.3576696710 | Mar 05 01:15:41 PM PST 24 | Mar 05 01:15:53 PM PST 24 | 639904816 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3982735776 | Mar 05 01:16:16 PM PST 24 | Mar 05 01:16:18 PM PST 24 | 40100264 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.258473127 | Mar 05 01:12:19 PM PST 24 | Mar 05 01:13:50 PM PST 24 | 3181150737 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1314427760 | Mar 05 01:13:22 PM PST 24 | Mar 05 01:13:31 PM PST 24 | 1979641715 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2055669550 | Mar 05 01:13:58 PM PST 24 | Mar 05 01:16:05 PM PST 24 | 122566162627 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1038123783 | Mar 05 01:15:39 PM PST 24 | Mar 05 01:15:48 PM PST 24 | 10942969664 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2399082530 | Mar 05 01:16:03 PM PST 24 | Mar 05 01:16:04 PM PST 24 | 18035366 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1840139150 | Mar 05 01:14:09 PM PST 24 | Mar 05 01:14:11 PM PST 24 | 80135581 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.303581826 | Mar 05 01:15:04 PM PST 24 | Mar 05 01:15:11 PM PST 24 | 2914656029 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2677748581 | Mar 05 01:12:09 PM PST 24 | Mar 05 01:14:18 PM PST 24 | 34045692074 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1577017618 | Mar 05 01:12:29 PM PST 24 | Mar 05 01:13:34 PM PST 24 | 9680596094 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3965446706 | Mar 05 01:16:01 PM PST 24 | Mar 05 01:16:04 PM PST 24 | 37657918 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.200582483 | Mar 05 01:15:01 PM PST 24 | Mar 05 01:15:03 PM PST 24 | 10028615 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/28.xbar_random.3734430129 | Mar 05 01:14:39 PM PST 24 | Mar 05 01:14:43 PM PST 24 | 39911396 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2867480193 | Mar 05 01:15:49 PM PST 24 | Mar 05 01:15:51 PM PST 24 | 72532338 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4140783458 | Mar 05 01:15:26 PM PST 24 | Mar 05 01:15:32 PM PST 24 | 1044349940 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1398090477 | Mar 05 01:13:47 PM PST 24 | Mar 05 01:14:00 PM PST 24 | 11122426801 ps | ||
| T11 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2882062102 | Mar 05 01:14:06 PM PST 24 | Mar 05 01:14:52 PM PST 24 | 323748022 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2014449483 | Mar 05 01:12:22 PM PST 24 | Mar 05 01:12:27 PM PST 24 | 42282406 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.622988029 | Mar 05 01:15:40 PM PST 24 | Mar 05 01:15:43 PM PST 24 | 28247435 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2041937940 | Mar 05 01:14:43 PM PST 24 | Mar 05 01:16:59 PM PST 24 | 111473768168 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1690819203 | Mar 05 01:15:57 PM PST 24 | Mar 05 01:16:07 PM PST 24 | 63785302 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.914284266 | Mar 05 01:12:19 PM PST 24 | Mar 05 01:12:28 PM PST 24 | 445311747 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2451500103 | Mar 05 01:13:35 PM PST 24 | Mar 05 01:14:11 PM PST 24 | 710906172 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/1.xbar_error_random.4187943429 | Mar 05 01:12:11 PM PST 24 | Mar 05 01:12:16 PM PST 24 | 262381776 ps |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3986362788 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1029844770 ps |
| CPU time | 9.79 seconds |
| Started | Mar 05 01:14:20 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-ef54ed87-e81a-4b40-b35c-2a9622ada3ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986362788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3986362788 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.975246993 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 43976895121 ps |
| CPU time | 339.69 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:17:51 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-d24a238c-5b9b-4686-aae8-ec01d6240dd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=975246993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.975246993 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.25681703 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 68068097333 ps |
| CPU time | 283.42 seconds |
| Started | Mar 05 01:15:21 PM PST 24 |
| Finished | Mar 05 01:20:04 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-5bfe62af-1805-41d4-8906-5ffb55f6ac69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=25681703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow _rsp.25681703 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3548834225 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 108710971059 ps |
| CPU time | 208.17 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:17:45 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-ab739511-9583-4c85-a1a0-6d6373868238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3548834225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3548834225 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.619407070 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3303898731 ps |
| CPU time | 100.22 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:17:19 PM PST 24 |
| Peak memory | 205716 kb |
| Host | smart-a5648caa-064b-44d1-bbda-0bc8e5851c64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=619407070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand _reset.619407070 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2494418970 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 127470552615 ps |
| CPU time | 210.53 seconds |
| Started | Mar 05 01:15:58 PM PST 24 |
| Finished | Mar 05 01:19:28 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-fe3dc564-0f3b-4b5f-aeb4-1bc3857b8edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2494418970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2494418970 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1276921656 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 46926033 ps |
| CPU time | 5.38 seconds |
| Started | Mar 05 01:12:15 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-0cdab748-f02a-4f5a-8e17-19700cb8b119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1276921656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1276921656 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4153089752 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 69494786029 ps |
| CPU time | 196.48 seconds |
| Started | Mar 05 01:13:15 PM PST 24 |
| Finished | Mar 05 01:16:32 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-6460dd1b-19b0-47f0-aee8-f947fefbd208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4153089752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.4153089752 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1424551203 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 174272469107 ps |
| CPU time | 367.98 seconds |
| Started | Mar 05 01:15:28 PM PST 24 |
| Finished | Mar 05 01:21:36 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-df9395a5-4bcb-408f-b39e-76a503e7b149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1424551203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1424551203 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2212179172 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 122776694281 ps |
| CPU time | 190.02 seconds |
| Started | Mar 05 01:15:23 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-9995b3b8-5833-4e6a-b7ff-ace97788cf11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212179172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2212179172 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3151077549 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2887079463 ps |
| CPU time | 135.04 seconds |
| Started | Mar 05 01:12:36 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 205452 kb |
| Host | smart-76c8bf5a-8299-4ada-af3a-be51b027a4ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151077549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.3151077549 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1865767492 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 47025693260 ps |
| CPU time | 213.91 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:17:42 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-8e434e95-657a-404d-b57f-257d34436f4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1865767492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1865767492 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.130375054 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 337797097 ps |
| CPU time | 28.37 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:30 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-4acda7fa-cfcf-4e26-a25b-d759ab1b9615 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=130375054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese t_error.130375054 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4134828626 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 505636135 ps |
| CPU time | 63.27 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:14:16 PM PST 24 |
| Peak memory | 204060 kb |
| Host | smart-b82b039e-053a-4de5-a49e-5ed71af0c4fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134828626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.4134828626 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.3583883374 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 709096735 ps |
| CPU time | 41.11 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-7f26d70e-c8d7-4906-8eda-56015fbf90f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3583883374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3583883374 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1483929641 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 11665172414 ps |
| CPU time | 187.89 seconds |
| Started | Mar 05 01:12:38 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 206500 kb |
| Host | smart-6613800b-30da-4528-b151-46e71aca9a1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1483929641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1483929641 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3971391249 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1119816035 ps |
| CPU time | 22.77 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:34 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-a0787ef6-55f2-490b-a626-97c85021f5d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3971391249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3971391249 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.779476057 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2423970532 ps |
| CPU time | 77.7 seconds |
| Started | Mar 05 01:14:01 PM PST 24 |
| Finished | Mar 05 01:15:18 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-7128763b-5ff5-4b57-954e-a4d9eb1956a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=779476057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.779476057 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3353674195 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 12836067368 ps |
| CPU time | 217.35 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:19:39 PM PST 24 |
| Peak memory | 208104 kb |
| Host | smart-d5d63375-1a7d-4b7f-a5dd-eb05662c0977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353674195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3353674195 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3486149149 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 46822361396 ps |
| CPU time | 354.57 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:20:14 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-e2937c63-62db-4565-bc7b-75691f682a69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3486149149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3486149149 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2784760261 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 8556723266 ps |
| CPU time | 127.54 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:16:38 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-cee06973-1ab0-4f3e-91c5-70f09c0687ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784760261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.2784760261 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2087542960 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 55033419985 ps |
| CPU time | 74.49 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:15:56 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-659147d7-b1f2-43ae-a6c0-29db9349d144 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2087542960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2087542960 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3810894822 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 108542195 ps |
| CPU time | 11.69 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:22 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-cb9b7c12-f4ea-4af8-b63a-94e854796dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810894822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3810894822 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.32947831 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1974188816 ps |
| CPU time | 13.6 seconds |
| Started | Mar 05 01:12:15 PM PST 24 |
| Finished | Mar 05 01:12:29 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-477c0cc1-9daa-42c2-a0b1-32732a47b92c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=32947831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.32947831 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.3424185631 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 38086744 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:12 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-900b6436-16ae-4b69-9b6b-b087241f6c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3424185631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3424185631 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.775915341 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 54778803244 ps |
| CPU time | 103.97 seconds |
| Started | Mar 05 01:12:12 PM PST 24 |
| Finished | Mar 05 01:13:57 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-ac50777e-eaae-4d9e-8be9-8e539b810085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=775915341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.775915341 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2036545198 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5668741675 ps |
| CPU time | 33.97 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:12:43 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-32ddfa81-5080-4f32-acfc-06a4e9db3cfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2036545198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2036545198 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3840015102 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 128680103 ps |
| CPU time | 6.81 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:12:18 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-35e6a156-6e8a-4aa7-b553-a90684382e74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840015102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3840015102 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.782615996 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2073348943 ps |
| CPU time | 9.46 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-3e247b66-3411-4dea-9343-3a1b20656a1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=782615996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.782615996 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.4016461662 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 55971787 ps |
| CPU time | 1.76 seconds |
| Started | Mar 05 01:12:15 PM PST 24 |
| Finished | Mar 05 01:12:17 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-95ff842d-000d-46c3-bb24-97c247c3a1fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016461662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4016461662 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2287939533 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4218374594 ps |
| CPU time | 9.56 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-abd00277-5cfe-4203-802a-30f37ec186d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287939533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2287939533 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.189407526 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1005392661 ps |
| CPU time | 5.14 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:12:15 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-af3f33a3-0f51-4192-a09c-e9fba7076090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=189407526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.189407526 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1471136269 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 12093864 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:12:08 PM PST 24 |
| Finished | Mar 05 01:12:10 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-efa052ca-fd74-4aab-8566-a2f03546d6ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471136269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1471136269 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.4128173371 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 511852881 ps |
| CPU time | 14.01 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:24 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-6a5f75ca-5fd0-4a4d-a384-f59ab6e3bb46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4128173371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4128173371 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4222602624 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4878101710 ps |
| CPU time | 61.43 seconds |
| Started | Mar 05 01:12:13 PM PST 24 |
| Finished | Mar 05 01:13:15 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-421277b2-4bab-4d51-ab06-ffe37577e3e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222602624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4222602624 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.46507193 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1473843381 ps |
| CPU time | 99.69 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:13:52 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-d601f649-b510-4ba7-8ee6-9758d10cce19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46507193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_r eset.46507193 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1996228382 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1585267750 ps |
| CPU time | 214.21 seconds |
| Started | Mar 05 01:12:08 PM PST 24 |
| Finished | Mar 05 01:15:43 PM PST 24 |
| Peak memory | 220260 kb |
| Host | smart-4fd950a2-af3e-4a4f-8846-7770ca8b610e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996228382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.1996228382 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3555955298 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 873640975 ps |
| CPU time | 11.77 seconds |
| Started | Mar 05 01:12:12 PM PST 24 |
| Finished | Mar 05 01:12:24 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-aaf39ae5-b66e-496c-a840-f36fb5694382 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555955298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3555955298 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3331554449 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 912430649 ps |
| CPU time | 18.51 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:12:30 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-3b0928ac-1c61-4976-9d08-f88f6d15d32c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3331554449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3331554449 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3847526855 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 39485086396 ps |
| CPU time | 259 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:16:28 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-29d1757c-842a-46f3-84d3-6ea048a548cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3847526855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3847526855 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2856510030 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 42204074 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-449129c4-dbda-4bc0-af23-81ee413e9b3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856510030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2856510030 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.4187943429 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 262381776 ps |
| CPU time | 4.57 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:12:16 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-39979b3c-3148-493d-b0bd-678feba9dc40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4187943429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4187943429 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.403445565 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 427655371 ps |
| CPU time | 7.44 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:12:17 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-3331082e-1a36-4a01-bcb4-79c53bdd5620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403445565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.403445565 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2677748581 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 34045692074 ps |
| CPU time | 128.42 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:14:18 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-81fb95ec-a2e1-46c0-8587-d48eb92adcaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677748581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2677748581 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.169159051 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 85307446633 ps |
| CPU time | 137.48 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e092ee70-0b4c-41cd-ad7e-190a918919bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=169159051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.169159051 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1218883529 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 50104582 ps |
| CPU time | 6.41 seconds |
| Started | Mar 05 01:12:13 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-5650cc3a-ebac-4205-bc65-621616e615c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218883529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1218883529 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.3013102654 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 67377339 ps |
| CPU time | 1.64 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 01:12:11 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-958880e8-d969-4a8a-a6b3-71de7198b323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013102654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3013102654 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.37059928 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 91010278 ps |
| CPU time | 1.67 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:12:13 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-166dd644-2d47-47d7-8410-32ba03e9f3b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=37059928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.37059928 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2856376832 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2417529674 ps |
| CPU time | 9.73 seconds |
| Started | Mar 05 01:12:13 PM PST 24 |
| Finished | Mar 05 01:12:23 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-67c7e85f-8e4e-4a20-9948-2b0a98a702bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856376832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2856376832 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.492300765 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4158424204 ps |
| CPU time | 12.04 seconds |
| Started | Mar 05 01:12:12 PM PST 24 |
| Finished | Mar 05 01:12:24 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-8b6a85df-8fe6-46d5-a2ec-0f8ec58965cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=492300765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.492300765 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1917988897 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 13858206 ps |
| CPU time | 1.26 seconds |
| Started | Mar 05 01:12:10 PM PST 24 |
| Finished | Mar 05 01:12:12 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-8e9b6998-d0c4-4555-aa64-d437e678eed9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917988897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1917988897 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1182916446 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2709100821 ps |
| CPU time | 39.84 seconds |
| Started | Mar 05 01:12:26 PM PST 24 |
| Finished | Mar 05 01:13:06 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-c5e7326f-7cf7-47fb-8cfd-a585bba939dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182916446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1182916446 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4080962215 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4032764304 ps |
| CPU time | 57.88 seconds |
| Started | Mar 05 01:12:24 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-c425e608-f851-4c7c-80c8-fa99f1e02860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4080962215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4080962215 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3368720014 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5748853936 ps |
| CPU time | 100.16 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-43c93a5c-9350-4927-8ece-a35b9f0644cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3368720014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.3368720014 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1118918665 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 184138249 ps |
| CPU time | 22.7 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-6a72c620-3279-49b6-beed-9a8383dbaf50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1118918665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1118918665 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3822800044 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 110075514 ps |
| CPU time | 3.82 seconds |
| Started | Mar 05 01:12:23 PM PST 24 |
| Finished | Mar 05 01:12:27 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-d56b2a43-dd9a-463d-b751-7757bae0bb20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822800044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3822800044 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1923156757 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 24866065956 ps |
| CPU time | 165.03 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:15:58 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-944d1be2-2d67-405c-a47e-be2f67403170 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1923156757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1923156757 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2182965650 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 938587845 ps |
| CPU time | 9.61 seconds |
| Started | Mar 05 01:13:10 PM PST 24 |
| Finished | Mar 05 01:13:20 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-a9ac4ac3-55c8-4a40-be95-7ad3640bd117 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182965650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2182965650 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2439572409 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 112877561 ps |
| CPU time | 9.72 seconds |
| Started | Mar 05 01:13:16 PM PST 24 |
| Finished | Mar 05 01:13:26 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-c66b12f9-2a6a-4188-abf9-af60d145edd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2439572409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2439572409 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.1061526537 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 20455888 ps |
| CPU time | 2.86 seconds |
| Started | Mar 05 01:12:59 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-9024d48d-532a-48f4-8458-52c1e8eb2646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1061526537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1061526537 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2656215654 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 117671972189 ps |
| CPU time | 164.14 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:15:45 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-607707e2-7459-49ee-82d5-9a0c5a36a9aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656215654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2656215654 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.493084135 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 18198334602 ps |
| CPU time | 73.58 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:14:16 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-424b2eb2-6424-4dff-b021-9fd4c37eb0da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=493084135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.493084135 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3855629940 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 181933532 ps |
| CPU time | 9.45 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:13:12 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-2eadf045-8cd7-4b96-a563-d7a3f145d74f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855629940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3855629940 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1878131474 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 615716174 ps |
| CPU time | 8.64 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:20 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-aa213a59-f4fd-424d-9faf-bace68512b10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878131474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1878131474 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2186118220 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 9667344 ps |
| CPU time | 1.45 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:13:04 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-2fe38cea-65cc-4194-a677-e54d5b01d16c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186118220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2186118220 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3847007771 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2529353336 ps |
| CPU time | 7.87 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:13:10 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-3c3123cb-a643-417e-bf66-5ae64a91c2a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847007771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3847007771 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.286386903 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4951712568 ps |
| CPU time | 12.16 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:14 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-77ba8096-7550-480f-9310-b4fb523f74e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=286386903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.286386903 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1039484807 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 9436374 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:13 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-bd53d5d4-83b1-4bfb-83d4-eb61d53ffd2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039484807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1039484807 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.302807353 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3908932065 ps |
| CPU time | 52.05 seconds |
| Started | Mar 05 01:13:10 PM PST 24 |
| Finished | Mar 05 01:14:02 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-79cdbab2-741f-4604-92be-3ce6f85c31ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302807353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.302807353 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1592061149 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4562984386 ps |
| CPU time | 62.01 seconds |
| Started | Mar 05 01:13:15 PM PST 24 |
| Finished | Mar 05 01:14:17 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-42cf46c8-ed43-4ac3-a9b8-a94e020baaac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1592061149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1592061149 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1942583633 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1718682659 ps |
| CPU time | 182.16 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:16:15 PM PST 24 |
| Peak memory | 207656 kb |
| Host | smart-751cd043-ad14-4ba2-8935-baeac9aae148 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942583633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1942583633 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.375530346 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 64863428 ps |
| CPU time | 3.64 seconds |
| Started | Mar 05 01:13:16 PM PST 24 |
| Finished | Mar 05 01:13:20 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-4514c48e-8771-4aee-86ca-b49fb1602dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=375530346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.375530346 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2678360331 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 665339896 ps |
| CPU time | 9.71 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-f8e35fa6-9ff0-4193-85b7-84e002875f37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2678360331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2678360331 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3322633278 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5127743753 ps |
| CPU time | 14.92 seconds |
| Started | Mar 05 01:13:14 PM PST 24 |
| Finished | Mar 05 01:13:29 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-44f0c40f-5db4-48d2-a7f2-677dc5a0d6a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3322633278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3322633278 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2742157478 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 369183482 ps |
| CPU time | 6.44 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:18 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-e0d1d8f9-5c7a-4533-89a5-365ad475a85a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742157478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2742157478 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1887144727 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5920377443 ps |
| CPU time | 13.13 seconds |
| Started | Mar 05 01:13:14 PM PST 24 |
| Finished | Mar 05 01:13:27 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-2ecf72cb-ea7e-4c4a-8557-b69a39d683d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887144727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1887144727 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.4064195109 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 34301608 ps |
| CPU time | 3.07 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:15 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-131cca27-65b6-4c2a-be61-1ef7a6555120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064195109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4064195109 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2536076252 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 39058706218 ps |
| CPU time | 110.24 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e0222508-969f-4fb7-876d-fcf34f3fbf6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536076252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2536076252 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2285632908 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 26125462607 ps |
| CPU time | 31.52 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:44 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-1ce7eeae-5b29-404b-a0cc-8877d22b6853 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2285632908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2285632908 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3128422720 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 180343783 ps |
| CPU time | 6.45 seconds |
| Started | Mar 05 01:13:15 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-5af38acb-fcfa-4b20-b644-16d4789276ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128422720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3128422720 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.1564123556 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 74298648 ps |
| CPU time | 6.57 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:20 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-88bb3c5f-909d-4497-9292-4dab8e813912 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1564123556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1564123556 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2323507113 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 9934169 ps |
| CPU time | 1.4 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:25 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-5cd58cd8-8732-4174-8fec-92caf0806309 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323507113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2323507113 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2830780905 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3138666744 ps |
| CPU time | 11.04 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-f72b5809-0770-4ecb-8cbe-89a454de54af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830780905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2830780905 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.603604541 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 4091416048 ps |
| CPU time | 7.93 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-13177884-d2a5-42a9-8bfb-c9e99144e4dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=603604541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.603604541 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.955907717 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 27314286 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:13:10 PM PST 24 |
| Finished | Mar 05 01:13:12 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-73307851-c19c-45f6-bb4a-c187354335fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955907717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.955907717 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2548311531 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 510743917 ps |
| CPU time | 47.28 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:58 PM PST 24 |
| Peak memory | 203976 kb |
| Host | smart-50830d68-d010-4912-900d-c7a1521d7ff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548311531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2548311531 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.693801664 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1651229357 ps |
| CPU time | 28.24 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-30e04428-21e7-4866-912f-cdbc09326367 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693801664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.693801664 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.4010338566 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 78432311 ps |
| CPU time | 10.24 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:23 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-44093a9d-804f-4513-9066-3e70ad7a36bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4010338566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.4010338566 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.188752191 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 297216900 ps |
| CPU time | 23.05 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:34 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-7852a0be-a6ea-4f3a-a11a-2ae37d5935d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188752191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res et_error.188752191 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.4273406978 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 42401716 ps |
| CPU time | 1.42 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:13 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-27cd3609-8e5c-457a-bcec-e43e0d9cde58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273406978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4273406978 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2251184330 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 55810651 ps |
| CPU time | 8.85 seconds |
| Started | Mar 05 01:13:16 PM PST 24 |
| Finished | Mar 05 01:13:25 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-f321f866-ede4-4604-93f2-d16668712ffb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2251184330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2251184330 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1029010524 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 519075007 ps |
| CPU time | 8.75 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:13:34 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-0db8804c-cbce-4b37-bbf2-65ee98c2df33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029010524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1029010524 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.2232124960 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1784044356 ps |
| CPU time | 10.66 seconds |
| Started | Mar 05 01:13:32 PM PST 24 |
| Finished | Mar 05 01:13:42 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-b70e5e22-a79e-4fd5-b8a9-caa338273389 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232124960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2232124960 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3016186640 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 18262746 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:15 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-592fb702-6267-449c-a218-47e9b761ca93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3016186640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3016186640 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.959045363 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11560816588 ps |
| CPU time | 54.4 seconds |
| Started | Mar 05 01:13:15 PM PST 24 |
| Finished | Mar 05 01:14:09 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-7a958336-22f5-4878-aed7-422e562713ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=959045363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.959045363 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3575222039 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3212636526 ps |
| CPU time | 26.28 seconds |
| Started | Mar 05 01:13:15 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-91fba156-0d0c-421e-96b9-b5c4995bb776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3575222039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3575222039 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1003182876 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 40938465 ps |
| CPU time | 4.28 seconds |
| Started | Mar 05 01:13:14 PM PST 24 |
| Finished | Mar 05 01:13:19 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-a5abeca0-954c-484b-ae4d-993b7c594709 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003182876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1003182876 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.184382116 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 50488593 ps |
| CPU time | 4.13 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:17 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-7c6ec99c-2c39-4a86-b4bb-e92713032c9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184382116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.184382116 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.3358963983 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 31149980 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:13:11 PM PST 24 |
| Finished | Mar 05 01:13:12 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-187d4037-e14a-42ae-88a8-0395ab316668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3358963983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3358963983 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3150856854 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2688212832 ps |
| CPU time | 5.67 seconds |
| Started | Mar 05 01:13:14 PM PST 24 |
| Finished | Mar 05 01:13:20 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-e642f87e-4a47-42a9-996f-eda084f42974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150856854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3150856854 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1656105732 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2466708224 ps |
| CPU time | 6.94 seconds |
| Started | Mar 05 01:13:10 PM PST 24 |
| Finished | Mar 05 01:13:17 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-4d69e6f1-3211-4401-923d-0f78ea2820d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1656105732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1656105732 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1667359447 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 13905647 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:13:13 PM PST 24 |
| Finished | Mar 05 01:13:14 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d96ed5e4-a1d4-4774-b126-ad6e42bedbda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667359447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1667359447 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1555111623 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 309767336 ps |
| CPU time | 19.97 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:13:42 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-63bb5158-68f4-4c02-9fb9-bd73c1597f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555111623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1555111623 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3955159702 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1348309338 ps |
| CPU time | 18.46 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-d14a104b-f33c-44e9-b030-d42cc0357a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3955159702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3955159702 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.55332128 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 554191944 ps |
| CPU time | 128.91 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 206428 kb |
| Host | smart-aa50fa33-e725-4a7f-be6a-30bb0c809a0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=55332128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_ reset.55332128 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3507004420 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1096427332 ps |
| CPU time | 31.9 seconds |
| Started | Mar 05 01:13:20 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-3e635d0f-5ba2-4030-9d7a-7789c44b5744 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507004420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3507004420 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.303623640 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 234170772 ps |
| CPU time | 5.41 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:13:31 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-fb838bf1-7658-4cb2-bdcc-7bf66961b073 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303623640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.303623640 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.395273107 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 112856220 ps |
| CPU time | 5.4 seconds |
| Started | Mar 05 01:13:31 PM PST 24 |
| Finished | Mar 05 01:13:37 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-3a9b742e-e6b7-49df-91be-aa0cd46248dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=395273107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.395273107 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3268732523 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 47836608998 ps |
| CPU time | 327.01 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:18:51 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-91a9f319-a4ab-4342-a811-5ff003e9a83a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3268732523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3268732523 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2395903952 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 366963075 ps |
| CPU time | 6.49 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:13:29 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-ee9a046b-798c-4334-8796-a87e7b93940e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395903952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2395903952 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.1270886427 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 306034112 ps |
| CPU time | 4.96 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:13:29 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d97a1966-b0d6-48f0-9516-958f52edbae9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1270886427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1270886427 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.2317600037 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 891324258 ps |
| CPU time | 13.89 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:38 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-247ac85a-d20d-4837-9087-c3c2abfa167f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2317600037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2317600037 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.973232393 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 9354186388 ps |
| CPU time | 29.29 seconds |
| Started | Mar 05 01:13:32 PM PST 24 |
| Finished | Mar 05 01:14:01 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-142421b9-7d4c-4b40-8f51-2b5f6f291f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=973232393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.973232393 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3112143549 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 19026144539 ps |
| CPU time | 65.92 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-87e1a313-4afd-4282-af2f-48c3dbb0b43a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3112143549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3112143549 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3947219504 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 31788769 ps |
| CPU time | 3.12 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:27 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-16a9b6a0-6c94-4b9a-b09b-8fe1c6413fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947219504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3947219504 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2397479980 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 84720577 ps |
| CPU time | 2.15 seconds |
| Started | Mar 05 01:13:31 PM PST 24 |
| Finished | Mar 05 01:13:33 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-f309bac7-3932-4fb7-8428-c6fbfe42942b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2397479980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2397479980 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2336318644 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 8051655 ps |
| CPU time | 0.99 seconds |
| Started | Mar 05 01:13:20 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-5a0f2c66-4aba-4d75-b636-0e1042bb2dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336318644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2336318644 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1395050664 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3511573725 ps |
| CPU time | 8.89 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:32 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-1e3a156d-e9f6-432c-94d6-baddafcfd268 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395050664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1395050664 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2965561433 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1029007727 ps |
| CPU time | 7.48 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:13:32 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-f170242e-1967-4da4-961e-c85223193696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2965561433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2965561433 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1191945324 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 13510454 ps |
| CPU time | 1.02 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:25 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-7a8a04e7-8c05-49b5-a1b0-7b3965ecadea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191945324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1191945324 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3197578448 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 49012587588 ps |
| CPU time | 103.82 seconds |
| Started | Mar 05 01:13:32 PM PST 24 |
| Finished | Mar 05 01:15:16 PM PST 24 |
| Peak memory | 204388 kb |
| Host | smart-15a54a63-2d3c-4332-94a9-b78c11798993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3197578448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3197578448 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2638282918 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2615369236 ps |
| CPU time | 20.92 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:13:44 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-d195f6bc-01ce-44b8-8ea7-5a3230a24eb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2638282918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2638282918 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2798211703 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6392335376 ps |
| CPU time | 62.15 seconds |
| Started | Mar 05 01:13:26 PM PST 24 |
| Finished | Mar 05 01:14:30 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-8e747abb-8f17-4134-86f0-c2d3d8aff4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2798211703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.2798211703 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.293348987 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3776521191 ps |
| CPU time | 110.58 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:15:15 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-1aa9ee94-3134-4b4c-a90e-008322d7df7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=293348987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.293348987 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.946950415 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 49216358 ps |
| CPU time | 4.28 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:28 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-be55ef81-cd8f-4a02-8ade-505e4bd82700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946950415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.946950415 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3006301861 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 969214225 ps |
| CPU time | 22.42 seconds |
| Started | Mar 05 01:13:31 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-ea104213-e7c2-4845-9c84-5abd56069562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3006301861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3006301861 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2851979201 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 27201325446 ps |
| CPU time | 131.6 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:15:34 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-005b6073-f391-4e4e-a069-5f6e5b02ea47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2851979201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.2851979201 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1013928884 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 44243524 ps |
| CPU time | 1.65 seconds |
| Started | Mar 05 01:13:31 PM PST 24 |
| Finished | Mar 05 01:13:33 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-611af18d-338f-404d-a0c8-fea3192ccabc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013928884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1013928884 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.1748539255 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 128194174 ps |
| CPU time | 6.04 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:13:30 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-b0f2e21b-8589-4758-ad98-1da4d2b9fa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748539255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1748539255 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.2756972484 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 43986039 ps |
| CPU time | 2.3 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:13:28 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-0b995564-401a-4993-af0e-eaf79cd0d33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756972484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2756972484 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1551173584 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 24650948012 ps |
| CPU time | 76.61 seconds |
| Started | Mar 05 01:13:20 PM PST 24 |
| Finished | Mar 05 01:14:37 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-a631d7ea-a576-46e3-8955-7835f732807f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551173584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1551173584 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1454471210 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 20751368030 ps |
| CPU time | 119.23 seconds |
| Started | Mar 05 01:13:28 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-0fd58d7a-5a1a-4057-ab50-a417a93b8f12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1454471210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1454471210 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3330515234 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 141470807 ps |
| CPU time | 3.92 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:13:28 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-a4f38863-3dc4-49d2-b4e1-84a2277174c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330515234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3330515234 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.132328863 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 85387078 ps |
| CPU time | 1.84 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:13:26 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-ef37be95-e108-4db4-a95c-619ba6efdd4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=132328863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.132328863 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.4242448548 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 174971557 ps |
| CPU time | 1.47 seconds |
| Started | Mar 05 01:13:23 PM PST 24 |
| Finished | Mar 05 01:13:26 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-aacda413-350d-4daf-80fa-e8051fcda236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242448548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4242448548 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1314427760 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1979641715 ps |
| CPU time | 7.28 seconds |
| Started | Mar 05 01:13:22 PM PST 24 |
| Finished | Mar 05 01:13:31 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-d8a43e40-3b96-4567-b6b2-d36e6f54d17e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314427760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1314427760 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.444986247 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1939660754 ps |
| CPU time | 7.16 seconds |
| Started | Mar 05 01:13:31 PM PST 24 |
| Finished | Mar 05 01:13:38 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-e3246b7a-0279-4d4f-98f1-025076ed3376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=444986247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.444986247 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1939996962 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 22623146 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:13:26 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-3b4461b6-2172-4255-8835-12f7b8e33062 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939996962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1939996962 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3063823933 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 10078563690 ps |
| CPU time | 125.19 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:15:31 PM PST 24 |
| Peak memory | 206380 kb |
| Host | smart-0d656d6a-880e-4a00-9d8d-f2daf2dfaa00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3063823933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3063823933 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3472811300 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1498031408 ps |
| CPU time | 13.16 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:48 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-76c837ec-0e3e-4d96-b77e-a534b071a1b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472811300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3472811300 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.639554165 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 710861856 ps |
| CPU time | 72.52 seconds |
| Started | Mar 05 01:13:24 PM PST 24 |
| Finished | Mar 05 01:14:37 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-9aecb71c-9ddf-422d-b746-69a049438c43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=639554165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.639554165 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2528266531 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 15840431839 ps |
| CPU time | 75.03 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:14:51 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-8a3720ef-c233-4960-bb48-d5c7733e3ff4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528266531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2528266531 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2347184787 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 525900412 ps |
| CPU time | 10.47 seconds |
| Started | Mar 05 01:13:21 PM PST 24 |
| Finished | Mar 05 01:13:33 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-ef09586c-093a-409d-96e8-39089e744336 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347184787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2347184787 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.117594021 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 842215859 ps |
| CPU time | 6.99 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:42 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-2db2f216-460a-42db-aa51-e902deed0d6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117594021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.117594021 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3752208003 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 15523110004 ps |
| CPU time | 115.39 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-aace3c39-0bd0-4398-a27f-c9e5af375901 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3752208003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.3752208003 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2265266543 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 503349795 ps |
| CPU time | 6.93 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:13:44 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-6c530224-a83d-4caf-be52-b655fa26ded8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2265266543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2265266543 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2206997509 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1310253387 ps |
| CPU time | 8.28 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:44 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-44317a1d-4a06-4064-bcfc-7522c42f5a3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2206997509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2206997509 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2772195400 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 255259804 ps |
| CPU time | 5.74 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:13:42 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-5fd45732-d226-42c8-8fb3-9d11b19895db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2772195400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2772195400 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2106551706 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 80765559417 ps |
| CPU time | 123.95 seconds |
| Started | Mar 05 01:13:34 PM PST 24 |
| Finished | Mar 05 01:15:38 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-6271eba0-94ff-49c1-93fc-2c3d60c4536c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106551706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2106551706 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1427048524 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 41636612262 ps |
| CPU time | 89.12 seconds |
| Started | Mar 05 01:13:34 PM PST 24 |
| Finished | Mar 05 01:15:04 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-fc72d5ed-0d7a-436c-ba6a-fd46fcaff8dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1427048524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1427048524 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1195649770 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 24677321 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:13:39 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-07e0084f-a314-4594-b95e-dadffafdb05c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195649770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1195649770 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.354202167 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 79179890 ps |
| CPU time | 3.9 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:39 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-ef1a7d87-092e-48dc-88b5-a212427790b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354202167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.354202167 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.1930967916 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8552074 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:37 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-e5835c29-a0cd-44f7-a35b-407e34ad2d22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1930967916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1930967916 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1321228761 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5598969336 ps |
| CPU time | 9.23 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:13:45 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-5b4fc5d7-e7f7-4ae9-9288-3eeba78236c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321228761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1321228761 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2544144841 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1200708434 ps |
| CPU time | 6.87 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:43 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-cff6eee1-8296-4d52-9ea6-ae98ff47c325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2544144841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2544144841 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4117695571 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 12237840 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:38 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-15c00dca-c0bc-4f6d-bcf9-ceca620db01f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117695571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.4117695571 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2011385397 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3769633101 ps |
| CPU time | 70.74 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-7fb700e6-7d8b-4aea-aa89-20e1127d4832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2011385397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2011385397 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3003682230 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 388087560 ps |
| CPU time | 22.84 seconds |
| Started | Mar 05 01:13:34 PM PST 24 |
| Finished | Mar 05 01:13:57 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-6761f4f4-518c-4661-95a2-da12c48b4a75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003682230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3003682230 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2147863278 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 45009770 ps |
| CPU time | 3.8 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:40 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-83efaf24-2f17-40ab-8bbe-58afb5b825dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2147863278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2147863278 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2451500103 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 710906172 ps |
| CPU time | 36.07 seconds |
| Started | Mar 05 01:13:35 PM PST 24 |
| Finished | Mar 05 01:14:11 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-1baf6386-f357-4b11-9efa-c82fa37e86b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2451500103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.2451500103 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2250232331 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1179220854 ps |
| CPU time | 7.85 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:44 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-3535ff5f-2ad2-4fea-a37e-dc817bcc897c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250232331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2250232331 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1284679181 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 36175354 ps |
| CPU time | 6.03 seconds |
| Started | Mar 05 01:13:43 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-98b6fa5f-4bd8-4154-be1f-c2ee8a3201f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1284679181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1284679181 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.946444322 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 80396414552 ps |
| CPU time | 172.83 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:16:38 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-77e339b5-b0a5-4c5d-8f32-062d92e8051a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=946444322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.946444322 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.640942299 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 164199631 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:13:48 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-e3e3ec3f-6186-462f-8522-bf5c5d76f4ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640942299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.640942299 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3500962335 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 72899896 ps |
| CPU time | 5.08 seconds |
| Started | Mar 05 01:13:44 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-1b422c0a-4c82-4f56-bb0e-d2116650821e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3500962335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3500962335 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1955344794 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 65683027 ps |
| CPU time | 1.49 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:13:38 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-c32a0894-7626-40fd-bd9d-605649aa6401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1955344794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1955344794 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2172167748 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 26882311635 ps |
| CPU time | 105.12 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-435bf07d-f870-4b24-bd9b-34e72bf9c4e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172167748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2172167748 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1585057025 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 55888106520 ps |
| CPU time | 73.98 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:15:01 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-1464bffe-d7f7-434d-9dc5-e2892c86dcce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1585057025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1585057025 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.136273408 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 121583392 ps |
| CPU time | 6.71 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:43 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-4589a3b5-8d22-4f7a-8303-75145fc824b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136273408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.136273408 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2072468823 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 11221079 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:13:51 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-52fe6e1b-4ad1-4d36-930a-31dec3712b4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2072468823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2072468823 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.4104314437 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 55218569 ps |
| CPU time | 1.54 seconds |
| Started | Mar 05 01:13:34 PM PST 24 |
| Finished | Mar 05 01:13:36 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-72164855-b595-4d19-ae95-279fe9ec98b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104314437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4104314437 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.348535445 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4951600861 ps |
| CPU time | 11.07 seconds |
| Started | Mar 05 01:13:38 PM PST 24 |
| Finished | Mar 05 01:13:49 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-03edcbe7-9980-45f0-af01-33953d628edf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=348535445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.348535445 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.659861369 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5480474961 ps |
| CPU time | 8.84 seconds |
| Started | Mar 05 01:13:37 PM PST 24 |
| Finished | Mar 05 01:13:46 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-74ec2e7a-71f0-4700-8ee2-351450a27ce7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=659861369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.659861369 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.703073316 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 13586636 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 01:13:36 PM PST 24 |
| Finished | Mar 05 01:13:37 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-c9785151-f5a1-49be-aef0-a8801b5cb027 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703073316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.703073316 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.4172490341 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 154448655 ps |
| CPU time | 19.99 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-7cd9c18d-ce0d-4931-bbae-806234357d48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172490341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4172490341 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2088642966 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 22063111655 ps |
| CPU time | 72.31 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:15:02 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-f9d2f13e-8781-4f96-a17d-112a90d0fbb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2088642966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2088642966 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.348483427 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1708131960 ps |
| CPU time | 167.27 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:16:35 PM PST 24 |
| Peak memory | 207880 kb |
| Host | smart-4ed96719-dd93-4903-ad1b-ac450df25517 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=348483427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.348483427 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2884205735 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 22168629 ps |
| CPU time | 1.63 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:13:47 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-736cb4f6-49f7-41a9-abfe-13735fae9e2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2884205735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2884205735 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2211461930 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1106249874 ps |
| CPU time | 5.68 seconds |
| Started | Mar 05 01:13:44 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-9fef410a-ee13-4fa2-928a-594a2ddb44be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211461930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2211461930 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1933227269 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1480159096 ps |
| CPU time | 21.93 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-a92aea64-82ab-46ce-bbd3-19e2022a4172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1933227269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1933227269 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2384113465 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 17924357517 ps |
| CPU time | 108.7 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:15:38 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-8a5dd983-2164-48d7-b375-6cc033bc4b8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2384113465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2384113465 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2477096501 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 945676214 ps |
| CPU time | 3.87 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:13:52 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-d353f955-7a64-44da-be69-cec539df2ff7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2477096501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2477096501 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.95185692 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 105224194 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-7b3b1dcb-4735-4f9a-a987-79861afcb9ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95185692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.95185692 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.2711575410 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 825582562 ps |
| CPU time | 9.94 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-6f7da5c8-1db1-4ba8-b014-78c015220e69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711575410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2711575410 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3717370019 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 102574855531 ps |
| CPU time | 115.72 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-268681ef-ba1d-4a27-ad05-d9887c832340 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717370019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3717370019 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.389891055 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 25601056543 ps |
| CPU time | 29.47 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:14:14 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-611890a8-d064-4110-9949-b7487375bc49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=389891055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.389891055 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.513998871 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 41607138 ps |
| CPU time | 5.34 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-19dba773-a3b3-4785-8714-4bf8396b4cfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513998871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.513998871 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1448753700 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2694320279 ps |
| CPU time | 4.91 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:13:51 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-e7d0e82b-688f-4634-97a1-a8ee9a9b35c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1448753700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1448753700 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1823911616 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 54849054 ps |
| CPU time | 1.63 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:13:47 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d143d45e-fada-4453-8830-97eb894b0f33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823911616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1823911616 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2574332207 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1687207549 ps |
| CPU time | 8.7 seconds |
| Started | Mar 05 01:13:44 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-a1578e01-49c8-402c-b76e-b57b9427c2ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574332207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2574332207 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.992727166 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1882731852 ps |
| CPU time | 9.49 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:13:54 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ab1dc19c-b894-471c-b386-8c9ffcb906c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=992727166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.992727166 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3782471407 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 26285466 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:13:49 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-ff4f780b-11ae-454b-8d7c-9bd5f744f69d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782471407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3782471407 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.754338777 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 10111991644 ps |
| CPU time | 48.95 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:14:39 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-b3e37d36-0a27-48d4-bc11-f59f31c67129 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=754338777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.754338777 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2750024269 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1794395938 ps |
| CPU time | 20.6 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:14:06 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-963ec576-0f7a-4972-9423-4f97c9e40a0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2750024269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2750024269 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1790352 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1754275525 ps |
| CPU time | 212.97 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:17:22 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-440606c6-20ad-4c0d-8ed1-000afbeae4a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1790352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_r eset.1790352 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3159660436 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 11115168868 ps |
| CPU time | 71.45 seconds |
| Started | Mar 05 01:13:44 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-13ca5ff0-3701-4675-ab83-76d80ba6f70f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3159660436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3159660436 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2940706642 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 54995680 ps |
| CPU time | 1.76 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:13:47 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-7003375a-9953-4386-a85e-65283cbb0469 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940706642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2940706642 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1219423346 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 286623508 ps |
| CPU time | 5.77 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:13:51 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-f4ac0f2d-ed26-44bd-a7a2-803efa088c69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1219423346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1219423346 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.11145465 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 13404866454 ps |
| CPU time | 86.69 seconds |
| Started | Mar 05 01:13:43 PM PST 24 |
| Finished | Mar 05 01:15:10 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-d650284e-c4c9-450e-8354-c7e5bb3737db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=11145465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow _rsp.11145465 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1320157897 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 257397344 ps |
| CPU time | 5.32 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:13:52 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-94f12201-068d-40bb-8f42-66871d243dc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1320157897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1320157897 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.2338206847 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 118517448 ps |
| CPU time | 2.37 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-6ebb8514-8a36-4821-acfd-00fc3e965cbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2338206847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2338206847 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1349931 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 342693544 ps |
| CPU time | 2.33 seconds |
| Started | Mar 05 01:13:50 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-c1be0e34-f695-4a2d-8122-ee43686d0ef0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1349931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1349931 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.477159864 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 22869207251 ps |
| CPU time | 101.53 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-74bb28c8-0a0e-43b8-a475-121f62f150c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=477159864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.477159864 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3385150323 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 7651379407 ps |
| CPU time | 58.4 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-c6db867d-c053-4041-9c57-1d22ca8dc62d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3385150323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3385150323 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2317975533 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 33714536 ps |
| CPU time | 2.95 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:13:51 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-d5d73a96-f22e-4b99-b9c4-97e3d9c0f078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317975533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2317975533 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.515539032 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 482538122 ps |
| CPU time | 5.73 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:13:55 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-2a776ef5-07a9-47b7-9519-ba9be8babb33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=515539032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.515539032 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.2053791521 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 11095657 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:13:46 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-340019d1-fce1-42e3-a9a4-b1bd0b1b4feb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2053791521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2053791521 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.600481780 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3048523573 ps |
| CPU time | 8.03 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:13:55 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-94fddbce-9eab-439c-ae96-81ac48ce98a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=600481780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.600481780 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1398090477 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 11122426801 ps |
| CPU time | 13.24 seconds |
| Started | Mar 05 01:13:47 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-2e043ee3-0ba0-484b-bf92-2d0608a3e689 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1398090477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1398090477 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2924869544 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 12230539 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:13:47 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-6a28ba14-b908-4540-92d2-f80df580c66a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924869544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2924869544 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1266810884 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7615728159 ps |
| CPU time | 31.97 seconds |
| Started | Mar 05 01:13:45 PM PST 24 |
| Finished | Mar 05 01:14:17 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-a7b62961-9d3d-448a-bc8c-79a092b710a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1266810884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1266810884 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2979099246 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2445583652 ps |
| CPU time | 16.93 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:14:06 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-6e1af751-b14f-484e-9562-f151a9bc3a5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979099246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2979099246 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3075656404 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1495444309 ps |
| CPU time | 59.84 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-7f2033dd-5132-4c61-9a87-ea8347f6c282 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075656404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3075656404 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1330047099 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 16454202453 ps |
| CPU time | 204.54 seconds |
| Started | Mar 05 01:13:44 PM PST 24 |
| Finished | Mar 05 01:17:09 PM PST 24 |
| Peak memory | 205700 kb |
| Host | smart-26347cba-a3f6-4da5-a8c5-0c6b81844368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330047099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1330047099 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2284072035 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 628301840 ps |
| CPU time | 4.48 seconds |
| Started | Mar 05 01:13:48 PM PST 24 |
| Finished | Mar 05 01:13:53 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-52890cd4-eb70-42cd-98dd-7240bc935ba2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2284072035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2284072035 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.24583951 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 71649741 ps |
| CPU time | 2.89 seconds |
| Started | Mar 05 01:13:54 PM PST 24 |
| Finished | Mar 05 01:13:57 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-f6af58e7-38b2-40c3-8602-7f4646526920 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24583951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.24583951 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2362484361 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 41458343746 ps |
| CPU time | 239.65 seconds |
| Started | Mar 05 01:13:55 PM PST 24 |
| Finished | Mar 05 01:17:54 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-0924262d-2b22-4d8a-88ff-afa533fda7e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2362484361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2362484361 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3530271926 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 616930288 ps |
| CPU time | 8.31 seconds |
| Started | Mar 05 01:13:59 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-9e3fdd5b-566d-47ed-b26e-acee983ba6a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3530271926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3530271926 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.956943789 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 108534232 ps |
| CPU time | 5.36 seconds |
| Started | Mar 05 01:13:57 PM PST 24 |
| Finished | Mar 05 01:14:02 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-e80f7292-31e1-4069-9e17-a43cc54371c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=956943789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.956943789 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2123211761 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 942301712 ps |
| CPU time | 3.57 seconds |
| Started | Mar 05 01:13:46 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-0f2e1ea3-dda0-4cf1-8aab-34cad3825ca0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123211761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2123211761 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.195102526 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 33394133363 ps |
| CPU time | 27.08 seconds |
| Started | Mar 05 01:14:01 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-7792e37c-79c7-4b55-ae63-d1a93ef2ad8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=195102526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.195102526 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1197375171 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 20474300471 ps |
| CPU time | 141.12 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:16:17 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-3bc413e6-16da-461f-8a70-0ab905024211 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1197375171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1197375171 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2604873601 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 65040766 ps |
| CPU time | 7.99 seconds |
| Started | Mar 05 01:14:03 PM PST 24 |
| Finished | Mar 05 01:14:11 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-1002d4a6-ff65-422d-9ae8-f348b9ab0575 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604873601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2604873601 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.851732009 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 46640021 ps |
| CPU time | 4.21 seconds |
| Started | Mar 05 01:13:55 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-8121e098-bfaf-42c4-9857-0438af6d9461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851732009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.851732009 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.439434306 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 107384671 ps |
| CPU time | 1.25 seconds |
| Started | Mar 05 01:13:43 PM PST 24 |
| Finished | Mar 05 01:13:45 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-c6767fe8-4c88-4269-aafb-2f681f1afa7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=439434306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.439434306 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3393004263 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9527697175 ps |
| CPU time | 10.13 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-588b6dc9-1f81-452d-8096-d023679a2a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393004263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3393004263 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2081558963 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2583637315 ps |
| CPU time | 8.37 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:13:57 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-41b5cd12-97ee-4b6e-b56a-bbc4bcf521d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2081558963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2081558963 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.984257805 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 16967685 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 01:13:49 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-e49427d5-adf4-4272-b0e3-04e7df9dea18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984257805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.984257805 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.566458477 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 33973251 ps |
| CPU time | 3.09 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-48891527-fd4f-4b11-aa88-1bec27298eca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=566458477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.566458477 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1012188471 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5521894961 ps |
| CPU time | 46.11 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:14:44 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-d242c0c9-ceaf-4e5e-932b-d4ade808f721 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1012188471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1012188471 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3297332323 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 261395355 ps |
| CPU time | 58.43 seconds |
| Started | Mar 05 01:14:03 PM PST 24 |
| Finished | Mar 05 01:15:01 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-ca6399a0-f70c-4d75-b252-c76338af91a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3297332323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3297332323 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2392763763 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3553677227 ps |
| CPU time | 72.12 seconds |
| Started | Mar 05 01:14:00 PM PST 24 |
| Finished | Mar 05 01:15:12 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-eeed1ddb-b90d-4731-ac9d-409594b83826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2392763763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.2392763763 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.841828920 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 10929812 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:13:59 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-f3134091-eefb-48a9-bd4e-12f8b19dc60c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841828920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.841828920 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3630079806 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 39823541 ps |
| CPU time | 7.73 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:27 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-08f35770-472a-4e74-b967-2602ad6d88e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3630079806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3630079806 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1056565255 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 41869748262 ps |
| CPU time | 277.94 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:16:59 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-35452f55-9f23-4b2b-b32d-5043f851ff44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1056565255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1056565255 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3009687884 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 889103500 ps |
| CPU time | 3.73 seconds |
| Started | Mar 05 01:12:26 PM PST 24 |
| Finished | Mar 05 01:12:30 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-1509d00d-017f-4032-9e64-65b4d95dafb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3009687884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3009687884 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.3851093304 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 608903604 ps |
| CPU time | 9.43 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:12:31 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-8606d096-b480-4a4e-8b44-81cb7c4be178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3851093304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3851093304 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1224337163 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 551130240 ps |
| CPU time | 10.75 seconds |
| Started | Mar 05 01:12:26 PM PST 24 |
| Finished | Mar 05 01:12:37 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-950ab4c6-dd7b-4a81-bd90-78c6f2cb2a67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1224337163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1224337163 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.221166563 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 28172018957 ps |
| CPU time | 42.67 seconds |
| Started | Mar 05 01:12:22 PM PST 24 |
| Finished | Mar 05 01:13:04 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-7be86363-7e01-4d35-ad45-1d1c9143e75a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=221166563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.221166563 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3077966607 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 36090337935 ps |
| CPU time | 136.04 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:14:37 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-a5da8449-d54b-48d3-a456-9eaa885bdc63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3077966607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3077966607 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1780406545 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 80705068 ps |
| CPU time | 11.82 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:31 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-a7ff9aba-e2df-43e0-99e7-a4d8ae418c68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780406545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1780406545 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3498485894 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 18996099 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 01:12:18 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-7952f0ef-ee6d-4677-8997-5e184940afaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498485894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3498485894 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3116300319 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 69026873 ps |
| CPU time | 1.51 seconds |
| Started | Mar 05 01:12:25 PM PST 24 |
| Finished | Mar 05 01:12:27 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-84f30043-6a0e-4823-b076-f756bd45715d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3116300319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3116300319 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.895115296 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2208515194 ps |
| CPU time | 8.63 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:12:29 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-a346a5cf-6100-4c92-9b1b-9b2a66106b36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=895115296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.895115296 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.781006812 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1967228726 ps |
| CPU time | 13.05 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:12:34 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-b8f4964a-b889-4f4e-886f-43348076e915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=781006812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.781006812 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3389763882 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 23144061 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-f828a43c-0a6e-4008-a20b-8c2dba9d9b9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389763882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3389763882 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.140659746 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2380292268 ps |
| CPU time | 41.8 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-e0a5d92b-9160-4dcc-8fe9-08b04452249f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=140659746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.140659746 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1600946434 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1002895267 ps |
| CPU time | 19.5 seconds |
| Started | Mar 05 01:12:23 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-ea34d05f-50e4-4729-8913-e2746df0eb4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1600946434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1600946434 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3424708937 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1354378391 ps |
| CPU time | 188.52 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-e91408fe-f5aa-4776-aa98-0239c220ffe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3424708937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3424708937 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4072773654 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1856175976 ps |
| CPU time | 43.26 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:13:04 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-ebbd7092-9a01-49a9-b5ea-d2b2ea1f2bbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4072773654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.4072773654 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.313187644 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 478109933 ps |
| CPU time | 6.53 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:12:28 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-73bcf620-e2ef-4001-8235-257eadaccdc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313187644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.313187644 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.674927991 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 98705834 ps |
| CPU time | 13.69 seconds |
| Started | Mar 05 01:13:59 PM PST 24 |
| Finished | Mar 05 01:14:13 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-db1152f3-07e2-4183-ae73-f7b77b395ff2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674927991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.674927991 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2683951660 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 14191359522 ps |
| CPU time | 93.74 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-df3031b4-ec98-4365-a21b-c05c6509cf8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2683951660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2683951660 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.730303551 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 63358558 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:13:57 PM PST 24 |
| Finished | Mar 05 01:13:58 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-000b9db3-a073-4d0b-af8a-28edbc440ec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730303551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.730303551 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.860226789 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 401034776 ps |
| CPU time | 6.37 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:14:03 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-23e93bde-175c-4c0b-b821-63122f487254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860226789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.860226789 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3973879221 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1859124054 ps |
| CPU time | 13.86 seconds |
| Started | Mar 05 01:13:55 PM PST 24 |
| Finished | Mar 05 01:14:09 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-be35ab06-1652-4da7-b95a-67956a8102af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3973879221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3973879221 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2146672471 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 6442329438 ps |
| CPU time | 27.44 seconds |
| Started | Mar 05 01:13:59 PM PST 24 |
| Finished | Mar 05 01:14:27 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-1967ef52-4f40-4d3c-9df0-e4bf1da91f07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146672471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2146672471 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2630332590 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 48904355546 ps |
| CPU time | 132.36 seconds |
| Started | Mar 05 01:14:01 PM PST 24 |
| Finished | Mar 05 01:16:13 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-ce674e0a-57c4-4c90-87a3-deafc4f6cb59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2630332590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2630332590 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3730459326 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 46622288 ps |
| CPU time | 5.08 seconds |
| Started | Mar 05 01:13:57 PM PST 24 |
| Finished | Mar 05 01:14:02 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-0de53ca8-0873-4872-8014-723b9f7acd62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730459326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3730459326 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1618601483 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 14421769 ps |
| CPU time | 1.43 seconds |
| Started | Mar 05 01:14:02 PM PST 24 |
| Finished | Mar 05 01:14:03 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-dfc35018-df11-4758-a28f-4f712339b6a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618601483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1618601483 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.681782899 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 12074935 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:13:59 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-ad824896-ee34-4aa1-91ab-2920648c0820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681782899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.681782899 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3477200345 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5666275110 ps |
| CPU time | 8.81 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:14:05 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-831acc20-f7ff-4502-a09b-743ad1dc89ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477200345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3477200345 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.287105512 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 7067893860 ps |
| CPU time | 13.41 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:14:12 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-e9b392c1-b82d-4460-a04a-0ba6baa2648d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=287105512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.287105512 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2742136451 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 15189856 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:13:59 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-2edf83dc-6a5e-4bb7-8687-410e68fafc0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742136451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2742136451 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3502997588 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 374661173 ps |
| CPU time | 31.57 seconds |
| Started | Mar 05 01:14:00 PM PST 24 |
| Finished | Mar 05 01:14:32 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-923a8ae5-8f75-4d02-8b8c-160fded57325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3502997588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3502997588 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2419746981 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 834564308 ps |
| CPU time | 26.69 seconds |
| Started | Mar 05 01:13:57 PM PST 24 |
| Finished | Mar 05 01:14:24 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-e7f06c9f-b23b-469c-91e2-fba300006289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419746981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2419746981 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2740667030 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 146512846 ps |
| CPU time | 24.82 seconds |
| Started | Mar 05 01:14:00 PM PST 24 |
| Finished | Mar 05 01:14:25 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-801fbb29-25a5-43c4-a48d-944fcc5c1f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740667030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2740667030 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3264463330 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 342130438 ps |
| CPU time | 6.03 seconds |
| Started | Mar 05 01:14:01 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-88a1015c-f950-48a8-abb4-0e972bf06977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3264463330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3264463330 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.731576905 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 104289149 ps |
| CPU time | 12.93 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:21 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-16368dd8-fff0-4343-b892-c147943ef28b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=731576905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.731576905 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1269506897 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 11791973176 ps |
| CPU time | 15.95 seconds |
| Started | Mar 05 01:14:05 PM PST 24 |
| Finished | Mar 05 01:14:21 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-2982a3cb-df83-4442-8ec6-cb59d86c1a5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1269506897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1269506897 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.616098233 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 153059678 ps |
| CPU time | 1.38 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:14:09 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-2a811182-7af9-4e5c-84e6-d7dba4f462e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=616098233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.616098233 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2657101468 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 56041760 ps |
| CPU time | 5.32 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:11 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-02be1270-26ef-461c-bceb-8e2343c58c08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657101468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2657101468 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.4274822273 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 838612107 ps |
| CPU time | 9.41 seconds |
| Started | Mar 05 01:13:55 PM PST 24 |
| Finished | Mar 05 01:14:04 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-15767317-2cff-477b-a311-38a96e0f365a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4274822273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4274822273 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2055669550 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 122566162627 ps |
| CPU time | 127.28 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:16:05 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-6d12b3fa-3994-47ed-b9cb-819828bc2ceb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055669550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2055669550 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2279244288 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 7666723483 ps |
| CPU time | 15.27 seconds |
| Started | Mar 05 01:14:05 PM PST 24 |
| Finished | Mar 05 01:14:20 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-1480217b-3bb5-43be-b2be-acb977804dcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2279244288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2279244288 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.278527614 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 38566779 ps |
| CPU time | 2.72 seconds |
| Started | Mar 05 01:13:56 PM PST 24 |
| Finished | Mar 05 01:13:59 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-e77f7ae1-b902-47f1-ad40-8b97c6cbd48d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278527614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.278527614 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.859026632 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 620759391 ps |
| CPU time | 8.98 seconds |
| Started | Mar 05 01:14:05 PM PST 24 |
| Finished | Mar 05 01:14:14 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-d1077bae-a161-44bc-b704-0ebf8010bcec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=859026632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.859026632 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.3183284382 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 95690370 ps |
| CPU time | 1.73 seconds |
| Started | Mar 05 01:14:02 PM PST 24 |
| Finished | Mar 05 01:14:04 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-92e72697-9dca-473f-8366-3f36aa8badf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3183284382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3183284382 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3537905879 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 9749229583 ps |
| CPU time | 9.33 seconds |
| Started | Mar 05 01:13:58 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-01d9102b-51ea-454b-b2a4-2e53ca7e254b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537905879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3537905879 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2377247816 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1706560817 ps |
| CPU time | 6.69 seconds |
| Started | Mar 05 01:14:01 PM PST 24 |
| Finished | Mar 05 01:14:07 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-b1327ac2-c91e-4d9d-9664-2b2a4eae0652 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2377247816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2377247816 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3862791404 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 22905708 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:13:57 PM PST 24 |
| Finished | Mar 05 01:13:58 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-a0da3a37-24a1-422b-8405-933f58f72e78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862791404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3862791404 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.749203162 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1818378177 ps |
| CPU time | 38.07 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-80e8b682-7ac5-42a2-a7f9-f78fced0320a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=749203162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.749203162 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3745043539 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 193018112 ps |
| CPU time | 21.98 seconds |
| Started | Mar 05 01:14:16 PM PST 24 |
| Finished | Mar 05 01:14:38 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-66c8b21d-bf21-4f2e-aea6-3706974fc3a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745043539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3745043539 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3461047059 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1168425441 ps |
| CPU time | 166.33 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:16:55 PM PST 24 |
| Peak memory | 206024 kb |
| Host | smart-7741f0a4-a8a9-46a5-bb6a-aff8c78996be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461047059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3461047059 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2605327186 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 282532842 ps |
| CPU time | 38.45 seconds |
| Started | Mar 05 01:14:05 PM PST 24 |
| Finished | Mar 05 01:14:44 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-b982c7f2-5d43-462e-a780-36629c0bee3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2605327186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2605327186 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.791045574 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 248630244 ps |
| CPU time | 6.03 seconds |
| Started | Mar 05 01:14:04 PM PST 24 |
| Finished | Mar 05 01:14:10 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-1210e5b7-c9d1-47a3-83c4-d94eb511d86e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791045574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.791045574 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2881815700 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 587421632 ps |
| CPU time | 8.07 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:16 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-ee9ba54c-54b0-4e01-a96d-e1a90cabee56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881815700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2881815700 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1840139150 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 80135581 ps |
| CPU time | 1.79 seconds |
| Started | Mar 05 01:14:09 PM PST 24 |
| Finished | Mar 05 01:14:11 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-4ead5d67-fc60-4910-bb57-ed310adfb005 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840139150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1840139150 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2423758962 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 489126650 ps |
| CPU time | 7.03 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:14:15 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-07a04a0e-a2b0-486a-80d8-922422dbbc24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2423758962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2423758962 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1957467025 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 26656392 ps |
| CPU time | 3.84 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:10 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-dc2985fd-003d-4f74-8642-09e455774240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1957467025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1957467025 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.370833279 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 47801938451 ps |
| CPU time | 105.9 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-e705e2d8-c2d7-4062-91f0-775fef5fec78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=370833279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.370833279 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3802209687 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 130641346433 ps |
| CPU time | 119.96 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:16:06 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-6eee737b-bf17-4354-ab8e-e6418255368a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3802209687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3802209687 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3988083448 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 182369320 ps |
| CPU time | 3.49 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:14:11 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-09bd8092-9931-4d77-8a86-0f42121d29db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988083448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3988083448 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2368266378 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1025569374 ps |
| CPU time | 7.11 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:15 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-b315e309-386d-41bd-955f-a0db76dcc693 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2368266378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2368266378 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2966224452 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 94899401 ps |
| CPU time | 1.56 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:14:08 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-62baecf2-ecc4-4737-93f9-35fa3194c0ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2966224452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2966224452 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3963751503 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3278842189 ps |
| CPU time | 8.12 seconds |
| Started | Mar 05 01:14:05 PM PST 24 |
| Finished | Mar 05 01:14:13 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-0ca50aca-fb24-4e72-981d-752b29f2639f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963751503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3963751503 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.209838137 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1243605743 ps |
| CPU time | 8.76 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:15 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-22ee5a13-fdc2-4fca-8bc9-aec32504a5d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=209838137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.209838137 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3143568265 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 15843642 ps |
| CPU time | 1.22 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:09 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-5246f43e-df9b-48b3-9136-447d32a7f893 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143568265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3143568265 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3250409663 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 588319616 ps |
| CPU time | 64.57 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:15:10 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-e56ecb4b-750b-4fb7-9314-9706b3f4ca6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250409663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3250409663 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2693994353 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9495717325 ps |
| CPU time | 69.76 seconds |
| Started | Mar 05 01:14:16 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-bb7aa469-b6e5-475c-baec-ec9cbf95aeb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693994353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2693994353 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.518344414 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 324082463 ps |
| CPU time | 76.66 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:15:24 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-36a19b74-27f1-48a6-9895-6bb39d7d6414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518344414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.518344414 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2882062102 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 323748022 ps |
| CPU time | 46 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 204048 kb |
| Host | smart-7abe2ec0-ab35-424d-92c6-69e1cc78bdc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2882062102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.2882062102 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.4098048072 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 744110164 ps |
| CPU time | 8.59 seconds |
| Started | Mar 05 01:14:06 PM PST 24 |
| Finished | Mar 05 01:14:15 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-7071a31b-320b-4a10-9377-b792ec7513ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4098048072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4098048072 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3738940306 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 31299020 ps |
| CPU time | 4.15 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:24 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-f49437e9-c13b-4348-a972-7d69dbcce7ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3738940306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3738940306 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1135496475 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 737211435 ps |
| CPU time | 5.73 seconds |
| Started | Mar 05 01:14:20 PM PST 24 |
| Finished | Mar 05 01:14:26 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-5573f9ec-8c34-4156-bd37-75b3dca68e89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1135496475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1135496475 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3355868498 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 9438953 ps |
| CPU time | 1.4 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:14:18 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-6954ef22-c339-48d6-9535-72b1b4548288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3355868498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3355868498 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.4293233076 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 557728392 ps |
| CPU time | 7.25 seconds |
| Started | Mar 05 01:14:09 PM PST 24 |
| Finished | Mar 05 01:14:17 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c7ae9795-cdf8-4d46-86d0-7cd1ba07545c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293233076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.4293233076 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3549508649 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 53736829962 ps |
| CPU time | 132 seconds |
| Started | Mar 05 01:14:10 PM PST 24 |
| Finished | Mar 05 01:16:22 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-03c1be7e-263e-4f24-889b-a64a1cd35e4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549508649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3549508649 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.29706015 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 51657547194 ps |
| CPU time | 79.63 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:15:36 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-63a4b2a5-bdda-45fd-8240-453ac66fc960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=29706015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.29706015 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2572884171 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 61775700 ps |
| CPU time | 7.09 seconds |
| Started | Mar 05 01:14:07 PM PST 24 |
| Finished | Mar 05 01:14:14 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b5dabce4-3743-42af-8097-78e23607a86c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572884171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2572884171 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.303528989 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 749982035 ps |
| CPU time | 7.75 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:14:26 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-0bc89245-7cbe-44f2-b89d-06ec6ff3db42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303528989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.303528989 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.2226355300 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 118719847 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:10 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-cd45fdbd-3177-457b-9a77-3831c3147acb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2226355300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2226355300 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3055267654 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1993333373 ps |
| CPU time | 8.9 seconds |
| Started | Mar 05 01:14:16 PM PST 24 |
| Finished | Mar 05 01:14:25 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-226380c6-a537-4779-ba48-9fd5358f964d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055267654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3055267654 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.864770237 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1161036312 ps |
| CPU time | 6.55 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:15 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-b8ef57ae-ce6d-431e-8280-7b6d5c702fa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=864770237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.864770237 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2311975463 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 10025367 ps |
| CPU time | 1.17 seconds |
| Started | Mar 05 01:14:08 PM PST 24 |
| Finished | Mar 05 01:14:09 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-aa254e64-2924-4c07-929a-b894fe825506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311975463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2311975463 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3386401481 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2844534206 ps |
| CPU time | 33.7 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-74ab3114-8e69-4310-9588-c3c66e4190be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386401481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3386401481 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1664463369 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 9820494785 ps |
| CPU time | 64.52 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:15:23 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-7ea985c3-e98f-4a1e-891d-c36f8304b45e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1664463369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1664463369 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3625704168 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3550943224 ps |
| CPU time | 142.39 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:16:40 PM PST 24 |
| Peak memory | 207440 kb |
| Host | smart-2ed07e76-5486-4515-9b56-cd318590e4a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625704168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3625704168 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3700498925 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 70306613 ps |
| CPU time | 12.24 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:14:31 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-ffba7fe8-bf37-4c1b-94f2-b2e5185f3f61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700498925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.3700498925 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2766540080 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 44167067 ps |
| CPU time | 6.75 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:14:25 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-0c8a230c-5d29-4dc3-b75e-6b99a03bcfc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2766540080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2766540080 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2950108341 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 481357731 ps |
| CPU time | 6.35 seconds |
| Started | Mar 05 01:14:22 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-f688cdd1-e24a-437a-be30-2680c74ca733 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950108341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2950108341 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2515542663 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 67234276 ps |
| CPU time | 9.8 seconds |
| Started | Mar 05 01:14:15 PM PST 24 |
| Finished | Mar 05 01:14:25 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-c5276eca-c077-4abe-8166-700a4cb16296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515542663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2515542663 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.865648959 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 598604805 ps |
| CPU time | 10.77 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:30 PM PST 24 |
| Peak memory | 201876 kb |
| Host | smart-bb2ae2e9-f15d-4d6a-a807-327412234e48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=865648959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.865648959 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.421676710 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 20512821944 ps |
| CPU time | 103.28 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:16:01 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-facc99dc-06ef-4157-9e88-ab0ea8d3a5e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=421676710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.421676710 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.616427444 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 31924462532 ps |
| CPU time | 98.22 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:15:56 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-321b3f0e-b940-4da1-a987-50094852f9d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=616427444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.616427444 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2729521363 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 20222144 ps |
| CPU time | 1.45 seconds |
| Started | Mar 05 01:14:20 PM PST 24 |
| Finished | Mar 05 01:14:22 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-0fa82e4c-c788-4735-beb9-bb0e6b7b9d1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729521363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2729521363 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1480997291 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2233503320 ps |
| CPU time | 12.09 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:14:30 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-7b3d7a75-0a02-4902-95e4-edb9480fff60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1480997291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1480997291 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.448846730 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 205195299 ps |
| CPU time | 1.44 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:21 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-194e69e2-92d2-450a-b813-a9d59bfe7e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=448846730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.448846730 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.132366674 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 11951700634 ps |
| CPU time | 10.49 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-c65eaf03-73c9-483a-b0cc-49644bab4b56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=132366674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.132366674 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3149802701 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1411321862 ps |
| CPU time | 6.42 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:26 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-87043bae-1d3d-40ad-a1bc-5d511077b7d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3149802701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3149802701 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1900569891 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 31310598 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:14:18 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-7ee96f01-1a8a-4f4f-8696-be0cc40c670c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900569891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1900569891 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.824895911 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 378434438 ps |
| CPU time | 46.36 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:15:05 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-59076da9-5225-4e87-920d-bcf16fa595d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824895911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.824895911 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2781028586 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5951663547 ps |
| CPU time | 89.85 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:15:48 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-0dca3717-7add-4681-9587-9a3aca4c1aa2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781028586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2781028586 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4215012248 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2509595959 ps |
| CPU time | 91.38 seconds |
| Started | Mar 05 01:14:18 PM PST 24 |
| Finished | Mar 05 01:15:50 PM PST 24 |
| Peak memory | 206132 kb |
| Host | smart-607f134f-c25a-48df-a98a-d6e36c359f1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215012248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.4215012248 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.341920654 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 282064691 ps |
| CPU time | 18.33 seconds |
| Started | Mar 05 01:14:17 PM PST 24 |
| Finished | Mar 05 01:14:35 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-89200ba6-353f-4ccd-ac9d-e468ff666862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341920654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.341920654 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2542769313 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1583187503 ps |
| CPU time | 11.77 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:31 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d7c1207d-ee9a-4fd8-b01b-d02773fc81eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2542769313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2542769313 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2026625472 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 51374946 ps |
| CPU time | 2.79 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:32 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-e9581674-83ce-4172-9e7d-580ca952f9bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2026625472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2026625472 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2290639477 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 42684992682 ps |
| CPU time | 261.45 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:18:53 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-b6bccf0f-5f4f-4376-9a49-4067983a9897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2290639477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2290639477 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.531620458 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 657074444 ps |
| CPU time | 7.18 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:36 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-e0b797ce-463b-4380-bedf-f92b80a5518a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531620458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.531620458 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2138935968 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 91475062 ps |
| CPU time | 3.65 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:35 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-d0a051e7-4a51-4a55-9a4f-cdacdab26bcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2138935968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2138935968 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.1704705308 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 24644045 ps |
| CPU time | 3.02 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-6d881b80-1704-4f48-8f10-1d62eca1622b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1704705308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1704705308 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2863045739 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6266719316 ps |
| CPU time | 16.09 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:47 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f403a3da-91ec-4bfb-85dd-05339957e4cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863045739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2863045739 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3459619245 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4753723972 ps |
| CPU time | 21.37 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-cdb15413-942a-45bb-9154-2ad1a898e864 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3459619245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3459619245 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.868641035 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 40963524 ps |
| CPU time | 2.54 seconds |
| Started | Mar 05 01:14:30 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-cf254ae1-e33f-48e4-8087-8f1a7171e461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868641035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.868641035 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2706650 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 160420437 ps |
| CPU time | 1.64 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-0467df39-c64e-443d-8da0-c134153b0968 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2706650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2706650 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1429236978 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 43052967 ps |
| CPU time | 1.25 seconds |
| Started | Mar 05 01:14:19 PM PST 24 |
| Finished | Mar 05 01:14:20 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-1ac023dc-ea3b-4af7-9842-becd0c1f1db5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1429236978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1429236978 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4672518 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3040292782 ps |
| CPU time | 8.96 seconds |
| Started | Mar 05 01:14:20 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-c34488fc-f7b0-4d2c-93ca-d4047931bef2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4672518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4672518 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3150464976 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1742093829 ps |
| CPU time | 12.5 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-d0b252a4-ca65-4706-b175-bb560a548805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3150464976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3150464976 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.807941819 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 12878357 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 01:14:22 PM PST 24 |
| Finished | Mar 05 01:14:23 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-2a9928a2-6e45-4a34-969b-9759943531d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807941819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.807941819 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3938915218 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 206579831 ps |
| CPU time | 17.64 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-2aba8180-821c-4752-b3b9-8bb50ed4f6da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938915218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3938915218 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2370989629 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3325410617 ps |
| CPU time | 59.01 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-1740c395-51af-4832-9929-4935f696c817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370989629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2370989629 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2192051639 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 18794758 ps |
| CPU time | 2.22 seconds |
| Started | Mar 05 01:14:27 PM PST 24 |
| Finished | Mar 05 01:14:30 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-d6f6520a-2f55-4ed8-b872-87ce1062451b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192051639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.2192051639 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.668060788 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2196360604 ps |
| CPU time | 12.83 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-c83d8821-674a-4da0-9963-b088827181a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=668060788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.668060788 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.673226465 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1080297239 ps |
| CPU time | 17.52 seconds |
| Started | Mar 05 01:14:30 PM PST 24 |
| Finished | Mar 05 01:14:48 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-c4850f8b-d404-4e9e-ac81-0a1591b52d5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=673226465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.673226465 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1531612874 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 35455189499 ps |
| CPU time | 115.34 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:16:27 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-6a461507-5228-4859-aebd-43c46a708a7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1531612874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1531612874 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.693937099 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 9260409 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:31 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-bf7162b0-cc01-4b1f-8dcb-531036ca0142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693937099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.693937099 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.478602020 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 581474061 ps |
| CPU time | 4.14 seconds |
| Started | Mar 05 01:14:30 PM PST 24 |
| Finished | Mar 05 01:14:35 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-07bf9130-e355-4aee-afff-99ac7dca4368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=478602020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.478602020 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2711004796 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 59719826 ps |
| CPU time | 6.75 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:37 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-404f25c5-8833-449f-8419-660816e9df05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711004796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2711004796 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4053972182 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 48022969750 ps |
| CPU time | 51.31 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-30b389d8-1b6a-4ebd-b8ed-2162e009ad22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053972182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4053972182 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.598658225 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 36651878687 ps |
| CPU time | 202.53 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:17:52 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-91d42fc8-a934-4fdd-8406-c0a5a1ac7747 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=598658225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.598658225 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.565297992 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 33246262 ps |
| CPU time | 2.28 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:31 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-e119fd82-7d75-461d-b838-ee3f3aea545a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565297992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.565297992 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.2294365296 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3523426149 ps |
| CPU time | 12.88 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-1c3d8254-b1d1-49d3-b964-1576ab5dce6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2294365296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2294365296 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.4165164164 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 185099362 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-3679e787-7a93-4b14-9e93-a1733d4f4e1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4165164164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4165164164 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3451622305 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2007178351 ps |
| CPU time | 6.94 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:36 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-7354beb2-d694-4c47-8ec2-6202ad82ee49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451622305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3451622305 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.500129245 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1732392795 ps |
| CPU time | 10.15 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:38 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-d6c13c52-99a0-47b0-9398-49c4c57cd2f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=500129245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.500129245 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3720941448 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9166687 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:30 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-5f95ef0d-113a-4aa8-81f6-48b3bc742cd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720941448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3720941448 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3733137976 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 221496887 ps |
| CPU time | 11.67 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-2fc62b24-7e4c-4723-bc08-11a8559565e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3733137976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3733137976 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1599645106 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2124966363 ps |
| CPU time | 11.08 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-bbe37167-f341-4103-923e-f917909046a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1599645106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1599645106 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1872979313 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4601021633 ps |
| CPU time | 96.52 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:16:08 PM PST 24 |
| Peak memory | 206832 kb |
| Host | smart-b51a010e-d7bf-45b2-913f-3ce99bb56897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872979313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1872979313 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2051185907 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 279624640 ps |
| CPU time | 26.24 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:55 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-0678ae40-2ba6-4832-8e5d-5e6d699a8710 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2051185907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.2051185907 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3739941934 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 105363888 ps |
| CPU time | 2.56 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:14:35 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-26f391ce-cc5b-4248-8a19-9cb0430c0d2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739941934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3739941934 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.742357641 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 430465896 ps |
| CPU time | 9.8 seconds |
| Started | Mar 05 01:14:33 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-569c899e-f28b-4af4-85e7-4eb36c1d9e3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742357641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.742357641 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3235472455 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 36438199880 ps |
| CPU time | 50.26 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:15:20 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-cec9df45-b5ec-40a2-ab0e-630e57ba3ef0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3235472455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3235472455 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2272864184 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 364343902 ps |
| CPU time | 4.98 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:36 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-30385d43-873b-4fec-bf79-ce77928b69ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2272864184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2272864184 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3192033809 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 95512965 ps |
| CPU time | 4.4 seconds |
| Started | Mar 05 01:14:28 PM PST 24 |
| Finished | Mar 05 01:14:34 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-1c8834cb-0f87-45e3-a3a4-baaad7fef24e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3192033809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3192033809 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2381579870 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 26584593 ps |
| CPU time | 2.74 seconds |
| Started | Mar 05 01:14:29 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-dc19e236-c40f-4c59-95de-17cf339d3b06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2381579870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2381579870 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2611585707 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 31641633505 ps |
| CPU time | 45.76 seconds |
| Started | Mar 05 01:14:34 PM PST 24 |
| Finished | Mar 05 01:15:20 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-3b7062f2-04d0-4925-a4a4-516563d6ae05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611585707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2611585707 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2368056309 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15774755482 ps |
| CPU time | 84.65 seconds |
| Started | Mar 05 01:14:34 PM PST 24 |
| Finished | Mar 05 01:15:59 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-1be424aa-6cb1-4bd8-8359-57e0574a8fd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2368056309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2368056309 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.549718730 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 100612969 ps |
| CPU time | 4.93 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:36 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-6fa5e88c-2e02-4794-9c18-1cdb4b101c62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549718730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.549718730 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.2195286420 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 962658627 ps |
| CPU time | 6.65 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:14:39 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-be1b6725-269c-4d4c-94b9-a6fae3c9f51e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2195286420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2195286420 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3380984416 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 43341556 ps |
| CPU time | 1.53 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-8ee9c2b6-4826-46d7-a144-eb60da3e3ebd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380984416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3380984416 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1671494555 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2999161327 ps |
| CPU time | 9.07 seconds |
| Started | Mar 05 01:14:34 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-e869b47d-fabb-4ca9-91c8-9107a226995e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671494555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1671494555 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2890591243 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4078230360 ps |
| CPU time | 8.21 seconds |
| Started | Mar 05 01:14:30 PM PST 24 |
| Finished | Mar 05 01:14:39 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-315a09f5-af70-42aa-98d4-720b281ce7e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2890591243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2890591243 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2979479555 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 16334225 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:14:31 PM PST 24 |
| Finished | Mar 05 01:14:33 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-eb900a19-38cc-483a-9bf4-12b7fca7b0d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979479555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2979479555 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1537186118 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 23248096120 ps |
| CPU time | 50.14 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:15:23 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-87683754-fd4f-462d-b665-75adf444b21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1537186118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1537186118 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3475443767 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 463368553 ps |
| CPU time | 4.35 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:14:36 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-83ef5f61-708f-4184-9a4b-a8ba6852fd3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3475443767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3475443767 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3646004767 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 413498568 ps |
| CPU time | 78.39 seconds |
| Started | Mar 05 01:14:27 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 206132 kb |
| Host | smart-d5180556-bc7b-4f8e-b3f1-e579969f2219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3646004767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3646004767 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4238174147 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7841582947 ps |
| CPU time | 44.99 seconds |
| Started | Mar 05 01:14:33 PM PST 24 |
| Finished | Mar 05 01:15:18 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-d4fd08aa-ce28-4e22-9c51-50d37b3b6f65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4238174147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.4238174147 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1607948553 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 59505100 ps |
| CPU time | 6.34 seconds |
| Started | Mar 05 01:14:33 PM PST 24 |
| Finished | Mar 05 01:14:40 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-d5cb477f-a46c-4e3f-acd8-0d421b9ddd3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1607948553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1607948553 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.758051877 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 582142462 ps |
| CPU time | 4.64 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-4a1cba65-7cb0-4bd0-a829-89aede6c97b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=758051877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.758051877 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.250875761 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 24353119004 ps |
| CPU time | 102.01 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:16:21 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-b357cce5-faa0-4f21-82b3-b4dae588a955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=250875761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.250875761 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3561621039 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 616253752 ps |
| CPU time | 5.69 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:49 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-a22582f7-4c02-497b-825e-7a52ceade77b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3561621039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3561621039 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.1650794415 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 748265721 ps |
| CPU time | 11.9 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-28eb9695-277a-4fe9-8f1e-2c0f6293fc4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1650794415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1650794415 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3734430129 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 39911396 ps |
| CPU time | 3.86 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-db9c7401-57a0-4820-bcb8-5bfe21c3b77f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3734430129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3734430129 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2041937940 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 111473768168 ps |
| CPU time | 136.16 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:16:59 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-3832108d-3ecc-4205-bbb9-7b8b2b69e17c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041937940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2041937940 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1904676760 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 28679547 ps |
| CPU time | 2.59 seconds |
| Started | Mar 05 01:14:38 PM PST 24 |
| Finished | Mar 05 01:14:41 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-d71b0063-b585-4250-b30b-3e91b16ddaa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904676760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1904676760 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3586897167 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3595271955 ps |
| CPU time | 11.68 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-4bb03af5-cf69-459c-8d21-955358c7f61b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3586897167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3586897167 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2673729172 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 88163070 ps |
| CPU time | 1.5 seconds |
| Started | Mar 05 01:14:30 PM PST 24 |
| Finished | Mar 05 01:14:32 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-42ee9b2d-cf99-4e24-8573-da0d2dd4170b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673729172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2673729172 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2159579478 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2362736142 ps |
| CPU time | 10.95 seconds |
| Started | Mar 05 01:14:32 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-6a471f49-446e-4977-b59a-bb6350ca7572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159579478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2159579478 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1536124913 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3166086740 ps |
| CPU time | 9.3 seconds |
| Started | Mar 05 01:14:33 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-5427c7ab-b79f-48fb-9aad-3cd7e4e2c810 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1536124913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1536124913 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1378797142 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 28771454 ps |
| CPU time | 1.26 seconds |
| Started | Mar 05 01:14:33 PM PST 24 |
| Finished | Mar 05 01:14:34 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-46a7c02d-9dbb-4c1d-ac11-af141a650c93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378797142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1378797142 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3484748181 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 281340339 ps |
| CPU time | 22.61 seconds |
| Started | Mar 05 01:14:38 PM PST 24 |
| Finished | Mar 05 01:15:01 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-d22d0d86-41bb-46fd-b8f4-2c2d55842311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484748181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3484748181 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.4257572185 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 122037493 ps |
| CPU time | 13.97 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-c7107a6d-4ee2-4bc9-9603-d61cab74bbf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257572185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4257572185 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2331130259 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 6880122063 ps |
| CPU time | 243.86 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:18:44 PM PST 24 |
| Peak memory | 209176 kb |
| Host | smart-0c70b726-b384-4c1d-af86-af381c6ca2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2331130259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2331130259 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1686089791 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 252306799 ps |
| CPU time | 35.29 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:15:15 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-b6b9b9a5-a364-4bf9-aaec-964b0a579ad7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1686089791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1686089791 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1166283261 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 603680568 ps |
| CPU time | 10.17 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-cb6893aa-1afd-4342-982d-8d02de14367e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1166283261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1166283261 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1577948961 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 22703577 ps |
| CPU time | 2.88 seconds |
| Started | Mar 05 01:14:42 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-3faf0528-b301-4d28-8cd1-83529a1349b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577948961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1577948961 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1198085052 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 14145927858 ps |
| CPU time | 87.8 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:16:08 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-5c34691a-5a0f-45e1-8127-3b415920d495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1198085052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1198085052 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1074073171 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1040976614 ps |
| CPU time | 9.55 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:50 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-d9e42dc7-76d9-4243-8589-872943397cd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1074073171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1074073171 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1871266036 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 43092667 ps |
| CPU time | 3.85 seconds |
| Started | Mar 05 01:14:38 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-e6c93dd7-1447-49a1-98c6-d86459817519 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871266036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1871266036 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.396800862 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 479636375 ps |
| CPU time | 6.88 seconds |
| Started | Mar 05 01:14:46 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-ea73228f-4721-4a3d-a07d-ecd2ede63da0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=396800862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.396800862 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1157868169 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 14063241041 ps |
| CPU time | 63.69 seconds |
| Started | Mar 05 01:14:37 PM PST 24 |
| Finished | Mar 05 01:15:41 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-10a7047b-1962-44a0-902c-8ce6dde994e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157868169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1157868169 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2023644386 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 18455795409 ps |
| CPU time | 64.02 seconds |
| Started | Mar 05 01:14:37 PM PST 24 |
| Finished | Mar 05 01:15:42 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-983c1682-b32f-49e3-bcb3-5da24eda0aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2023644386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2023644386 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3496955211 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 28162774 ps |
| CPU time | 3.49 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-6978a89d-ca82-487e-95b8-a310f0d7a923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496955211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3496955211 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.919804654 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 7783605632 ps |
| CPU time | 13.67 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-f8b856f1-a6ba-468f-94ea-ebd546d35c74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919804654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.919804654 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.4230478208 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8707731 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:14:42 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-db0debdd-b3f8-445c-9929-5647643167ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230478208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4230478208 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.172297247 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1645673766 ps |
| CPU time | 8.62 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-5ffdb1f9-dded-45bd-9998-02649950c1f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=172297247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.172297247 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.718672379 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1052592864 ps |
| CPU time | 5.76 seconds |
| Started | Mar 05 01:14:46 PM PST 24 |
| Finished | Mar 05 01:14:52 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-4cc6144c-e835-41cf-94ec-5438afb12f92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=718672379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.718672379 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.172998495 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 15576397 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-bce24888-375a-4ef2-b937-e7fd7d464dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172998495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.172998495 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4116792218 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3577743121 ps |
| CPU time | 12.35 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-11a0de59-8210-4954-96e0-ae4f7b966d0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4116792218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4116792218 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2840413891 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 158866390 ps |
| CPU time | 2.81 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-98bf21f0-d9db-42b6-8fa2-a3257213d220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840413891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2840413891 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4037264024 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 92353771 ps |
| CPU time | 22.1 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-0588fb34-4bd8-4eda-b198-ac964bcad2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4037264024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.4037264024 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2976143772 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 9264655 ps |
| CPU time | 2.07 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-5f86f91b-a4f6-41f9-88fe-4175e2e117f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2976143772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2976143772 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.637343481 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 21674228 ps |
| CPU time | 2.58 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:14:44 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-86bc3263-0ddc-402b-bf24-c8dce44b969d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=637343481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.637343481 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.914284266 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 445311747 ps |
| CPU time | 8.09 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:28 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-3a76764e-9cf6-492f-9504-c140a799b612 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=914284266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.914284266 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.401959371 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 20182983389 ps |
| CPU time | 122.58 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:14:22 PM PST 24 |
| Peak memory | 203328 kb |
| Host | smart-ebfb6d64-d358-4ec8-81d5-9955016637ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=401959371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow _rsp.401959371 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1321029528 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 17027462 ps |
| CPU time | 1.77 seconds |
| Started | Mar 05 01:12:26 PM PST 24 |
| Finished | Mar 05 01:12:28 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-3a442a78-c03b-4568-99eb-9f77b93a2f3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1321029528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1321029528 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2014449483 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 42282406 ps |
| CPU time | 4.9 seconds |
| Started | Mar 05 01:12:22 PM PST 24 |
| Finished | Mar 05 01:12:27 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-f737f72c-3d30-40e2-84e5-f272058689cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014449483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2014449483 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.323162055 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 92435347 ps |
| CPU time | 4.88 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:12:25 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-d05a673b-532e-4810-9732-87bdd2b9303c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323162055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.323162055 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1470963011 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 33183271008 ps |
| CPU time | 121.15 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:14:22 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-ef9e44aa-7eb1-4cd9-b8fe-8b36b92cd6db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470963011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1470963011 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1158174003 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 10233811145 ps |
| CPU time | 76.08 seconds |
| Started | Mar 05 01:12:22 PM PST 24 |
| Finished | Mar 05 01:13:39 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-feb8c37f-fd79-4ccd-905a-638ad20c03c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1158174003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1158174003 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3799081728 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 15771086 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:12:18 PM PST 24 |
| Finished | Mar 05 01:12:19 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-6f6bc977-c38d-45dc-b656-fdbf0c03f810 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799081728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3799081728 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.455883328 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 422683154 ps |
| CPU time | 5.59 seconds |
| Started | Mar 05 01:12:18 PM PST 24 |
| Finished | Mar 05 01:12:23 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-2a6826fa-03e8-4653-a3e3-f627203ca79e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=455883328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.455883328 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.4281463855 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 53614325 ps |
| CPU time | 1.59 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-6e736053-b786-4b62-8cc5-b42aa2c699a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4281463855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4281463855 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2226791764 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 7920956625 ps |
| CPU time | 7.13 seconds |
| Started | Mar 05 01:12:26 PM PST 24 |
| Finished | Mar 05 01:12:33 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-0e05f253-8ed7-435b-a792-a60f1eb169c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226791764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2226791764 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3642826216 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3895700842 ps |
| CPU time | 9.16 seconds |
| Started | Mar 05 01:12:23 PM PST 24 |
| Finished | Mar 05 01:12:32 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-2f553e01-bd0b-4cde-81f6-2cf81c373d7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3642826216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3642826216 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3683984640 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 8867493 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:12:20 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-7e9c0945-cf00-4121-a791-f73443959cb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683984640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3683984640 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.389426503 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 516054032 ps |
| CPU time | 9.59 seconds |
| Started | Mar 05 01:12:21 PM PST 24 |
| Finished | Mar 05 01:12:31 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-1b33f5e8-babf-4cff-83b0-e99ee1d49948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=389426503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.389426503 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1141913540 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3049785385 ps |
| CPU time | 19.63 seconds |
| Started | Mar 05 01:12:18 PM PST 24 |
| Finished | Mar 05 01:12:38 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-f31a870e-e1b6-473f-be40-cee171a9d759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1141913540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1141913540 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.258473127 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3181150737 ps |
| CPU time | 90.21 seconds |
| Started | Mar 05 01:12:19 PM PST 24 |
| Finished | Mar 05 01:13:50 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-8a8c5ff8-036d-469e-af68-234c603c2d55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=258473127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.258473127 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1262751618 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 405679114 ps |
| CPU time | 6.94 seconds |
| Started | Mar 05 01:12:25 PM PST 24 |
| Finished | Mar 05 01:12:32 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-f7f3e806-e73f-47bb-8c8b-136d8adf0780 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262751618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1262751618 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.981397922 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 12860568 ps |
| CPU time | 2.03 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-361aebd7-2720-4679-a0e4-33aebf0a43e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981397922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.981397922 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3249898650 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 17517168550 ps |
| CPU time | 128.47 seconds |
| Started | Mar 05 01:14:45 PM PST 24 |
| Finished | Mar 05 01:16:54 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-308ec545-48b1-422c-9ae2-7787179719a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3249898650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3249898650 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2386549307 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1816774542 ps |
| CPU time | 8.31 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:48 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-073ee9c1-88b7-44c0-a0e7-987f9c043b87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2386549307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2386549307 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.273532705 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1023317612 ps |
| CPU time | 14.81 seconds |
| Started | Mar 05 01:14:46 PM PST 24 |
| Finished | Mar 05 01:15:01 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-80afce07-25be-490c-befd-d0ebdb712f68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273532705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.273532705 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.973179475 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1418891463 ps |
| CPU time | 5.65 seconds |
| Started | Mar 05 01:14:40 PM PST 24 |
| Finished | Mar 05 01:14:46 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-baf8e68e-1d8c-4b03-9034-b0a315eee32e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973179475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.973179475 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2576627990 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 11779522927 ps |
| CPU time | 40.54 seconds |
| Started | Mar 05 01:14:46 PM PST 24 |
| Finished | Mar 05 01:15:27 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-7d8b972c-bdc7-44bc-8844-b8eeb93eb01b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576627990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2576627990 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2221352869 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 33190184782 ps |
| CPU time | 99.11 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:16:22 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-e2a09eac-fd09-492c-840b-b04ffbd82c44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2221352869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2221352869 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3699063656 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 277907975 ps |
| CPU time | 5.53 seconds |
| Started | Mar 05 01:14:41 PM PST 24 |
| Finished | Mar 05 01:14:47 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-9e5179ce-9168-473f-acca-7edee173d72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699063656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3699063656 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3581979470 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 652942679 ps |
| CPU time | 4.6 seconds |
| Started | Mar 05 01:14:46 PM PST 24 |
| Finished | Mar 05 01:14:51 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-4e8a9bb7-df94-49cc-b950-481b18ce025e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3581979470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3581979470 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.1731495524 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 53704620 ps |
| CPU time | 1.64 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-a8f3a01c-b9fc-41ab-a407-0b839434075e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1731495524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1731495524 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4090463142 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1417772521 ps |
| CPU time | 6.29 seconds |
| Started | Mar 05 01:14:42 PM PST 24 |
| Finished | Mar 05 01:14:48 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-dc65162a-ed07-40c7-b8d5-4b45dbdee085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090463142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4090463142 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3361815484 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1502638961 ps |
| CPU time | 10.28 seconds |
| Started | Mar 05 01:14:38 PM PST 24 |
| Finished | Mar 05 01:14:49 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-f04e6c3d-2d75-4fcf-8c42-4a7655ffb550 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3361815484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3361815484 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.765696218 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 8914536 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:14:43 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-a4d02a2d-93b2-4225-a7d2-3e7369a22cdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765696218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.765696218 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1478412690 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 695465568 ps |
| CPU time | 10.91 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-a2eb381e-5906-4ac1-98c3-f39c2df157cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1478412690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1478412690 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2570367632 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1496636522 ps |
| CPU time | 6.24 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:14:59 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-582daa5b-35dc-4593-9fd1-78c52510a6e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2570367632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2570367632 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2133152004 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 32352776 ps |
| CPU time | 3.35 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:55 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-48b51a4d-50be-4a8e-be75-d2aef2e3a3b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133152004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2133152004 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2923450897 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5640463793 ps |
| CPU time | 50.8 seconds |
| Started | Mar 05 01:14:54 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-3f3cf830-db64-42e6-954a-55c066dc6db6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2923450897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2923450897 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2080748809 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 200035060 ps |
| CPU time | 4.78 seconds |
| Started | Mar 05 01:14:39 PM PST 24 |
| Finished | Mar 05 01:14:45 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-1b971f0c-f36b-4ffa-8818-6348ba1b6df1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080748809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2080748809 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3379716355 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1082194447 ps |
| CPU time | 17.2 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:09 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-a45e1529-fc0f-4f83-9ee4-085561fe3adb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379716355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3379716355 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1462304512 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 90622073662 ps |
| CPU time | 138.63 seconds |
| Started | Mar 05 01:14:55 PM PST 24 |
| Finished | Mar 05 01:17:14 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-a6bfb70b-9bf8-4ccc-9ab2-c5c1ef25ff3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1462304512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.1462304512 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1168996422 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 237788103 ps |
| CPU time | 4 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:14:57 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-b882415a-eb08-434e-aa61-dc0dbcfedecc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168996422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1168996422 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.2735303904 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 36480559 ps |
| CPU time | 3.42 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-c7a41952-a334-4ed7-85cf-a8bb938c71c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2735303904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2735303904 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.1197190035 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 168751633 ps |
| CPU time | 6.54 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:57 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-3c8810c5-6b4c-44d8-b6fb-d34d7f0744e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1197190035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1197190035 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2014423423 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 36087021162 ps |
| CPU time | 79.78 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:16:14 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-42b84ce8-c27a-4f6e-9182-3951c1cf7023 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014423423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2014423423 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1008688525 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 13869800136 ps |
| CPU time | 82.72 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:16:14 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-a9a8d1b2-ef22-4072-af95-4678bde6cb0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1008688525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1008688525 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.487562195 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 52301523 ps |
| CPU time | 6.32 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:15:01 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-458309bd-5a20-435a-af23-53fb352029f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487562195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.487562195 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1002856162 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1242514512 ps |
| CPU time | 13.33 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:04 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-242fd40a-4359-47af-af59-2d2751b8736a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002856162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1002856162 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2146904657 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 8798768 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-6da1e7ed-2adc-412f-b84d-bf7047b49b38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2146904657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2146904657 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1090303318 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1558474838 ps |
| CPU time | 6.69 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:58 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-ae8a7b88-9c25-42b9-a960-22bed19925cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090303318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1090303318 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3482575859 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 969567624 ps |
| CPU time | 7.51 seconds |
| Started | Mar 05 01:14:55 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-88260092-631e-4e62-961e-f2fb1a54170e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3482575859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3482575859 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3067684938 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 13539583 ps |
| CPU time | 1.13 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-daf4bc26-f19e-4ee5-a758-05c362bcf7a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067684938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3067684938 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.301233645 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 619601102 ps |
| CPU time | 11.95 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:15:05 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-7d28a7a7-cf8e-40a5-9b40-300e3000a215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=301233645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.301233645 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1686450904 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1367815570 ps |
| CPU time | 17.32 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:08 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-a4aa66ad-d606-42ca-8864-fcb1d04330d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1686450904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1686450904 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3522813664 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 844057762 ps |
| CPU time | 121.12 seconds |
| Started | Mar 05 01:14:54 PM PST 24 |
| Finished | Mar 05 01:16:55 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-fa323f04-5c5b-4a06-9779-c2d424b1c288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3522813664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3522813664 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1583025204 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 852029546 ps |
| CPU time | 38.35 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-ebaa33e0-3ede-4c7d-9acf-5536fbfc79b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583025204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1583025204 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1425719982 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 307872130 ps |
| CPU time | 5.44 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:57 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-7fb88bbf-f6a9-4f51-bb73-e5a7550ba1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1425719982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1425719982 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3035166502 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 15918741 ps |
| CPU time | 2.93 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:55 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-0c04cfdd-3d9d-4692-adc8-85786fec4099 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3035166502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3035166502 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.128337607 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 60646852327 ps |
| CPU time | 202.73 seconds |
| Started | Mar 05 01:14:54 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 203580 kb |
| Host | smart-17f82d75-dd1b-400b-acdc-6848eb00674d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=128337607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.128337607 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.4207033200 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 95747407 ps |
| CPU time | 4.52 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:57 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-fe6c6bd0-75a7-4de2-8768-c796ae2951b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4207033200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.4207033200 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.461546652 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 368696505 ps |
| CPU time | 6.26 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:58 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-bc69713e-edd9-46ce-aa95-a1c547410b5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461546652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.461546652 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.1824724021 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 8704662 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 01:14:54 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-d0a9aa39-f0ce-4cfb-82c4-7140d43770ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1824724021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1824724021 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3306752867 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 56919132386 ps |
| CPU time | 33.77 seconds |
| Started | Mar 05 01:14:54 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-c70ee833-3ce8-419a-a545-60486c88506b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306752867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3306752867 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.764458666 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 38608681802 ps |
| CPU time | 148.59 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:17:22 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-62f4d3d7-e93c-43a7-9190-b5ad0495eacf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=764458666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.764458666 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4115489879 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 16377759 ps |
| CPU time | 1.46 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-5f50f733-cbcd-4448-9243-07af1af56aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115489879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4115489879 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2969466705 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1051387260 ps |
| CPU time | 4.48 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:57 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-c8dafd8d-3a2c-4620-bd0f-ea0f75aa5f88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2969466705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2969466705 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.512765021 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 12317228 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-60cdba95-2057-4c40-b3b7-0de4f9f46beb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512765021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.512765021 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2497523163 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2452100537 ps |
| CPU time | 12.11 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-26273871-e958-48b7-a95d-03af2f1bb9a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497523163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2497523163 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.782669687 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 3088762504 ps |
| CPU time | 4.8 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:56 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-abdcf4c6-19be-499c-947a-716c556e4cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=782669687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.782669687 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3337209090 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 8250852 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:14:52 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3e47e992-4af7-4e94-b168-0587fb040771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337209090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3337209090 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1910158530 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2413432321 ps |
| CPU time | 30.56 seconds |
| Started | Mar 05 01:14:55 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-58b22107-d011-4f5a-83dc-af4f5ba34071 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1910158530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1910158530 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3480577391 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 253717948 ps |
| CPU time | 18.5 seconds |
| Started | Mar 05 01:14:53 PM PST 24 |
| Finished | Mar 05 01:15:13 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-8995e1d8-0aac-4566-8e24-3fa58b655b9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3480577391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3480577391 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.225181440 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 484000733 ps |
| CPU time | 78.89 seconds |
| Started | Mar 05 01:14:55 PM PST 24 |
| Finished | Mar 05 01:16:14 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-58eee1a1-ef44-405c-9a5c-f81ef9530adb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=225181440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand _reset.225181440 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2790352589 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 250346542 ps |
| CPU time | 29.61 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-0c43c1f5-31d0-4164-8bd3-5ca95b2f4288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790352589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.2790352589 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3851282056 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 48057647 ps |
| CPU time | 3.01 seconds |
| Started | Mar 05 01:14:51 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-cb51e239-3f33-4902-bea6-f302f418a625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3851282056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3851282056 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1029587111 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 31491651 ps |
| CPU time | 3.45 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:06 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-ef668a1b-c5cf-4db5-bb1e-ef1f86fa0a20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029587111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1029587111 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2933747753 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 15812816318 ps |
| CPU time | 19.82 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:22 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-a7f48693-6cf1-4b7c-91bd-7ac1bc361ebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2933747753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2933747753 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2402873104 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 67686139 ps |
| CPU time | 6.27 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:08 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-26282a49-3bb9-49bb-8ab1-d67e34357be5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2402873104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2402873104 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2308775884 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 696987415 ps |
| CPU time | 12.33 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:15 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-bc19ae79-c647-469e-ae5c-efe286fa0433 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2308775884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2308775884 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2003245636 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1462475044 ps |
| CPU time | 15.66 seconds |
| Started | Mar 05 01:15:04 PM PST 24 |
| Finished | Mar 05 01:15:20 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-491d72fa-3a9a-4797-bb3d-ead976624323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2003245636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2003245636 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3371985178 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 54838863210 ps |
| CPU time | 122.87 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:17:07 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-03d08f26-5c25-427d-88c3-cde211f7aeb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371985178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3371985178 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2519566058 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 21048599776 ps |
| CPU time | 150.84 seconds |
| Started | Mar 05 01:15:04 PM PST 24 |
| Finished | Mar 05 01:17:35 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-4a9f4260-5f6e-475a-b45d-784edde7de37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2519566058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2519566058 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1218503284 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 17160917 ps |
| CPU time | 2.22 seconds |
| Started | Mar 05 01:15:07 PM PST 24 |
| Finished | Mar 05 01:15:09 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-a8f663b4-67b9-43ad-8381-36175c49eb87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218503284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1218503284 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.276437576 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 14081184 ps |
| CPU time | 1.26 seconds |
| Started | Mar 05 01:15:07 PM PST 24 |
| Finished | Mar 05 01:15:09 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-3aab820a-c263-4832-a493-8d891986c930 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276437576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.276437576 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2147582169 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 67920124 ps |
| CPU time | 1.8 seconds |
| Started | Mar 05 01:15:04 PM PST 24 |
| Finished | Mar 05 01:15:06 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-eed5c7b8-4100-4918-ba5d-ba23e51e80b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2147582169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2147582169 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2556912604 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3695115659 ps |
| CPU time | 8.65 seconds |
| Started | Mar 05 01:14:59 PM PST 24 |
| Finished | Mar 05 01:15:09 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-14108cab-b4d7-4f27-bf2f-0d7cabdb81c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556912604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2556912604 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.303581826 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2914656029 ps |
| CPU time | 6.05 seconds |
| Started | Mar 05 01:15:04 PM PST 24 |
| Finished | Mar 05 01:15:11 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-058e04df-af02-459a-8e81-d9fdd472d897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=303581826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.303581826 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2138792284 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 11387132 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:15:05 PM PST 24 |
| Finished | Mar 05 01:15:07 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-542d08fa-cb8f-4b5c-b4a2-1959f5eb6ade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138792284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2138792284 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2235403300 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 974856992 ps |
| CPU time | 21.98 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:24 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-c2b2ebf3-126c-4c74-a519-e8cea51c95cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2235403300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2235403300 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.687901194 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1800008397 ps |
| CPU time | 28.39 seconds |
| Started | Mar 05 01:15:00 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-6bcb85fd-4a1a-4e9c-9d32-619a52c43a28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=687901194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.687901194 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3547524071 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 614835165 ps |
| CPU time | 64.39 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-f1c307fa-4f4b-489f-8367-c2355263bbb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3547524071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3547524071 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2582710921 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 9328036687 ps |
| CPU time | 124.13 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:17:07 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-bec8b332-e3cb-4e08-b9e4-3b1a82ecea5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582710921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2582710921 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3469497123 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 135236992 ps |
| CPU time | 5.85 seconds |
| Started | Mar 05 01:15:00 PM PST 24 |
| Finished | Mar 05 01:15:07 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-853f7a0e-8fa3-4422-9271-8172d57604c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3469497123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3469497123 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2724652887 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 48410492 ps |
| CPU time | 10.67 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:15:15 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-a54edd44-72dc-461b-9214-f86d97b952e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2724652887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2724652887 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.299797949 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 50626297336 ps |
| CPU time | 147.92 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:17:32 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-97677fac-b9d5-473e-8457-62524569a670 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=299797949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.299797949 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1543415478 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 187726195 ps |
| CPU time | 3.4 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:06 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-5a224ffb-d9a1-41d6-8397-c8a2109710d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543415478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1543415478 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.534302468 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 19752055 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-63e78e22-e90f-4268-8c9e-40ff33e739d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534302468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.534302468 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2412616504 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 40274038 ps |
| CPU time | 1.49 seconds |
| Started | Mar 05 01:15:06 PM PST 24 |
| Finished | Mar 05 01:15:08 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-7dd1aca0-19a2-48ed-963b-75db6b880d8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2412616504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2412616504 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.341719779 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 27349308367 ps |
| CPU time | 85.06 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:16:26 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-840871f2-1758-4a33-a198-5cf50e90f098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=341719779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.341719779 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1031344509 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 25766845854 ps |
| CPU time | 119.42 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:17:03 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-8b94522c-e418-430e-88cb-9513bc1481fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1031344509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1031344509 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.83980017 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 147267741 ps |
| CPU time | 6.82 seconds |
| Started | Mar 05 01:15:07 PM PST 24 |
| Finished | Mar 05 01:15:14 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-2afd8ae4-4983-43e7-90a4-b3cefac7ecb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83980017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.83980017 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.1586881544 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 94712192 ps |
| CPU time | 5.4 seconds |
| Started | Mar 05 01:15:00 PM PST 24 |
| Finished | Mar 05 01:15:06 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-9422cf61-b0ff-4877-9962-acb37d353457 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1586881544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1586881544 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.49520655 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 58788262 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 01:15:05 PM PST 24 |
| Finished | Mar 05 01:15:07 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-289a9602-df05-40a9-ae46-b0bcbaaf91da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=49520655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.49520655 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3565633139 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 12575683135 ps |
| CPU time | 12.95 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:15:17 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-1cf61ace-a295-4f0d-99b0-d82ecee61a0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565633139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3565633139 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.110875118 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1060186971 ps |
| CPU time | 8.89 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:12 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-55cb3854-e50f-4413-bf51-bfe84651720d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=110875118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.110875118 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.200582483 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 10028615 ps |
| CPU time | 1.33 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-8c876e00-7d95-4905-af27-b1ffbdfe4efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200582483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.200582483 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2503198489 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 319489267 ps |
| CPU time | 30.1 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:15:34 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-0b43e28f-fb0e-4faf-bcbe-3ca8287e759a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2503198489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2503198489 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.276247614 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 19006277256 ps |
| CPU time | 58.84 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:16:01 PM PST 24 |
| Peak memory | 203272 kb |
| Host | smart-51febc2e-5526-41bc-8c79-140a8dfef0e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276247614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.276247614 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3859527237 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 192342990 ps |
| CPU time | 13.43 seconds |
| Started | Mar 05 01:15:04 PM PST 24 |
| Finished | Mar 05 01:15:18 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-71dc66f7-4e60-4ad0-9298-18f699d7febc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859527237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3859527237 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.559626163 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3663800647 ps |
| CPU time | 86.35 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:16:29 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-6d4a0254-9c57-46db-abfb-b02bab0de460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=559626163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.559626163 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3777219211 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2758921798 ps |
| CPU time | 11.16 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:12 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-38425c8e-8cff-4c2d-aae1-7462ae565731 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3777219211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3777219211 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2769041350 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 213301719 ps |
| CPU time | 5.1 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-18f8b3ae-ee8c-4a7c-8daf-ce2d2d1c29ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769041350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2769041350 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.494786969 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 45252368236 ps |
| CPU time | 304.6 seconds |
| Started | Mar 05 01:15:15 PM PST 24 |
| Finished | Mar 05 01:20:20 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-6201913d-f1f9-41d8-86f1-227a584a59de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=494786969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.494786969 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2593774754 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 513208686 ps |
| CPU time | 2.61 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:19 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-949c4662-48bf-4c46-9d9d-c980f2c5fccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2593774754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2593774754 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2670125859 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 36816941 ps |
| CPU time | 3.34 seconds |
| Started | Mar 05 01:15:13 PM PST 24 |
| Finished | Mar 05 01:15:17 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-df18e372-39d7-4423-934e-d22b4f84dd3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2670125859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2670125859 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.2548843875 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 47712381 ps |
| CPU time | 4.13 seconds |
| Started | Mar 05 01:15:03 PM PST 24 |
| Finished | Mar 05 01:15:07 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-fdb476fb-d849-4d5f-b2fc-949d6c06d146 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548843875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2548843875 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2175871945 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 61572455065 ps |
| CPU time | 121.36 seconds |
| Started | Mar 05 01:15:15 PM PST 24 |
| Finished | Mar 05 01:17:17 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-e9b52020-31cd-44d1-a747-ecb12d4fe258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175871945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2175871945 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.529937432 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 51427629548 ps |
| CPU time | 95.56 seconds |
| Started | Mar 05 01:15:14 PM PST 24 |
| Finished | Mar 05 01:16:51 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-5e5002c7-fa7c-4785-b091-56e831ffad7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=529937432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.529937432 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3719717529 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 114505320 ps |
| CPU time | 4.46 seconds |
| Started | Mar 05 01:15:14 PM PST 24 |
| Finished | Mar 05 01:15:19 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-a5be0148-8b30-42bb-968f-4388f24699fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719717529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3719717529 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.2103820653 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 49461697 ps |
| CPU time | 2.08 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:19 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-121fa842-74f4-4ed3-ab14-afe3dc4ef45e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103820653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2103820653 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1149884619 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 13658051 ps |
| CPU time | 1.35 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:04 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-bcb89f55-27f3-49d3-8a04-6186c1530d54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149884619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1149884619 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3203216086 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1237505206 ps |
| CPU time | 6.1 seconds |
| Started | Mar 05 01:15:02 PM PST 24 |
| Finished | Mar 05 01:15:09 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-4ddcd627-204c-4a2e-80d3-62ef06c4be5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203216086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3203216086 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3499086940 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5484672678 ps |
| CPU time | 9.42 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:10 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-f50ad33c-c12c-4135-a07e-5f42383a2352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3499086940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3499086940 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4003613168 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 9536710 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:15:01 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-aa56f33c-8aae-40d9-b54c-3617516d728e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003613168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4003613168 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3447572414 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 995944802 ps |
| CPU time | 37.1 seconds |
| Started | Mar 05 01:15:15 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-40ae421f-7932-437a-9795-8c95a1c53525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3447572414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3447572414 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1503377252 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 12910499860 ps |
| CPU time | 91.17 seconds |
| Started | Mar 05 01:15:17 PM PST 24 |
| Finished | Mar 05 01:16:48 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-4751a069-e1a9-4241-a009-ad99a26c648a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1503377252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1503377252 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.520622177 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1271665383 ps |
| CPU time | 98.24 seconds |
| Started | Mar 05 01:15:15 PM PST 24 |
| Finished | Mar 05 01:16:54 PM PST 24 |
| Peak memory | 205800 kb |
| Host | smart-ed62cba3-c3e3-4a21-9a57-d33b852277b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=520622177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.520622177 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1171056030 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 83168815 ps |
| CPU time | 8.2 seconds |
| Started | Mar 05 01:15:13 PM PST 24 |
| Finished | Mar 05 01:15:22 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-ec34a91d-e25a-48c2-b517-a0355b5d0d90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171056030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1171056030 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3398722808 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 65848625 ps |
| CPU time | 2.38 seconds |
| Started | Mar 05 01:15:13 PM PST 24 |
| Finished | Mar 05 01:15:16 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-72ba671b-967a-4355-ba97-0b3981edc52e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3398722808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3398722808 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2320903655 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 63045425 ps |
| CPU time | 5.25 seconds |
| Started | Mar 05 01:15:20 PM PST 24 |
| Finished | Mar 05 01:15:25 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d3265fc1-800a-4aac-be31-904ece5525aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2320903655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2320903655 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.4169532793 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 48050967041 ps |
| CPU time | 225.25 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:19:04 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-61b10456-7ab9-47ca-8081-4034763a4f56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4169532793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.4169532793 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2276862256 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 12871817 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-41b80874-0dc0-4b98-a8e6-f8728890109c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2276862256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2276862256 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.900054513 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 773337690 ps |
| CPU time | 11.86 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:31 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-4681c962-4b63-4550-ac64-fc649238bd36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900054513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.900054513 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.178877471 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 63130245 ps |
| CPU time | 7 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-3c86af43-ecb5-4ae2-9626-b28f08c57e8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178877471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.178877471 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.868566436 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 51235795650 ps |
| CPU time | 151.2 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:17:49 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-309b0795-0aeb-4545-9af5-83778c699c3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=868566436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.868566436 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1733963337 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 58602977491 ps |
| CPU time | 88.42 seconds |
| Started | Mar 05 01:15:20 PM PST 24 |
| Finished | Mar 05 01:16:49 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-00ee6457-3d92-478e-a11a-bd1d23d0f26c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1733963337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1733963337 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2541269416 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 20655113 ps |
| CPU time | 1.25 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:15:19 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-dea18d48-cc17-4bb8-a453-1c13e1571840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541269416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2541269416 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2794897289 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1750946553 ps |
| CPU time | 10.33 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-dcc2281e-c6bc-4526-8339-121e84595a48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2794897289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2794897289 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.858630282 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 50255728 ps |
| CPU time | 1.75 seconds |
| Started | Mar 05 01:15:15 PM PST 24 |
| Finished | Mar 05 01:15:17 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-27c89a0f-3138-4845-bc66-5d7ea676e299 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858630282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.858630282 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.4242031072 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2023060536 ps |
| CPU time | 6.88 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:23 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-62218dc7-15b4-43f7-8bdf-ab7fb7f82bcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242031072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4242031072 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4069944693 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1392549163 ps |
| CPU time | 8.04 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:24 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-6ab798d0-8916-4e60-b928-01423644ddac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4069944693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4069944693 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3114500332 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 19163062 ps |
| CPU time | 1.4 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:17 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-52d1ea7b-9fcd-4782-91b5-5f32d5ea2302 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114500332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3114500332 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3559720560 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3397731567 ps |
| CPU time | 40.36 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-43b3261e-a15a-4015-976e-4cd485625ef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559720560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3559720560 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1165887181 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 19117283000 ps |
| CPU time | 74.43 seconds |
| Started | Mar 05 01:15:17 PM PST 24 |
| Finished | Mar 05 01:16:32 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-4a6a729c-f3b2-4a2b-966a-60ca3866f39a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1165887181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1165887181 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1311087634 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 529498425 ps |
| CPU time | 75.95 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:16:35 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-292d96f1-1ed2-4e60-853b-6669a92dd5cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1311087634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1311087634 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.117273695 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 622943277 ps |
| CPU time | 64.36 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:16:21 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-b5c2f79b-ab27-472d-84e4-f6a9d42e5871 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117273695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.117273695 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1934522778 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 182706623 ps |
| CPU time | 3.32 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:23 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3fb65890-20b8-4a8e-9790-839750cf7f5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934522778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1934522778 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1872968042 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 414984895 ps |
| CPU time | 9.38 seconds |
| Started | Mar 05 01:15:23 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-f97857d3-bcbd-4388-8aec-d50db6b32081 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872968042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1872968042 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3916300804 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 623858739 ps |
| CPU time | 7.31 seconds |
| Started | Mar 05 01:15:22 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-f16137f8-5a5d-448e-bd8e-e9a0ca7e4e16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3916300804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3916300804 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.780820401 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 48204866 ps |
| CPU time | 3.99 seconds |
| Started | Mar 05 01:15:22 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-88fc0e0f-1419-4cbe-904e-ef93e9a583f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=780820401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.780820401 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.3957291995 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 401342605 ps |
| CPU time | 3.99 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:15:23 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-7c666f7c-6c51-4135-9d27-24f4f52a8ae9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957291995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3957291995 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3045507161 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 19885618347 ps |
| CPU time | 84.52 seconds |
| Started | Mar 05 01:15:17 PM PST 24 |
| Finished | Mar 05 01:16:42 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-b1f1d2f4-48ae-44d3-9dec-a7d93298585d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045507161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3045507161 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2719966954 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 21897946711 ps |
| CPU time | 82.38 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:16:42 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-0939e488-958f-48df-b74c-669c3960af2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2719966954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2719966954 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3015995923 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 111581319 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:19 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-f04f787d-07a7-49f7-bb2d-80ec0cbe3106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015995923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3015995923 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3019468045 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4589429914 ps |
| CPU time | 12.24 seconds |
| Started | Mar 05 01:15:21 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-648fb526-7a79-477e-8828-b8e10e2dda2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3019468045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3019468045 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.864316865 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 53905146 ps |
| CPU time | 1.68 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:15:20 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-0bacc1c2-fa05-45ba-ba8f-c4d2dd1d864e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=864316865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.864316865 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3944571982 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1124300479 ps |
| CPU time | 6.32 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202144 kb |
| Host | smart-e20f1d2e-6f88-475f-b1fc-b5cfb05ead6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944571982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3944571982 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2435450469 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1189735795 ps |
| CPU time | 7.64 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:15:27 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-2e5f32c8-6f66-4187-81b4-c071d59ab2b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2435450469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2435450469 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3559890789 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 8772735 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:15:16 PM PST 24 |
| Finished | Mar 05 01:15:18 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-10e72020-c040-4340-8e86-b07929d23a90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559890789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3559890789 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3351388094 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2881762097 ps |
| CPU time | 56.54 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:16:16 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-80ec502b-f1a0-44d4-af39-bdb8f425b1c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3351388094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3351388094 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3109377951 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3897728805 ps |
| CPU time | 57.08 seconds |
| Started | Mar 05 01:15:23 PM PST 24 |
| Finished | Mar 05 01:16:20 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-940aa6b1-aa67-4ebd-8045-abfc2d2fa992 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109377951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3109377951 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3114583740 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 404464994 ps |
| CPU time | 50.91 seconds |
| Started | Mar 05 01:15:19 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-9990701f-f487-4480-a1d6-5382cd1b71d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3114583740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3114583740 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.583715559 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 15312487179 ps |
| CPU time | 179.51 seconds |
| Started | Mar 05 01:15:18 PM PST 24 |
| Finished | Mar 05 01:18:18 PM PST 24 |
| Peak memory | 206276 kb |
| Host | smart-4cee73ba-828b-46e5-88f7-bf951b6931fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=583715559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res et_error.583715559 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2304856065 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 151182281 ps |
| CPU time | 2.76 seconds |
| Started | Mar 05 01:15:22 PM PST 24 |
| Finished | Mar 05 01:15:25 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-bec8aa5e-8667-43d3-b375-a7d1b227abc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304856065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2304856065 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2012282224 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1139015591 ps |
| CPU time | 16.99 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:42 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-b5063257-ab18-4813-83d0-978804d3f8e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2012282224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2012282224 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2744096573 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 59565782371 ps |
| CPU time | 115.53 seconds |
| Started | Mar 05 01:15:29 PM PST 24 |
| Finished | Mar 05 01:17:24 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-d31c1094-77e8-4058-9449-aa3e602f24f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2744096573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2744096573 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3944477527 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 535767839 ps |
| CPU time | 8.55 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:34 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-5974d649-17d7-4499-9cd9-bded80c517ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3944477527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3944477527 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.726721238 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1293788519 ps |
| CPU time | 6.74 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-102cb7df-823c-48d8-8848-0ce5e89d46ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726721238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.726721238 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.1792929416 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 854946344 ps |
| CPU time | 9.74 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:34 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-f0448137-01ad-4e27-8e64-fd648f4b72a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792929416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1792929416 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.457128001 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 14817428637 ps |
| CPU time | 70.76 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:16:35 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-d45dfd57-debf-4f7a-a644-b34560170ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=457128001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.457128001 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2168156717 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 60496394 ps |
| CPU time | 4.59 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-5fd63c53-c7af-4c2e-bfaf-4d5ab4c17d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168156717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2168156717 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1006635236 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 3283978126 ps |
| CPU time | 12.37 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:40 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-e2bbc1f8-f2b1-4438-ad90-9af6a3657b4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1006635236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1006635236 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1460718498 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 17118409 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:15:22 PM PST 24 |
| Finished | Mar 05 01:15:24 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-f13fd344-ddfe-4466-807d-e561942b66fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460718498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1460718498 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1820067588 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3689700023 ps |
| CPU time | 9.55 seconds |
| Started | Mar 05 01:15:23 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-46fa6e1f-e5c9-4bf2-b75b-1b83aa3821d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820067588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1820067588 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.641612796 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2676480456 ps |
| CPU time | 12.67 seconds |
| Started | Mar 05 01:15:21 PM PST 24 |
| Finished | Mar 05 01:15:34 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-8f97af4e-3115-4d11-a8a4-79db0e5dd205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=641612796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.641612796 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.174464150 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 9307819 ps |
| CPU time | 1.17 seconds |
| Started | Mar 05 01:15:20 PM PST 24 |
| Finished | Mar 05 01:15:21 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-7b3cd2ac-f31c-4c38-9f56-eea0bea7db6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174464150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.174464150 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1275839106 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2484188967 ps |
| CPU time | 20.55 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-4963d6da-2e54-4777-87f8-2ff7e636617c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1275839106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1275839106 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2430847343 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 58048727 ps |
| CPU time | 4.65 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-73a8f0ec-c112-411e-983c-057feb8502e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2430847343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2430847343 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2345735440 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 9000917285 ps |
| CPU time | 47.27 seconds |
| Started | Mar 05 01:15:28 PM PST 24 |
| Finished | Mar 05 01:16:15 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-d60e1c93-7dc0-49e4-b2fd-cd5a87d18b2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345735440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2345735440 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.4047791637 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 85389077 ps |
| CPU time | 11.77 seconds |
| Started | Mar 05 01:15:31 PM PST 24 |
| Finished | Mar 05 01:15:43 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-80e2a0ef-d270-4222-bc5d-afb448fb9317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4047791637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.4047791637 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1160276224 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 232813668 ps |
| CPU time | 6.74 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-ccb0c741-593a-426a-aebd-f29ec2f0cb5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1160276224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1160276224 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.274190472 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 477785904 ps |
| CPU time | 12.26 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:39 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-c54df5c2-452a-4222-95b3-87d3eba584c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274190472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.274190472 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3572223112 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2036551236 ps |
| CPU time | 16.32 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:42 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-54217503-ab59-41f8-bdf6-0b363710677a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3572223112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3572223112 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.343124125 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 56316840 ps |
| CPU time | 5.65 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-81711aa0-ef59-4011-94aa-38501f5e7af3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=343124125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.343124125 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.4038860514 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 99801688 ps |
| CPU time | 5.6 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-85a57151-7f4f-4dc7-93ec-033f4470ae18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4038860514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4038860514 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3203282308 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 282398402 ps |
| CPU time | 4.6 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:31 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-a38c326a-d18f-450c-89a4-64d45291f72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203282308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3203282308 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2708267763 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 37594354887 ps |
| CPU time | 146.67 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:17:53 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e4efabae-028e-473d-8c19-a71bb0d81bef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708267763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2708267763 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3533800647 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 13482389558 ps |
| CPU time | 84.33 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:16:51 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-cc91b867-14a4-46dd-a450-2cb918d37f43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3533800647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3533800647 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.496565890 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 79066329 ps |
| CPU time | 5.57 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-a614d161-623a-4290-9023-b571c1273c9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496565890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.496565890 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.348425728 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 123012354 ps |
| CPU time | 4.83 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-b3b09d34-6930-4a8a-a87d-72175af1a7cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=348425728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.348425728 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1675716583 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 95705157 ps |
| CPU time | 1.65 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c35344ca-2cb1-44d0-b53a-6468b4fcfcc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1675716583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1675716583 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1517871324 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2910806319 ps |
| CPU time | 8.37 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:35 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-cd9bf2f0-a4b8-4a41-a744-25e627ea9d00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517871324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1517871324 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.649829821 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4035843097 ps |
| CPU time | 9.53 seconds |
| Started | Mar 05 01:15:28 PM PST 24 |
| Finished | Mar 05 01:15:37 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-5b622966-ce82-4d07-94bf-268e8a90d127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=649829821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.649829821 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4182484938 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 10083339 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 01:15:30 PM PST 24 |
| Finished | Mar 05 01:15:31 PM PST 24 |
| Peak memory | 201860 kb |
| Host | smart-b9db6625-f5f9-4627-994e-3e7fb9fe1108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182484938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4182484938 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1034270916 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 724427979 ps |
| CPU time | 21.08 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:48 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-47ec0821-9946-43d1-93ab-87a0a14cd83a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034270916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1034270916 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2275127138 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4193915165 ps |
| CPU time | 30.5 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-20925ad3-74c6-4e38-81e8-ae3da4ca2d10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275127138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2275127138 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4130939973 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 3846907182 ps |
| CPU time | 107.9 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:17:15 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-f1e1dedb-9ff2-4506-8bd6-f8b88127ce54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4130939973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.4130939973 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2282868975 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 659344576 ps |
| CPU time | 92.77 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:17:00 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-4c68bd21-8dd4-4cae-bba1-bdcaec4b984d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282868975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2282868975 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.4214326527 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 12262005 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:15:30 PM PST 24 |
| Finished | Mar 05 01:15:31 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-dfda2e45-5974-4bed-a756-aa312f8f6852 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4214326527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.4214326527 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.781171406 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 51974322 ps |
| CPU time | 11.04 seconds |
| Started | Mar 05 01:12:37 PM PST 24 |
| Finished | Mar 05 01:12:48 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-64c9c5d0-7528-4502-abe5-ae4a7090e96c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=781171406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.781171406 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3869004176 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 19336228626 ps |
| CPU time | 77.9 seconds |
| Started | Mar 05 01:12:33 PM PST 24 |
| Finished | Mar 05 01:13:51 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-60cfd99d-baf0-45c8-840f-f347581aebe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3869004176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.3869004176 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2162607678 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 39608753 ps |
| CPU time | 2.56 seconds |
| Started | Mar 05 01:12:32 PM PST 24 |
| Finished | Mar 05 01:12:35 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-d8227cdd-9061-4c41-8aba-6f3f5dd867c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162607678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2162607678 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3983268947 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 11825877 ps |
| CPU time | 1.47 seconds |
| Started | Mar 05 01:12:30 PM PST 24 |
| Finished | Mar 05 01:12:32 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-726fdd56-6df9-4c5d-8619-393f6faf07b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983268947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3983268947 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1892195780 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 154536583 ps |
| CPU time | 7.6 seconds |
| Started | Mar 05 01:12:30 PM PST 24 |
| Finished | Mar 05 01:12:37 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-7ffb1978-b427-4ba0-a6cf-f014cd113b73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1892195780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1892195780 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3121796379 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 10789283187 ps |
| CPU time | 50.7 seconds |
| Started | Mar 05 01:12:30 PM PST 24 |
| Finished | Mar 05 01:13:21 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-f52c532e-87fb-4f30-8519-cad3a57e74a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121796379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3121796379 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1577017618 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 9680596094 ps |
| CPU time | 64.61 seconds |
| Started | Mar 05 01:12:29 PM PST 24 |
| Finished | Mar 05 01:13:34 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-40c6d2c3-8271-45eb-a445-77d99832f1c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1577017618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1577017618 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1496253951 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 19913215 ps |
| CPU time | 2.15 seconds |
| Started | Mar 05 01:12:30 PM PST 24 |
| Finished | Mar 05 01:12:32 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-24aca674-8ed8-4285-9b71-f59fb7a543f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496253951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1496253951 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.832894250 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 57455167 ps |
| CPU time | 2.45 seconds |
| Started | Mar 05 01:12:32 PM PST 24 |
| Finished | Mar 05 01:12:35 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-b6b59c6c-90ca-445a-8b7b-902768cd1162 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=832894250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.832894250 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.4070563627 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 63334039 ps |
| CPU time | 1.49 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:30 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-410cc815-1810-43e4-ac1e-3e7f01a8e137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070563627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4070563627 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3039736544 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1849044610 ps |
| CPU time | 9.42 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:37 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-5ba49732-6731-4ddc-a820-8738e691e78d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039736544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3039736544 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1923997583 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1031501837 ps |
| CPU time | 7.67 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:35 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-12b2a239-a1bc-461f-bf21-298aac495402 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1923997583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1923997583 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.392131753 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 10893900 ps |
| CPU time | 1.35 seconds |
| Started | Mar 05 01:12:33 PM PST 24 |
| Finished | Mar 05 01:12:35 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-d1f11608-1997-487d-aad4-15f5618167e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392131753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.392131753 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.20515635 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1402739599 ps |
| CPU time | 26.12 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:55 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-ae593f09-05d1-4968-af38-81e05d50d10d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20515635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.20515635 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3923371328 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4554458385 ps |
| CPU time | 39.84 seconds |
| Started | Mar 05 01:12:29 PM PST 24 |
| Finished | Mar 05 01:13:09 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-05512f36-7516-45e8-af9a-fc7bf5991867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3923371328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3923371328 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2278031290 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 605623643 ps |
| CPU time | 81.24 seconds |
| Started | Mar 05 01:12:30 PM PST 24 |
| Finished | Mar 05 01:13:51 PM PST 24 |
| Peak memory | 206620 kb |
| Host | smart-dcc4b956-f4af-4d7e-ac96-32265b53884f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2278031290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2278031290 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1149706488 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 381925665 ps |
| CPU time | 42.93 seconds |
| Started | Mar 05 01:12:35 PM PST 24 |
| Finished | Mar 05 01:13:18 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-fe3fe994-4bd9-4cb5-ace3-7e2fea476199 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149706488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1149706488 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3107629525 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 653470474 ps |
| CPU time | 9.79 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:38 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-7e54f802-6266-4e67-8cf6-01fa3ab74c8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107629525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3107629525 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3759526000 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 19070196 ps |
| CPU time | 2.1 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-366666eb-769e-471f-95f5-9d23e3cf753f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3759526000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3759526000 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1056800792 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 51339079 ps |
| CPU time | 4.52 seconds |
| Started | Mar 05 01:15:28 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-d17fa530-bec6-4024-9e05-f5bd05f29909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1056800792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1056800792 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3689723827 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 27519573 ps |
| CPU time | 2.95 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-5edd7c4b-73b8-4cb5-aaa0-efd1e7a1fc4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3689723827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3689723827 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.1758924417 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 29733916 ps |
| CPU time | 2.56 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:27 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c0c21bc1-2a77-4ff4-a327-07e8e400f2d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758924417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1758924417 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3789465969 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 84753955528 ps |
| CPU time | 141.06 seconds |
| Started | Mar 05 01:15:31 PM PST 24 |
| Finished | Mar 05 01:17:52 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-762e28c7-19b8-4073-98ab-a783ec2522c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789465969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3789465969 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3181666774 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5786737067 ps |
| CPU time | 31.21 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:58 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-c084e084-4272-45e6-be21-a12e2600da2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3181666774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3181666774 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3099972500 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 15974463 ps |
| CPU time | 1.44 seconds |
| Started | Mar 05 01:15:31 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-ff436190-5293-4445-b179-422d29b70ace |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099972500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3099972500 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.877709030 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 764260225 ps |
| CPU time | 11.28 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:35 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-14d829b7-b3ba-4097-ab58-1c866c75cd7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877709030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.877709030 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1534390321 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 80272580 ps |
| CPU time | 1.33 seconds |
| Started | Mar 05 01:15:28 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-3ba1b3d4-ea5a-41d9-9f29-86821eb1c495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1534390321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1534390321 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.608912779 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 5866937439 ps |
| CPU time | 14.26 seconds |
| Started | Mar 05 01:15:30 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 201976 kb |
| Host | smart-ae8610fa-c58d-4ad6-a5c4-bedd93ab68e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=608912779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.608912779 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4140783458 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1044349940 ps |
| CPU time | 5.57 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:32 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-b500f97a-d781-4fd1-93f8-3bd513852012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4140783458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4140783458 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2204888947 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 12814172 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-b7bf557c-4eb1-42c4-bc39-afbbd9607333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204888947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2204888947 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1546152524 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 356480746 ps |
| CPU time | 22.28 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:47 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-b40f228b-384a-4dc5-933b-2a4c99fa31f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1546152524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1546152524 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1455190480 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 676516455 ps |
| CPU time | 21.21 seconds |
| Started | Mar 05 01:15:31 PM PST 24 |
| Finished | Mar 05 01:15:52 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-dad6d205-6d41-48af-9f86-b053695a07c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1455190480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1455190480 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3883062569 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 139778458 ps |
| CPU time | 37.48 seconds |
| Started | Mar 05 01:15:31 PM PST 24 |
| Finished | Mar 05 01:16:08 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-80dda856-052a-46ab-9f67-8da62e6581d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3883062569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.3883062569 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1726931192 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 48735447 ps |
| CPU time | 4.31 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-343126cd-9b25-4ecb-a50c-b5a2c04e6774 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1726931192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1726931192 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3592840851 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 36790565 ps |
| CPU time | 2.58 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:30 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-d197557e-d2e4-458b-8fc9-c578d02830f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3592840851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3592840851 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4041446665 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3513931601 ps |
| CPU time | 20.49 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:15:58 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3bea8c42-3056-4018-9670-ec697e1741fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041446665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4041446665 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1097473134 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 242051551555 ps |
| CPU time | 324.18 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:21:03 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-525d41a3-38fa-49a4-bc92-c285b7363016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1097473134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1097473134 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.608978489 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 261094484 ps |
| CPU time | 4.25 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:43 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-271288eb-4b5e-45c2-9d4b-598fcf26b119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=608978489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.608978489 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.4091200677 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 53953627 ps |
| CPU time | 4.07 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:15:42 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-073fb62f-0a45-4462-9138-320750f73338 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091200677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4091200677 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2285148691 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 23835005 ps |
| CPU time | 2.52 seconds |
| Started | Mar 05 01:15:41 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-13f264eb-b532-4bca-856e-8ebfc4675d64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2285148691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2285148691 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.175294760 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 191521457283 ps |
| CPU time | 149.68 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:18:08 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-1ec4d7ce-c2fe-4e7c-98e0-7b0ffe37e114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=175294760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.175294760 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.431504183 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 44280497926 ps |
| CPU time | 110.21 seconds |
| Started | Mar 05 01:15:41 PM PST 24 |
| Finished | Mar 05 01:17:31 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-9d8c0923-0910-41e9-9c70-b60ac569d649 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=431504183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.431504183 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1206234895 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 215365858 ps |
| CPU time | 4.37 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-6db0f0b2-5a5a-4be7-9d28-63cea853eebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206234895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1206234895 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.622988029 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 28247435 ps |
| CPU time | 2.77 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:43 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-e688e3ea-f699-44c2-82ce-d4342b641659 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=622988029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.622988029 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.1598706699 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8419980 ps |
| CPU time | 1.17 seconds |
| Started | Mar 05 01:15:26 PM PST 24 |
| Finished | Mar 05 01:15:28 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-e5f9d5fb-0795-42f4-9972-fc2cf363f28d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1598706699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1598706699 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2619186041 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2369238570 ps |
| CPU time | 8.27 seconds |
| Started | Mar 05 01:15:27 PM PST 24 |
| Finished | Mar 05 01:15:36 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-6f6cd0d6-e297-47f8-8f1d-a9d62a0848d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619186041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2619186041 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4263386777 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1476252993 ps |
| CPU time | 8.52 seconds |
| Started | Mar 05 01:15:24 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-cfb610e8-0cc2-4a8f-b0a0-f1cc6d0c7f90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4263386777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4263386777 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.417069017 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10767944 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:15:25 PM PST 24 |
| Finished | Mar 05 01:15:26 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-a8755db1-fa45-4b70-9d6b-903a3a756cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417069017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.417069017 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3157482616 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1834150707 ps |
| CPU time | 16.17 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:56 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-60628c84-a83a-440b-b85d-79d33afb0d45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157482616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3157482616 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.355391865 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5310586688 ps |
| CPU time | 70.6 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:16:51 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-2d824ef7-2ee2-46b8-a573-6d82974801ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=355391865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.355391865 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1600413017 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 8061408916 ps |
| CPU time | 84.31 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:17:04 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-1e4b4e7e-e5e6-4a47-89e5-a0fb308c1d90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1600413017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1600413017 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3112038811 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5996582242 ps |
| CPU time | 148.64 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:18:07 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-4b3b0653-a24d-4c79-bcb0-0bccd222d625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3112038811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.3112038811 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3506279350 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 37219993 ps |
| CPU time | 4.64 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-4f46375b-75e0-402d-a65a-c0c4e539c72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3506279350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3506279350 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.629786179 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 73887304 ps |
| CPU time | 12.01 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:52 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-f0ee75b5-7b1e-4bda-8a71-29c7caf19450 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629786179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.629786179 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2228646056 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 26964631524 ps |
| CPU time | 57.89 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:16:41 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-a1fdc0aa-3c6b-42dc-85d0-7456b9aeae25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2228646056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2228646056 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3644246102 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 60193898 ps |
| CPU time | 3.16 seconds |
| Started | Mar 05 01:15:41 PM PST 24 |
| Finished | Mar 05 01:15:45 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-edc86394-2bd1-4287-bcd9-c876615dae33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644246102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3644246102 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.834929446 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 51103599 ps |
| CPU time | 7.46 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-4c77a9b0-4930-4172-ae98-6df33f3475d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=834929446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.834929446 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.4230258573 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 717851813 ps |
| CPU time | 14.55 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:54 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-f5d27850-9940-41bf-8795-dda11f00f6c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230258573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.4230258573 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.974135 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 23522520679 ps |
| CPU time | 93.95 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:17:13 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-25c48768-87ae-44ef-b6a6-2007e45228fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=974135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.974135 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.4011048693 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 8997588954 ps |
| CPU time | 45.59 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:16:26 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-d460915b-6050-4c80-bb97-db63d3345b20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4011048693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4011048693 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.919189269 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9958214 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:15:39 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-82828be3-58da-40be-a37b-040c1a7c53e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919189269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.919189269 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3527432517 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1043875951 ps |
| CPU time | 2.52 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:41 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-e5ff9912-17a1-47b6-b056-9662c6993820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527432517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3527432517 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.952190482 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 265336711 ps |
| CPU time | 1.61 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-39dadbb1-f1ff-4daf-abfb-83e4ae6f1582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=952190482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.952190482 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1038123783 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 10942969664 ps |
| CPU time | 8.57 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:48 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-b54a3bd2-8069-4f79-9c37-78586d842a48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038123783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1038123783 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.4147375746 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 799820114 ps |
| CPU time | 5.59 seconds |
| Started | Mar 05 01:15:37 PM PST 24 |
| Finished | Mar 05 01:15:43 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-49c1750f-d836-4117-86e8-082a4cdee342 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4147375746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4147375746 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.939765772 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 7920719 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-8ee388c4-644e-47fa-ae48-53305fdd9d5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939765772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.939765772 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.46899355 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 854333361 ps |
| CPU time | 25.21 seconds |
| Started | Mar 05 01:15:44 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-79df3eb7-33e2-4e67-8e49-d45e048b337d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46899355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.46899355 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4260124550 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3982719200 ps |
| CPU time | 31.53 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-121c72da-a28a-4e8a-acdb-91c1e804b78e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4260124550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4260124550 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.727659127 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 89934359 ps |
| CPU time | 8.21 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:48 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-4b188acd-890e-453a-b188-2d8d76277f5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=727659127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.727659127 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3138086554 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 97228574 ps |
| CPU time | 8.12 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:15:47 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-b088c285-6522-46d4-9500-39b7e7e68b54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3138086554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3138086554 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.955507549 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2020447724 ps |
| CPU time | 25.07 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-958da6e2-c61a-4de7-953a-b40bf84190af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=955507549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.955507549 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.482886136 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 96815961722 ps |
| CPU time | 302.31 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:20:44 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-78ea0c8e-39c1-4994-b748-a579c5016335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=482886136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.482886136 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3141921120 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 629609280 ps |
| CPU time | 11.12 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-3f901ec4-3d43-4bf1-b349-12638032228f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141921120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3141921120 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.150538782 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 60519224 ps |
| CPU time | 2.78 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-7cd116d4-7f1e-48b3-8339-3a77d187ddaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=150538782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.150538782 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3576696710 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 639904816 ps |
| CPU time | 11.29 seconds |
| Started | Mar 05 01:15:41 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-865932d3-bf40-44b9-97b6-b4bb89bd1a71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3576696710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3576696710 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1038275291 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 44392977532 ps |
| CPU time | 118.23 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:17:41 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-75284dd6-87f9-46ca-a9f2-62bee127aff3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038275291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1038275291 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.325308362 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 23700620793 ps |
| CPU time | 52.82 seconds |
| Started | Mar 05 01:15:39 PM PST 24 |
| Finished | Mar 05 01:16:32 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-bde2b233-2a63-4c39-ba72-e88752928ba5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=325308362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.325308362 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2978711428 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 15413475 ps |
| CPU time | 1.75 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:15:45 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-ef632c13-9c2f-48f8-b9ac-4b2991fb1ed6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978711428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2978711428 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.464046175 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 24366857 ps |
| CPU time | 2.38 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-545a6f1b-6ff9-4428-8862-429d88ab3b86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464046175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.464046175 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3717757314 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 75434556 ps |
| CPU time | 1.6 seconds |
| Started | Mar 05 01:15:43 PM PST 24 |
| Finished | Mar 05 01:15:45 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-8eb4c47c-1869-4b55-a3f5-e69071004251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717757314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3717757314 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2808032324 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2886124786 ps |
| CPU time | 12.86 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-eb7e6211-ab31-49e3-9706-beac609a7374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808032324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2808032324 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2935063502 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3960919003 ps |
| CPU time | 4.52 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-f0b5a1df-7627-4813-994f-db567865a47a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2935063502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2935063502 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4134052459 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8392178 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:15:44 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b9e1ff8a-9c4f-41ac-85bd-2414ead86993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134052459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4134052459 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.959911725 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 151760770 ps |
| CPU time | 13.36 seconds |
| Started | Mar 05 01:15:38 PM PST 24 |
| Finished | Mar 05 01:15:52 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-19cc75c2-570f-447f-9b52-6b3684a0dc7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=959911725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.959911725 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3278547911 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 10110090425 ps |
| CPU time | 45.34 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:16:27 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-ca2d7e8c-e6a0-4ee0-8bfb-b08bf07542cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3278547911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3278547911 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3779833503 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 526604208 ps |
| CPU time | 42.31 seconds |
| Started | Mar 05 01:15:40 PM PST 24 |
| Finished | Mar 05 01:16:23 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-9bad2f59-c93d-4028-a309-75fc2000ed3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3779833503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3779833503 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.811610248 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1621083520 ps |
| CPU time | 20.47 seconds |
| Started | Mar 05 01:15:42 PM PST 24 |
| Finished | Mar 05 01:16:02 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-b4a2cf26-2043-43da-9b87-c671745c867c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811610248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.811610248 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1608981015 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 45734240 ps |
| CPU time | 5.53 seconds |
| Started | Mar 05 01:15:41 PM PST 24 |
| Finished | Mar 05 01:15:46 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-afb8aa4d-e89f-4d54-b3d1-6167ccd3beeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608981015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1608981015 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1167940917 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 619193996 ps |
| CPU time | 16.2 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-431f5c69-9306-4fd3-a9a4-ed744a8de927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1167940917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1167940917 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1520771526 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 37398151036 ps |
| CPU time | 113.3 seconds |
| Started | Mar 05 01:15:53 PM PST 24 |
| Finished | Mar 05 01:17:46 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-b0cc68e8-3203-486b-9d3e-0b6d8db338fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1520771526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.1520771526 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2476983456 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 157098302 ps |
| CPU time | 1.18 seconds |
| Started | Mar 05 01:15:55 PM PST 24 |
| Finished | Mar 05 01:15:56 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-409857c9-166e-4208-b4e7-c1b930f6073d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2476983456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2476983456 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2662307820 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 302733262 ps |
| CPU time | 3.09 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:15:54 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-775e4f5a-9713-4cdc-8f98-42af3f308472 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662307820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2662307820 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.513837679 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 9792407 ps |
| CPU time | 1 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:15:50 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-a032262f-02b7-4357-be5b-aab438f77cc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513837679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.513837679 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1093863750 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13948809063 ps |
| CPU time | 50.87 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:43 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-1f1447b6-61d1-43d8-8c15-b10cb61e39b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093863750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1093863750 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.176859759 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 11829830009 ps |
| CPU time | 59.51 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:16:50 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-73effadd-4247-4873-9ac3-a50244dc3eda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=176859759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.176859759 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.912205616 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 9372077 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:15:50 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-90849810-078b-426b-bcc1-3d67ff69de56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912205616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.912205616 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3277930161 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4090828306 ps |
| CPU time | 11.59 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:16:02 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-65c9c811-56cc-4145-8bc7-e9c7d14e9352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277930161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3277930161 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3232641694 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 73469622 ps |
| CPU time | 1.58 seconds |
| Started | Mar 05 01:15:53 PM PST 24 |
| Finished | Mar 05 01:15:55 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-cc3adb38-5268-441a-bcad-9cd17bf10897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3232641694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3232641694 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.41092665 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1089720376 ps |
| CPU time | 5.98 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:15:55 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-a1aeafd4-1c65-4540-afa2-224ebaddc564 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.41092665 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1141671680 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 5300000658 ps |
| CPU time | 13.93 seconds |
| Started | Mar 05 01:15:48 PM PST 24 |
| Finished | Mar 05 01:16:02 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-9bbfbdb0-4f0b-4217-9073-8dd45e0d6a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1141671680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1141671680 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2191927747 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 15012809 ps |
| CPU time | 1.01 seconds |
| Started | Mar 05 01:15:55 PM PST 24 |
| Finished | Mar 05 01:15:56 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-9a8de84c-c76e-42b3-8669-cfff26ce7dde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191927747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2191927747 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1885240384 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 896767331 ps |
| CPU time | 41.01 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:16:31 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-d2dc911e-a399-4d8f-99ef-4adebfe82ef1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1885240384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1885240384 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3821731073 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1362096345 ps |
| CPU time | 23.73 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:16:13 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-726a3090-e5a9-4588-be09-3560d355a745 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3821731073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3821731073 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3308375883 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3035767632 ps |
| CPU time | 130.53 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:18:01 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-3df855eb-9000-4655-901a-e4c8009c4d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3308375883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3308375883 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1792745645 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 223693215 ps |
| CPU time | 37.69 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:16:28 PM PST 24 |
| Peak memory | 204204 kb |
| Host | smart-71e10c49-d18d-4e57-8aae-a3ba1be15297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792745645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.1792745645 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3041260272 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 670290943 ps |
| CPU time | 10.8 seconds |
| Started | Mar 05 01:15:56 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-b2dd7869-b654-47be-b88f-cd588f0ff707 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3041260272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3041260272 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3900134444 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 71812707 ps |
| CPU time | 10.51 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:16:00 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-e1781c6d-c4b2-4adb-95b1-3cdaa231f84e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3900134444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3900134444 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2908681000 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 23194709197 ps |
| CPU time | 167.32 seconds |
| Started | Mar 05 01:15:56 PM PST 24 |
| Finished | Mar 05 01:18:43 PM PST 24 |
| Peak memory | 203328 kb |
| Host | smart-a0ed3c21-9e39-4089-b01f-1631f80176df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2908681000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2908681000 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2671356118 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 169078395 ps |
| CPU time | 2.1 seconds |
| Started | Mar 05 01:15:55 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-1134717a-3619-40b7-92bc-aab350153498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2671356118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2671356118 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2538429634 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1921067014 ps |
| CPU time | 6.4 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-35c02527-148c-4bed-a38b-1df46376adeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2538429634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2538429634 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3253525979 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 267981805 ps |
| CPU time | 8.09 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:15:59 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-a5954c4c-5a96-4837-9cbc-0d4f13cac0d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253525979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3253525979 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2358055413 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 11498276393 ps |
| CPU time | 53 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:46 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-101ac36b-d38e-47e2-b3a4-212b72af14a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358055413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2358055413 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.969637541 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 146698055734 ps |
| CPU time | 146.54 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-ea34afc4-cbe5-4e7e-999b-e46f9d62eefa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=969637541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.969637541 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.707479913 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 28454873 ps |
| CPU time | 2.9 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:15:55 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-b08d8da3-df20-4394-b4ce-a4dd54f77303 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707479913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.707479913 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2001798465 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 517465190 ps |
| CPU time | 8.05 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:00 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-8387f7da-ae4d-4d38-bff0-fdd3dc906411 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2001798465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2001798465 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2867480193 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 72532338 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:15:51 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-9378d5ab-54c1-4c12-be58-ba072b8eef10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2867480193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2867480193 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3393633553 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2637906863 ps |
| CPU time | 11.26 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:16:01 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-2638692d-1e4c-4409-a141-baeb7a54c1d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393633553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3393633553 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2528065045 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1282716658 ps |
| CPU time | 7.13 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:15:59 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-7d01b12c-7c1b-48b1-86d1-8aad3426ebcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2528065045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2528065045 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.495818301 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9114035 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:15:52 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-ced7b8e5-7511-4c17-9a40-a42228473b2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495818301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.495818301 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1690819203 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 63785302 ps |
| CPU time | 9.7 seconds |
| Started | Mar 05 01:15:57 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-ac98ad06-19fa-428d-b855-a4fff3a86bac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690819203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1690819203 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2185332069 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2300475523 ps |
| CPU time | 21.19 seconds |
| Started | Mar 05 01:15:50 PM PST 24 |
| Finished | Mar 05 01:16:11 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-c0253df6-8525-4125-96ac-fa437aaa21d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185332069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2185332069 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2020069425 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 125941492 ps |
| CPU time | 7.78 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:00 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-2052b3d4-2ca2-4782-b568-e7feb906cb12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020069425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2020069425 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3702143601 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 10173310048 ps |
| CPU time | 78.58 seconds |
| Started | Mar 05 01:15:54 PM PST 24 |
| Finished | Mar 05 01:17:13 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-6e62c5bf-6218-4537-876a-f99785c658ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702143601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3702143601 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1498828408 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 709308845 ps |
| CPU time | 8.21 seconds |
| Started | Mar 05 01:15:49 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-c320c796-85cb-4b0d-b671-f340bbe84f2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498828408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1498828408 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3338199776 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 361961050 ps |
| CPU time | 7.28 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:15:59 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-f1ff2b03-c9a1-4f89-998e-b15e4613081a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3338199776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3338199776 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3589032856 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 244581595 ps |
| CPU time | 5.09 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:15:57 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-8af89046-fbbb-4ea4-a3f1-62d6f9f14155 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3589032856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3589032856 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1458885607 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2415992236 ps |
| CPU time | 15.19 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:19 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-85907dbf-2c87-4c43-b0cc-b5189b2d05b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1458885607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1458885607 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3257108030 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 966188179 ps |
| CPU time | 14.33 seconds |
| Started | Mar 05 01:15:58 PM PST 24 |
| Finished | Mar 05 01:16:12 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-7229156e-f05c-446f-9d3c-ab6e955df2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3257108030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3257108030 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2074558541 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 7681222349 ps |
| CPU time | 25.87 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:29 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-384995aa-686d-4726-ae49-d9134408de72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074558541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2074558541 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1042403973 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 25666003289 ps |
| CPU time | 64.7 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:57 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-8b8b73d4-c918-41ce-ad1f-b62175e3fddb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1042403973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1042403973 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1943164759 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 96783817 ps |
| CPU time | 4.25 seconds |
| Started | Mar 05 01:15:58 PM PST 24 |
| Finished | Mar 05 01:16:03 PM PST 24 |
| Peak memory | 202300 kb |
| Host | smart-bbf98e4c-75ca-4ea8-ae25-6aa6ad53ccf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943164759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1943164759 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2399082530 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 18035366 ps |
| CPU time | 1.4 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:04 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-93c75b88-592f-44f0-aacb-2426e0b5e20a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399082530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2399082530 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.4004204266 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 172518485 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:15:57 PM PST 24 |
| Finished | Mar 05 01:15:59 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-e472c9db-1642-481c-a572-bba6aba47364 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4004204266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4004204266 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3576100648 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 6668443540 ps |
| CPU time | 11.46 seconds |
| Started | Mar 05 01:15:55 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-25a59394-5889-4f99-bdb2-f660ad9ba8e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576100648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3576100648 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3422052983 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 8058490735 ps |
| CPU time | 10.17 seconds |
| Started | Mar 05 01:15:57 PM PST 24 |
| Finished | Mar 05 01:16:07 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-34ba25e9-930b-4197-92ce-b9e6deb373ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3422052983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3422052983 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.244484516 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 9290662 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:15:53 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-d5be09de-b898-432e-94ea-22627d085e5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244484516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.244484516 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2186375813 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 531767812 ps |
| CPU time | 17.3 seconds |
| Started | Mar 05 01:15:51 PM PST 24 |
| Finished | Mar 05 01:16:08 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d8dc91f4-b825-401e-abce-f651ebbeab9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186375813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2186375813 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2176555855 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 5201831644 ps |
| CPU time | 78.05 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:17:10 PM PST 24 |
| Peak memory | 203556 kb |
| Host | smart-08b31547-f068-4259-91b4-27c630c531d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176555855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2176555855 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2674133194 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 34399207 ps |
| CPU time | 17.34 seconds |
| Started | Mar 05 01:15:52 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-f0a16a30-35e4-4e5e-9235-fed49806590b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674133194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.2674133194 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2593724191 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1285412302 ps |
| CPU time | 156.82 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:18:40 PM PST 24 |
| Peak memory | 205616 kb |
| Host | smart-c59f74c1-0f0a-434d-acec-8cd53c5346aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2593724191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2593724191 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2789957306 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 77809843 ps |
| CPU time | 1.52 seconds |
| Started | Mar 05 01:15:59 PM PST 24 |
| Finished | Mar 05 01:16:00 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-e816f4ee-f79b-45fe-8acf-a9a714e1b71a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789957306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2789957306 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1379987336 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 269314449 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:05 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-6d809aa7-97e2-4d51-a5d0-325e0822fa32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379987336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1379987336 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.155727802 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 7005026649 ps |
| CPU time | 22.8 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:25 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-458fc8f0-9657-4b9d-b855-42e43a3485d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155727802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo w_rsp.155727802 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2814868673 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 574303507 ps |
| CPU time | 10.41 seconds |
| Started | Mar 05 01:16:00 PM PST 24 |
| Finished | Mar 05 01:16:11 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-4e7ab6b8-3770-4a0c-9e44-2796327560d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2814868673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2814868673 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.1692954388 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 53942590 ps |
| CPU time | 7.21 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-ec410cee-ac96-43b4-b641-571db2dacb27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1692954388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1692954388 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3936642086 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1424156778 ps |
| CPU time | 14.01 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:16 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-d7783319-11ac-4398-95a2-9a648b3f669c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3936642086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3936642086 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1096696909 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 27774615442 ps |
| CPU time | 82.12 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:17:24 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-be9814d2-64e6-43b9-99d5-d363dace110d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096696909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1096696909 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.402968095 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6874773863 ps |
| CPU time | 41.6 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:16:58 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-5c20aa5e-3aae-4e61-b6ad-cd6e9506832b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=402968095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.402968095 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2166227883 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 68741408 ps |
| CPU time | 10.2 seconds |
| Started | Mar 05 01:16:01 PM PST 24 |
| Finished | Mar 05 01:16:11 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-709bc773-7650-4494-b02e-eff56d10fd10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166227883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2166227883 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.268798569 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 117008718 ps |
| CPU time | 2.66 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:06 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-dbbce46e-6b52-4cc6-9265-560e5a299db6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=268798569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.268798569 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.814308528 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 12654771 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:05 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-16f55c8d-3835-41b8-b2f7-fec38e35d2c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=814308528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.814308528 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.681846098 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5194245717 ps |
| CPU time | 6.72 seconds |
| Started | Mar 05 01:15:58 PM PST 24 |
| Finished | Mar 05 01:16:05 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-44875b12-bae7-4109-ba45-7daa439315f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=681846098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.681846098 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3009832370 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 920780031 ps |
| CPU time | 7.38 seconds |
| Started | Mar 05 01:15:58 PM PST 24 |
| Finished | Mar 05 01:16:06 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-b087364e-4998-4fc9-be3c-3ced5372da60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3009832370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3009832370 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.936453483 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 10541993 ps |
| CPU time | 1.24 seconds |
| Started | Mar 05 01:15:57 PM PST 24 |
| Finished | Mar 05 01:15:58 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-a8d08109-deac-4cfa-b1e0-c7f2b5cf0e83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936453483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.936453483 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.292168537 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 489179450 ps |
| CPU time | 60.34 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:17:02 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-22ab5f81-c35b-4df9-ba4a-2b6096e3e6fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292168537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.292168537 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3917705798 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1304305485 ps |
| CPU time | 22.28 seconds |
| Started | Mar 05 01:16:05 PM PST 24 |
| Finished | Mar 05 01:16:28 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-a310fe85-f086-4d5f-9bed-6bffdb9d7375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3917705798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3917705798 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3034285827 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 253111610 ps |
| CPU time | 24.99 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:30 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-c7b9aec6-a288-42ae-ac74-532bf0d3b094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034285827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3034285827 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3965446706 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 37657918 ps |
| CPU time | 2.91 seconds |
| Started | Mar 05 01:16:01 PM PST 24 |
| Finished | Mar 05 01:16:04 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-53eeaf9c-16f4-4a7e-a692-ccca58b95e95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3965446706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3965446706 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3462289209 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 495553023 ps |
| CPU time | 4.64 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-954f1463-c4a9-4acc-b59e-3d1f8df39a30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462289209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3462289209 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4201511930 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 9686230769 ps |
| CPU time | 34.11 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:39 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-90f7f7bb-d9d2-484b-8961-2ecf13f6a6ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4201511930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.4201511930 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3661225044 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2950333830 ps |
| CPU time | 7.23 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-f1312bde-f1d2-4d14-ac9f-5b315644ac43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3661225044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3661225044 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.4245678951 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 107990339 ps |
| CPU time | 4.93 seconds |
| Started | Mar 05 01:16:05 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-dc379f23-eaf9-4530-bafc-1f74941ac4df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4245678951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4245678951 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.132655551 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 97011142 ps |
| CPU time | 7.92 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:11 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-25a0b04f-720e-4f13-863b-586928560667 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=132655551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.132655551 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1336794247 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 65234554400 ps |
| CPU time | 82.8 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:17:26 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-0ef763c4-4d80-4a8c-aff6-d704100f039b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336794247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1336794247 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1140897531 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 17920927409 ps |
| CPU time | 123.26 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-19678898-c64e-4457-9a86-410118465304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1140897531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1140897531 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2661909443 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 264007342 ps |
| CPU time | 6.13 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:11 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-28537a36-9331-4ada-95b1-fb70c8abcc12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661909443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2661909443 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.2817290490 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 209799107 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:05 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-7dcf01d0-6206-42c5-9661-ab1f8270876d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817290490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2817290490 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.614960584 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 46325569 ps |
| CPU time | 1.35 seconds |
| Started | Mar 05 01:16:02 PM PST 24 |
| Finished | Mar 05 01:16:04 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-02d71801-b5ff-40c5-8c71-565baa62ecf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=614960584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.614960584 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3335538849 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6597653060 ps |
| CPU time | 7.96 seconds |
| Started | Mar 05 01:16:01 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-2359323d-3feb-49cc-aceb-a38bec666de6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335538849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3335538849 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.842252420 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1321346777 ps |
| CPU time | 10.27 seconds |
| Started | Mar 05 01:16:00 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d433a5f0-0ed6-44f3-ac18-09a54e6933ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=842252420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.842252420 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3769534010 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 9044561 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:06 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-ca02ebb1-efa6-49f6-95b9-24addde4778f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769534010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3769534010 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.24559478 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 215083027 ps |
| CPU time | 22.2 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:25 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-dc878fed-60be-4936-9ba8-41448c78cd2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24559478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.24559478 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3066957507 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 115557643 ps |
| CPU time | 9.63 seconds |
| Started | Mar 05 01:16:05 PM PST 24 |
| Finished | Mar 05 01:16:15 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-cd12a0b4-54be-4602-b11a-fb47857dba05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3066957507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3066957507 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1980922875 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 330412331 ps |
| CPU time | 33.88 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:37 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-ff403de7-d6f8-45ce-a63a-73bb0a22b39d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1980922875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1980922875 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1002515603 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1595727095 ps |
| CPU time | 108.75 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 204968 kb |
| Host | smart-bde9ed3c-b869-45cf-9142-c97c596af705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002515603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1002515603 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2366922000 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 42914030 ps |
| CPU time | 5.64 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-9eacee0f-aecf-4251-b3a5-f9adf3072372 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2366922000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2366922000 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.4202376532 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1876102935 ps |
| CPU time | 10.8 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:15 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-d5c197b8-1504-4165-856c-8074a268ec9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4202376532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4202376532 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3998932072 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 37346018667 ps |
| CPU time | 252.74 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:20:30 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-24e7f95c-d594-41eb-b1bf-c4e97a5a6cd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3998932072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3998932072 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3397560097 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 253983224 ps |
| CPU time | 4.61 seconds |
| Started | Mar 05 01:16:05 PM PST 24 |
| Finished | Mar 05 01:16:10 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-e60c96c0-619f-43a7-a2bc-b9893913f8fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397560097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3397560097 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.2108982852 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 467315769 ps |
| CPU time | 7.78 seconds |
| Started | Mar 05 01:16:00 PM PST 24 |
| Finished | Mar 05 01:16:08 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-12d7daad-3342-4dde-aada-191933b6d30c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2108982852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2108982852 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.2854724690 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 76608888 ps |
| CPU time | 7.01 seconds |
| Started | Mar 05 01:16:05 PM PST 24 |
| Finished | Mar 05 01:16:12 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-f6812f5c-694f-4d56-a1de-aacf7d85b47c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854724690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2854724690 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2263010380 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 43959582923 ps |
| CPU time | 51.5 seconds |
| Started | Mar 05 01:16:01 PM PST 24 |
| Finished | Mar 05 01:16:53 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-929d7e56-2076-4bc3-94c3-ec2d1b0a22c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263010380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2263010380 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1942235639 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 38319535674 ps |
| CPU time | 165.45 seconds |
| Started | Mar 05 01:16:03 PM PST 24 |
| Finished | Mar 05 01:18:49 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-6209ee08-280b-49c6-aace-b8f0b55dca21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1942235639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1942235639 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.261484408 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 49061163 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:16:20 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-c9b42aa0-5b4a-4d26-b2fa-b4f4e0223216 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261484408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.261484408 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2795774919 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 600973791 ps |
| CPU time | 7.77 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:12 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-c323487f-8be7-43a7-a7f3-aa7e1507b460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2795774919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2795774919 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.4270948336 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 10183327 ps |
| CPU time | 1.29 seconds |
| Started | Mar 05 01:16:01 PM PST 24 |
| Finished | Mar 05 01:16:02 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-96adcb12-4d25-4413-bddf-5d1ccec1d723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4270948336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4270948336 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3436752208 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 9695143363 ps |
| CPU time | 11.54 seconds |
| Started | Mar 05 01:16:04 PM PST 24 |
| Finished | Mar 05 01:16:16 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-64a48667-619f-4845-bc1c-81a64c6d6d76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436752208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3436752208 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3795860729 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2330303041 ps |
| CPU time | 8.12 seconds |
| Started | Mar 05 01:16:07 PM PST 24 |
| Finished | Mar 05 01:16:16 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-ce53286f-ba15-4da8-9ff9-2ab0f4cb0b8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3795860729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3795860729 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.484718195 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 10654383 ps |
| CPU time | 1.27 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:16:18 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-e7e3aee9-670d-4c2c-9ad5-144f49480fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484718195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.484718195 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.822641927 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6568599366 ps |
| CPU time | 54.44 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:17:11 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-f3db7b7c-a96d-4c67-8ee0-181c33c57295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=822641927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.822641927 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2702893559 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 16477383516 ps |
| CPU time | 83.57 seconds |
| Started | Mar 05 01:16:07 PM PST 24 |
| Finished | Mar 05 01:17:31 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-0c0581c6-618c-48a2-9342-72da5c163234 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702893559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2702893559 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3361003758 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 790998467 ps |
| CPU time | 107.02 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:18:03 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-f26aef85-2df3-4ad6-907c-50c0ccf9700d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3361003758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3361003758 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4051573375 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5429708654 ps |
| CPU time | 47.52 seconds |
| Started | Mar 05 01:16:10 PM PST 24 |
| Finished | Mar 05 01:16:58 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-ac56668c-a68e-4831-addd-19e8d623d502 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4051573375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.4051573375 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3982735776 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 40100264 ps |
| CPU time | 1.45 seconds |
| Started | Mar 05 01:16:16 PM PST 24 |
| Finished | Mar 05 01:16:18 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-661bd983-1624-4e86-b233-3fb58aa950ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3982735776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3982735776 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1374315790 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 101035522 ps |
| CPU time | 2.71 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-dc1b9376-e14d-4f0e-975e-b73e61b26758 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1374315790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1374315790 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3914739492 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 64000601526 ps |
| CPU time | 123.55 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:14:43 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-46044c9d-ec86-4c7c-9df9-aea35786c5ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3914739492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3914739492 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1853568601 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 22140149 ps |
| CPU time | 2.14 seconds |
| Started | Mar 05 01:12:38 PM PST 24 |
| Finished | Mar 05 01:12:40 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-3803efbb-ed88-44f6-a4f6-7c9405bf86eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853568601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1853568601 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.838178777 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1480111411 ps |
| CPU time | 16.6 seconds |
| Started | Mar 05 01:12:37 PM PST 24 |
| Finished | Mar 05 01:12:53 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-7cd02fc4-d18b-4b58-9a90-277053e8eb2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=838178777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.838178777 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.1594290287 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 57450863 ps |
| CPU time | 6.13 seconds |
| Started | Mar 05 01:12:28 PM PST 24 |
| Finished | Mar 05 01:12:34 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-cfe0864a-5183-41b9-80d4-86c73324648b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1594290287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1594290287 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1210636612 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 33589574961 ps |
| CPU time | 81.34 seconds |
| Started | Mar 05 01:12:36 PM PST 24 |
| Finished | Mar 05 01:13:57 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-7954dabc-4481-42e0-b2db-fcc03b30d5fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210636612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1210636612 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3792423848 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 3018810971 ps |
| CPU time | 12.59 seconds |
| Started | Mar 05 01:12:36 PM PST 24 |
| Finished | Mar 05 01:12:49 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-e77ec626-79c3-4460-990e-01aa17c3a25f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3792423848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3792423848 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3229331681 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 85029918 ps |
| CPU time | 6.37 seconds |
| Started | Mar 05 01:12:36 PM PST 24 |
| Finished | Mar 05 01:12:43 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-152d57ee-639f-4d29-9613-13c1aeeb818a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229331681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3229331681 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.3149411692 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 27911204 ps |
| CPU time | 2.8 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-3d13577d-ccbe-4372-b7b7-dedd60077287 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3149411692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3149411692 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2685742573 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 60264099 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:12:31 PM PST 24 |
| Finished | Mar 05 01:12:33 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-a8b547ca-2ed0-4989-9899-e4b61f43884f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2685742573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2685742573 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.806345046 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 9537017823 ps |
| CPU time | 8.69 seconds |
| Started | Mar 05 01:12:31 PM PST 24 |
| Finished | Mar 05 01:12:40 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-1580b8c5-518b-40f1-b047-f18c5c2a9ca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=806345046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.806345046 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2433432337 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 782355480 ps |
| CPU time | 6.67 seconds |
| Started | Mar 05 01:12:37 PM PST 24 |
| Finished | Mar 05 01:12:43 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-85e6913c-ed5e-4e3e-80cd-8432e2bc3384 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2433432337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2433432337 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2961045861 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 23933131 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:12:29 PM PST 24 |
| Finished | Mar 05 01:12:30 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-52391238-5074-4986-9a41-2515f0e0b3d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961045861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2961045861 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2797327239 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2087599281 ps |
| CPU time | 49.66 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:13:29 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-81ff205d-e2a7-4a6d-adaa-9312ffce2699 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2797327239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2797327239 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3189870297 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3857067060 ps |
| CPU time | 32.62 seconds |
| Started | Mar 05 01:12:43 PM PST 24 |
| Finished | Mar 05 01:13:16 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-6f06f735-7c06-42a0-aa10-046e933f7610 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3189870297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3189870297 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4276918158 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5066896686 ps |
| CPU time | 86.19 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:14:06 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-99c9c5c7-3253-4d45-b729-822c7c5b116a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4276918158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.4276918158 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3606539387 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 74496919 ps |
| CPU time | 6 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:45 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-74d6aa08-2202-4a33-bc37-515e0002d259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3606539387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3606539387 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2250340432 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 724845274 ps |
| CPU time | 11.46 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:12:51 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-4e95aca7-2a9c-4532-8281-40f0c4a2907b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250340432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2250340432 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1940314673 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 31749124766 ps |
| CPU time | 197.9 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:15:58 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-8f3ed591-0641-4346-bc07-4f296e8559f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1940314673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1940314673 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1411418699 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 236496310 ps |
| CPU time | 5.56 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:45 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-a6986e6e-806b-4926-b318-141a73faa8d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1411418699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1411418699 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.2388814484 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2084625233 ps |
| CPU time | 14.18 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-40427357-ede6-4486-89dd-fda688e0c141 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388814484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2388814484 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1854651106 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1261233999 ps |
| CPU time | 13.75 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 202344 kb |
| Host | smart-0bb0530e-bc33-42d1-b74e-7a03049254be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854651106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1854651106 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2474995771 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 29200953769 ps |
| CPU time | 76.18 seconds |
| Started | Mar 05 01:12:43 PM PST 24 |
| Finished | Mar 05 01:14:00 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-caf2a357-b489-47e3-a931-db580ff6cd47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474995771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2474995771 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2092738089 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 18672300040 ps |
| CPU time | 135.19 seconds |
| Started | Mar 05 01:12:38 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-64677fad-4c8f-44d9-9433-cbae4f99f938 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2092738089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2092738089 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1288594389 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 36925439 ps |
| CPU time | 5.37 seconds |
| Started | Mar 05 01:12:43 PM PST 24 |
| Finished | Mar 05 01:12:49 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-d92a2faa-ce57-4aa8-b90f-4505c70cec09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288594389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1288594389 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3496987793 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1243381420 ps |
| CPU time | 14.54 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-ab0d9abf-bdec-4793-9428-c3ff2e99e6fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3496987793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3496987793 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3047772117 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 55907937 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:12:41 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-851a9b48-cb44-493c-8918-b02403916002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047772117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3047772117 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1294167301 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2335405550 ps |
| CPU time | 10.23 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:49 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-48507fa5-98b7-4ee4-92d3-15b8cf2325b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294167301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1294167301 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3160507830 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7810117521 ps |
| CPU time | 10.95 seconds |
| Started | Mar 05 01:12:40 PM PST 24 |
| Finished | Mar 05 01:12:51 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-02ef1eff-4c36-4559-b11e-ed4e837b18b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3160507830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3160507830 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3047640159 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 8693896 ps |
| CPU time | 1.25 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:40 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-fb3aa1ed-63f8-46e6-a80f-654e55c9e64b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047640159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3047640159 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.837357839 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 201678661 ps |
| CPU time | 16.13 seconds |
| Started | Mar 05 01:12:52 PM PST 24 |
| Finished | Mar 05 01:13:09 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-ab95b724-9f2a-4057-9c23-96393a509a94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837357839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.837357839 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2594662783 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 12239004968 ps |
| CPU time | 96.23 seconds |
| Started | Mar 05 01:12:51 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-7f4f5745-2a8b-4d70-b656-99c740aa48bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2594662783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2594662783 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1427702473 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 6231469730 ps |
| CPU time | 121.5 seconds |
| Started | Mar 05 01:12:52 PM PST 24 |
| Finished | Mar 05 01:14:54 PM PST 24 |
| Peak memory | 205628 kb |
| Host | smart-e2a400d5-69ec-45a1-ab30-e74b1d8a38c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427702473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1427702473 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2869395886 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 261981001 ps |
| CPU time | 29.26 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:13:19 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-ec21bb08-fade-4946-a354-bc528302c0ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2869395886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2869395886 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3695424659 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 407293677 ps |
| CPU time | 3.76 seconds |
| Started | Mar 05 01:12:38 PM PST 24 |
| Finished | Mar 05 01:12:41 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-2c4478e5-ba6e-46bc-9c3d-0cc222b4f951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3695424659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3695424659 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3127053700 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 47547728 ps |
| CPU time | 5.46 seconds |
| Started | Mar 05 01:12:49 PM PST 24 |
| Finished | Mar 05 01:12:55 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-04ffb974-2ecf-41fe-809a-713f19c13421 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127053700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3127053700 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3700214309 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 18468335921 ps |
| CPU time | 91.04 seconds |
| Started | Mar 05 01:12:52 PM PST 24 |
| Finished | Mar 05 01:14:25 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-238320f6-a949-468b-8f07-92119d8447ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3700214309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3700214309 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2803313200 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1644357317 ps |
| CPU time | 6.51 seconds |
| Started | Mar 05 01:12:53 PM PST 24 |
| Finished | Mar 05 01:13:01 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-2607556e-288e-48db-92b4-0b5497dd6751 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2803313200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2803313200 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.4110351710 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 667420702 ps |
| CPU time | 2.9 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-4c72c49c-bd7e-4ca0-a58e-915412a85e21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4110351710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4110351710 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.3531844792 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 503501509 ps |
| CPU time | 11.95 seconds |
| Started | Mar 05 01:12:54 PM PST 24 |
| Finished | Mar 05 01:13:07 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-e88d7653-3366-457b-9a8e-f5e7ba7e2a8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531844792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3531844792 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.4293395377 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 44339489735 ps |
| CPU time | 31.72 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:13:23 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-e6ac55fa-2450-4792-9b28-1deb6fc8cd62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293395377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4293395377 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.322449797 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 13953510726 ps |
| CPU time | 97.67 seconds |
| Started | Mar 05 01:12:51 PM PST 24 |
| Finished | Mar 05 01:14:29 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-b2021569-541c-44b2-8607-6cb4d4b69792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=322449797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.322449797 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.428233239 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 185664546 ps |
| CPU time | 7.5 seconds |
| Started | Mar 05 01:12:51 PM PST 24 |
| Finished | Mar 05 01:12:59 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-30db3471-35b6-46d2-bd93-1e07d289c931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428233239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.428233239 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.444235387 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 232867737 ps |
| CPU time | 5.47 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:12:56 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-aca702b2-98c9-4228-a9bd-1819aed1f3db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=444235387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.444235387 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3352479542 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 12953935 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:12:51 PM PST 24 |
| Finished | Mar 05 01:12:53 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-062824d1-a71b-4e90-bd3d-66d56a93d048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3352479542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3352479542 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2385074863 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3217384336 ps |
| CPU time | 10.86 seconds |
| Started | Mar 05 01:12:49 PM PST 24 |
| Finished | Mar 05 01:13:00 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-d86c0552-86a1-4ab6-b651-df6cf1a9bccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385074863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2385074863 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2195591107 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5555217031 ps |
| CPU time | 7.09 seconds |
| Started | Mar 05 01:12:52 PM PST 24 |
| Finished | Mar 05 01:13:00 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-aa6acefc-22f9-4424-86f1-d93570cd75ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2195591107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2195591107 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1834065958 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 8000957 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:12:52 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-1a8869ed-acf3-4efe-86e1-e43de74a9670 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834065958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1834065958 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3096305989 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 120626604 ps |
| CPU time | 5.41 seconds |
| Started | Mar 05 01:12:53 PM PST 24 |
| Finished | Mar 05 01:12:59 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-5d580b84-8d43-4e23-a620-3bb086c1611e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3096305989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3096305989 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2363648210 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1056735318 ps |
| CPU time | 15.47 seconds |
| Started | Mar 05 01:12:51 PM PST 24 |
| Finished | Mar 05 01:13:08 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-6c4d1e4e-08c6-48bb-8bff-20d732176b3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2363648210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2363648210 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1910752429 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 583679304 ps |
| CPU time | 96.82 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 206756 kb |
| Host | smart-ee5867fa-89dd-4a69-9c7d-157a398e72d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1910752429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1910752429 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4293964785 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 954953768 ps |
| CPU time | 96.86 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:14:28 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-ecf70750-f072-4f44-9c90-0e59d927ce4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293964785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.4293964785 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.756423925 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 39485341 ps |
| CPU time | 4.78 seconds |
| Started | Mar 05 01:12:50 PM PST 24 |
| Finished | Mar 05 01:12:55 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-61900b36-1c19-4090-90e0-2473c9e44442 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=756423925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.756423925 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.995543210 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 736932398 ps |
| CPU time | 5.46 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:07 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-edffbab1-042f-4f7f-aeec-ef5cc333d644 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=995543210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.995543210 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.737955543 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 193924059565 ps |
| CPU time | 296.66 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:17:57 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-f045aa0c-7749-43b7-9316-b6e5c473cafa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=737955543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.737955543 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2455549335 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 334170011 ps |
| CPU time | 6.34 seconds |
| Started | Mar 05 01:12:59 PM PST 24 |
| Finished | Mar 05 01:13:06 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-d94e27df-cbaf-4cb7-8143-11aacd61421e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455549335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2455549335 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.733266852 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 125932963 ps |
| CPU time | 2.53 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-22f8d119-beb3-4622-92c5-15d79355aedb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733266852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.733266852 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.84438475 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 376353021 ps |
| CPU time | 2.76 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:15 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-eb28de3e-2f22-4d44-9aec-f3790fe584c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=84438475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.84438475 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1496932508 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 74791935622 ps |
| CPU time | 69.57 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:14:10 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-dd390352-397c-48f8-aeb8-ddbd5451a8af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496932508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1496932508 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2758925927 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10564806952 ps |
| CPU time | 82.45 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:14:24 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-dd856ca4-bc75-468b-a6f7-615f1e728322 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2758925927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2758925927 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2987709554 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 50759882 ps |
| CPU time | 7.17 seconds |
| Started | Mar 05 01:13:03 PM PST 24 |
| Finished | Mar 05 01:13:11 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-ea2c6771-1a6e-49c0-9389-e5992bc16ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987709554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2987709554 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2304316185 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 137102146 ps |
| CPU time | 2.23 seconds |
| Started | Mar 05 01:13:03 PM PST 24 |
| Finished | Mar 05 01:13:06 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-a53b23d6-4c3c-4496-a2d9-a2150a3f5a12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304316185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2304316185 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1338590750 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 34986905 ps |
| CPU time | 1.39 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-0ff2ed74-d304-4fda-a2e9-325a8c80458b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1338590750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1338590750 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2318773061 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3494920502 ps |
| CPU time | 12.15 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:12 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-d138ef12-9147-4800-8a83-6f15483787cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318773061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2318773061 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2431115942 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1510167019 ps |
| CPU time | 4.84 seconds |
| Started | Mar 05 01:13:03 PM PST 24 |
| Finished | Mar 05 01:13:09 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-5d050c7e-69ab-44d9-bb05-79292af0cf50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2431115942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2431115942 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.291109685 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 10586893 ps |
| CPU time | 1.23 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-b40f4f48-217c-403d-93a0-02e5cc9df74a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291109685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.291109685 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4237165458 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 351958988 ps |
| CPU time | 26.12 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:27 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-5f9280c5-13cc-4b08-a42c-cebdf7129eab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4237165458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4237165458 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4007791055 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6501834131 ps |
| CPU time | 135.97 seconds |
| Started | Mar 05 01:13:03 PM PST 24 |
| Finished | Mar 05 01:15:20 PM PST 24 |
| Peak memory | 206340 kb |
| Host | smart-0a1b0953-f2f9-47d1-a603-c66109fde7af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4007791055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.4007791055 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2769075804 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 141514884 ps |
| CPU time | 2.03 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-00ee3633-d160-4c58-8270-178c7e7733f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769075804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2769075804 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.843427088 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 32081439 ps |
| CPU time | 6.59 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:13:09 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-4a67101a-9141-4747-a703-0671acc7b949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=843427088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.843427088 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2591880387 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 53537391531 ps |
| CPU time | 121.91 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:15:03 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-056eda61-38bc-4701-9702-dfc5f9e99613 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2591880387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2591880387 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2357765408 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 62690696 ps |
| CPU time | 1.71 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:02 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-fbf4c9ea-efb3-4854-b9a4-50690639c444 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357765408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2357765408 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.300980180 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 515958900 ps |
| CPU time | 10.06 seconds |
| Started | Mar 05 01:13:12 PM PST 24 |
| Finished | Mar 05 01:13:22 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-39545b97-f12c-4044-bc18-1e7d3a7e08b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=300980180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.300980180 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3507015493 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 339716155 ps |
| CPU time | 6.34 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:07 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-35b8f425-13f3-48ac-8d26-c4288ac2f1df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507015493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3507015493 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3937500562 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 79453351459 ps |
| CPU time | 152.34 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:15:33 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-c49f0469-a774-4eae-8591-0a472ec5ddd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937500562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3937500562 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.387135754 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 16400928638 ps |
| CPU time | 101.32 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:14:42 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-39da9ae0-e508-4637-a910-f339f6ff1b24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=387135754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.387135754 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4070237092 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 11049654 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:02 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-bda8cd3d-09bd-413b-9db5-dd0d564e653a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070237092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4070237092 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3535852359 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 36102390 ps |
| CPU time | 3.69 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:06 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-6f62230f-5d78-47f3-9e03-82154e7b911b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3535852359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3535852359 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3559883929 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 69775209 ps |
| CPU time | 1.42 seconds |
| Started | Mar 05 01:13:01 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-6c1fdd0c-e359-4d55-981f-7afce958148d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559883929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3559883929 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1346901804 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 12265325848 ps |
| CPU time | 10.7 seconds |
| Started | Mar 05 01:13:03 PM PST 24 |
| Finished | Mar 05 01:13:14 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-faa73219-d4fe-4d3d-885f-20bcc838d81d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346901804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1346901804 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2240225519 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 9728200706 ps |
| CPU time | 10.26 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:11 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-e2b6798e-7d87-4b0c-9855-822960d1558a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2240225519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2240225519 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2092126577 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 9571959 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:01 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-b518e464-0837-4af3-8140-85cd39b54651 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092126577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2092126577 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3186082399 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 356400774 ps |
| CPU time | 39.22 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:40 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-f1c6d659-a8b8-418b-ac8a-0af2bd8335c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186082399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3186082399 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.363055263 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 10097087809 ps |
| CPU time | 40.78 seconds |
| Started | Mar 05 01:13:02 PM PST 24 |
| Finished | Mar 05 01:13:43 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-ddae3d20-51d8-4e67-80de-e7fefc115b7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=363055263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.363055263 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.219082948 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 734226256 ps |
| CPU time | 84.57 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:14:26 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-0ef109f5-8e09-4f93-8d30-4194d9d00706 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=219082948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.219082948 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.688680077 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 181169152 ps |
| CPU time | 29.43 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:30 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-bd6fad1f-9363-4632-a382-eea88156fe76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=688680077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.688680077 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2720631149 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 501943890 ps |
| CPU time | 3.21 seconds |
| Started | Mar 05 01:13:00 PM PST 24 |
| Finished | Mar 05 01:13:04 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-8dfdcd85-056a-4d5d-8611-53e98d8c8b00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2720631149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2720631149 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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