Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	462	1			T9	6		T20	6		T24	5
all_values[1]	429	1			T9	2		T20	6		T24	6
all_values[2]	492	1			T9	3		T20	7		T24	1
all_values[3]	466	1			T9	2		T20	3		T24	11
all_values[4]	448	1			T9	3		T20	5		T24	6
all_values[5]	488	1			T9	4		T20	4		T24	6
all_values[6]	481	1			T9	3		T20	7		T24	4
all_values[7]	474	1			T9	7		T20	6		T24	3
all_values[8]	469	1			T9	3		T20	7		T24	4
all_values[9]	448	1			T20	5		T24	5		T27	2
all_values[10]	473	1			T9	14		T20	5		T24	5
all_values[11]	484	1			T9	5		T20	5		T24	3
all_values[12]	464	1			T9	3		T20	5		T24	4
all_values[13]	454	1			T9	6		T20	8		T24	11
all_values[14]	488	1			T9	6		T20	4		T24	6
all_values[15]	462	1			T9	9		T20	4		T24	5
all_values[16]	457	1			T9	5		T20	1		T24	2
all_values[17]	455	1			T9	3		T20	3		T24	2
all_values[18]	465	1			T9	5		T20	2		T24	1
all_values[19]	462	1			T9	6		T20	6		T24	5
all_values[20]	511	1			T9	4		T20	6		T24	8
all_values[21]	482	1			T9	6		T20	5		T24	10
all_values[22]	469	1			T9	5		T20	3		T24	6
all_values[23]	469	1			T9	3		T20	4		T24	3
all_values[24]	487	1			T9	4		T20	5		T24	3
all_values[25]	503	1			T9	5		T20	7		T24	5
all_values[26]	480	1			T9	4		T20	4		T24	7