Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	496	1			T10	4		T11	1		T31	2
all_values[1]	484	1			T10	3		T11	1		T31	1
all_values[2]	472	1			T3	1		T10	6		T11	1
all_values[3]	471	1			T3	2		T10	2		T34	3
all_values[4]	500	1			T10	4		T11	2		T34	2
all_values[5]	473	1			T10	2		T11	1		T31	1
all_values[6]	486	1			T3	2		T10	2		T11	1
all_values[7]	479	1			T10	7		T11	2		T31	1
all_values[8]	523	1			T10	3		T11	1		T31	1
all_values[9]	460	1			T3	1		T10	3		T11	1
all_values[10]	474	1			T10	8		T34	1		T54	4
all_values[11]	490	1			T10	2		T11	1		T34	1
all_values[12]	476	1			T10	5		T11	1		T54	3
all_values[13]	479	1			T3	2		T11	1		T19	2
all_values[14]	481	1			T10	2		T31	1		T83	1
all_values[15]	480	1			T3	1		T10	1		T11	1
all_values[16]	497	1			T3	1		T10	5		T31	1
all_values[17]	457	1			T3	1		T10	3		T31	2
all_values[18]	463	1			T3	1		T10	3		T19	1
all_values[19]	478	1			T10	5		T31	1		T84	2
all_values[20]	483	1			T3	1		T10	4		T11	1
all_values[21]	449	1			T3	1		T10	3		T11	3
all_values[22]	496	1			T3	1		T10	2		T31	4
all_values[23]	484	1			T3	2		T10	6		T54	1
all_values[24]	473	1			T10	4		T31	2		T34	1
all_values[25]	487	1			T3	2		T31	1		T54	5
all_values[26]	466	1			T10	2		T31	1		T19	1