Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 100.00 95.71 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T759 /workspace/coverage/xbar_build_mode/25.xbar_same_source.1448560153 Mar 10 02:09:40 PM PDT 24 Mar 10 02:09:48 PM PDT 24 823124791 ps
T760 /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.206976111 Mar 10 02:07:57 PM PDT 24 Mar 10 02:08:03 PM PDT 24 3077283947 ps
T761 /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.604691501 Mar 10 02:09:08 PM PDT 24 Mar 10 02:11:05 PM PDT 24 24567959185 ps
T762 /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3544573847 Mar 10 02:10:02 PM PDT 24 Mar 10 02:12:53 PM PDT 24 43915648423 ps
T763 /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3943043628 Mar 10 02:08:19 PM PDT 24 Mar 10 02:08:20 PM PDT 24 19773940 ps
T764 /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2350853371 Mar 10 02:09:11 PM PDT 24 Mar 10 02:10:50 PM PDT 24 8182533109 ps
T765 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3031993269 Mar 10 02:09:08 PM PDT 24 Mar 10 02:09:27 PM PDT 24 9406454466 ps
T766 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1161803447 Mar 10 02:09:19 PM PDT 24 Mar 10 02:10:53 PM PDT 24 46897651978 ps
T767 /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.675483077 Mar 10 02:09:22 PM PDT 24 Mar 10 02:09:24 PM PDT 24 20392276 ps
T768 /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3218243064 Mar 10 02:09:15 PM PDT 24 Mar 10 02:09:16 PM PDT 24 140546225 ps
T769 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3689867191 Mar 10 02:07:45 PM PDT 24 Mar 10 02:12:47 PM PDT 24 76529506976 ps
T770 /workspace/coverage/xbar_build_mode/24.xbar_random.2476491343 Mar 10 02:09:24 PM PDT 24 Mar 10 02:09:34 PM PDT 24 124455000 ps
T771 /workspace/coverage/xbar_build_mode/14.xbar_smoke.3523908064 Mar 10 02:08:24 PM PDT 24 Mar 10 02:08:26 PM PDT 24 52635720 ps
T772 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1317768577 Mar 10 02:10:38 PM PDT 24 Mar 10 02:11:15 PM PDT 24 459493693 ps
T773 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1429272947 Mar 10 02:06:44 PM PDT 24 Mar 10 02:07:24 PM PDT 24 252095857 ps
T774 /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1362510719 Mar 10 02:10:37 PM PDT 24 Mar 10 02:10:40 PM PDT 24 56524942 ps
T775 /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1355862810 Mar 10 02:10:54 PM PDT 24 Mar 10 02:13:49 PM PDT 24 151647908044 ps
T776 /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1769710901 Mar 10 02:06:41 PM PDT 24 Mar 10 02:08:31 PM PDT 24 38292700733 ps
T777 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3645970305 Mar 10 02:09:33 PM PDT 24 Mar 10 02:09:45 PM PDT 24 874634335 ps
T778 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1935260047 Mar 10 02:08:08 PM PDT 24 Mar 10 02:09:49 PM PDT 24 52672555686 ps
T779 /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1418429343 Mar 10 02:07:42 PM PDT 24 Mar 10 02:07:51 PM PDT 24 2568394611 ps
T780 /workspace/coverage/xbar_build_mode/37.xbar_same_source.1272539575 Mar 10 02:10:34 PM PDT 24 Mar 10 02:10:41 PM PDT 24 53523453 ps
T108 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.51078298 Mar 10 02:09:08 PM PDT 24 Mar 10 02:14:13 PM PDT 24 93853631030 ps
T781 /workspace/coverage/xbar_build_mode/39.xbar_same_source.26752580 Mar 10 02:10:40 PM PDT 24 Mar 10 02:10:45 PM PDT 24 249246716 ps
T782 /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2367294132 Mar 10 02:08:26 PM PDT 24 Mar 10 02:08:28 PM PDT 24 17960026 ps
T783 /workspace/coverage/xbar_build_mode/13.xbar_same_source.1750362838 Mar 10 02:08:23 PM PDT 24 Mar 10 02:08:26 PM PDT 24 30569646 ps
T784 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.91426273 Mar 10 02:07:16 PM PDT 24 Mar 10 02:07:33 PM PDT 24 146069004 ps
T785 /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2154102890 Mar 10 02:09:38 PM PDT 24 Mar 10 02:10:55 PM PDT 24 34263403391 ps
T786 /workspace/coverage/xbar_build_mode/31.xbar_smoke.939965266 Mar 10 02:10:01 PM PDT 24 Mar 10 02:10:03 PM PDT 24 75317301 ps
T787 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.360693736 Mar 10 02:07:11 PM PDT 24 Mar 10 02:08:53 PM PDT 24 7481961622 ps
T788 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2263738003 Mar 10 02:10:56 PM PDT 24 Mar 10 02:11:12 PM PDT 24 915699409 ps
T789 /workspace/coverage/xbar_build_mode/6.xbar_same_source.510110607 Mar 10 02:07:38 PM PDT 24 Mar 10 02:07:43 PM PDT 24 347631046 ps
T790 /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2765591659 Mar 10 02:09:07 PM PDT 24 Mar 10 02:09:19 PM PDT 24 12055759713 ps
T791 /workspace/coverage/xbar_build_mode/44.xbar_random.4224572019 Mar 10 02:10:59 PM PDT 24 Mar 10 02:11:11 PM PDT 24 984460412 ps
T792 /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.585394552 Mar 10 02:10:07 PM PDT 24 Mar 10 02:10:13 PM PDT 24 834063656 ps
T793 /workspace/coverage/xbar_build_mode/8.xbar_error_random.707268639 Mar 10 02:07:52 PM PDT 24 Mar 10 02:08:02 PM PDT 24 116336402 ps
T794 /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.120696087 Mar 10 02:11:24 PM PDT 24 Mar 10 02:11:30 PM PDT 24 935771621 ps
T795 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2739285596 Mar 10 02:08:55 PM PDT 24 Mar 10 02:09:11 PM PDT 24 242120304 ps
T796 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1865979144 Mar 10 02:07:15 PM PDT 24 Mar 10 02:10:12 PM PDT 24 43366961386 ps
T797 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1618703201 Mar 10 02:10:08 PM PDT 24 Mar 10 02:10:19 PM PDT 24 1317482147 ps
T798 /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2315182647 Mar 10 02:11:00 PM PDT 24 Mar 10 02:11:01 PM PDT 24 9598273 ps
T799 /workspace/coverage/xbar_build_mode/2.xbar_same_source.3408961118 Mar 10 02:07:04 PM PDT 24 Mar 10 02:07:10 PM PDT 24 164301331 ps
T800 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3968895748 Mar 10 02:10:24 PM PDT 24 Mar 10 02:12:51 PM PDT 24 6693479142 ps
T801 /workspace/coverage/xbar_build_mode/18.xbar_smoke.3302057945 Mar 10 02:08:56 PM PDT 24 Mar 10 02:08:57 PM PDT 24 48903949 ps
T802 /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3019364361 Mar 10 02:09:40 PM PDT 24 Mar 10 02:12:01 PM PDT 24 36679657695 ps
T803 /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1662744793 Mar 10 02:08:08 PM PDT 24 Mar 10 02:08:14 PM PDT 24 505173766 ps
T804 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2960725121 Mar 10 02:08:24 PM PDT 24 Mar 10 02:08:30 PM PDT 24 41409811 ps
T805 /workspace/coverage/xbar_build_mode/46.xbar_same_source.2134645103 Mar 10 02:11:11 PM PDT 24 Mar 10 02:11:14 PM PDT 24 1489416354 ps
T806 /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1942737389 Mar 10 02:10:00 PM PDT 24 Mar 10 02:10:31 PM PDT 24 304556439 ps
T807 /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3702494287 Mar 10 02:08:51 PM PDT 24 Mar 10 02:08:57 PM PDT 24 147800526 ps
T808 /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2405209802 Mar 10 02:11:26 PM PDT 24 Mar 10 02:11:28 PM PDT 24 10797153 ps
T809 /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3204933645 Mar 10 02:06:49 PM PDT 24 Mar 10 02:06:57 PM PDT 24 1730775985 ps
T810 /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2464459404 Mar 10 02:08:34 PM PDT 24 Mar 10 02:08:36 PM PDT 24 8085026 ps
T811 /workspace/coverage/xbar_build_mode/22.xbar_stress_all.218208874 Mar 10 02:09:21 PM PDT 24 Mar 10 02:09:43 PM PDT 24 4906100719 ps
T812 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1916933514 Mar 10 02:10:44 PM PDT 24 Mar 10 02:10:53 PM PDT 24 116445153 ps
T813 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.696222722 Mar 10 02:08:39 PM PDT 24 Mar 10 02:08:41 PM PDT 24 82366533 ps
T814 /workspace/coverage/xbar_build_mode/3.xbar_same_source.790092331 Mar 10 02:07:14 PM PDT 24 Mar 10 02:07:17 PM PDT 24 25525805 ps
T161 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3689124638 Mar 10 02:09:40 PM PDT 24 Mar 10 02:12:19 PM PDT 24 7934918246 ps
T815 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3211717426 Mar 10 02:09:38 PM PDT 24 Mar 10 02:09:45 PM PDT 24 57582308 ps
T816 /workspace/coverage/xbar_build_mode/43.xbar_error_random.1882308495 Mar 10 02:11:07 PM PDT 24 Mar 10 02:11:20 PM PDT 24 733371865 ps
T817 /workspace/coverage/xbar_build_mode/41.xbar_same_source.697195742 Mar 10 02:10:49 PM PDT 24 Mar 10 02:11:03 PM PDT 24 1110853564 ps
T818 /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3088062095 Mar 10 02:07:37 PM PDT 24 Mar 10 02:07:48 PM PDT 24 147256339 ps
T819 /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1788895784 Mar 10 02:06:50 PM PDT 24 Mar 10 02:06:51 PM PDT 24 7950431 ps
T820 /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3316244306 Mar 10 02:08:56 PM PDT 24 Mar 10 02:09:10 PM PDT 24 1827528604 ps
T821 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.317188698 Mar 10 02:10:00 PM PDT 24 Mar 10 02:11:25 PM PDT 24 1253354917 ps
T822 /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2799016889 Mar 10 02:08:56 PM PDT 24 Mar 10 02:09:00 PM PDT 24 72276989 ps
T823 /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1317698359 Mar 10 02:10:34 PM PDT 24 Mar 10 02:10:36 PM PDT 24 9040836 ps
T824 /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2602705090 Mar 10 02:07:37 PM PDT 24 Mar 10 02:09:49 PM PDT 24 55794011433 ps
T825 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2479863679 Mar 10 02:07:42 PM PDT 24 Mar 10 02:08:20 PM PDT 24 3269419017 ps
T826 /workspace/coverage/xbar_build_mode/27.xbar_smoke.2250805421 Mar 10 02:09:40 PM PDT 24 Mar 10 02:09:42 PM PDT 24 33178956 ps
T827 /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.109237816 Mar 10 02:11:06 PM PDT 24 Mar 10 02:12:50 PM PDT 24 16166401916 ps
T828 /workspace/coverage/xbar_build_mode/45.xbar_error_random.2329308096 Mar 10 02:11:04 PM PDT 24 Mar 10 02:11:07 PM PDT 24 155318563 ps
T829 /workspace/coverage/xbar_build_mode/22.xbar_smoke.3478705902 Mar 10 02:09:14 PM PDT 24 Mar 10 02:09:16 PM PDT 24 98735619 ps
T830 /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1322061854 Mar 10 02:11:23 PM PDT 24 Mar 10 02:11:28 PM PDT 24 776506758 ps
T831 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2327373479 Mar 10 02:09:33 PM PDT 24 Mar 10 02:10:36 PM PDT 24 3687657620 ps
T832 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.502363179 Mar 10 02:11:00 PM PDT 24 Mar 10 02:11:07 PM PDT 24 62987681 ps
T833 /workspace/coverage/xbar_build_mode/8.xbar_random.1467532079 Mar 10 02:07:52 PM PDT 24 Mar 10 02:07:56 PM PDT 24 163165706 ps
T834 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2155028279 Mar 10 02:08:19 PM PDT 24 Mar 10 02:10:52 PM PDT 24 7186583972 ps
T835 /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2263972487 Mar 10 02:08:41 PM PDT 24 Mar 10 02:08:43 PM PDT 24 20454288 ps
T836 /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1776876351 Mar 10 02:07:50 PM PDT 24 Mar 10 02:09:03 PM PDT 24 30698941756 ps
T837 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.109378119 Mar 10 02:10:07 PM PDT 24 Mar 10 02:10:11 PM PDT 24 40898063 ps
T838 /workspace/coverage/xbar_build_mode/27.xbar_same_source.2822254493 Mar 10 02:09:47 PM PDT 24 Mar 10 02:09:51 PM PDT 24 40173399 ps
T839 /workspace/coverage/xbar_build_mode/45.xbar_smoke.1654771802 Mar 10 02:11:05 PM PDT 24 Mar 10 02:11:07 PM PDT 24 12561238 ps
T840 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1584781023 Mar 10 02:11:21 PM PDT 24 Mar 10 02:11:39 PM PDT 24 195348649 ps
T841 /workspace/coverage/xbar_build_mode/33.xbar_smoke.3836255303 Mar 10 02:10:09 PM PDT 24 Mar 10 02:10:11 PM PDT 24 264950388 ps
T842 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2292425129 Mar 10 02:09:39 PM PDT 24 Mar 10 02:09:47 PM PDT 24 1483606925 ps
T843 /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2630994018 Mar 10 02:10:03 PM PDT 24 Mar 10 02:10:14 PM PDT 24 3686641244 ps
T844 /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3845642009 Mar 10 02:09:01 PM PDT 24 Mar 10 02:09:05 PM PDT 24 55822301 ps
T845 /workspace/coverage/xbar_build_mode/40.xbar_random.3729327702 Mar 10 02:10:42 PM PDT 24 Mar 10 02:10:46 PM PDT 24 13999419 ps
T846 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3661783479 Mar 10 02:07:58 PM PDT 24 Mar 10 02:09:32 PM PDT 24 967472727 ps
T847 /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1891741670 Mar 10 02:08:40 PM PDT 24 Mar 10 02:08:45 PM PDT 24 170692563 ps
T159 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.543117383 Mar 10 02:08:10 PM PDT 24 Mar 10 02:08:53 PM PDT 24 7014084476 ps
T174 /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1063403761 Mar 10 02:11:22 PM PDT 24 Mar 10 02:11:56 PM PDT 24 4589991574 ps
T848 /workspace/coverage/xbar_build_mode/12.xbar_smoke.3704510815 Mar 10 02:08:16 PM PDT 24 Mar 10 02:08:17 PM PDT 24 9828097 ps
T849 /workspace/coverage/xbar_build_mode/43.xbar_random.3309328751 Mar 10 02:10:56 PM PDT 24 Mar 10 02:11:05 PM PDT 24 90527210 ps
T850 /workspace/coverage/xbar_build_mode/35.xbar_same_source.2847288144 Mar 10 02:10:24 PM PDT 24 Mar 10 02:10:37 PM PDT 24 1033009629 ps
T851 /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1715755423 Mar 10 02:09:37 PM PDT 24 Mar 10 02:09:50 PM PDT 24 213857621 ps
T852 /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.989459338 Mar 10 02:09:50 PM PDT 24 Mar 10 02:10:25 PM PDT 24 7545868399 ps
T853 /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2513628116 Mar 10 02:08:08 PM PDT 24 Mar 10 02:08:10 PM PDT 24 11914996 ps
T204 /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3778130751 Mar 10 02:08:29 PM PDT 24 Mar 10 02:10:56 PM PDT 24 78357669460 ps
T854 /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2046699094 Mar 10 02:10:38 PM PDT 24 Mar 10 02:10:50 PM PDT 24 2770724742 ps
T855 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3740400778 Mar 10 02:11:23 PM PDT 24 Mar 10 02:13:36 PM PDT 24 3191471768 ps
T856 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1943109846 Mar 10 02:10:59 PM PDT 24 Mar 10 02:11:28 PM PDT 24 237931897 ps
T857 /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2615355492 Mar 10 02:10:27 PM PDT 24 Mar 10 02:10:33 PM PDT 24 42036937 ps
T858 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1816854489 Mar 10 02:07:54 PM PDT 24 Mar 10 02:07:55 PM PDT 24 8410911 ps
T859 /workspace/coverage/xbar_build_mode/13.xbar_error_random.2346519062 Mar 10 02:08:24 PM PDT 24 Mar 10 02:08:33 PM PDT 24 1112303083 ps
T860 /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1782308034 Mar 10 02:08:51 PM PDT 24 Mar 10 02:10:39 PM PDT 24 8737008644 ps
T861 /workspace/coverage/xbar_build_mode/32.xbar_error_random.1957297145 Mar 10 02:10:08 PM PDT 24 Mar 10 02:10:17 PM PDT 24 2124327942 ps
T862 /workspace/coverage/xbar_build_mode/3.xbar_random.574840732 Mar 10 02:07:09 PM PDT 24 Mar 10 02:07:13 PM PDT 24 39336209 ps
T863 /workspace/coverage/xbar_build_mode/31.xbar_random.2515137261 Mar 10 02:10:03 PM PDT 24 Mar 10 02:10:06 PM PDT 24 185998512 ps
T864 /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3142381627 Mar 10 02:10:26 PM PDT 24 Mar 10 02:10:35 PM PDT 24 2202936500 ps
T865 /workspace/coverage/xbar_build_mode/34.xbar_random.178657711 Mar 10 02:10:18 PM PDT 24 Mar 10 02:10:33 PM PDT 24 1353084288 ps
T866 /workspace/coverage/xbar_build_mode/29.xbar_error_random.4195707152 Mar 10 02:09:52 PM PDT 24 Mar 10 02:09:59 PM PDT 24 620701836 ps
T867 /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1791650688 Mar 10 02:07:57 PM PDT 24 Mar 10 02:08:03 PM PDT 24 46420177 ps
T868 /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2699614235 Mar 10 02:09:45 PM PDT 24 Mar 10 02:09:47 PM PDT 24 32075722 ps
T185 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.835990423 Mar 10 02:11:01 PM PDT 24 Mar 10 02:11:14 PM PDT 24 536949245 ps
T869 /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3026274773 Mar 10 02:09:36 PM PDT 24 Mar 10 02:09:47 PM PDT 24 2758927306 ps
T870 /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.393470095 Mar 10 02:10:00 PM PDT 24 Mar 10 02:10:08 PM PDT 24 100040120 ps
T871 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2394827431 Mar 10 02:10:49 PM PDT 24 Mar 10 02:12:25 PM PDT 24 531076623 ps
T872 /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1091339998 Mar 10 02:11:03 PM PDT 24 Mar 10 02:11:14 PM PDT 24 7599758791 ps
T873 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3614082454 Mar 10 02:10:39 PM PDT 24 Mar 10 02:11:00 PM PDT 24 3195917084 ps
T874 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1589113025 Mar 10 02:10:24 PM PDT 24 Mar 10 02:13:04 PM PDT 24 63493294280 ps
T875 /workspace/coverage/xbar_build_mode/30.xbar_random.2648156163 Mar 10 02:09:57 PM PDT 24 Mar 10 02:10:03 PM PDT 24 106642896 ps
T876 /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3315665153 Mar 10 02:09:05 PM PDT 24 Mar 10 02:09:14 PM PDT 24 1308921880 ps
T877 /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.404096665 Mar 10 02:10:39 PM PDT 24 Mar 10 02:12:56 PM PDT 24 54248123615 ps
T878 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.875037351 Mar 10 02:07:52 PM PDT 24 Mar 10 02:08:04 PM PDT 24 47830559 ps
T879 /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.779811363 Mar 10 02:10:17 PM PDT 24 Mar 10 02:10:25 PM PDT 24 106312102 ps
T880 /workspace/coverage/xbar_build_mode/11.xbar_random.1660058917 Mar 10 02:08:06 PM PDT 24 Mar 10 02:08:18 PM PDT 24 825343249 ps
T881 /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1467436688 Mar 10 02:10:00 PM PDT 24 Mar 10 02:11:01 PM PDT 24 630675731 ps
T882 /workspace/coverage/xbar_build_mode/47.xbar_random.1385693754 Mar 10 02:11:18 PM PDT 24 Mar 10 02:11:25 PM PDT 24 394239052 ps
T883 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3036206951 Mar 10 02:07:04 PM PDT 24 Mar 10 02:08:00 PM PDT 24 637150730 ps
T884 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1529779905 Mar 10 02:11:07 PM PDT 24 Mar 10 02:13:53 PM PDT 24 5877464385 ps
T885 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3889439401 Mar 10 02:10:25 PM PDT 24 Mar 10 02:16:35 PM PDT 24 54709857012 ps
T886 /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.736410691 Mar 10 02:11:12 PM PDT 24 Mar 10 02:11:13 PM PDT 24 8226519 ps
T887 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1037889104 Mar 10 02:07:43 PM PDT 24 Mar 10 02:09:40 PM PDT 24 6896178470 ps
T888 /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2582785438 Mar 10 02:10:53 PM PDT 24 Mar 10 02:10:56 PM PDT 24 21899601 ps
T889 /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2563014995 Mar 10 02:08:25 PM PDT 24 Mar 10 02:08:26 PM PDT 24 9291750 ps
T890 /workspace/coverage/xbar_build_mode/38.xbar_random.679017704 Mar 10 02:10:32 PM PDT 24 Mar 10 02:10:34 PM PDT 24 20215219 ps
T109 /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.760203411 Mar 10 02:09:39 PM PDT 24 Mar 10 02:12:28 PM PDT 24 61499671854 ps
T891 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3604414423 Mar 10 02:08:06 PM PDT 24 Mar 10 02:08:12 PM PDT 24 2124851411 ps
T892 /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1077626447 Mar 10 02:10:23 PM PDT 24 Mar 10 02:10:31 PM PDT 24 1484855198 ps
T893 /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.560172759 Mar 10 02:08:43 PM PDT 24 Mar 10 02:08:55 PM PDT 24 3323537416 ps
T894 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.243962654 Mar 10 02:11:18 PM PDT 24 Mar 10 02:11:31 PM PDT 24 141772002 ps
T895 /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1162463943 Mar 10 02:09:22 PM PDT 24 Mar 10 02:09:33 PM PDT 24 4570732185 ps
T896 /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2275983375 Mar 10 02:08:55 PM PDT 24 Mar 10 02:09:05 PM PDT 24 1337042430 ps
T897 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4176659945 Mar 10 02:10:32 PM PDT 24 Mar 10 02:11:53 PM PDT 24 1767980771 ps
T898 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3962518628 Mar 10 02:08:37 PM PDT 24 Mar 10 02:08:44 PM PDT 24 4163178391 ps
T203 /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2886256287 Mar 10 02:08:56 PM PDT 24 Mar 10 02:09:27 PM PDT 24 10431493525 ps
T899 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2213379952 Mar 10 02:09:58 PM PDT 24 Mar 10 02:10:26 PM PDT 24 155309173 ps
T900 /workspace/coverage/xbar_build_mode/24.xbar_smoke.2357989524 Mar 10 02:09:22 PM PDT 24 Mar 10 02:09:24 PM PDT 24 129451390 ps

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.1918002276
Short name T3
Test name
Test status
Simulation time 3246320636 ps
CPU time 50.59 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:47 PM PDT 24
Peak memory 203676 kb
Host smart-23e1905d-5e5f-4bcc-a5fb-a54b0456426b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1918002276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1918002276
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.538129842
Short name T75
Test name
Test status
Simulation time 87653325188 ps
CPU time 350.24 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:17:06 PM PDT 24
Peak memory 204184 kb
Host smart-ed0861f3-f036-4c8c-ae65-5baf5e4a1369
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=538129842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.538129842
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1835669719
Short name T102
Test name
Test status
Simulation time 121425261613 ps
CPU time 327.76 seconds
Started Mar 10 02:06:40 PM PDT 24
Finished Mar 10 02:12:08 PM PDT 24
Peak memory 203580 kb
Host smart-67963b72-f65f-433c-a989-be7209df6dfc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1835669719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1835669719
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2707001814
Short name T78
Test name
Test status
Simulation time 83807046160 ps
CPU time 342.29 seconds
Started Mar 10 02:08:23 PM PDT 24
Finished Mar 10 02:14:06 PM PDT 24
Peak memory 204076 kb
Host smart-b07f5973-a42e-40f7-a80b-01252c2e0005
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2707001814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2707001814
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.277228451
Short name T10
Test name
Test status
Simulation time 200286726 ps
CPU time 43.59 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 203960 kb
Host smart-92075022-1c83-40ce-8544-afa11822eba3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277228451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.277228451
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2313272542
Short name T83
Test name
Test status
Simulation time 18423086244 ps
CPU time 120.73 seconds
Started Mar 10 02:10:45 PM PDT 24
Finished Mar 10 02:12:46 PM PDT 24
Peak memory 202572 kb
Host smart-a1226eee-2ac1-43fb-b161-8af9517f8615
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2313272542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.2313272542
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.984008291
Short name T214
Test name
Test status
Simulation time 47240492992 ps
CPU time 319.57 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:14:22 PM PDT 24
Peak memory 203596 kb
Host smart-a7bcedce-ac4b-4021-98f6-eef4713ff083
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=984008291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo
w_rsp.984008291
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3156822072
Short name T34
Test name
Test status
Simulation time 1446921251 ps
CPU time 21.23 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:49 PM PDT 24
Peak memory 202220 kb
Host smart-8e7edb2a-0c17-45a2-a753-bf25fd39a1f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3156822072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3156822072
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3198128506
Short name T6
Test name
Test status
Simulation time 1476783051 ps
CPU time 204.76 seconds
Started Mar 10 02:07:41 PM PDT 24
Finished Mar 10 02:11:06 PM PDT 24
Peak memory 204920 kb
Host smart-126d0a42-f6a4-4633-8d14-a4d3b8209698
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3198128506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.3198128506
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1881648416
Short name T56
Test name
Test status
Simulation time 2274894662 ps
CPU time 10.23 seconds
Started Mar 10 02:10:30 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202560 kb
Host smart-f5654a65-d62f-445d-a4ab-0961c26ec03c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881648416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1881648416
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.4203945402
Short name T87
Test name
Test status
Simulation time 6638714119 ps
CPU time 93.82 seconds
Started Mar 10 02:08:35 PM PDT 24
Finished Mar 10 02:10:09 PM PDT 24
Peak memory 203588 kb
Host smart-56d94510-e3e3-4beb-b287-3229a5911a26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4203945402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4203945402
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.138056311
Short name T9
Test name
Test status
Simulation time 1391437750 ps
CPU time 153.22 seconds
Started Mar 10 02:11:28 PM PDT 24
Finished Mar 10 02:14:02 PM PDT 24
Peak memory 205640 kb
Host smart-eb71a573-c6ff-4d2b-9cd5-f4319a6c6f81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138056311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.138056311
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1291328023
Short name T44
Test name
Test status
Simulation time 2032809376 ps
CPU time 74.2 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:11:05 PM PDT 24
Peak memory 204880 kb
Host smart-fa7aff9c-b7b9-4dcf-930d-cb1697c125d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291328023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.1291328023
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3945904207
Short name T7
Test name
Test status
Simulation time 2606417153 ps
CPU time 120.42 seconds
Started Mar 10 02:09:34 PM PDT 24
Finished Mar 10 02:11:35 PM PDT 24
Peak memory 204640 kb
Host smart-304131df-8ef4-476a-b4a0-94b19a8ec526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3945904207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3945904207
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.457003879
Short name T2
Test name
Test status
Simulation time 980938328 ps
CPU time 11 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 202416 kb
Host smart-9d2b2172-f979-4fff-8b31-39e19f7d0878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457003879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.457003879
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4208779919
Short name T127
Test name
Test status
Simulation time 66839423381 ps
CPU time 134.54 seconds
Started Mar 10 02:09:57 PM PDT 24
Finished Mar 10 02:12:12 PM PDT 24
Peak memory 202512 kb
Host smart-f7b30779-d7c8-4a65-9b18-5315442b472e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4208779919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.4208779919
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.809973409
Short name T227
Test name
Test status
Simulation time 70961378427 ps
CPU time 188.71 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:11:17 PM PDT 24
Peak memory 203456 kb
Host smart-28275279-9d40-4e04-a379-33c91f916b3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=809973409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.809973409
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3452353434
Short name T111
Test name
Test status
Simulation time 2427017394 ps
CPU time 126.62 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:12:21 PM PDT 24
Peak memory 205168 kb
Host smart-605bf7f0-9045-4513-bb48-d76d5de9cbe0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3452353434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3452353434
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3333251168
Short name T16
Test name
Test status
Simulation time 145334806 ps
CPU time 19.05 seconds
Started Mar 10 02:09:24 PM PDT 24
Finished Mar 10 02:09:43 PM PDT 24
Peak memory 202412 kb
Host smart-65e400e8-01af-4e91-9dbd-49a19d869cf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3333251168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3333251168
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.125780888
Short name T82
Test name
Test status
Simulation time 503501371 ps
CPU time 8.18 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:10:47 PM PDT 24
Peak memory 202392 kb
Host smart-366e14c1-dcea-4358-b23b-3dba2576f3a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125780888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.125780888
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1733398734
Short name T165
Test name
Test status
Simulation time 8275464748 ps
CPU time 69.56 seconds
Started Mar 10 02:08:41 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 204908 kb
Host smart-c86d6fa8-ea4a-4e0d-9ae0-217913e8c646
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733398734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.1733398734
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.779648344
Short name T238
Test name
Test status
Simulation time 3535019720 ps
CPU time 129.83 seconds
Started Mar 10 02:09:43 PM PDT 24
Finished Mar 10 02:11:53 PM PDT 24
Peak memory 206560 kb
Host smart-5129f92a-3baa-42bc-9ace-de13ca566871
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=779648344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res
et_error.779648344
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.667384133
Short name T380
Test name
Test status
Simulation time 190547601 ps
CPU time 1.86 seconds
Started Mar 10 02:06:40 PM PDT 24
Finished Mar 10 02:06:42 PM PDT 24
Peak memory 202448 kb
Host smart-a39a4805-c5a3-4246-822f-692168ccf182
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=667384133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.667384133
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2990346703
Short name T517
Test name
Test status
Simulation time 259946008 ps
CPU time 3.34 seconds
Started Mar 10 02:06:50 PM PDT 24
Finished Mar 10 02:06:53 PM PDT 24
Peak memory 202392 kb
Host smart-e983d6e8-13d5-40cf-802d-54254da181d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2990346703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2990346703
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.1421211088
Short name T414
Test name
Test status
Simulation time 1857001328 ps
CPU time 9.81 seconds
Started Mar 10 02:06:46 PM PDT 24
Finished Mar 10 02:06:58 PM PDT 24
Peak memory 202420 kb
Host smart-1e885f15-b90a-48ab-87c7-8716d94fb100
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1421211088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1421211088
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.2616594118
Short name T178
Test name
Test status
Simulation time 28148837 ps
CPU time 2.59 seconds
Started Mar 10 02:06:40 PM PDT 24
Finished Mar 10 02:06:43 PM PDT 24
Peak memory 202308 kb
Host smart-df1eeb66-7b91-4238-919c-b8ea4e0bd4b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2616594118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2616594118
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2399205661
Short name T564
Test name
Test status
Simulation time 5685294264 ps
CPU time 19.22 seconds
Started Mar 10 02:06:41 PM PDT 24
Finished Mar 10 02:07:00 PM PDT 24
Peak memory 202504 kb
Host smart-a9ffe30a-4805-4ea1-a363-b3a2a8b97a96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399205661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2399205661
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1769710901
Short name T776
Test name
Test status
Simulation time 38292700733 ps
CPU time 109.46 seconds
Started Mar 10 02:06:41 PM PDT 24
Finished Mar 10 02:08:31 PM PDT 24
Peak memory 202536 kb
Host smart-2e8e2fc4-fbfe-46ac-af75-280e12d4978a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1769710901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1769710901
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.862094802
Short name T169
Test name
Test status
Simulation time 19268724 ps
CPU time 1.9 seconds
Started Mar 10 02:06:46 PM PDT 24
Finished Mar 10 02:06:50 PM PDT 24
Peak memory 202444 kb
Host smart-3706c3cf-6b9d-49da-b36d-d0eeba765821
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862094802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.862094802
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.3426062864
Short name T723
Test name
Test status
Simulation time 53431751 ps
CPU time 3.12 seconds
Started Mar 10 02:06:45 PM PDT 24
Finished Mar 10 02:06:51 PM PDT 24
Peak memory 202440 kb
Host smart-8b5103e8-b4d1-48d2-8208-20467af723a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3426062864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3426062864
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.3155110424
Short name T377
Test name
Test status
Simulation time 19461911 ps
CPU time 1.16 seconds
Started Mar 10 02:06:37 PM PDT 24
Finished Mar 10 02:06:38 PM PDT 24
Peak memory 202364 kb
Host smart-799d241e-953b-4522-bc70-07c7f8cc523c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3155110424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3155110424
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2725846476
Short name T68
Test name
Test status
Simulation time 2014805523 ps
CPU time 7.93 seconds
Started Mar 10 02:06:39 PM PDT 24
Finished Mar 10 02:06:47 PM PDT 24
Peak memory 202404 kb
Host smart-76e47682-cc7a-4ef6-87ca-9c4c742be73e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725846476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2725846476
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1222849740
Short name T172
Test name
Test status
Simulation time 2385480233 ps
CPU time 11.57 seconds
Started Mar 10 02:06:35 PM PDT 24
Finished Mar 10 02:06:47 PM PDT 24
Peak memory 202588 kb
Host smart-02abcace-88f3-4fa0-82f6-61ced9cd4482
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1222849740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1222849740
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2042454910
Short name T499
Test name
Test status
Simulation time 11708062 ps
CPU time 1.07 seconds
Started Mar 10 02:06:37 PM PDT 24
Finished Mar 10 02:06:38 PM PDT 24
Peak memory 202356 kb
Host smart-f20eaa12-f595-451a-9521-152bf7df2a95
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042454910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2042454910
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3744965924
Short name T512
Test name
Test status
Simulation time 1465343138 ps
CPU time 30.61 seconds
Started Mar 10 02:06:45 PM PDT 24
Finished Mar 10 02:07:19 PM PDT 24
Peak memory 202448 kb
Host smart-b82731d6-46a3-43a3-9ffa-0b5fcded3f56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3744965924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3744965924
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1378425717
Short name T63
Test name
Test status
Simulation time 955949711 ps
CPU time 13.57 seconds
Started Mar 10 02:06:46 PM PDT 24
Finished Mar 10 02:07:02 PM PDT 24
Peak memory 202436 kb
Host smart-5b9df6e0-bc02-4af8-b1c4-2801354245a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1378425717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1378425717
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2955925953
Short name T482
Test name
Test status
Simulation time 313883844 ps
CPU time 36.59 seconds
Started Mar 10 02:06:45 PM PDT 24
Finished Mar 10 02:07:25 PM PDT 24
Peak memory 204548 kb
Host smart-3ce31304-2dd1-4204-a2db-314a352c7f33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2955925953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.2955925953
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1429272947
Short name T773
Test name
Test status
Simulation time 252095857 ps
CPU time 37.46 seconds
Started Mar 10 02:06:44 PM PDT 24
Finished Mar 10 02:07:24 PM PDT 24
Peak memory 203716 kb
Host smart-56fea9cd-a85b-4e69-aa08-dd20b4e6d041
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1429272947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1429272947
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3204933645
Short name T809
Test name
Test status
Simulation time 1730775985 ps
CPU time 7.79 seconds
Started Mar 10 02:06:49 PM PDT 24
Finished Mar 10 02:06:57 PM PDT 24
Peak memory 202388 kb
Host smart-9be79f97-1bf0-4afb-9ca4-dd0061e8e86a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3204933645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3204933645
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.502049701
Short name T53
Test name
Test status
Simulation time 107831778 ps
CPU time 2.7 seconds
Started Mar 10 02:06:54 PM PDT 24
Finished Mar 10 02:06:58 PM PDT 24
Peak memory 202440 kb
Host smart-a73b81c6-8dbe-41d2-9c0a-530b62c6e8ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502049701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.502049701
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.145149010
Short name T234
Test name
Test status
Simulation time 45727300122 ps
CPU time 337.11 seconds
Started Mar 10 02:06:57 PM PDT 24
Finished Mar 10 02:12:36 PM PDT 24
Peak memory 203580 kb
Host smart-17db1385-a210-4611-b6cb-3d01ec8062e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=145149010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow
_rsp.145149010
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1841883402
Short name T341
Test name
Test status
Simulation time 62941001 ps
CPU time 3.42 seconds
Started Mar 10 02:06:56 PM PDT 24
Finished Mar 10 02:07:01 PM PDT 24
Peak memory 202364 kb
Host smart-bab0e4eb-f568-4ed3-93fb-9c36c6fb869f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1841883402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1841883402
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.3702726752
Short name T658
Test name
Test status
Simulation time 2874199719 ps
CPU time 10.42 seconds
Started Mar 10 02:06:54 PM PDT 24
Finished Mar 10 02:07:06 PM PDT 24
Peak memory 202492 kb
Host smart-388a3a6e-df5c-409b-9a9f-0da2ee3389e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3702726752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3702726752
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.1812667113
Short name T726
Test name
Test status
Simulation time 79808913 ps
CPU time 7.28 seconds
Started Mar 10 02:06:51 PM PDT 24
Finished Mar 10 02:06:58 PM PDT 24
Peak memory 202400 kb
Host smart-dfbb5d2d-2b0e-4be0-bea8-74feefa99172
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1812667113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1812667113
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3942737209
Short name T324
Test name
Test status
Simulation time 1360336046 ps
CPU time 7.39 seconds
Started Mar 10 02:06:50 PM PDT 24
Finished Mar 10 02:06:58 PM PDT 24
Peak memory 202452 kb
Host smart-a9d0db4d-ed26-410b-a132-03e403cff9f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942737209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3942737209
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.579404292
Short name T598
Test name
Test status
Simulation time 33299736816 ps
CPU time 90.63 seconds
Started Mar 10 02:06:50 PM PDT 24
Finished Mar 10 02:08:21 PM PDT 24
Peak memory 202568 kb
Host smart-81eadd3f-43d9-41be-a836-5de3c1f84c31
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=579404292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.579404292
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2741398015
Short name T131
Test name
Test status
Simulation time 15099816 ps
CPU time 1.2 seconds
Started Mar 10 02:06:52 PM PDT 24
Finished Mar 10 02:06:54 PM PDT 24
Peak memory 202376 kb
Host smart-7fa852d5-8a24-462d-b0a4-811f7dc1b588
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741398015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2741398015
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.2000294322
Short name T581
Test name
Test status
Simulation time 60552714 ps
CPU time 4.17 seconds
Started Mar 10 02:06:56 PM PDT 24
Finished Mar 10 02:07:03 PM PDT 24
Peak memory 202352 kb
Host smart-7044f1cf-07f9-4efe-b72a-ab9c05b1558b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2000294322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2000294322
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.815347908
Short name T560
Test name
Test status
Simulation time 102677774 ps
CPU time 1.66 seconds
Started Mar 10 02:06:44 PM PDT 24
Finished Mar 10 02:06:49 PM PDT 24
Peak memory 202392 kb
Host smart-765fafd8-27a7-4042-aa2f-d2f53ef5ec18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=815347908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.815347908
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3097073594
Short name T411
Test name
Test status
Simulation time 1890033093 ps
CPU time 8.64 seconds
Started Mar 10 02:06:50 PM PDT 24
Finished Mar 10 02:07:00 PM PDT 24
Peak memory 202452 kb
Host smart-6eb050d2-d62a-4a22-b770-bea3e38b827f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097073594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3097073594
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.54560285
Short name T666
Test name
Test status
Simulation time 1841170993 ps
CPU time 13.36 seconds
Started Mar 10 02:06:51 PM PDT 24
Finished Mar 10 02:07:05 PM PDT 24
Peak memory 202424 kb
Host smart-b85c552d-454d-4b91-9e65-b02f00f3e040
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54560285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.54560285
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1788895784
Short name T819
Test name
Test status
Simulation time 7950431 ps
CPU time 1 seconds
Started Mar 10 02:06:50 PM PDT 24
Finished Mar 10 02:06:51 PM PDT 24
Peak memory 202388 kb
Host smart-433d6a1d-02d1-4cb7-bb8d-f5b854d7cae4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788895784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1788895784
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2763896986
Short name T625
Test name
Test status
Simulation time 10160001746 ps
CPU time 92.55 seconds
Started Mar 10 02:06:54 PM PDT 24
Finished Mar 10 02:08:28 PM PDT 24
Peak memory 203624 kb
Host smart-dcb11570-eb80-47d6-9c0a-8f64ec08316f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2763896986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2763896986
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4182835388
Short name T117
Test name
Test status
Simulation time 282115456 ps
CPU time 28.71 seconds
Started Mar 10 02:07:00 PM PDT 24
Finished Mar 10 02:07:29 PM PDT 24
Peak memory 202452 kb
Host smart-e314baa2-acf9-4b52-b75c-8b4b8607ade7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4182835388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4182835388
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.493713319
Short name T348
Test name
Test status
Simulation time 1377961895 ps
CPU time 119.35 seconds
Started Mar 10 02:06:57 PM PDT 24
Finished Mar 10 02:08:58 PM PDT 24
Peak memory 206660 kb
Host smart-26efcb85-f98f-4d81-9078-2de11b50d5a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=493713319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.493713319
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.45554831
Short name T707
Test name
Test status
Simulation time 1956461064 ps
CPU time 84.6 seconds
Started Mar 10 02:07:01 PM PDT 24
Finished Mar 10 02:08:25 PM PDT 24
Peak memory 204716 kb
Host smart-aba66cc2-c775-4695-ad95-980ec73eb14e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45554831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset
_error.45554831
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3132547202
Short name T292
Test name
Test status
Simulation time 147880579 ps
CPU time 3.14 seconds
Started Mar 10 02:06:56 PM PDT 24
Finished Mar 10 02:07:02 PM PDT 24
Peak memory 202356 kb
Host smart-908af13d-b041-480f-b121-87c51b56d3d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3132547202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3132547202
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2724279860
Short name T521
Test name
Test status
Simulation time 51534176 ps
CPU time 9.28 seconds
Started Mar 10 02:08:02 PM PDT 24
Finished Mar 10 02:08:11 PM PDT 24
Peak memory 202456 kb
Host smart-375a5af8-1da6-4478-b8f0-3b3509e2224d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2724279860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2724279860
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3929702119
Short name T221
Test name
Test status
Simulation time 283954772345 ps
CPU time 322.91 seconds
Started Mar 10 02:08:02 PM PDT 24
Finished Mar 10 02:13:25 PM PDT 24
Peak memory 204660 kb
Host smart-5d1e2831-3b2b-45ef-a0dc-2a3cbb75c5d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3929702119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.3929702119
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.557344635
Short name T600
Test name
Test status
Simulation time 64582287 ps
CPU time 1.44 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:08:10 PM PDT 24
Peak memory 202380 kb
Host smart-152eb934-8215-4a7b-9ab5-30806350f5a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=557344635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.557344635
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3037975939
Short name T665
Test name
Test status
Simulation time 1537869491 ps
CPU time 13.33 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:08:19 PM PDT 24
Peak memory 202392 kb
Host smart-5de109ba-bae4-4175-a4e4-7cbbcb26ae19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037975939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3037975939
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.633535935
Short name T328
Test name
Test status
Simulation time 444796416 ps
CPU time 7.36 seconds
Started Mar 10 02:08:01 PM PDT 24
Finished Mar 10 02:08:09 PM PDT 24
Peak memory 202332 kb
Host smart-a479fbf4-42ed-4ab9-a9b8-c5a4c7f44c45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=633535935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.633535935
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.192830889
Short name T661
Test name
Test status
Simulation time 53194492369 ps
CPU time 125.02 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 202560 kb
Host smart-02a8c890-f891-40d1-b02d-a6bb0f6b8e26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=192830889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.192830889
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3500189455
Short name T454
Test name
Test status
Simulation time 11863652449 ps
CPU time 40.56 seconds
Started Mar 10 02:08:02 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 202540 kb
Host smart-021739f9-32f2-4792-9f61-8d7ea6f70a66
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3500189455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3500189455
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2849932403
Short name T667
Test name
Test status
Simulation time 39857967 ps
CPU time 4.6 seconds
Started Mar 10 02:08:05 PM PDT 24
Finished Mar 10 02:08:10 PM PDT 24
Peak memory 202448 kb
Host smart-0225b745-2d5e-4044-8add-325492b19765
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849932403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2849932403
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2950466367
Short name T541
Test name
Test status
Simulation time 29349186 ps
CPU time 2.64 seconds
Started Mar 10 02:08:02 PM PDT 24
Finished Mar 10 02:08:05 PM PDT 24
Peak memory 202388 kb
Host smart-434991a9-0cf8-4f8b-8992-d98eb3a4c2de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2950466367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2950466367
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.2051066397
Short name T191
Test name
Test status
Simulation time 51730787 ps
CPU time 1.22 seconds
Started Mar 10 02:08:03 PM PDT 24
Finished Mar 10 02:08:04 PM PDT 24
Peak memory 202360 kb
Host smart-fd937d18-c48c-4781-aca9-d5aca8719949
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2051066397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2051066397
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3604414423
Short name T891
Test name
Test status
Simulation time 2124851411 ps
CPU time 6.14 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:08:12 PM PDT 24
Peak memory 202364 kb
Host smart-4c505461-dbdc-4a72-8854-160171248a29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604414423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3604414423
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.209935408
Short name T688
Test name
Test status
Simulation time 1877380971 ps
CPU time 5.42 seconds
Started Mar 10 02:08:02 PM PDT 24
Finished Mar 10 02:08:07 PM PDT 24
Peak memory 202424 kb
Host smart-b117068e-c4d0-4951-8798-a1b06161a042
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=209935408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.209935408
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3551231391
Short name T721
Test name
Test status
Simulation time 10146908 ps
CPU time 1.15 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:08:07 PM PDT 24
Peak memory 202384 kb
Host smart-1a4be84d-4c9a-4863-afad-c89e43c9ed9c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551231391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3551231391
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3339335286
Short name T45
Test name
Test status
Simulation time 197911821 ps
CPU time 16.96 seconds
Started Mar 10 02:08:07 PM PDT 24
Finished Mar 10 02:08:24 PM PDT 24
Peak memory 202392 kb
Host smart-668dcb4a-ab66-47da-8e87-80413f88a72f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3339335286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3339335286
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4193715748
Short name T382
Test name
Test status
Simulation time 11202345250 ps
CPU time 70.26 seconds
Started Mar 10 02:08:09 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 202536 kb
Host smart-db716d6c-a8e4-4734-8be2-0f9861fb13d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4193715748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4193715748
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.234810004
Short name T686
Test name
Test status
Simulation time 602471321 ps
CPU time 71.07 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 204508 kb
Host smart-0d09a416-a5aa-441a-af2a-79ee203efb90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=234810004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand
_reset.234810004
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1095361158
Short name T547
Test name
Test status
Simulation time 674032747 ps
CPU time 98.04 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:09:46 PM PDT 24
Peak memory 204308 kb
Host smart-3c98ef7d-52cb-4cd8-a21b-ebc56501225d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1095361158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.1095361158
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1662744793
Short name T803
Test name
Test status
Simulation time 505173766 ps
CPU time 6.6 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:08:14 PM PDT 24
Peak memory 202436 kb
Host smart-b432f5e6-60c7-475c-8b78-430bdf1959fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1662744793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1662744793
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3031608771
Short name T99
Test name
Test status
Simulation time 1268594486 ps
CPU time 27.39 seconds
Started Mar 10 02:08:07 PM PDT 24
Finished Mar 10 02:08:35 PM PDT 24
Peak memory 202368 kb
Host smart-0c8f3094-cc8c-41dc-a246-b57254c63c65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031608771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3031608771
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1072753515
Short name T139
Test name
Test status
Simulation time 3036862234 ps
CPU time 7.56 seconds
Started Mar 10 02:08:20 PM PDT 24
Finished Mar 10 02:08:28 PM PDT 24
Peak memory 202580 kb
Host smart-effcea97-db68-43d6-a63b-9873a25f05b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1072753515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1072753515
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2179060570
Short name T30
Test name
Test status
Simulation time 1629750077 ps
CPU time 11.47 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202448 kb
Host smart-77cffdd3-ed86-43dc-922e-e0bdc37472a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2179060570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2179060570
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1660058917
Short name T880
Test name
Test status
Simulation time 825343249 ps
CPU time 11.97 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:08:18 PM PDT 24
Peak memory 202328 kb
Host smart-d6b7c617-ca5f-40e0-b753-c5057d1603ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1660058917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1660058917
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1935260047
Short name T778
Test name
Test status
Simulation time 52672555686 ps
CPU time 101.1 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:09:49 PM PDT 24
Peak memory 202556 kb
Host smart-a7d302d9-021a-4b10-9f58-6f162a282e18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935260047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1935260047
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.543117383
Short name T159
Test name
Test status
Simulation time 7014084476 ps
CPU time 42.61 seconds
Started Mar 10 02:08:10 PM PDT 24
Finished Mar 10 02:08:53 PM PDT 24
Peak memory 202580 kb
Host smart-a134c46d-c515-454e-b6ec-a55158d8f8ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=543117383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.543117383
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1789473613
Short name T399
Test name
Test status
Simulation time 56457429 ps
CPU time 5.56 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:08:13 PM PDT 24
Peak memory 202456 kb
Host smart-5e211618-4c67-4485-bb40-ce35fafcc1a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789473613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1789473613
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3536599597
Short name T524
Test name
Test status
Simulation time 887367920 ps
CPU time 12.91 seconds
Started Mar 10 02:08:07 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202420 kb
Host smart-bc753084-1ee3-45aa-a55e-ad1f77167e79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3536599597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3536599597
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.2457661998
Short name T130
Test name
Test status
Simulation time 63994548 ps
CPU time 1.56 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:08:08 PM PDT 24
Peak memory 202388 kb
Host smart-a99a972b-3c24-4a1e-aa31-96cbcc339b25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457661998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2457661998
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1549255116
Short name T676
Test name
Test status
Simulation time 2390590370 ps
CPU time 9.34 seconds
Started Mar 10 02:08:10 PM PDT 24
Finished Mar 10 02:08:19 PM PDT 24
Peak memory 202576 kb
Host smart-86760c27-4559-4c3a-90ef-e5e6c0255989
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549255116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1549255116
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.436361864
Short name T29
Test name
Test status
Simulation time 5301441772 ps
CPU time 9.54 seconds
Started Mar 10 02:08:09 PM PDT 24
Finished Mar 10 02:08:19 PM PDT 24
Peak memory 202496 kb
Host smart-a304d15e-0c95-4801-af44-db81f15f9323
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=436361864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.436361864
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2513628116
Short name T853
Test name
Test status
Simulation time 11914996 ps
CPU time 1.23 seconds
Started Mar 10 02:08:08 PM PDT 24
Finished Mar 10 02:08:10 PM PDT 24
Peak memory 202436 kb
Host smart-46799070-8eda-4347-97b4-e40dc419a90e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513628116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2513628116
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2754261966
Short name T558
Test name
Test status
Simulation time 826048939 ps
CPU time 46.19 seconds
Started Mar 10 02:08:15 PM PDT 24
Finished Mar 10 02:09:01 PM PDT 24
Peak memory 202512 kb
Host smart-400d85c1-417a-466d-9228-5a2afa332a12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2754261966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2754261966
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1697194270
Short name T642
Test name
Test status
Simulation time 18327734729 ps
CPU time 68.56 seconds
Started Mar 10 02:08:13 PM PDT 24
Finished Mar 10 02:09:22 PM PDT 24
Peak memory 203548 kb
Host smart-ce718ddb-dcbc-4390-ae6c-8aeacd9e944c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1697194270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1697194270
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2338181240
Short name T236
Test name
Test status
Simulation time 523050593 ps
CPU time 88.63 seconds
Started Mar 10 02:08:15 PM PDT 24
Finished Mar 10 02:09:44 PM PDT 24
Peak memory 206056 kb
Host smart-9b47b020-3cb4-44d3-a741-e8758141a32c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2338181240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.2338181240
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3012580472
Short name T663
Test name
Test status
Simulation time 27598575 ps
CPU time 7.48 seconds
Started Mar 10 02:08:14 PM PDT 24
Finished Mar 10 02:08:22 PM PDT 24
Peak memory 202388 kb
Host smart-1f357262-868c-4ec6-975c-68ea7fea07c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3012580472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.3012580472
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2964500039
Short name T458
Test name
Test status
Simulation time 1779850157 ps
CPU time 6.29 seconds
Started Mar 10 02:08:14 PM PDT 24
Finished Mar 10 02:08:21 PM PDT 24
Peak memory 202400 kb
Host smart-531ac557-7627-4b3b-90bb-91ba9c08cbe9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2964500039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2964500039
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2168730038
Short name T291
Test name
Test status
Simulation time 38859861 ps
CPU time 4.83 seconds
Started Mar 10 02:08:20 PM PDT 24
Finished Mar 10 02:08:25 PM PDT 24
Peak memory 202440 kb
Host smart-a3b7b218-d39f-4d2e-9454-3d3d0b662643
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2168730038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2168730038
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1876835608
Short name T218
Test name
Test status
Simulation time 54517478190 ps
CPU time 313.31 seconds
Started Mar 10 02:08:18 PM PDT 24
Finished Mar 10 02:13:31 PM PDT 24
Peak memory 203604 kb
Host smart-65607691-50bf-4b0b-9b45-288396d9fbc3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1876835608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.1876835608
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.772106042
Short name T32
Test name
Test status
Simulation time 45294824 ps
CPU time 5.7 seconds
Started Mar 10 02:08:18 PM PDT 24
Finished Mar 10 02:08:24 PM PDT 24
Peak memory 202436 kb
Host smart-70f7f9d0-d65d-42e9-9295-e5b3a40bebe9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=772106042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.772106042
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1038719117
Short name T662
Test name
Test status
Simulation time 46753282 ps
CPU time 5.18 seconds
Started Mar 10 02:08:22 PM PDT 24
Finished Mar 10 02:08:28 PM PDT 24
Peak memory 202436 kb
Host smart-a6011cba-f675-4846-8114-3428e844d9a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1038719117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1038719117
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3276358329
Short name T402
Test name
Test status
Simulation time 132897273 ps
CPU time 2.77 seconds
Started Mar 10 02:08:20 PM PDT 24
Finished Mar 10 02:08:22 PM PDT 24
Peak memory 202384 kb
Host smart-ccecad0e-5b46-438f-b2d5-822f98dd71d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276358329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3276358329
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1440871932
Short name T390
Test name
Test status
Simulation time 10189922139 ps
CPU time 41.43 seconds
Started Mar 10 02:08:20 PM PDT 24
Finished Mar 10 02:09:02 PM PDT 24
Peak memory 202584 kb
Host smart-f0c7fbc5-8fb6-44a5-8b77-6bad70b1ecfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440871932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1440871932
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2630521080
Short name T387
Test name
Test status
Simulation time 5668145415 ps
CPU time 37.89 seconds
Started Mar 10 02:08:22 PM PDT 24
Finished Mar 10 02:09:01 PM PDT 24
Peak memory 202568 kb
Host smart-933ba689-69ab-4288-b8e8-0b66a9a323fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2630521080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2630521080
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.996138567
Short name T701
Test name
Test status
Simulation time 40173139 ps
CPU time 2.41 seconds
Started Mar 10 02:08:18 PM PDT 24
Finished Mar 10 02:08:21 PM PDT 24
Peak memory 202464 kb
Host smart-ce9cbd70-2a95-4b43-8ca6-618b5758dc8e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996138567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.996138567
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.2701125836
Short name T343
Test name
Test status
Simulation time 333313079 ps
CPU time 3.72 seconds
Started Mar 10 02:08:16 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202440 kb
Host smart-7f45d932-b554-4556-b2ef-523e282a757d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2701125836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2701125836
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.3704510815
Short name T848
Test name
Test status
Simulation time 9828097 ps
CPU time 1.23 seconds
Started Mar 10 02:08:16 PM PDT 24
Finished Mar 10 02:08:17 PM PDT 24
Peak memory 202364 kb
Host smart-b2217974-904b-4860-87c6-621dda4659e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3704510815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3704510815
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2939419496
Short name T553
Test name
Test status
Simulation time 3877865294 ps
CPU time 9.22 seconds
Started Mar 10 02:08:15 PM PDT 24
Finished Mar 10 02:08:24 PM PDT 24
Peak memory 202524 kb
Host smart-eb5c874b-26f0-4652-907a-fea376c20082
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939419496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2939419496
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1133539189
Short name T321
Test name
Test status
Simulation time 639800417 ps
CPU time 5.14 seconds
Started Mar 10 02:08:15 PM PDT 24
Finished Mar 10 02:08:21 PM PDT 24
Peak memory 202456 kb
Host smart-419bd55b-0360-418b-8ba5-c929ddf933a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1133539189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1133539189
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3404995054
Short name T316
Test name
Test status
Simulation time 8291698 ps
CPU time 1.22 seconds
Started Mar 10 02:08:14 PM PDT 24
Finished Mar 10 02:08:15 PM PDT 24
Peak memory 202404 kb
Host smart-c11ffa4f-b8d6-4261-b157-5dcd59a5add5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404995054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3404995054
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2818771146
Short name T516
Test name
Test status
Simulation time 22270527452 ps
CPU time 56.41 seconds
Started Mar 10 02:08:19 PM PDT 24
Finished Mar 10 02:09:15 PM PDT 24
Peak memory 203556 kb
Host smart-2866e8e4-ea87-4414-b6c9-6d82342c8bdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2818771146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2818771146
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3955285740
Short name T443
Test name
Test status
Simulation time 1936858992 ps
CPU time 57 seconds
Started Mar 10 02:08:21 PM PDT 24
Finished Mar 10 02:09:18 PM PDT 24
Peak memory 204672 kb
Host smart-982ef5a5-dc14-4809-bc1c-769b199c3c5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3955285740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3955285740
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2999199675
Short name T657
Test name
Test status
Simulation time 153692073 ps
CPU time 30.99 seconds
Started Mar 10 02:08:21 PM PDT 24
Finished Mar 10 02:08:52 PM PDT 24
Peak memory 204644 kb
Host smart-2dd746e3-7280-4006-a33e-609e22db0416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2999199675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.2999199675
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2155028279
Short name T834
Test name
Test status
Simulation time 7186583972 ps
CPU time 153.24 seconds
Started Mar 10 02:08:19 PM PDT 24
Finished Mar 10 02:10:52 PM PDT 24
Peak memory 208280 kb
Host smart-90e822d4-70b6-4b71-86af-a38f67162cde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2155028279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2155028279
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.734841141
Short name T616
Test name
Test status
Simulation time 566918603 ps
CPU time 9.36 seconds
Started Mar 10 02:08:21 PM PDT 24
Finished Mar 10 02:08:30 PM PDT 24
Peak memory 202448 kb
Host smart-3ad9bfde-64f6-48fe-bd70-81d1fc3d8f97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=734841141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.734841141
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2960725121
Short name T804
Test name
Test status
Simulation time 41409811 ps
CPU time 6.31 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:08:30 PM PDT 24
Peak memory 202484 kb
Host smart-ed8d2c9f-e81a-4bc5-9b32-16b96d03ad14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2960725121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2960725121
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2367294132
Short name T782
Test name
Test status
Simulation time 17960026 ps
CPU time 1.78 seconds
Started Mar 10 02:08:26 PM PDT 24
Finished Mar 10 02:08:28 PM PDT 24
Peak memory 202456 kb
Host smart-2f8ffe99-566f-42fa-9355-5cd0939238d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2367294132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2367294132
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.2346519062
Short name T859
Test name
Test status
Simulation time 1112303083 ps
CPU time 8.88 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:08:33 PM PDT 24
Peak memory 202380 kb
Host smart-a7710550-ad46-4a19-be86-6cf3e21c0657
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346519062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2346519062
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.2513457467
Short name T261
Test name
Test status
Simulation time 153039876 ps
CPU time 6.22 seconds
Started Mar 10 02:08:21 PM PDT 24
Finished Mar 10 02:08:27 PM PDT 24
Peak memory 202400 kb
Host smart-57e9c2bc-ec80-4e25-8c2f-2a35f9127e8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2513457467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2513457467
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1785066110
Short name T710
Test name
Test status
Simulation time 23420194400 ps
CPU time 78.56 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:09:43 PM PDT 24
Peak memory 202572 kb
Host smart-48b9fcfd-4b00-4f46-878a-858dcbc931b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785066110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1785066110
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3973652310
Short name T412
Test name
Test status
Simulation time 26437719273 ps
CPU time 112.11 seconds
Started Mar 10 02:08:26 PM PDT 24
Finished Mar 10 02:10:19 PM PDT 24
Peak memory 202384 kb
Host smart-24cb2391-6ac1-46cb-8b32-4994d6b03383
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3973652310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3973652310
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1326122020
Short name T489
Test name
Test status
Simulation time 36181474 ps
CPU time 3.33 seconds
Started Mar 10 02:08:25 PM PDT 24
Finished Mar 10 02:08:28 PM PDT 24
Peak memory 202388 kb
Host smart-c1488856-7743-43b2-8c9b-6255887216a7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326122020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1326122020
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.1750362838
Short name T783
Test name
Test status
Simulation time 30569646 ps
CPU time 2.96 seconds
Started Mar 10 02:08:23 PM PDT 24
Finished Mar 10 02:08:26 PM PDT 24
Peak memory 202448 kb
Host smart-32bc7b4f-f7a8-4bb6-ab34-b88a57a156ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1750362838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1750362838
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.2971109982
Short name T36
Test name
Test status
Simulation time 13363418 ps
CPU time 1.38 seconds
Started Mar 10 02:08:18 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202388 kb
Host smart-f4896613-f217-4ef2-aa69-02a2091a8c0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2971109982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2971109982
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2990389679
Short name T619
Test name
Test status
Simulation time 4113550376 ps
CPU time 12.42 seconds
Started Mar 10 02:08:19 PM PDT 24
Finished Mar 10 02:08:31 PM PDT 24
Peak memory 202488 kb
Host smart-911d732e-d258-4f23-a210-e00a3299dd17
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990389679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2990389679
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3938788142
Short name T679
Test name
Test status
Simulation time 1523299826 ps
CPU time 7.74 seconds
Started Mar 10 02:08:18 PM PDT 24
Finished Mar 10 02:08:26 PM PDT 24
Peak memory 202444 kb
Host smart-f0189ad5-91f3-4990-9921-368a29ec02b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3938788142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3938788142
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3943043628
Short name T763
Test name
Test status
Simulation time 19773940 ps
CPU time 1.12 seconds
Started Mar 10 02:08:19 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202444 kb
Host smart-ebe8379f-52e2-4eab-9b4d-76a0b4e25433
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943043628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3943043628
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1486875089
Short name T705
Test name
Test status
Simulation time 1446838796 ps
CPU time 28.74 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:08:53 PM PDT 24
Peak memory 202408 kb
Host smart-07b4a5cb-0239-422c-9136-a9e46a4528a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486875089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1486875089
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.690883603
Short name T315
Test name
Test status
Simulation time 515581619 ps
CPU time 24.21 seconds
Started Mar 10 02:08:25 PM PDT 24
Finished Mar 10 02:08:49 PM PDT 24
Peak memory 202440 kb
Host smart-8cba56a0-6e7e-46ea-b5b4-2e0cfe8b3565
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=690883603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.690883603
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1911539947
Short name T463
Test name
Test status
Simulation time 69573847 ps
CPU time 10 seconds
Started Mar 10 02:08:25 PM PDT 24
Finished Mar 10 02:08:35 PM PDT 24
Peak memory 202456 kb
Host smart-9e343351-edae-43df-8db9-9f9fa963c396
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911539947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.1911539947
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.194973253
Short name T691
Test name
Test status
Simulation time 751579503 ps
CPU time 111.94 seconds
Started Mar 10 02:08:26 PM PDT 24
Finished Mar 10 02:10:18 PM PDT 24
Peak memory 206896 kb
Host smart-879fa3ed-5186-46b3-89bf-3d7b6da00c14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=194973253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res
et_error.194973253
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.183239928
Short name T486
Test name
Test status
Simulation time 268603991 ps
CPU time 7.62 seconds
Started Mar 10 02:08:22 PM PDT 24
Finished Mar 10 02:08:31 PM PDT 24
Peak memory 202412 kb
Host smart-b78450b7-d5a7-45ac-8b1f-86c930d882dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=183239928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.183239928
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2585239758
Short name T459
Test name
Test status
Simulation time 2800032515 ps
CPU time 20.75 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:08:51 PM PDT 24
Peak memory 202560 kb
Host smart-a31b2a77-67b2-45a2-96f1-a3fcc514d80b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2585239758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2585239758
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3250364316
Short name T224
Test name
Test status
Simulation time 112765536781 ps
CPU time 205.65 seconds
Started Mar 10 02:08:29 PM PDT 24
Finished Mar 10 02:11:55 PM PDT 24
Peak memory 203724 kb
Host smart-76c51acc-2971-42d3-bf32-4586b8a8fe1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3250364316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.3250364316
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3975222555
Short name T717
Test name
Test status
Simulation time 330767854 ps
CPU time 5.47 seconds
Started Mar 10 02:08:28 PM PDT 24
Finished Mar 10 02:08:34 PM PDT 24
Peak memory 202472 kb
Host smart-cdd4ab3a-90d6-4f68-804f-2a11335fb5bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3975222555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3975222555
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.1912767833
Short name T246
Test name
Test status
Simulation time 84217292 ps
CPU time 6.84 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 202444 kb
Host smart-98ad0466-d7aa-4b37-b98f-0b6154304732
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1912767833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1912767833
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1728073768
Short name T59
Test name
Test status
Simulation time 705503215 ps
CPU time 4.84 seconds
Started Mar 10 02:08:28 PM PDT 24
Finished Mar 10 02:08:33 PM PDT 24
Peak memory 202392 kb
Host smart-b3a1eeb8-79ae-4f46-ab1b-6c174e0bd545
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1728073768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1728073768
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3778130751
Short name T204
Test name
Test status
Simulation time 78357669460 ps
CPU time 147.42 seconds
Started Mar 10 02:08:29 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202572 kb
Host smart-7165e871-20f8-4002-980f-f3dbe35e9266
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778130751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3778130751
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.481342431
Short name T694
Test name
Test status
Simulation time 11972587217 ps
CPU time 87.97 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:09:58 PM PDT 24
Peak memory 202504 kb
Host smart-316f4c4a-17b2-4ee1-ae62-22b36ac28649
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=481342431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.481342431
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.342531936
Short name T593
Test name
Test status
Simulation time 65606312 ps
CPU time 6.45 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 202456 kb
Host smart-70c79948-9a4c-4a7e-b4b0-a598836ca1f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342531936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.342531936
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.4003547559
Short name T93
Test name
Test status
Simulation time 12658287 ps
CPU time 1.4 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:08:32 PM PDT 24
Peak memory 202480 kb
Host smart-2652b1af-c95f-4ce4-8c81-7bfa2b25c07e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003547559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4003547559
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.3523908064
Short name T771
Test name
Test status
Simulation time 52635720 ps
CPU time 1.45 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:08:26 PM PDT 24
Peak memory 202384 kb
Host smart-07ad2346-03fa-4a32-9ddb-d42a2c904e71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3523908064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3523908064
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1892759700
Short name T366
Test name
Test status
Simulation time 2743049636 ps
CPU time 7.71 seconds
Started Mar 10 02:08:23 PM PDT 24
Finished Mar 10 02:08:31 PM PDT 24
Peak memory 202572 kb
Host smart-d3176239-5863-4b31-84a5-373db1c05870
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892759700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1892759700
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3959141696
Short name T654
Test name
Test status
Simulation time 5358172778 ps
CPU time 12.95 seconds
Started Mar 10 02:08:24 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 202500 kb
Host smart-3e29df0a-2f4e-446f-bf42-8d80b1a040ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3959141696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3959141696
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2563014995
Short name T889
Test name
Test status
Simulation time 9291750 ps
CPU time 1.31 seconds
Started Mar 10 02:08:25 PM PDT 24
Finished Mar 10 02:08:26 PM PDT 24
Peak memory 202436 kb
Host smart-2d7a4c7d-4af5-4be2-87c0-272555e93b94
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563014995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2563014995
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.488222076
Short name T260
Test name
Test status
Simulation time 311290198 ps
CPU time 32.83 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:09:03 PM PDT 24
Peak memory 202356 kb
Host smart-f70702f2-464a-42be-aa64-ab8bcbdbe93a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=488222076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.488222076
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3861226507
Short name T144
Test name
Test status
Simulation time 319412527 ps
CPU time 51.06 seconds
Started Mar 10 02:08:29 PM PDT 24
Finished Mar 10 02:09:20 PM PDT 24
Peak memory 204416 kb
Host smart-e29f0107-7abd-4965-9c24-4bc4892a45fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3861226507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3861226507
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.773021717
Short name T241
Test name
Test status
Simulation time 733226719 ps
CPU time 88.65 seconds
Started Mar 10 02:08:37 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 204648 kb
Host smart-521663c3-cc5b-417f-89ea-75cd3516bfb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773021717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.773021717
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1370879033
Short name T612
Test name
Test status
Simulation time 65898646 ps
CPU time 6.54 seconds
Started Mar 10 02:08:30 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 202384 kb
Host smart-919bffa7-c85f-46da-802e-d19d0bb2d7b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370879033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1370879033
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1736285677
Short name T403
Test name
Test status
Simulation time 29674774 ps
CPU time 7.05 seconds
Started Mar 10 02:08:37 PM PDT 24
Finished Mar 10 02:08:44 PM PDT 24
Peak memory 202324 kb
Host smart-fa31e44a-74ce-4ea8-a0e8-c873dbfe71c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1736285677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1736285677
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3754129422
Short name T720
Test name
Test status
Simulation time 55006486755 ps
CPU time 341.62 seconds
Started Mar 10 02:08:32 PM PDT 24
Finished Mar 10 02:14:14 PM PDT 24
Peak memory 203984 kb
Host smart-b53b4944-0f2b-4641-b861-e1c154fc0be3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3754129422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.3754129422
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1849683148
Short name T469
Test name
Test status
Simulation time 3119749138 ps
CPU time 10.19 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:08:49 PM PDT 24
Peak memory 202552 kb
Host smart-6cf2808b-4207-4ff2-a103-51b1c32e3848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1849683148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1849683148
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3915517178
Short name T758
Test name
Test status
Simulation time 78933317 ps
CPU time 9.07 seconds
Started Mar 10 02:08:36 PM PDT 24
Finished Mar 10 02:08:45 PM PDT 24
Peak memory 202440 kb
Host smart-7428af04-2119-4a5e-813c-62796bd97f97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3915517178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3915517178
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.1744020194
Short name T173
Test name
Test status
Simulation time 92997018 ps
CPU time 9.37 seconds
Started Mar 10 02:08:35 PM PDT 24
Finished Mar 10 02:08:45 PM PDT 24
Peak memory 202364 kb
Host smart-484deff1-beb6-49eb-a6aa-7de5c3659d30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744020194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1744020194
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.132804061
Short name T539
Test name
Test status
Simulation time 9603700838 ps
CPU time 37.4 seconds
Started Mar 10 02:08:34 PM PDT 24
Finished Mar 10 02:09:12 PM PDT 24
Peak memory 202568 kb
Host smart-148bc82c-758d-478d-9cb2-56e7f9fc7ea1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=132804061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.132804061
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1789344223
Short name T186
Test name
Test status
Simulation time 39161366317 ps
CPU time 60.61 seconds
Started Mar 10 02:08:34 PM PDT 24
Finished Mar 10 02:09:34 PM PDT 24
Peak memory 202580 kb
Host smart-5db6a763-848e-4f57-a684-520f6f207599
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1789344223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1789344223
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2464459404
Short name T810
Test name
Test status
Simulation time 8085026 ps
CPU time 1.08 seconds
Started Mar 10 02:08:34 PM PDT 24
Finished Mar 10 02:08:36 PM PDT 24
Peak memory 202480 kb
Host smart-86c05f40-4689-4f5d-affd-6bc69f57eded
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464459404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2464459404
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.4146238840
Short name T497
Test name
Test status
Simulation time 47810653 ps
CPU time 4.81 seconds
Started Mar 10 02:08:34 PM PDT 24
Finished Mar 10 02:08:39 PM PDT 24
Peak memory 202432 kb
Host smart-5e3b40ab-fde0-4fe8-841c-dd3842340a95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4146238840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4146238840
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.1409533556
Short name T538
Test name
Test status
Simulation time 96858027 ps
CPU time 1.6 seconds
Started Mar 10 02:08:34 PM PDT 24
Finished Mar 10 02:08:35 PM PDT 24
Peak memory 202384 kb
Host smart-9073342a-23e5-4ac6-8f0f-4c77ce96464d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1409533556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1409533556
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3962518628
Short name T898
Test name
Test status
Simulation time 4163178391 ps
CPU time 6.32 seconds
Started Mar 10 02:08:37 PM PDT 24
Finished Mar 10 02:08:44 PM PDT 24
Peak memory 202460 kb
Host smart-94740fe7-1dcd-45ac-a710-da34f05a4ee6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962518628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3962518628
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2513898416
Short name T472
Test name
Test status
Simulation time 1757745857 ps
CPU time 10.04 seconds
Started Mar 10 02:08:33 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 202428 kb
Host smart-4ce70163-67b3-4754-b18c-61d51aab913d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2513898416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2513898416
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3979733974
Short name T400
Test name
Test status
Simulation time 8414400 ps
CPU time 1.16 seconds
Started Mar 10 02:08:35 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 202376 kb
Host smart-0013c90e-f618-4085-9a5e-89318e43017b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979733974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3979733974
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1891741670
Short name T847
Test name
Test status
Simulation time 170692563 ps
CPU time 4.16 seconds
Started Mar 10 02:08:40 PM PDT 24
Finished Mar 10 02:08:45 PM PDT 24
Peak memory 202392 kb
Host smart-1708fb02-4be1-4968-b5ea-e5539f6e6013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1891741670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1891741670
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.696222722
Short name T813
Test name
Test status
Simulation time 82366533 ps
CPU time 2.5 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:08:41 PM PDT 24
Peak memory 202440 kb
Host smart-69bcf1e5-468d-4b5b-8fd5-718966bcc80a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=696222722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.696222722
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2196506738
Short name T373
Test name
Test status
Simulation time 1188746758 ps
CPU time 82.75 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 205024 kb
Host smart-d0c3c854-d59d-46d6-b3f4-c47d6c8b3d5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2196506738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.2196506738
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.629981807
Short name T193
Test name
Test status
Simulation time 11571580 ps
CPU time 1.22 seconds
Started Mar 10 02:08:38 PM PDT 24
Finished Mar 10 02:08:39 PM PDT 24
Peak memory 202436 kb
Host smart-bd0a070b-fb59-4c5d-adb6-de4118a4993b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=629981807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.629981807
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1931095471
Short name T632
Test name
Test status
Simulation time 1092026965 ps
CPU time 21.94 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:09:01 PM PDT 24
Peak memory 202460 kb
Host smart-a7d66ccd-670a-41f1-acbf-49386e025d04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931095471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1931095471
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3036080465
Short name T222
Test name
Test status
Simulation time 37872068311 ps
CPU time 188.8 seconds
Started Mar 10 02:08:42 PM PDT 24
Finished Mar 10 02:11:51 PM PDT 24
Peak memory 203536 kb
Host smart-7ac59a06-d6df-48a6-86cc-164b0e3abc1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3036080465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3036080465
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3220545619
Short name T357
Test name
Test status
Simulation time 1371951923 ps
CPU time 4.05 seconds
Started Mar 10 02:08:45 PM PDT 24
Finished Mar 10 02:08:50 PM PDT 24
Peak memory 202412 kb
Host smart-361d995b-26c7-42ee-a823-f8217d4771a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220545619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3220545619
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.2676379573
Short name T434
Test name
Test status
Simulation time 911684023 ps
CPU time 7.46 seconds
Started Mar 10 02:08:38 PM PDT 24
Finished Mar 10 02:08:46 PM PDT 24
Peak memory 202440 kb
Host smart-5a0bf638-d59e-4ef1-b1e0-b7d6bc8257b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676379573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2676379573
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.4006387844
Short name T646
Test name
Test status
Simulation time 2843102313 ps
CPU time 14.69 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:08:54 PM PDT 24
Peak memory 202528 kb
Host smart-d10450c5-c673-4ff3-8c2f-c56e0be8321c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4006387844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4006387844
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.4115866714
Short name T724
Test name
Test status
Simulation time 73806795115 ps
CPU time 186.37 seconds
Started Mar 10 02:08:40 PM PDT 24
Finished Mar 10 02:11:47 PM PDT 24
Peak memory 202572 kb
Host smart-1a3a9612-365b-4a49-aa61-f8ffefede242
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115866714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.4115866714
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3488364713
Short name T128
Test name
Test status
Simulation time 41557457881 ps
CPU time 144.02 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:11:04 PM PDT 24
Peak memory 202528 kb
Host smart-0438bd54-7ecd-48ce-8ef9-b6de70d13d78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3488364713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3488364713
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2661315913
Short name T687
Test name
Test status
Simulation time 229966786 ps
CPU time 7.25 seconds
Started Mar 10 02:08:39 PM PDT 24
Finished Mar 10 02:08:47 PM PDT 24
Peak memory 202384 kb
Host smart-159a4a53-c7e3-4128-8696-d9b65cc981ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661315913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2661315913
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.2361068234
Short name T445
Test name
Test status
Simulation time 847855794 ps
CPU time 6.43 seconds
Started Mar 10 02:08:40 PM PDT 24
Finished Mar 10 02:08:46 PM PDT 24
Peak memory 202360 kb
Host smart-2943400b-3216-42ef-a044-6a51b5f70ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2361068234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2361068234
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.3769546433
Short name T603
Test name
Test status
Simulation time 10097307 ps
CPU time 1.11 seconds
Started Mar 10 02:08:42 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 202376 kb
Host smart-3381fa80-e75a-42e9-a297-fe86ed42612d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3769546433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3769546433
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3233337312
Short name T415
Test name
Test status
Simulation time 1291515029 ps
CPU time 6.62 seconds
Started Mar 10 02:08:41 PM PDT 24
Finished Mar 10 02:08:48 PM PDT 24
Peak memory 202388 kb
Host smart-fbcdbbe7-d134-4c30-82f5-a05a7d3f14ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233337312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3233337312
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.82016477
Short name T597
Test name
Test status
Simulation time 1249623412 ps
CPU time 6.51 seconds
Started Mar 10 02:08:37 PM PDT 24
Finished Mar 10 02:08:44 PM PDT 24
Peak memory 202460 kb
Host smart-6b45e946-c47d-401e-b8e3-d950e26d5572
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82016477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.82016477
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2263972487
Short name T835
Test name
Test status
Simulation time 20454288 ps
CPU time 1.14 seconds
Started Mar 10 02:08:41 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 202412 kb
Host smart-ce65460c-c9e3-42d0-b0e6-34cd080d4d15
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263972487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2263972487
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.431862793
Short name T358
Test name
Test status
Simulation time 4069744329 ps
CPU time 68.99 seconds
Started Mar 10 02:08:46 PM PDT 24
Finished Mar 10 02:09:55 PM PDT 24
Peak memory 202580 kb
Host smart-4f22fab3-24df-4603-87cd-33893ac02376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=431862793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.431862793
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1690913155
Short name T614
Test name
Test status
Simulation time 268769708 ps
CPU time 23.42 seconds
Started Mar 10 02:08:46 PM PDT 24
Finished Mar 10 02:09:09 PM PDT 24
Peak memory 202416 kb
Host smart-9f02d1c4-9060-4b69-b3d0-efc1869fae0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690913155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1690913155
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.111961977
Short name T744
Test name
Test status
Simulation time 8419803917 ps
CPU time 86.24 seconds
Started Mar 10 02:08:46 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 205048 kb
Host smart-e3e7d7bb-73cc-44e0-aeab-7c6899b4d90f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111961977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.111961977
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.698805518
Short name T605
Test name
Test status
Simulation time 745270471 ps
CPU time 55.89 seconds
Started Mar 10 02:08:45 PM PDT 24
Finished Mar 10 02:09:42 PM PDT 24
Peak memory 203460 kb
Host smart-368395e7-ebce-4d40-9f8e-75480a7e1eb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698805518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res
et_error.698805518
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1003062519
Short name T416
Test name
Test status
Simulation time 87149987 ps
CPU time 1.78 seconds
Started Mar 10 02:08:40 PM PDT 24
Finished Mar 10 02:08:41 PM PDT 24
Peak memory 202384 kb
Host smart-ca655529-77a9-41b8-a610-5668f1d652a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1003062519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1003062519
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2424799498
Short name T752
Test name
Test status
Simulation time 2118340616 ps
CPU time 21.76 seconds
Started Mar 10 02:08:50 PM PDT 24
Finished Mar 10 02:09:12 PM PDT 24
Peak memory 202452 kb
Host smart-e97507ef-fc52-42ea-9236-cfd4f16a5f01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2424799498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2424799498
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.916949914
Short name T681
Test name
Test status
Simulation time 57243492483 ps
CPU time 229.95 seconds
Started Mar 10 02:08:53 PM PDT 24
Finished Mar 10 02:12:43 PM PDT 24
Peak memory 203532 kb
Host smart-ff42243e-097b-4bca-9e9f-38b53ee04516
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=916949914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo
w_rsp.916949914
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3702494287
Short name T807
Test name
Test status
Simulation time 147800526 ps
CPU time 5.57 seconds
Started Mar 10 02:08:51 PM PDT 24
Finished Mar 10 02:08:57 PM PDT 24
Peak memory 202408 kb
Host smart-38302a37-e24d-4371-92e8-6932e0c6dc9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3702494287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3702494287
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.3823215133
Short name T690
Test name
Test status
Simulation time 148657963 ps
CPU time 1.9 seconds
Started Mar 10 02:08:49 PM PDT 24
Finished Mar 10 02:08:51 PM PDT 24
Peak memory 202436 kb
Host smart-482b1c09-8b05-471c-b15c-c9ef88d79156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3823215133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3823215133
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.720133733
Short name T58
Test name
Test status
Simulation time 324559724 ps
CPU time 3.17 seconds
Started Mar 10 02:08:46 PM PDT 24
Finished Mar 10 02:08:49 PM PDT 24
Peak memory 202384 kb
Host smart-aed89488-f69a-4fc8-9da7-495142c6155f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=720133733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.720133733
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2492879341
Short name T567
Test name
Test status
Simulation time 70226795757 ps
CPU time 139.4 seconds
Started Mar 10 02:08:54 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202508 kb
Host smart-7a58114e-ac48-4019-9003-4381f6e419ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492879341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2492879341
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.662077077
Short name T153
Test name
Test status
Simulation time 22908163091 ps
CPU time 149.24 seconds
Started Mar 10 02:08:51 PM PDT 24
Finished Mar 10 02:11:21 PM PDT 24
Peak memory 202584 kb
Host smart-b031107a-85cd-4807-86f6-b0b102066216
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=662077077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.662077077
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.554684537
Short name T394
Test name
Test status
Simulation time 61986977 ps
CPU time 7.91 seconds
Started Mar 10 02:08:45 PM PDT 24
Finished Mar 10 02:08:54 PM PDT 24
Peak memory 202384 kb
Host smart-8b2bb434-1a36-46ce-a641-3aa2b84af826
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554684537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.554684537
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.3913896047
Short name T368
Test name
Test status
Simulation time 693545900 ps
CPU time 4.02 seconds
Started Mar 10 02:08:50 PM PDT 24
Finished Mar 10 02:08:54 PM PDT 24
Peak memory 202356 kb
Host smart-999bc0f6-2348-4067-9657-5333d6c68bc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3913896047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3913896047
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2794221865
Short name T195
Test name
Test status
Simulation time 10615160 ps
CPU time 1.2 seconds
Started Mar 10 02:08:47 PM PDT 24
Finished Mar 10 02:08:48 PM PDT 24
Peak memory 202324 kb
Host smart-8b69b883-6ec3-40b9-b544-94d7e39bf9a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2794221865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2794221865
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.560172759
Short name T893
Test name
Test status
Simulation time 3323537416 ps
CPU time 11.39 seconds
Started Mar 10 02:08:43 PM PDT 24
Finished Mar 10 02:08:55 PM PDT 24
Peak memory 202500 kb
Host smart-50fe70bf-3789-4d15-96c5-d86017182829
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=560172759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.560172759
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.646044287
Short name T27
Test name
Test status
Simulation time 902650992 ps
CPU time 6.67 seconds
Started Mar 10 02:08:45 PM PDT 24
Finished Mar 10 02:08:53 PM PDT 24
Peak memory 202428 kb
Host smart-47b80c22-ebfd-455f-adc6-7475de162031
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=646044287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.646044287
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2218745175
Short name T96
Test name
Test status
Simulation time 9654684 ps
CPU time 1.05 seconds
Started Mar 10 02:08:45 PM PDT 24
Finished Mar 10 02:08:47 PM PDT 24
Peak memory 202448 kb
Host smart-7962bbef-187f-4aa4-a854-755243972b25
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218745175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2218745175
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1782308034
Short name T860
Test name
Test status
Simulation time 8737008644 ps
CPU time 106.78 seconds
Started Mar 10 02:08:51 PM PDT 24
Finished Mar 10 02:10:39 PM PDT 24
Peak memory 204488 kb
Host smart-9f393fd9-3f40-41e5-a8e0-2af5630aebde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782308034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1782308034
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3444556194
Short name T266
Test name
Test status
Simulation time 262583115 ps
CPU time 31.54 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:09:27 PM PDT 24
Peak memory 202364 kb
Host smart-1838c4ca-e625-42fd-8c4a-eada63bf6964
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3444556194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3444556194
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1401928916
Short name T537
Test name
Test status
Simulation time 2540235287 ps
CPU time 55.2 seconds
Started Mar 10 02:08:53 PM PDT 24
Finished Mar 10 02:09:48 PM PDT 24
Peak memory 204868 kb
Host smart-5438bb31-fcc5-4295-b494-a521771a840d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1401928916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.1401928916
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4200389259
Short name T318
Test name
Test status
Simulation time 636922303 ps
CPU time 66.49 seconds
Started Mar 10 02:08:57 PM PDT 24
Finished Mar 10 02:10:04 PM PDT 24
Peak memory 203780 kb
Host smart-64416a75-7cb3-4993-841d-b5f6c7aeaa95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4200389259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.4200389259
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2446879462
Short name T393
Test name
Test status
Simulation time 397292925 ps
CPU time 7.86 seconds
Started Mar 10 02:08:51 PM PDT 24
Finished Mar 10 02:08:59 PM PDT 24
Peak memory 202436 kb
Host smart-89e3e2f5-8771-423f-9b45-553ebb2790f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2446879462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2446879462
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1639902463
Short name T228
Test name
Test status
Simulation time 744158831 ps
CPU time 10.39 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:08 PM PDT 24
Peak memory 202452 kb
Host smart-6d11f15a-b940-486e-a2dd-16e23910e450
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1639902463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1639902463
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.585102978
Short name T120
Test name
Test status
Simulation time 50257638674 ps
CPU time 227.16 seconds
Started Mar 10 02:08:57 PM PDT 24
Finished Mar 10 02:12:45 PM PDT 24
Peak memory 204944 kb
Host smart-bfea0440-8469-4344-8e17-f65a16859eb8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=585102978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.585102978
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2799016889
Short name T822
Test name
Test status
Simulation time 72276989 ps
CPU time 3.04 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:00 PM PDT 24
Peak memory 202416 kb
Host smart-5c1e3bfc-a394-4969-aec7-e5b115a48bce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2799016889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2799016889
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.997057799
Short name T708
Test name
Test status
Simulation time 38249692 ps
CPU time 3.96 seconds
Started Mar 10 02:08:58 PM PDT 24
Finished Mar 10 02:09:04 PM PDT 24
Peak memory 202448 kb
Host smart-e415ea6c-f6f3-4996-a133-afb93ceaff22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=997057799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.997057799
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.3259145938
Short name T703
Test name
Test status
Simulation time 170602847 ps
CPU time 2.47 seconds
Started Mar 10 02:08:58 PM PDT 24
Finished Mar 10 02:09:02 PM PDT 24
Peak memory 202396 kb
Host smart-8c1de3fa-595c-4818-8070-40bbbad382ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3259145938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3259145938
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2886256287
Short name T203
Test name
Test status
Simulation time 10431493525 ps
CPU time 30.9 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:27 PM PDT 24
Peak memory 202548 kb
Host smart-4fe189cb-b50e-4fbd-bc3c-cd0bcce240f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886256287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2886256287
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3316244306
Short name T820
Test name
Test status
Simulation time 1827528604 ps
CPU time 13.13 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202400 kb
Host smart-6e8e4e96-3ccc-4998-afa0-664ea98429ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3316244306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3316244306
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3845642009
Short name T844
Test name
Test status
Simulation time 55822301 ps
CPU time 3.72 seconds
Started Mar 10 02:09:01 PM PDT 24
Finished Mar 10 02:09:05 PM PDT 24
Peak memory 202440 kb
Host smart-c21cbae9-429a-4f40-aa9e-71858b4d70d9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845642009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3845642009
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.657877072
Short name T146
Test name
Test status
Simulation time 134602175 ps
CPU time 5.38 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:03 PM PDT 24
Peak memory 202440 kb
Host smart-bd237ef9-cec1-44b3-b2da-26990846a298
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=657877072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.657877072
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.3302057945
Short name T801
Test name
Test status
Simulation time 48903949 ps
CPU time 1.52 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:08:57 PM PDT 24
Peak memory 202324 kb
Host smart-cbb569a0-957a-4d33-bac1-5ae8c5797381
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302057945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3302057945
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3900211827
Short name T347
Test name
Test status
Simulation time 3116085979 ps
CPU time 10.74 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:08 PM PDT 24
Peak memory 202564 kb
Host smart-63cd06f5-709b-46a9-8345-d786484ecb65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900211827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3900211827
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1267132629
Short name T495
Test name
Test status
Simulation time 3675978002 ps
CPU time 11.38 seconds
Started Mar 10 02:08:57 PM PDT 24
Finished Mar 10 02:09:09 PM PDT 24
Peak memory 202496 kb
Host smart-3d043198-122a-45eb-9d54-fcfe4ad16539
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1267132629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1267132629
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2973527848
Short name T618
Test name
Test status
Simulation time 11895634 ps
CPU time 1.15 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:08:57 PM PDT 24
Peak memory 202464 kb
Host smart-4fbfc145-2352-4f14-beb1-8f22c4015b8c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973527848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2973527848
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2268819131
Short name T156
Test name
Test status
Simulation time 1599789042 ps
CPU time 25.42 seconds
Started Mar 10 02:08:58 PM PDT 24
Finished Mar 10 02:09:25 PM PDT 24
Peak memory 202440 kb
Host smart-8545d099-a655-419e-9b49-9b949fc59b39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2268819131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2268819131
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3558106767
Short name T432
Test name
Test status
Simulation time 1058644450 ps
CPU time 19.68 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:17 PM PDT 24
Peak memory 202464 kb
Host smart-0fab62e6-c42c-415f-894d-98a6a055880e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558106767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3558106767
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2739285596
Short name T795
Test name
Test status
Simulation time 242120304 ps
CPU time 15.94 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:09:11 PM PDT 24
Peak memory 203396 kb
Host smart-479213f5-2564-4d25-bdd2-4e269b6b5744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739285596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2739285596
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2263427597
Short name T307
Test name
Test status
Simulation time 8985036274 ps
CPU time 74.29 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 204712 kb
Host smart-a17cd917-8eb5-4ed8-9e6d-159480946c23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2263427597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2263427597
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2289359198
Short name T631
Test name
Test status
Simulation time 30485605 ps
CPU time 3.68 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:01 PM PDT 24
Peak memory 202420 kb
Host smart-34f2b065-3010-44fd-9875-68307bbfa5a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2289359198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2289359198
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2665262649
Short name T163
Test name
Test status
Simulation time 1200316546 ps
CPU time 11.01 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:09:08 PM PDT 24
Peak memory 202456 kb
Host smart-8a316122-a00e-4e4a-af51-d9f25e93d42e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2665262649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2665262649
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3755041416
Short name T19
Test name
Test status
Simulation time 46821670455 ps
CPU time 85.47 seconds
Started Mar 10 02:09:04 PM PDT 24
Finished Mar 10 02:10:32 PM PDT 24
Peak memory 202520 kb
Host smart-3ff0df5a-1e1f-46bb-b1ec-f555c60ae042
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3755041416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.3755041416
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3866649888
Short name T91
Test name
Test status
Simulation time 45469083 ps
CPU time 4.12 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:11 PM PDT 24
Peak memory 202444 kb
Host smart-beb9ecd1-ef4f-4c8d-be6e-d4cd0990ff79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3866649888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3866649888
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.71366661
Short name T257
Test name
Test status
Simulation time 1503324510 ps
CPU time 11.05 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:14 PM PDT 24
Peak memory 202444 kb
Host smart-31a07836-ca17-4164-9258-6725b1496d87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71366661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.71366661
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.437068564
Short name T644
Test name
Test status
Simulation time 549947006 ps
CPU time 4.89 seconds
Started Mar 10 02:08:57 PM PDT 24
Finished Mar 10 02:09:03 PM PDT 24
Peak memory 202324 kb
Host smart-8289733b-b7cb-45a1-beec-7174461d95db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=437068564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.437068564
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.14402842
Short name T557
Test name
Test status
Simulation time 172304274128 ps
CPU time 121.07 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202580 kb
Host smart-556b7b23-7225-43af-9984-4bbed80feefc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.14402842
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3478694908
Short name T523
Test name
Test status
Simulation time 8946898677 ps
CPU time 30.56 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:09:26 PM PDT 24
Peak memory 202544 kb
Host smart-ad86f719-21b7-4bfd-a952-13358a645aab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3478694908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3478694908
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3735779036
Short name T372
Test name
Test status
Simulation time 40151838 ps
CPU time 6.53 seconds
Started Mar 10 02:08:57 PM PDT 24
Finished Mar 10 02:09:04 PM PDT 24
Peak memory 202428 kb
Host smart-9595fe90-c5c0-417c-963a-ff378e89a1f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735779036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3735779036
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.1029786329
Short name T568
Test name
Test status
Simulation time 396282068 ps
CPU time 6.54 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:09 PM PDT 24
Peak memory 202432 kb
Host smart-4b0dbc96-a622-4049-8f3f-2534055698a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1029786329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1029786329
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.1073842465
Short name T742
Test name
Test status
Simulation time 53862294 ps
CPU time 1.61 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:08:59 PM PDT 24
Peak memory 202380 kb
Host smart-f5d5baf4-17ef-420d-ac43-f294a8f70847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1073842465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1073842465
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3853983691
Short name T363
Test name
Test status
Simulation time 1868960462 ps
CPU time 7.05 seconds
Started Mar 10 02:08:54 PM PDT 24
Finished Mar 10 02:09:02 PM PDT 24
Peak memory 202368 kb
Host smart-d78cfec1-a1b3-4f6c-9333-1c240f2bc31a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853983691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3853983691
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2275983375
Short name T896
Test name
Test status
Simulation time 1337042430 ps
CPU time 8.83 seconds
Started Mar 10 02:08:55 PM PDT 24
Finished Mar 10 02:09:05 PM PDT 24
Peak memory 202460 kb
Host smart-75f6d1b9-ee50-4668-be61-456d3aa9209e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2275983375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2275983375
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1863617965
Short name T449
Test name
Test status
Simulation time 10027771 ps
CPU time 1.22 seconds
Started Mar 10 02:08:56 PM PDT 24
Finished Mar 10 02:08:58 PM PDT 24
Peak memory 202464 kb
Host smart-4c2beffe-d0e6-455f-89cb-1cf6c53a1b8a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863617965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1863617965
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.2305536438
Short name T757
Test name
Test status
Simulation time 16669009573 ps
CPU time 100.22 seconds
Started Mar 10 02:09:04 PM PDT 24
Finished Mar 10 02:10:47 PM PDT 24
Peak memory 205084 kb
Host smart-53ee155f-337e-4a87-84cc-c7671dce72d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2305536438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2305536438
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.273840436
Short name T233
Test name
Test status
Simulation time 5903346838 ps
CPU time 76.18 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:10:23 PM PDT 24
Peak memory 203588 kb
Host smart-d0393734-adac-414c-9e3e-1fe0c2707c5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273840436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.273840436
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1643151744
Short name T71
Test name
Test status
Simulation time 274341469 ps
CPU time 27.64 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:29 PM PDT 24
Peak memory 203460 kb
Host smart-c516c376-32b4-4d13-96fc-076fec8e25f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1643151744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1643151744
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.34238542
Short name T242
Test name
Test status
Simulation time 172625764 ps
CPU time 9.01 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:11 PM PDT 24
Peak memory 202436 kb
Host smart-57fd8503-a90d-4f38-8fbe-afedda20abb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34238542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rese
t_error.34238542
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.842417278
Short name T171
Test name
Test status
Simulation time 199083858 ps
CPU time 4.59 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:07 PM PDT 24
Peak memory 202404 kb
Host smart-728d54d4-af22-4fdf-9eda-32c4248c7510
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842417278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.842417278
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3384459866
Short name T151
Test name
Test status
Simulation time 197706135 ps
CPU time 4.02 seconds
Started Mar 10 02:07:01 PM PDT 24
Finished Mar 10 02:07:05 PM PDT 24
Peak memory 202444 kb
Host smart-2b62b0fc-e8ef-47d7-b6ae-585b5fcda5c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3384459866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3384459866
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1347915925
Short name T190
Test name
Test status
Simulation time 42505303241 ps
CPU time 249.67 seconds
Started Mar 10 02:07:03 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 203836 kb
Host smart-373554fa-bbfa-4a98-8801-928a0b072c6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1347915925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1347915925
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3366874135
Short name T740
Test name
Test status
Simulation time 1546043884 ps
CPU time 5.52 seconds
Started Mar 10 02:07:06 PM PDT 24
Finished Mar 10 02:07:11 PM PDT 24
Peak memory 202380 kb
Host smart-5cf607a0-d317-4071-8411-ff99ec6879eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3366874135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3366874135
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1217092342
Short name T588
Test name
Test status
Simulation time 818202114 ps
CPU time 11.5 seconds
Started Mar 10 02:07:05 PM PDT 24
Finished Mar 10 02:07:17 PM PDT 24
Peak memory 202388 kb
Host smart-9ce306c7-f6df-484b-918e-23ec61b6dfd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1217092342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1217092342
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.379081188
Short name T680
Test name
Test status
Simulation time 128943521 ps
CPU time 3.64 seconds
Started Mar 10 02:07:00 PM PDT 24
Finished Mar 10 02:07:04 PM PDT 24
Peak memory 202420 kb
Host smart-cae35696-f7c5-47fe-be5c-0554c18cb0f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=379081188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.379081188
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3684227305
Short name T322
Test name
Test status
Simulation time 10312546984 ps
CPU time 39.03 seconds
Started Mar 10 02:07:01 PM PDT 24
Finished Mar 10 02:07:40 PM PDT 24
Peak memory 202568 kb
Host smart-2770eb70-3ad4-412a-83e1-fe35a1ce60c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684227305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3684227305
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1331408362
Short name T116
Test name
Test status
Simulation time 13599675738 ps
CPU time 60 seconds
Started Mar 10 02:07:00 PM PDT 24
Finished Mar 10 02:08:01 PM PDT 24
Peak memory 202572 kb
Host smart-cdeec39a-afde-413f-9774-677f34c344be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1331408362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1331408362
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2268876978
Short name T391
Test name
Test status
Simulation time 194684759 ps
CPU time 7.23 seconds
Started Mar 10 02:07:00 PM PDT 24
Finished Mar 10 02:07:08 PM PDT 24
Peak memory 202472 kb
Host smart-440e1171-8e18-4e50-9812-9a965cbec67c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268876978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2268876978
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.3408961118
Short name T799
Test name
Test status
Simulation time 164301331 ps
CPU time 6.18 seconds
Started Mar 10 02:07:04 PM PDT 24
Finished Mar 10 02:07:10 PM PDT 24
Peak memory 202436 kb
Host smart-68ca1cc0-585f-4f54-baa4-ba5d075886cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3408961118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3408961118
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.208598151
Short name T559
Test name
Test status
Simulation time 189349413 ps
CPU time 1.22 seconds
Started Mar 10 02:06:59 PM PDT 24
Finished Mar 10 02:07:01 PM PDT 24
Peak memory 202424 kb
Host smart-8211dc84-9ef6-4ff0-8627-670137626cf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=208598151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.208598151
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2577851616
Short name T587
Test name
Test status
Simulation time 2787833787 ps
CPU time 11.35 seconds
Started Mar 10 02:07:02 PM PDT 24
Finished Mar 10 02:07:14 PM PDT 24
Peak memory 202516 kb
Host smart-624de0ec-b87e-49f3-8dd2-799ae2577b9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577851616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2577851616
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3008113969
Short name T476
Test name
Test status
Simulation time 1734268646 ps
CPU time 10.27 seconds
Started Mar 10 02:07:01 PM PDT 24
Finished Mar 10 02:07:11 PM PDT 24
Peak memory 202440 kb
Host smart-f0e26bb2-34f7-4e8d-8fba-11a87f7ef5b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3008113969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3008113969
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3458539173
Short name T334
Test name
Test status
Simulation time 21104283 ps
CPU time 1.16 seconds
Started Mar 10 02:07:00 PM PDT 24
Finished Mar 10 02:07:02 PM PDT 24
Peak memory 202420 kb
Host smart-9a0db252-f516-4eb4-b984-7d77506f7682
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458539173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3458539173
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2861076756
Short name T413
Test name
Test status
Simulation time 1198209801 ps
CPU time 27.1 seconds
Started Mar 10 02:07:05 PM PDT 24
Finished Mar 10 02:07:32 PM PDT 24
Peak memory 202448 kb
Host smart-835546f5-75df-4918-adb8-a399eb95fd97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2861076756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2861076756
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.360693736
Short name T787
Test name
Test status
Simulation time 7481961622 ps
CPU time 101.66 seconds
Started Mar 10 02:07:11 PM PDT 24
Finished Mar 10 02:08:53 PM PDT 24
Peak memory 205172 kb
Host smart-7b02fdbb-fe39-40df-acd3-895549162506
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=360693736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.360693736
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3036206951
Short name T883
Test name
Test status
Simulation time 637150730 ps
CPU time 55.63 seconds
Started Mar 10 02:07:04 PM PDT 24
Finished Mar 10 02:08:00 PM PDT 24
Peak memory 204432 kb
Host smart-8bb8d91d-2325-4091-b874-8f94a8afcc72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3036206951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3036206951
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2565092962
Short name T381
Test name
Test status
Simulation time 237184792 ps
CPU time 35.46 seconds
Started Mar 10 02:07:09 PM PDT 24
Finished Mar 10 02:07:45 PM PDT 24
Peak memory 203616 kb
Host smart-ed9441ac-de08-4dcd-98d9-4bc8d529029f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2565092962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.2565092962
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2553651764
Short name T576
Test name
Test status
Simulation time 420323381 ps
CPU time 9.98 seconds
Started Mar 10 02:07:06 PM PDT 24
Finished Mar 10 02:07:16 PM PDT 24
Peak memory 202412 kb
Host smart-44f18f42-6491-4626-8e99-d4628ad04f0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2553651764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2553651764
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1174350121
Short name T136
Test name
Test status
Simulation time 1024582145 ps
CPU time 8.26 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:15 PM PDT 24
Peak memory 202444 kb
Host smart-749fd875-7535-40d9-839b-fbc84a12bfc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174350121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1174350121
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1961920584
Short name T344
Test name
Test status
Simulation time 102873437 ps
CPU time 2.82 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202396 kb
Host smart-359a4509-f3e2-41d8-9910-cae7681b3fce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1961920584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1961920584
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.4042196603
Short name T478
Test name
Test status
Simulation time 56485590 ps
CPU time 2.34 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:04 PM PDT 24
Peak memory 202440 kb
Host smart-735b8737-ff17-4aac-b742-f5cd141e7f64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4042196603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4042196603
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.3605202044
Short name T313
Test name
Test status
Simulation time 1036839959 ps
CPU time 6.64 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:13 PM PDT 24
Peak memory 202360 kb
Host smart-91204e9e-c921-4699-b23c-cfa5b76e57a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3605202044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3605202044
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3315665153
Short name T876
Test name
Test status
Simulation time 1308921880 ps
CPU time 7.34 seconds
Started Mar 10 02:09:05 PM PDT 24
Finished Mar 10 02:09:14 PM PDT 24
Peak memory 202408 kb
Host smart-2091d2b1-e838-4a01-97a3-faf10ce3f0d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315665153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3315665153
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.719010900
Short name T621
Test name
Test status
Simulation time 13993892394 ps
CPU time 78.3 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:10:20 PM PDT 24
Peak memory 202568 kb
Host smart-87054c20-4410-464c-9725-13bf390aa39a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=719010900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.719010900
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.437924611
Short name T430
Test name
Test status
Simulation time 17359204 ps
CPU time 1.58 seconds
Started Mar 10 02:09:05 PM PDT 24
Finished Mar 10 02:09:08 PM PDT 24
Peak memory 202440 kb
Host smart-57530d50-aff8-4204-86b0-d9d3e34caa73
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437924611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.437924611
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3484241140
Short name T331
Test name
Test status
Simulation time 325070016 ps
CPU time 2.47 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:05 PM PDT 24
Peak memory 202432 kb
Host smart-2148a304-8c55-4ed7-acb8-b7de74c5b9c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3484241140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3484241140
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.54053017
Short name T535
Test name
Test status
Simulation time 10481834 ps
CPU time 1.21 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:03 PM PDT 24
Peak memory 202388 kb
Host smart-af071c1b-8da0-4d02-b782-55563169992f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54053017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.54053017
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.4245029251
Short name T282
Test name
Test status
Simulation time 1768514492 ps
CPU time 8.31 seconds
Started Mar 10 02:09:02 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202444 kb
Host smart-d5392dfa-7ce3-477c-8ca8-892bd0d38023
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245029251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4245029251
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3884438278
Short name T470
Test name
Test status
Simulation time 8753379164 ps
CPU time 13.77 seconds
Started Mar 10 02:09:03 PM PDT 24
Finished Mar 10 02:09:20 PM PDT 24
Peak memory 202560 kb
Host smart-814a66e1-6c54-48d0-be59-fff688a48753
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3884438278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3884438278
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3991721498
Short name T314
Test name
Test status
Simulation time 14101649 ps
CPU time 1.16 seconds
Started Mar 10 02:09:06 PM PDT 24
Finished Mar 10 02:09:08 PM PDT 24
Peak memory 202460 kb
Host smart-21ed093e-c1a8-4daf-a0a4-28c1552e39ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991721498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3991721498
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2434220570
Short name T279
Test name
Test status
Simulation time 117781169 ps
CPU time 8.54 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:16 PM PDT 24
Peak memory 202484 kb
Host smart-852081d5-c002-4226-be62-c5f9e7ca4f55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2434220570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2434220570
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1235462946
Short name T31
Test name
Test status
Simulation time 537410147 ps
CPU time 44.12 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:52 PM PDT 24
Peak memory 204488 kb
Host smart-2915b36f-f0e6-45b8-935d-cc8d294ed30a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1235462946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1235462946
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2792309110
Short name T166
Test name
Test status
Simulation time 606993037 ps
CPU time 65.53 seconds
Started Mar 10 02:09:10 PM PDT 24
Finished Mar 10 02:10:16 PM PDT 24
Peak memory 204504 kb
Host smart-352d5a30-381e-496c-b4ac-c78fb5f30d7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2792309110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.2792309110
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3540746660
Short name T645
Test name
Test status
Simulation time 41600052 ps
CPU time 7.65 seconds
Started Mar 10 02:09:13 PM PDT 24
Finished Mar 10 02:09:22 PM PDT 24
Peak memory 202436 kb
Host smart-671032c9-c989-40df-b0b3-8df0dcedbc6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3540746660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3540746660
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.51078298
Short name T108
Test name
Test status
Simulation time 93853631030 ps
CPU time 305.03 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:14:13 PM PDT 24
Peak memory 204808 kb
Host smart-6b44fec3-f1fb-4549-8d85-286142d9e03d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=51078298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow
_rsp.51078298
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3218243064
Short name T768
Test name
Test status
Simulation time 140546225 ps
CPU time 1.46 seconds
Started Mar 10 02:09:15 PM PDT 24
Finished Mar 10 02:09:16 PM PDT 24
Peak memory 202436 kb
Host smart-7546825d-37f9-4c4c-9f35-174a433f8954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3218243064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3218243064
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.2562108891
Short name T573
Test name
Test status
Simulation time 3544795096 ps
CPU time 16.06 seconds
Started Mar 10 02:09:14 PM PDT 24
Finished Mar 10 02:09:31 PM PDT 24
Peak memory 202568 kb
Host smart-562ef4b4-71f1-4ac8-b394-821ff4a0a705
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562108891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2562108891
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.1380716817
Short name T262
Test name
Test status
Simulation time 23953606 ps
CPU time 2.35 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202300 kb
Host smart-e61e0054-f326-4db3-a8aa-db0d51763449
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1380716817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1380716817
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3031993269
Short name T765
Test name
Test status
Simulation time 9406454466 ps
CPU time 18.33 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:27 PM PDT 24
Peak memory 202540 kb
Host smart-d071c89a-4b50-42f4-a183-1f67e4aba246
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031993269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3031993269
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.604691501
Short name T761
Test name
Test status
Simulation time 24567959185 ps
CPU time 116.79 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:11:05 PM PDT 24
Peak memory 202524 kb
Host smart-3fe5e656-3d11-44ca-be0c-aec7fe557ab7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=604691501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.604691501
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1302307538
Short name T548
Test name
Test status
Simulation time 73883839 ps
CPU time 4.17 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:12 PM PDT 24
Peak memory 202456 kb
Host smart-aa2a6711-7d85-402c-acd2-bba5f6247e7c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302307538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1302307538
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.1596556167
Short name T733
Test name
Test status
Simulation time 1450204094 ps
CPU time 13.29 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:21 PM PDT 24
Peak memory 202440 kb
Host smart-b831528d-6a88-4582-9e74-186bb9f31ec1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1596556167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1596556167
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.3560657544
Short name T611
Test name
Test status
Simulation time 9883102 ps
CPU time 1.01 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202384 kb
Host smart-8335fbc7-915b-42a4-a80a-808d5e1a1f67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3560657544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3560657544
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2765591659
Short name T790
Test name
Test status
Simulation time 12055759713 ps
CPU time 12.78 seconds
Started Mar 10 02:09:07 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 202520 kb
Host smart-e224dd53-a80e-4862-96a9-ee5b10718801
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765591659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2765591659
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.125267440
Short name T424
Test name
Test status
Simulation time 5256266230 ps
CPU time 8.25 seconds
Started Mar 10 02:09:08 PM PDT 24
Finished Mar 10 02:09:16 PM PDT 24
Peak memory 202552 kb
Host smart-223c5ada-395d-44d5-b7f1-edde27300939
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=125267440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.125267440
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.919472776
Short name T319
Test name
Test status
Simulation time 9002915 ps
CPU time 1.2 seconds
Started Mar 10 02:09:10 PM PDT 24
Finished Mar 10 02:09:12 PM PDT 24
Peak memory 202452 kb
Host smart-f53aec28-e0de-4ab2-be59-25bd735f3a76
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919472776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.919472776
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2350853371
Short name T764
Test name
Test status
Simulation time 8182533109 ps
CPU time 97.59 seconds
Started Mar 10 02:09:11 PM PDT 24
Finished Mar 10 02:10:50 PM PDT 24
Peak memory 202604 kb
Host smart-89edabb9-84af-44f5-8f2b-606c5a5aa5bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350853371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2350853371
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.823788954
Short name T735
Test name
Test status
Simulation time 1072259045 ps
CPU time 10.84 seconds
Started Mar 10 02:09:13 PM PDT 24
Finished Mar 10 02:09:25 PM PDT 24
Peak memory 202416 kb
Host smart-a75c87c4-348c-4e1b-a84c-c7376fc4ea18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823788954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.823788954
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3036683314
Short name T677
Test name
Test status
Simulation time 838333128 ps
CPU time 113.7 seconds
Started Mar 10 02:09:14 PM PDT 24
Finished Mar 10 02:11:08 PM PDT 24
Peak memory 206740 kb
Host smart-048b14a3-850c-45b1-bc33-bad99c724eed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3036683314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.3036683314
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1854339937
Short name T493
Test name
Test status
Simulation time 174152432 ps
CPU time 6.47 seconds
Started Mar 10 02:09:12 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 202452 kb
Host smart-8f3f09e6-71e2-47c4-a684-36da08abca2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1854339937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1854339937
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1596206993
Short name T47
Test name
Test status
Simulation time 242949263 ps
CPU time 4.89 seconds
Started Mar 10 02:09:13 PM PDT 24
Finished Mar 10 02:09:20 PM PDT 24
Peak memory 202364 kb
Host smart-944ea3ff-30af-4bb2-a26e-a35c7653dff8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1596206993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1596206993
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1982641475
Short name T501
Test name
Test status
Simulation time 4772749716 ps
CPU time 13.16 seconds
Started Mar 10 02:09:20 PM PDT 24
Finished Mar 10 02:09:33 PM PDT 24
Peak memory 202572 kb
Host smart-102e3aa3-6e34-4089-8b53-a07a1f1d52fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1982641475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1982641475
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3715874181
Short name T607
Test name
Test status
Simulation time 114968505754 ps
CPU time 137.94 seconds
Started Mar 10 02:09:17 PM PDT 24
Finished Mar 10 02:11:35 PM PDT 24
Peak memory 202512 kb
Host smart-2bb62250-3cfe-4daf-a9f9-379bc8ee720c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3715874181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3715874181
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4000828828
Short name T533
Test name
Test status
Simulation time 765451529 ps
CPU time 10.96 seconds
Started Mar 10 02:09:17 PM PDT 24
Finished Mar 10 02:09:28 PM PDT 24
Peak memory 202420 kb
Host smart-3126ede2-6e2a-4ee8-ae94-4d6520058044
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4000828828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4000828828
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1529416164
Short name T738
Test name
Test status
Simulation time 1449817764 ps
CPU time 14.84 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:33 PM PDT 24
Peak memory 202412 kb
Host smart-20b620e7-2b75-4a2a-9117-7b5f492c7826
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529416164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1529416164
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.2416589897
Short name T714
Test name
Test status
Simulation time 405260334 ps
CPU time 7.85 seconds
Started Mar 10 02:09:15 PM PDT 24
Finished Mar 10 02:09:23 PM PDT 24
Peak memory 202432 kb
Host smart-bbc15ea0-01e6-4ae9-bb5b-1d356511ba97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2416589897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2416589897
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1927443515
Short name T579
Test name
Test status
Simulation time 38336214219 ps
CPU time 52.17 seconds
Started Mar 10 02:09:20 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 202580 kb
Host smart-22ef4ee2-7151-4c41-b7ca-78e553f4968f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927443515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1927443515
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3579012442
Short name T270
Test name
Test status
Simulation time 93290200114 ps
CPU time 84.95 seconds
Started Mar 10 02:09:17 PM PDT 24
Finished Mar 10 02:10:43 PM PDT 24
Peak memory 202524 kb
Host smart-e97223c0-1447-46a0-80c9-9f07f5363d2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3579012442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3579012442
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.132812252
Short name T433
Test name
Test status
Simulation time 16864738 ps
CPU time 1.86 seconds
Started Mar 10 02:09:15 PM PDT 24
Finished Mar 10 02:09:17 PM PDT 24
Peak memory 202488 kb
Host smart-4eb4020c-a322-43e6-9f80-32ecb0c756e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132812252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.132812252
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1058970551
Short name T95
Test name
Test status
Simulation time 2657418759 ps
CPU time 7.17 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:26 PM PDT 24
Peak memory 202516 kb
Host smart-9e7ebffc-fa44-4d29-b664-284df67088de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1058970551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1058970551
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.3478705902
Short name T829
Test name
Test status
Simulation time 98735619 ps
CPU time 1.58 seconds
Started Mar 10 02:09:14 PM PDT 24
Finished Mar 10 02:09:16 PM PDT 24
Peak memory 202384 kb
Host smart-311f9226-03ce-4635-97b8-981f71e2f1ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478705902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3478705902
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2946741109
Short name T408
Test name
Test status
Simulation time 9600588394 ps
CPU time 11.87 seconds
Started Mar 10 02:09:15 PM PDT 24
Finished Mar 10 02:09:27 PM PDT 24
Peak memory 202524 kb
Host smart-a1b26c78-524d-4522-890d-ca0266903a2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946741109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2946741109
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.606308932
Short name T253
Test name
Test status
Simulation time 4982851882 ps
CPU time 11.91 seconds
Started Mar 10 02:09:12 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202588 kb
Host smart-3d6f74f5-6bdd-40d5-9e07-ca6213090716
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=606308932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.606308932
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3566150632
Short name T609
Test name
Test status
Simulation time 28317414 ps
CPU time 1.23 seconds
Started Mar 10 02:09:19 PM PDT 24
Finished Mar 10 02:09:21 PM PDT 24
Peak memory 202448 kb
Host smart-38aa1a9f-f385-4dc4-b27d-25e5b8e3b621
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566150632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3566150632
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.218208874
Short name T811
Test name
Test status
Simulation time 4906100719 ps
CPU time 21.63 seconds
Started Mar 10 02:09:21 PM PDT 24
Finished Mar 10 02:09:43 PM PDT 24
Peak memory 202548 kb
Host smart-69de8524-a6fd-4abd-8b6e-0514d6e15b05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=218208874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.218208874
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1161803447
Short name T766
Test name
Test status
Simulation time 46897651978 ps
CPU time 94.1 seconds
Started Mar 10 02:09:19 PM PDT 24
Finished Mar 10 02:10:53 PM PDT 24
Peak memory 203824 kb
Host smart-0c2b79ab-af4d-4973-818d-a5ad3286e6de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1161803447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1161803447
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1213183548
Short name T689
Test name
Test status
Simulation time 241692870 ps
CPU time 21.46 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:40 PM PDT 24
Peak memory 204460 kb
Host smart-bafae00d-cd3e-4801-b366-bc199028f6a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1213183548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1213183548
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2391069158
Short name T237
Test name
Test status
Simulation time 517817570 ps
CPU time 23.69 seconds
Started Mar 10 02:09:20 PM PDT 24
Finished Mar 10 02:09:44 PM PDT 24
Peak memory 203376 kb
Host smart-fab2bf29-353f-4f36-a97f-24f9f3f09934
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2391069158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.2391069158
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3917512078
Short name T684
Test name
Test status
Simulation time 74963740 ps
CPU time 4.41 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:22 PM PDT 24
Peak memory 202392 kb
Host smart-56b7c044-1646-4dc5-b25d-46d7314776e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3917512078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3917512078
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2712691570
Short name T563
Test name
Test status
Simulation time 36596897 ps
CPU time 6.15 seconds
Started Mar 10 02:09:16 PM PDT 24
Finished Mar 10 02:09:23 PM PDT 24
Peak memory 202376 kb
Host smart-df3a3498-b3f9-4017-841b-eed6ed052537
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2712691570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2712691570
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3539982365
Short name T606
Test name
Test status
Simulation time 91336296985 ps
CPU time 257.13 seconds
Started Mar 10 02:09:17 PM PDT 24
Finished Mar 10 02:13:35 PM PDT 24
Peak memory 202664 kb
Host smart-fc15539f-9c4b-4da8-9202-67e2e74fec44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3539982365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.3539982365
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1348561984
Short name T339
Test name
Test status
Simulation time 431711866 ps
CPU time 6.56 seconds
Started Mar 10 02:09:21 PM PDT 24
Finished Mar 10 02:09:27 PM PDT 24
Peak memory 202452 kb
Host smart-5570c052-0973-430a-b941-81ca0cc86aa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1348561984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1348561984
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.3561657636
Short name T511
Test name
Test status
Simulation time 727862304 ps
CPU time 10.62 seconds
Started Mar 10 02:09:19 PM PDT 24
Finished Mar 10 02:09:29 PM PDT 24
Peak memory 202444 kb
Host smart-2247b0bd-3888-4d39-9c3f-f1e3530935ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3561657636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3561657636
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3042465349
Short name T395
Test name
Test status
Simulation time 30659578 ps
CPU time 4.48 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:23 PM PDT 24
Peak memory 202380 kb
Host smart-105f92e5-e725-4c3b-b128-605c06f0831c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3042465349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3042465349
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1441478301
Short name T164
Test name
Test status
Simulation time 148367804746 ps
CPU time 94.94 seconds
Started Mar 10 02:09:19 PM PDT 24
Finished Mar 10 02:10:54 PM PDT 24
Peak memory 202616 kb
Host smart-34cb95aa-6a25-47ff-a3d2-7ff94f64c7c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441478301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1441478301
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.4098860708
Short name T267
Test name
Test status
Simulation time 18645039640 ps
CPU time 72.98 seconds
Started Mar 10 02:09:21 PM PDT 24
Finished Mar 10 02:10:34 PM PDT 24
Peak memory 202568 kb
Host smart-c60a86fa-0d86-4722-8605-df9bf41138f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4098860708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4098860708
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4045353749
Short name T201
Test name
Test status
Simulation time 109656947 ps
CPU time 6.5 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202416 kb
Host smart-62be76d8-2b89-4107-ab49-d510bc2e6fb6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045353749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.4045353749
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2515951999
Short name T500
Test name
Test status
Simulation time 13473920 ps
CPU time 1.22 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 202452 kb
Host smart-a13eaf16-7d4c-45ff-9d88-6e823e8ecc39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2515951999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2515951999
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2341718891
Short name T456
Test name
Test status
Simulation time 67818060 ps
CPU time 1.62 seconds
Started Mar 10 02:09:20 PM PDT 24
Finished Mar 10 02:09:22 PM PDT 24
Peak memory 202324 kb
Host smart-b5db2685-a06b-4020-9048-e40a7c707406
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2341718891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2341718891
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3366944708
Short name T643
Test name
Test status
Simulation time 1450491045 ps
CPU time 5.57 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202396 kb
Host smart-39eaf562-c848-40fc-9e77-9a4169e51fbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366944708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3366944708
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4291398821
Short name T480
Test name
Test status
Simulation time 1996869825 ps
CPU time 5.79 seconds
Started Mar 10 02:09:18 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202404 kb
Host smart-ebcbb2d0-e58a-47cf-a6d8-2b0d28cd3a94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4291398821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4291398821
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.204604234
Short name T194
Test name
Test status
Simulation time 16774121 ps
CPU time 0.99 seconds
Started Mar 10 02:09:16 PM PDT 24
Finished Mar 10 02:09:18 PM PDT 24
Peak memory 202420 kb
Host smart-f7df3a7e-c398-4f94-ab30-f5004faa6998
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204604234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.204604234
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1674463903
Short name T115
Test name
Test status
Simulation time 10688778450 ps
CPU time 32.35 seconds
Started Mar 10 02:09:22 PM PDT 24
Finished Mar 10 02:09:54 PM PDT 24
Peak memory 202524 kb
Host smart-b7ac60b1-e203-4e1c-b4f8-ceefdceb0297
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1674463903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1674463903
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2511239519
Short name T305
Test name
Test status
Simulation time 162158596 ps
CPU time 19.52 seconds
Started Mar 10 02:09:23 PM PDT 24
Finished Mar 10 02:09:43 PM PDT 24
Peak memory 204124 kb
Host smart-d364e4bb-c83b-4824-9914-9e875a373b67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511239519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2511239519
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3120845900
Short name T485
Test name
Test status
Simulation time 4430221922 ps
CPU time 108.53 seconds
Started Mar 10 02:09:24 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 205656 kb
Host smart-d1b937ee-11d5-4fb4-81ef-8c926b4403a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3120845900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3120845900
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1807267047
Short name T544
Test name
Test status
Simulation time 180405769 ps
CPU time 6.6 seconds
Started Mar 10 02:09:16 PM PDT 24
Finished Mar 10 02:09:23 PM PDT 24
Peak memory 202432 kb
Host smart-b24cbc08-fd89-4e73-b254-afa7783bde49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1807267047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1807267047
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1540509874
Short name T35
Test name
Test status
Simulation time 807593849 ps
CPU time 12.84 seconds
Started Mar 10 02:09:23 PM PDT 24
Finished Mar 10 02:09:36 PM PDT 24
Peak memory 202444 kb
Host smart-6bc419e8-e950-41d2-bb80-2e1b519f1f91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540509874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1540509874
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.814138715
Short name T570
Test name
Test status
Simulation time 90616179772 ps
CPU time 146.23 seconds
Started Mar 10 02:09:24 PM PDT 24
Finished Mar 10 02:11:50 PM PDT 24
Peak memory 203568 kb
Host smart-a3b31a8f-9acb-4fa6-b041-e885ac764bde
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=814138715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo
w_rsp.814138715
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4189093474
Short name T422
Test name
Test status
Simulation time 24358897 ps
CPU time 1.93 seconds
Started Mar 10 02:09:33 PM PDT 24
Finished Mar 10 02:09:35 PM PDT 24
Peak memory 202436 kb
Host smart-0aa6cff8-cbbb-43aa-a416-456787c8e3b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4189093474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4189093474
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1765963138
Short name T114
Test name
Test status
Simulation time 68534177 ps
CPU time 3.73 seconds
Started Mar 10 02:09:28 PM PDT 24
Finished Mar 10 02:09:32 PM PDT 24
Peak memory 202376 kb
Host smart-ac0ed96c-1e8f-485d-a093-d4e99a91b648
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1765963138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1765963138
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2476491343
Short name T770
Test name
Test status
Simulation time 124455000 ps
CPU time 7.73 seconds
Started Mar 10 02:09:24 PM PDT 24
Finished Mar 10 02:09:34 PM PDT 24
Peak memory 202364 kb
Host smart-56d2d4ff-255f-42fa-884f-dac357180bdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2476491343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2476491343
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.843491519
Short name T610
Test name
Test status
Simulation time 21210178928 ps
CPU time 103.96 seconds
Started Mar 10 02:09:26 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 202556 kb
Host smart-57d59073-ca2c-45ef-bae7-bc277ba2f51c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=843491519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.843491519
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.985846636
Short name T168
Test name
Test status
Simulation time 23602741434 ps
CPU time 75.85 seconds
Started Mar 10 02:09:23 PM PDT 24
Finished Mar 10 02:10:39 PM PDT 24
Peak memory 202528 kb
Host smart-c4869d41-3582-449d-bd2c-2129bbf5dbd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=985846636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.985846636
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.675483077
Short name T767
Test name
Test status
Simulation time 20392276 ps
CPU time 1.78 seconds
Started Mar 10 02:09:22 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202440 kb
Host smart-b1927522-bd56-40a7-bdef-e7dedb2a7aa5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675483077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.675483077
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.565487995
Short name T383
Test name
Test status
Simulation time 42498125 ps
CPU time 3.56 seconds
Started Mar 10 02:09:22 PM PDT 24
Finished Mar 10 02:09:26 PM PDT 24
Peak memory 202436 kb
Host smart-135c948e-06f0-419c-927c-a669842fd909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=565487995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.565487995
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2357989524
Short name T900
Test name
Test status
Simulation time 129451390 ps
CPU time 1.65 seconds
Started Mar 10 02:09:22 PM PDT 24
Finished Mar 10 02:09:24 PM PDT 24
Peak memory 202404 kb
Host smart-707cc885-969b-4b32-8f87-196e1d189eb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2357989524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2357989524
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3574726138
Short name T704
Test name
Test status
Simulation time 2195248822 ps
CPU time 9.04 seconds
Started Mar 10 02:09:23 PM PDT 24
Finished Mar 10 02:09:33 PM PDT 24
Peak memory 202580 kb
Host smart-4d5d7b7e-937c-4d40-b19a-889219539bfc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574726138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3574726138
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1162463943
Short name T895
Test name
Test status
Simulation time 4570732185 ps
CPU time 11.58 seconds
Started Mar 10 02:09:22 PM PDT 24
Finished Mar 10 02:09:33 PM PDT 24
Peak memory 202500 kb
Host smart-edb517ab-8ba9-4d51-bbee-f3f67f46e154
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1162463943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1162463943
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3451194018
Short name T549
Test name
Test status
Simulation time 13000510 ps
CPU time 1.3 seconds
Started Mar 10 02:09:23 PM PDT 24
Finished Mar 10 02:09:25 PM PDT 24
Peak memory 202392 kb
Host smart-e70b005c-2ee6-4523-85bc-0e280ca345fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451194018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3451194018
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2768435837
Short name T5
Test name
Test status
Simulation time 6689857855 ps
CPU time 41.7 seconds
Started Mar 10 02:09:29 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 203720 kb
Host smart-715164c6-9ded-4b7a-a9c3-29b20799693d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2768435837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2768435837
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2815583343
Short name T216
Test name
Test status
Simulation time 13818356218 ps
CPU time 36.86 seconds
Started Mar 10 02:09:28 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 202572 kb
Host smart-0dc0c310-e774-4991-8daf-fbd09e6518bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2815583343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2815583343
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3262704460
Short name T361
Test name
Test status
Simulation time 215883470 ps
CPU time 21.4 seconds
Started Mar 10 02:09:28 PM PDT 24
Finished Mar 10 02:09:50 PM PDT 24
Peak memory 204456 kb
Host smart-29df72f0-4abb-4d6b-bc19-85e4b2141a9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3262704460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.3262704460
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2327373479
Short name T831
Test name
Test status
Simulation time 3687657620 ps
CPU time 62.92 seconds
Started Mar 10 02:09:33 PM PDT 24
Finished Mar 10 02:10:36 PM PDT 24
Peak memory 204892 kb
Host smart-89a6c83a-34d3-4439-b782-3abf4e0576b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2327373479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.2327373479
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3980149301
Short name T94
Test name
Test status
Simulation time 39481300 ps
CPU time 3.16 seconds
Started Mar 10 02:09:29 PM PDT 24
Finished Mar 10 02:09:33 PM PDT 24
Peak memory 202436 kb
Host smart-c0507a83-5682-4bc3-820d-4827d1d0c0c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3980149301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3980149301
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3645970305
Short name T777
Test name
Test status
Simulation time 874634335 ps
CPU time 11.38 seconds
Started Mar 10 02:09:33 PM PDT 24
Finished Mar 10 02:09:45 PM PDT 24
Peak memory 202368 kb
Host smart-dd342548-503c-4054-8f78-04147f23dac0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3645970305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3645970305
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.412687518
Short name T37
Test name
Test status
Simulation time 37236425052 ps
CPU time 196.17 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:12:55 PM PDT 24
Peak memory 202680 kb
Host smart-7495d195-7dbd-4942-a8c3-072bf53b5c67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=412687518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.412687518
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3211717426
Short name T815
Test name
Test status
Simulation time 57582308 ps
CPU time 5.86 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:09:45 PM PDT 24
Peak memory 202440 kb
Host smart-40541982-daa3-4efc-af4d-4b8b3e61d9c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3211717426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3211717426
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.2260059186
Short name T460
Test name
Test status
Simulation time 144468588 ps
CPU time 2.46 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:09:41 PM PDT 24
Peak memory 202436 kb
Host smart-8e33ee2d-e81f-4bcd-8551-906217487cbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2260059186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2260059186
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.2049088198
Short name T550
Test name
Test status
Simulation time 51818550 ps
CPU time 6.43 seconds
Started Mar 10 02:09:34 PM PDT 24
Finished Mar 10 02:09:40 PM PDT 24
Peak memory 202328 kb
Host smart-b97f383a-6635-4d9d-9444-0abdac56b34f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049088198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2049088198
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.4191427410
Short name T259
Test name
Test status
Simulation time 50207018449 ps
CPU time 107.32 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 202572 kb
Host smart-af11b00e-a149-4a4b-a858-df266df765fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191427410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4191427410
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3973336270
Short name T157
Test name
Test status
Simulation time 5711341353 ps
CPU time 33.58 seconds
Started Mar 10 02:09:32 PM PDT 24
Finished Mar 10 02:10:06 PM PDT 24
Peak memory 202532 kb
Host smart-b2774212-ce7a-42bf-a891-362871cb7115
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3973336270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3973336270
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1551603292
Short name T453
Test name
Test status
Simulation time 146741241 ps
CPU time 7.22 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:09:46 PM PDT 24
Peak memory 202356 kb
Host smart-eb51b3e6-5302-4906-82a5-267f6a4e498d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551603292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1551603292
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.1448560153
Short name T759
Test name
Test status
Simulation time 823124791 ps
CPU time 7.94 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:09:48 PM PDT 24
Peak memory 202432 kb
Host smart-a4697042-16b6-48ce-8b65-f3e49b54bd19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448560153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1448560153
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.19531235
Short name T617
Test name
Test status
Simulation time 8585363 ps
CPU time 1.13 seconds
Started Mar 10 02:09:29 PM PDT 24
Finished Mar 10 02:09:30 PM PDT 24
Peak memory 202352 kb
Host smart-645f3679-a67d-4d72-a923-4aa50b587843
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19531235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.19531235
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1227880509
Short name T49
Test name
Test status
Simulation time 2214335350 ps
CPU time 9.5 seconds
Started Mar 10 02:09:29 PM PDT 24
Finished Mar 10 02:09:38 PM PDT 24
Peak memory 202572 kb
Host smart-5e5841ff-2c89-40ac-945c-18d5ba708a73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227880509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1227880509
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3475649007
Short name T462
Test name
Test status
Simulation time 3019324889 ps
CPU time 9.49 seconds
Started Mar 10 02:09:29 PM PDT 24
Finished Mar 10 02:09:38 PM PDT 24
Peak memory 202480 kb
Host smart-748f35c4-a7cc-4778-bad3-8b3ddae218b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3475649007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3475649007
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1503656697
Short name T86
Test name
Test status
Simulation time 11903935 ps
CPU time 1.16 seconds
Started Mar 10 02:09:27 PM PDT 24
Finished Mar 10 02:09:28 PM PDT 24
Peak memory 202456 kb
Host smart-3c59ec52-75b8-4680-b890-593c3c795761
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503656697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1503656697
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1715755423
Short name T851
Test name
Test status
Simulation time 213857621 ps
CPU time 10.77 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:09:50 PM PDT 24
Peak memory 202408 kb
Host smart-210a0573-39cb-4547-b329-7a10fcb35410
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1715755423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1715755423
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1199939570
Short name T718
Test name
Test status
Simulation time 4585718869 ps
CPU time 93.16 seconds
Started Mar 10 02:09:35 PM PDT 24
Finished Mar 10 02:11:09 PM PDT 24
Peak memory 203780 kb
Host smart-309a04b4-0ff6-4cf6-8da4-83c88d1bc4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1199939570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1199939570
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2470536495
Short name T240
Test name
Test status
Simulation time 701647116 ps
CPU time 116.3 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:11:35 PM PDT 24
Peak memory 204624 kb
Host smart-9ea7f8bf-b80f-41c8-8743-dada5808a666
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2470536495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.2470536495
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3435024574
Short name T308
Test name
Test status
Simulation time 1995800703 ps
CPU time 11.98 seconds
Started Mar 10 02:09:34 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 202408 kb
Host smart-dc10793d-919d-4ef1-b251-2e8686e77fd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3435024574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3435024574
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1342287113
Short name T669
Test name
Test status
Simulation time 681351095 ps
CPU time 16.53 seconds
Started Mar 10 02:09:41 PM PDT 24
Finished Mar 10 02:09:58 PM PDT 24
Peak memory 202416 kb
Host smart-3887c283-0cec-4bf3-81d3-a05f468e8972
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1342287113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1342287113
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.445501007
Short name T121
Test name
Test status
Simulation time 17832334382 ps
CPU time 89.99 seconds
Started Mar 10 02:09:43 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202572 kb
Host smart-45419e0e-b75d-4e6b-83ba-cf4c99e78192
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=445501007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo
w_rsp.445501007
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2110900093
Short name T574
Test name
Test status
Simulation time 2030071379 ps
CPU time 5.63 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:09:45 PM PDT 24
Peak memory 202444 kb
Host smart-733443d1-f56f-4fa3-942d-40676591eaee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2110900093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2110900093
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.3922771097
Short name T446
Test name
Test status
Simulation time 315933895 ps
CPU time 5.95 seconds
Started Mar 10 02:09:39 PM PDT 24
Finished Mar 10 02:09:45 PM PDT 24
Peak memory 202408 kb
Host smart-0b710052-047d-4eb5-b7e3-a5f2641d9ac8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922771097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3922771097
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.1973226493
Short name T755
Test name
Test status
Simulation time 5200628340 ps
CPU time 15.4 seconds
Started Mar 10 02:09:34 PM PDT 24
Finished Mar 10 02:09:50 PM PDT 24
Peak memory 202500 kb
Host smart-315abe17-721e-45ff-bda9-1621aef3c2ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973226493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1973226493
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2154102890
Short name T785
Test name
Test status
Simulation time 34263403391 ps
CPU time 75.89 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:10:55 PM PDT 24
Peak memory 202576 kb
Host smart-15d3442d-ca55-4627-8a2d-415b15be18c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154102890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2154102890
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.969710991
Short name T481
Test name
Test status
Simulation time 43299508815 ps
CPU time 70.74 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:10:50 PM PDT 24
Peak memory 202552 kb
Host smart-2cf3a244-38a9-41a9-8d0e-4bfe7b143825
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=969710991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.969710991
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2410359268
Short name T656
Test name
Test status
Simulation time 198559776 ps
CPU time 5.68 seconds
Started Mar 10 02:09:41 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 202420 kb
Host smart-1bbca1fb-96f7-4a04-bf4d-99b8ab43687b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410359268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2410359268
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.1748413479
Short name T473
Test name
Test status
Simulation time 2150481873 ps
CPU time 15.13 seconds
Started Mar 10 02:09:39 PM PDT 24
Finished Mar 10 02:09:54 PM PDT 24
Peak memory 202536 kb
Host smart-27432203-a3d3-4932-a071-fc45d27e923d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1748413479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1748413479
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.3424624584
Short name T649
Test name
Test status
Simulation time 106377752 ps
CPU time 1.78 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:09:41 PM PDT 24
Peak memory 202324 kb
Host smart-8739397f-53d4-4b4a-aa07-f07d9884d534
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3424624584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3424624584
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3026274773
Short name T869
Test name
Test status
Simulation time 2758927306 ps
CPU time 10.04 seconds
Started Mar 10 02:09:36 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 202492 kb
Host smart-627ea80b-e62f-4939-b644-d981e5b75e8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026274773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3026274773
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.723738824
Short name T181
Test name
Test status
Simulation time 4326017346 ps
CPU time 5.33 seconds
Started Mar 10 02:09:33 PM PDT 24
Finished Mar 10 02:09:39 PM PDT 24
Peak memory 202572 kb
Host smart-9c3a3de0-acf2-4987-a71b-335c9bce1d82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=723738824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.723738824
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1729499625
Short name T269
Test name
Test status
Simulation time 9821484 ps
CPU time 1.34 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:09:42 PM PDT 24
Peak memory 202464 kb
Host smart-8e76f29f-6dfc-450b-9eea-aea6ea951a89
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729499625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1729499625
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.145789753
Short name T258
Test name
Test status
Simulation time 525002607 ps
CPU time 53.21 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:10:34 PM PDT 24
Peak memory 203440 kb
Host smart-7a265aab-4c7a-4e67-b0b6-317163fde7ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=145789753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.145789753
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2332217694
Short name T672
Test name
Test status
Simulation time 464023024 ps
CPU time 23.16 seconds
Started Mar 10 02:09:39 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202448 kb
Host smart-6a3d1119-edaa-4121-8c0e-ef8e3500b52b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2332217694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2332217694
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3689124638
Short name T161
Test name
Test status
Simulation time 7934918246 ps
CPU time 158.36 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:12:19 PM PDT 24
Peak memory 206772 kb
Host smart-53a39d0c-8791-4127-9e27-898d99464807
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3689124638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.3689124638
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.725610769
Short name T545
Test name
Test status
Simulation time 4986167340 ps
CPU time 104.3 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:11:23 PM PDT 24
Peak memory 205924 kb
Host smart-c624e7b7-3221-4dca-82a9-e2facbd267d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=725610769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res
et_error.725610769
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2680743128
Short name T14
Test name
Test status
Simulation time 1143023190 ps
CPU time 6.51 seconds
Started Mar 10 02:09:38 PM PDT 24
Finished Mar 10 02:09:45 PM PDT 24
Peak memory 202352 kb
Host smart-7ce39414-6fd2-4ef6-b7fa-27adfe7e5548
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2680743128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2680743128
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1630202345
Short name T556
Test name
Test status
Simulation time 893109134 ps
CPU time 13.31 seconds
Started Mar 10 02:09:45 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 202444 kb
Host smart-a6c13d0a-f461-4024-844b-685c009de075
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630202345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1630202345
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.4221901988
Short name T219
Test name
Test status
Simulation time 56573892202 ps
CPU time 338.12 seconds
Started Mar 10 02:09:42 PM PDT 24
Finished Mar 10 02:15:20 PM PDT 24
Peak memory 204032 kb
Host smart-00395f7a-0633-408b-bb65-f02d32980dbe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4221901988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.4221901988
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3078635962
Short name T62
Test name
Test status
Simulation time 11583741 ps
CPU time 0.9 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:50 PM PDT 24
Peak memory 202224 kb
Host smart-dc8c2de4-03d3-4f87-9872-a56d5ec14ece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3078635962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3078635962
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.1916476903
Short name T333
Test name
Test status
Simulation time 170155893 ps
CPU time 4.78 seconds
Started Mar 10 02:09:44 PM PDT 24
Finished Mar 10 02:09:49 PM PDT 24
Peak memory 202448 kb
Host smart-35f227e1-df99-4ddf-980a-9156f4e74db2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916476903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1916476903
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.155052789
Short name T683
Test name
Test status
Simulation time 14635226 ps
CPU time 1.97 seconds
Started Mar 10 02:09:41 PM PDT 24
Finished Mar 10 02:09:43 PM PDT 24
Peak memory 202360 kb
Host smart-2c9c129a-3adc-4c6b-849d-5e0f58c99c9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=155052789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.155052789
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3019364361
Short name T802
Test name
Test status
Simulation time 36679657695 ps
CPU time 140.89 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:12:01 PM PDT 24
Peak memory 202568 kb
Host smart-77220d93-a4ea-49d2-8d6a-ee12cf92e4cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019364361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3019364361
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.760203411
Short name T109
Test name
Test status
Simulation time 61499671854 ps
CPU time 168.19 seconds
Started Mar 10 02:09:39 PM PDT 24
Finished Mar 10 02:12:28 PM PDT 24
Peak memory 202568 kb
Host smart-ab0ef0f6-e083-4dc5-b039-87ba6d80cebd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=760203411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.760203411
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3354429788
Short name T513
Test name
Test status
Simulation time 35622460 ps
CPU time 3.18 seconds
Started Mar 10 02:09:37 PM PDT 24
Finished Mar 10 02:09:42 PM PDT 24
Peak memory 202428 kb
Host smart-a5a07995-c618-483e-8e43-40af2a783b32
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354429788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3354429788
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.2822254493
Short name T838
Test name
Test status
Simulation time 40173399 ps
CPU time 4.08 seconds
Started Mar 10 02:09:47 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 202444 kb
Host smart-3836c5ab-df55-4018-b2cf-f7209a677065
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822254493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2822254493
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.2250805421
Short name T826
Test name
Test status
Simulation time 33178956 ps
CPU time 1.34 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:09:42 PM PDT 24
Peak memory 202324 kb
Host smart-c6f44f75-bc69-48a4-9b07-a098405b401d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2250805421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2250805421
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2292425129
Short name T842
Test name
Test status
Simulation time 1483606925 ps
CPU time 7.09 seconds
Started Mar 10 02:09:39 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 202424 kb
Host smart-40966e77-1503-4fa6-82b5-28a2356dcaad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292425129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2292425129
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1537935076
Short name T736
Test name
Test status
Simulation time 2104479594 ps
CPU time 5.37 seconds
Started Mar 10 02:09:40 PM PDT 24
Finished Mar 10 02:09:46 PM PDT 24
Peak memory 202360 kb
Host smart-1a1f5238-1878-4557-b065-da7dbc6b1ff3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1537935076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1537935076
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2867855398
Short name T725
Test name
Test status
Simulation time 10675283 ps
CPU time 1.2 seconds
Started Mar 10 02:09:42 PM PDT 24
Finished Mar 10 02:09:44 PM PDT 24
Peak memory 202464 kb
Host smart-8f875e10-eff0-4906-b5f1-b19f9978ea88
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867855398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2867855398
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.2445046295
Short name T106
Test name
Test status
Simulation time 2138047376 ps
CPU time 46.22 seconds
Started Mar 10 02:09:44 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 203468 kb
Host smart-c7adcd06-059b-4740-8921-7fd0cb6522ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2445046295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2445046295
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1838544883
Short name T147
Test name
Test status
Simulation time 625043131 ps
CPU time 41.32 seconds
Started Mar 10 02:09:56 PM PDT 24
Finished Mar 10 02:10:38 PM PDT 24
Peak memory 203488 kb
Host smart-2c4a72ee-ac22-4398-9329-2713888fe58b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1838544883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1838544883
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2737061601
Short name T719
Test name
Test status
Simulation time 5581271295 ps
CPU time 167.17 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:12:36 PM PDT 24
Peak memory 206668 kb
Host smart-339bc708-12a0-4848-8d47-f5cb51ba1fc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2737061601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.2737061601
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2699614235
Short name T868
Test name
Test status
Simulation time 32075722 ps
CPU time 1.63 seconds
Started Mar 10 02:09:45 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 202436 kb
Host smart-ed2cb8e8-2d2a-4949-9cad-656bd60703ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2699614235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2699614235
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2558511363
Short name T578
Test name
Test status
Simulation time 1631795083 ps
CPU time 21.76 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 202224 kb
Host smart-23c427b9-02bc-4e0f-bbed-9ab81b4c746a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2558511363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2558511363
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4236538772
Short name T682
Test name
Test status
Simulation time 43446150 ps
CPU time 4.8 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:09:55 PM PDT 24
Peak memory 202432 kb
Host smart-9341ae63-1832-4d96-8868-f1544a88ac16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236538772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4236538772
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.3327742160
Short name T698
Test name
Test status
Simulation time 1008154425 ps
CPU time 11.97 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202440 kb
Host smart-b8525a63-bd38-4ebc-a9b1-eab53c46b8ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3327742160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3327742160
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.1498062747
Short name T57
Test name
Test status
Simulation time 48458752 ps
CPU time 1.56 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 202172 kb
Host smart-591db26f-791b-406e-9518-973342667337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1498062747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1498062747
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.989459338
Short name T852
Test name
Test status
Simulation time 7545868399 ps
CPU time 35.08 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:10:25 PM PDT 24
Peak memory 202572 kb
Host smart-53302ab3-54a9-47b6-aa6f-d4d618e54413
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=989459338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.989459338
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.405517166
Short name T338
Test name
Test status
Simulation time 508188970 ps
CPU time 4.74 seconds
Started Mar 10 02:09:51 PM PDT 24
Finished Mar 10 02:09:56 PM PDT 24
Peak memory 202452 kb
Host smart-b5508f9a-2b40-424e-9bdb-c4255f5499a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=405517166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.405517166
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.116064202
Short name T589
Test name
Test status
Simulation time 145640064 ps
CPU time 5.5 seconds
Started Mar 10 02:09:45 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 202444 kb
Host smart-894f8c47-0ad9-45c0-8978-f91100560630
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116064202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.116064202
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3962143422
Short name T448
Test name
Test status
Simulation time 188986390 ps
CPU time 2.82 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:01 PM PDT 24
Peak memory 202412 kb
Host smart-a4649246-c685-40fe-b73d-9182b6a61c97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3962143422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3962143422
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.3792044990
Short name T1
Test name
Test status
Simulation time 84494090 ps
CPU time 1.47 seconds
Started Mar 10 02:09:46 PM PDT 24
Finished Mar 10 02:09:48 PM PDT 24
Peak memory 202360 kb
Host smart-fae46d74-9f3c-440d-bb43-10c02dcdcfc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3792044990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3792044990
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.101600152
Short name T142
Test name
Test status
Simulation time 3267788063 ps
CPU time 9.81 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 202336 kb
Host smart-4081787e-e391-4e66-9d04-14eb5b864d60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=101600152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.101600152
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3508295005
Short name T200
Test name
Test status
Simulation time 3698314865 ps
CPU time 8.21 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:57 PM PDT 24
Peak memory 202332 kb
Host smart-f7a4f8b7-75bf-4638-8b8f-8110e9234a38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3508295005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3508295005
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3448786845
Short name T483
Test name
Test status
Simulation time 9363101 ps
CPU time 1.11 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:50 PM PDT 24
Peak memory 202468 kb
Host smart-6f8d111b-cdbf-4b72-b38a-ce8ca5d846d6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448786845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3448786845
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1467436688
Short name T881
Test name
Test status
Simulation time 630675731 ps
CPU time 61.04 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 203440 kb
Host smart-09c8744b-0733-40f2-9e02-f433d5b27420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1467436688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1467436688
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3300647527
Short name T455
Test name
Test status
Simulation time 248948220 ps
CPU time 3.98 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202432 kb
Host smart-1487dc32-d0f9-4d00-8639-069244404b02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3300647527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3300647527
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3749022665
Short name T167
Test name
Test status
Simulation time 340440405 ps
CPU time 17.97 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:10:07 PM PDT 24
Peak memory 203464 kb
Host smart-abe1377f-2e26-4ef4-af86-f5d49b629a1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3749022665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.3749022665
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.107252497
Short name T653
Test name
Test status
Simulation time 577870219 ps
CPU time 10.62 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 202380 kb
Host smart-d876b9cb-b2d0-4e0d-af7d-193c5fa81792
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107252497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.107252497
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2069950814
Short name T634
Test name
Test status
Simulation time 881318682 ps
CPU time 18.34 seconds
Started Mar 10 02:09:49 PM PDT 24
Finished Mar 10 02:10:08 PM PDT 24
Peak memory 202408 kb
Host smart-3a87301c-c6df-4995-8a50-2517532d51b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2069950814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2069950814
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2132581790
Short name T103
Test name
Test status
Simulation time 72318963778 ps
CPU time 338.4 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:15:36 PM PDT 24
Peak memory 204100 kb
Host smart-59c639e6-ba0a-4a38-89d0-6db59d922ab3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2132581790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.2132581790
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.654685595
Short name T369
Test name
Test status
Simulation time 215225681 ps
CPU time 3.8 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202364 kb
Host smart-b634eec6-2d50-4f50-a153-80049dc81720
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=654685595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.654685595
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.4195707152
Short name T866
Test name
Test status
Simulation time 620701836 ps
CPU time 7.44 seconds
Started Mar 10 02:09:52 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 202416 kb
Host smart-a96ef15f-602f-4901-91c7-630e777ab655
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195707152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4195707152
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2281246120
Short name T61
Test name
Test status
Simulation time 152661425 ps
CPU time 3.57 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:09:54 PM PDT 24
Peak memory 202408 kb
Host smart-9ad9801c-f8b8-4f10-903f-c2124c54e3a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281246120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2281246120
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1127756071
Short name T122
Test name
Test status
Simulation time 33509221819 ps
CPU time 112.5 seconds
Started Mar 10 02:09:51 PM PDT 24
Finished Mar 10 02:11:44 PM PDT 24
Peak memory 202520 kb
Host smart-3f5a0286-f388-4898-9126-cba39f3d1a09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127756071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1127756071
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2376826359
Short name T423
Test name
Test status
Simulation time 2870639187 ps
CPU time 21.02 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:19 PM PDT 24
Peak memory 202572 kb
Host smart-ca584aa1-470d-47b5-a5ec-e4f7a10f57dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2376826359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2376826359
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.866644376
Short name T325
Test name
Test status
Simulation time 83549404 ps
CPU time 5.31 seconds
Started Mar 10 02:09:51 PM PDT 24
Finished Mar 10 02:09:56 PM PDT 24
Peak memory 202416 kb
Host smart-561b944e-3f04-4cfd-bb5f-4fd81ce9d4d5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866644376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.866644376
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.2577043360
Short name T582
Test name
Test status
Simulation time 718902341 ps
CPU time 8.62 seconds
Started Mar 10 02:09:51 PM PDT 24
Finished Mar 10 02:10:00 PM PDT 24
Peak memory 202388 kb
Host smart-2682b0d7-e017-406c-98c0-4bda186e4623
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2577043360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2577043360
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.2692490885
Short name T713
Test name
Test status
Simulation time 24271853 ps
CPU time 1.06 seconds
Started Mar 10 02:09:57 PM PDT 24
Finished Mar 10 02:09:58 PM PDT 24
Peak memory 202376 kb
Host smart-a07a195c-cba6-40e1-a34c-dc8ad08ad3d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2692490885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2692490885
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2958691702
Short name T648
Test name
Test status
Simulation time 6383146196 ps
CPU time 10.43 seconds
Started Mar 10 02:09:51 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202504 kb
Host smart-5dca8431-1494-4cd5-9107-6752d6d943b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958691702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2958691702
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.67644034
Short name T626
Test name
Test status
Simulation time 1851944573 ps
CPU time 8.85 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 202376 kb
Host smart-1fc818e4-d194-4e8e-83fa-348bb1ecb2ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=67644034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.67644034
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3286380810
Short name T281
Test name
Test status
Simulation time 9091955 ps
CPU time 1.01 seconds
Started Mar 10 02:09:50 PM PDT 24
Finished Mar 10 02:09:51 PM PDT 24
Peak memory 202448 kb
Host smart-7720718e-2462-4fd1-a2f5-ce5217a38799
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286380810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3286380810
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1835693023
Short name T79
Test name
Test status
Simulation time 25890446327 ps
CPU time 96.97 seconds
Started Mar 10 02:10:02 PM PDT 24
Finished Mar 10 02:11:39 PM PDT 24
Peak memory 204820 kb
Host smart-e19dc3b7-a64a-4a5b-8f30-6d56f1e2cabc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1835693023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1835693023
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3417280323
Short name T365
Test name
Test status
Simulation time 1622765952 ps
CPU time 29.12 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:10:28 PM PDT 24
Peak memory 202484 kb
Host smart-50b1a580-d58c-4e16-ac64-7b9dc17f2569
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417280323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3417280323
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.372926360
Short name T583
Test name
Test status
Simulation time 1524374059 ps
CPU time 209.29 seconds
Started Mar 10 02:09:56 PM PDT 24
Finished Mar 10 02:13:25 PM PDT 24
Peak memory 209684 kb
Host smart-bcef1d74-b0d7-4155-9daf-8d900b602ad0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=372926360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand
_reset.372926360
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.317188698
Short name T821
Test name
Test status
Simulation time 1253354917 ps
CPU time 84.84 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 205800 kb
Host smart-be74d60f-77ee-4059-a1d9-9d91e4cbde1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=317188698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res
et_error.317188698
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.896726345
Short name T566
Test name
Test status
Simulation time 15038072 ps
CPU time 1.77 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202448 kb
Host smart-3c8cf1c8-34e1-4e22-a84c-9a50f770cd3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=896726345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.896726345
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2253918767
Short name T396
Test name
Test status
Simulation time 568007155 ps
CPU time 11.3 seconds
Started Mar 10 02:07:20 PM PDT 24
Finished Mar 10 02:07:31 PM PDT 24
Peak memory 202452 kb
Host smart-c61f94bc-d1c2-4036-96df-e9188dd8a496
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2253918767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2253918767
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1865979144
Short name T796
Test name
Test status
Simulation time 43366961386 ps
CPU time 176.77 seconds
Started Mar 10 02:07:15 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 203712 kb
Host smart-df4f044a-3dd1-4cb7-8807-a3a7a7152100
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1865979144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.1865979144
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1604829300
Short name T143
Test name
Test status
Simulation time 489596191 ps
CPU time 7.97 seconds
Started Mar 10 02:07:13 PM PDT 24
Finished Mar 10 02:07:22 PM PDT 24
Peak memory 202440 kb
Host smart-7e15cef9-a17e-47d2-9f0c-572bb3b489ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604829300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1604829300
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2476962811
Short name T280
Test name
Test status
Simulation time 3092103602 ps
CPU time 11.9 seconds
Started Mar 10 02:07:14 PM PDT 24
Finished Mar 10 02:07:26 PM PDT 24
Peak memory 202500 kb
Host smart-8dee9c0f-2f22-4c52-af0f-b3a30b48fa3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2476962811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2476962811
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.574840732
Short name T862
Test name
Test status
Simulation time 39336209 ps
CPU time 1.96 seconds
Started Mar 10 02:07:09 PM PDT 24
Finished Mar 10 02:07:13 PM PDT 24
Peak memory 202388 kb
Host smart-f02bf2ae-0f64-4acb-8b91-b9d8bd8990f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=574840732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.574840732
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1910660727
Short name T388
Test name
Test status
Simulation time 93614391865 ps
CPU time 90.84 seconds
Started Mar 10 02:07:15 PM PDT 24
Finished Mar 10 02:08:46 PM PDT 24
Peak memory 202564 kb
Host smart-f8409b45-9822-4db8-98a5-99cb8222be10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910660727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1910660727
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4115752336
Short name T528
Test name
Test status
Simulation time 18062214240 ps
CPU time 113.52 seconds
Started Mar 10 02:07:16 PM PDT 24
Finished Mar 10 02:09:10 PM PDT 24
Peak memory 202580 kb
Host smart-e069eaa5-5301-45b5-8bbe-a8c6ecf43ec6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4115752336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4115752336
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2411049825
Short name T302
Test name
Test status
Simulation time 12407058 ps
CPU time 1.3 seconds
Started Mar 10 02:07:11 PM PDT 24
Finished Mar 10 02:07:13 PM PDT 24
Peak memory 202452 kb
Host smart-5e374ab5-cad5-4c8c-85a8-59693a87ef7e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411049825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2411049825
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.790092331
Short name T814
Test name
Test status
Simulation time 25525805 ps
CPU time 2.84 seconds
Started Mar 10 02:07:14 PM PDT 24
Finished Mar 10 02:07:17 PM PDT 24
Peak memory 202388 kb
Host smart-9cccef19-5eb2-4589-b6b8-78db30769a10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=790092331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.790092331
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3815484413
Short name T613
Test name
Test status
Simulation time 133084285 ps
CPU time 1.18 seconds
Started Mar 10 02:07:11 PM PDT 24
Finished Mar 10 02:07:12 PM PDT 24
Peak memory 202388 kb
Host smart-e75502d8-a1c3-4678-a651-746f9ea85e19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3815484413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3815484413
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.103858291
Short name T651
Test name
Test status
Simulation time 1556157440 ps
CPU time 6.43 seconds
Started Mar 10 02:07:12 PM PDT 24
Finished Mar 10 02:07:19 PM PDT 24
Peak memory 202448 kb
Host smart-c7836288-0298-49a0-8986-19901c32ce83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=103858291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.103858291
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.908870838
Short name T732
Test name
Test status
Simulation time 3415197196 ps
CPU time 9.2 seconds
Started Mar 10 02:07:10 PM PDT 24
Finished Mar 10 02:07:20 PM PDT 24
Peak memory 202572 kb
Host smart-2b0d776e-43f2-416b-a748-79acbc9ccb38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=908870838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.908870838
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2386136209
Short name T293
Test name
Test status
Simulation time 9155685 ps
CPU time 1.28 seconds
Started Mar 10 02:07:10 PM PDT 24
Finished Mar 10 02:07:12 PM PDT 24
Peak memory 202444 kb
Host smart-1c793b3a-424c-4d46-8c5e-a4729aa97d30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386136209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2386136209
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3622136888
Short name T695
Test name
Test status
Simulation time 703253087 ps
CPU time 46.03 seconds
Started Mar 10 02:07:16 PM PDT 24
Finished Mar 10 02:08:02 PM PDT 24
Peak memory 204536 kb
Host smart-6d3412b0-70b6-4a98-93ec-71b7fd81b164
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622136888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3622136888
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.91426273
Short name T784
Test name
Test status
Simulation time 146069004 ps
CPU time 16.61 seconds
Started Mar 10 02:07:16 PM PDT 24
Finished Mar 10 02:07:33 PM PDT 24
Peak memory 202388 kb
Host smart-9e23b5ee-4fe0-4dbb-83f8-6c322fab2aff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91426273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.91426273
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1696969750
Short name T565
Test name
Test status
Simulation time 149173356 ps
CPU time 25.34 seconds
Started Mar 10 02:07:14 PM PDT 24
Finished Mar 10 02:07:40 PM PDT 24
Peak memory 206236 kb
Host smart-4c7b502a-8d46-4dd1-b1d6-91acbddd71bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1696969750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.1696969750
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2843158678
Short name T510
Test name
Test status
Simulation time 516106143 ps
CPU time 50.88 seconds
Started Mar 10 02:07:15 PM PDT 24
Finished Mar 10 02:08:06 PM PDT 24
Peak memory 204000 kb
Host smart-258a6ff1-6b29-4b77-9d11-e8ba0784b07c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2843158678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.2843158678
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3563148362
Short name T297
Test name
Test status
Simulation time 669446201 ps
CPU time 4.34 seconds
Started Mar 10 02:07:15 PM PDT 24
Finished Mar 10 02:07:20 PM PDT 24
Peak memory 202368 kb
Host smart-c9620199-89b1-4196-b53c-3678fed8e038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3563148362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3563148362
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2925363122
Short name T272
Test name
Test status
Simulation time 18587547 ps
CPU time 3.09 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202488 kb
Host smart-ca687cfe-88a4-4683-a7bb-29df539d49ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2925363122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2925363122
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.119008423
Short name T100
Test name
Test status
Simulation time 73605451518 ps
CPU time 222.06 seconds
Started Mar 10 02:09:57 PM PDT 24
Finished Mar 10 02:13:39 PM PDT 24
Peak memory 203744 kb
Host smart-b1eecfd9-2f87-422c-b8d1-bf898a959d0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=119008423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo
w_rsp.119008423
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3113376015
Short name T288
Test name
Test status
Simulation time 401533970 ps
CPU time 5.57 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 202408 kb
Host smart-389f814e-1a0e-45e1-aba6-63feb6afdb72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3113376015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3113376015
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.2755316449
Short name T622
Test name
Test status
Simulation time 68964497 ps
CPU time 5.8 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:06 PM PDT 24
Peak memory 202404 kb
Host smart-c936e937-39fb-4e93-b382-868673683038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2755316449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2755316449
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.2648156163
Short name T875
Test name
Test status
Simulation time 106642896 ps
CPU time 5.58 seconds
Started Mar 10 02:09:57 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202364 kb
Host smart-039fdb91-e156-408d-8a6d-0613317d31c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2648156163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2648156163
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3544573847
Short name T762
Test name
Test status
Simulation time 43915648423 ps
CPU time 170.83 seconds
Started Mar 10 02:10:02 PM PDT 24
Finished Mar 10 02:12:53 PM PDT 24
Peak memory 202612 kb
Host smart-61732271-1657-4354-9ec2-05a076a3acfe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544573847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3544573847
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1781889266
Short name T668
Test name
Test status
Simulation time 19250039863 ps
CPU time 107.25 seconds
Started Mar 10 02:10:02 PM PDT 24
Finished Mar 10 02:11:49 PM PDT 24
Peak memory 202588 kb
Host smart-6e0a6e4a-4baf-4d82-815a-c82203b7e6f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1781889266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1781889266
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.62656693
Short name T184
Test name
Test status
Simulation time 12385948 ps
CPU time 1.43 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:01 PM PDT 24
Peak memory 202452 kb
Host smart-e79fa594-7a60-4e92-bf41-b7630f2a60df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62656693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.62656693
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.4212649136
Short name T206
Test name
Test status
Simulation time 997800693 ps
CPU time 5.2 seconds
Started Mar 10 02:09:57 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202440 kb
Host smart-6e77fc84-d188-41f0-be8c-1b26eaf4b667
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4212649136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4212649136
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.3281244402
Short name T637
Test name
Test status
Simulation time 11621594 ps
CPU time 1.08 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:01 PM PDT 24
Peak memory 202368 kb
Host smart-a6305f6c-074a-46ab-aea5-3276b97ec4c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281244402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3281244402
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.162226934
Short name T243
Test name
Test status
Simulation time 4029315471 ps
CPU time 11.09 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:09 PM PDT 24
Peak memory 202568 kb
Host smart-a7989181-9082-4ff5-a507-90a6c2becba1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=162226934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.162226934
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.4230280875
Short name T706
Test name
Test status
Simulation time 2829086603 ps
CPU time 10.6 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:10 PM PDT 24
Peak memory 202520 kb
Host smart-52a35261-23e5-472d-8c9d-914e954ad870
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4230280875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4230280875
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.958774075
Short name T602
Test name
Test status
Simulation time 14961646 ps
CPU time 1.28 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:10:00 PM PDT 24
Peak memory 202368 kb
Host smart-f026c4ce-8e68-4574-b540-30a82bcb9da9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958774075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.958774075
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1503354234
Short name T575
Test name
Test status
Simulation time 325882799 ps
CPU time 19.59 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:18 PM PDT 24
Peak memory 202436 kb
Host smart-ba6b253c-cf1b-487e-a188-91d033bad593
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1503354234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1503354234
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.4070871497
Short name T84
Test name
Test status
Simulation time 280698771 ps
CPU time 30.49 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:29 PM PDT 24
Peak memory 202444 kb
Host smart-642c282f-efdc-4463-95c2-9bd1f7f56804
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4070871497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4070871497
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2213379952
Short name T899
Test name
Test status
Simulation time 155309173 ps
CPU time 28.1 seconds
Started Mar 10 02:09:58 PM PDT 24
Finished Mar 10 02:10:26 PM PDT 24
Peak memory 205944 kb
Host smart-b598fd2c-16cd-42c1-8fa2-f0e601089ff1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2213379952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.2213379952
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.682955185
Short name T346
Test name
Test status
Simulation time 5979858 ps
CPU time 0.8 seconds
Started Mar 10 02:10:04 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 194176 kb
Host smart-a7cf2a75-f4a1-4edd-9df3-63a11347bb20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682955185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res
et_error.682955185
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3146055590
Short name T467
Test name
Test status
Simulation time 107598250 ps
CPU time 2.29 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:02 PM PDT 24
Peak memory 202416 kb
Host smart-7967d819-5f07-439d-8085-5ba1b6a308b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3146055590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3146055590
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3211053842
Short name T475
Test name
Test status
Simulation time 32559007 ps
CPU time 6.4 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:10:06 PM PDT 24
Peak memory 202440 kb
Host smart-09455cc7-3ff4-454e-a6e4-42c278308ea1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3211053842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3211053842
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.4102056449
Short name T158
Test name
Test status
Simulation time 44187044221 ps
CPU time 105.24 seconds
Started Mar 10 02:09:59 PM PDT 24
Finished Mar 10 02:11:45 PM PDT 24
Peak memory 202512 kb
Host smart-b8f245f5-5eb8-41f2-95d6-e2071dc15416
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4102056449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.4102056449
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2562524280
Short name T323
Test name
Test status
Simulation time 308064858 ps
CPU time 5.67 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:06 PM PDT 24
Peak memory 202440 kb
Host smart-44855dc3-9f4a-4b23-9edc-7368103cba6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562524280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2562524280
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.693126185
Short name T398
Test name
Test status
Simulation time 1452186586 ps
CPU time 11.16 seconds
Started Mar 10 02:10:03 PM PDT 24
Finished Mar 10 02:10:14 PM PDT 24
Peak memory 202436 kb
Host smart-e2a4c2d4-cdf7-4730-844b-433a92fb5bf1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693126185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.693126185
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.2515137261
Short name T863
Test name
Test status
Simulation time 185998512 ps
CPU time 2.9 seconds
Started Mar 10 02:10:03 PM PDT 24
Finished Mar 10 02:10:06 PM PDT 24
Peak memory 202380 kb
Host smart-aad66326-b4e9-4c81-875a-38112149c8c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2515137261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2515137261
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4031987516
Short name T125
Test name
Test status
Simulation time 304927395534 ps
CPU time 172.9 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:12:53 PM PDT 24
Peak memory 202568 kb
Host smart-c7f0fd41-45e5-4462-b1cb-7938d896b390
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031987516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4031987516
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4058287334
Short name T474
Test name
Test status
Simulation time 141546618018 ps
CPU time 138.96 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:12:20 PM PDT 24
Peak memory 202560 kb
Host smart-209ed116-63db-4ef2-9dd7-c656bdb13859
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4058287334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4058287334
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.393470095
Short name T870
Test name
Test status
Simulation time 100040120 ps
CPU time 7.39 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:08 PM PDT 24
Peak memory 202420 kb
Host smart-ac6d47af-0f3d-4955-9558-a61bfd38914f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393470095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.393470095
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3213838133
Short name T595
Test name
Test status
Simulation time 1887032369 ps
CPU time 6.3 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:07 PM PDT 24
Peak memory 202424 kb
Host smart-6748ab98-8dd6-4762-8271-0736b88c6ebb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3213838133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3213838133
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.939965266
Short name T786
Test name
Test status
Simulation time 75317301 ps
CPU time 1.6 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202324 kb
Host smart-33e7cdf3-1ad5-4f7c-86dc-88c248ccb7bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=939965266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.939965266
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4212072185
Short name T520
Test name
Test status
Simulation time 4087753336 ps
CPU time 7.44 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:09 PM PDT 24
Peak memory 202484 kb
Host smart-6c7c8f5a-4208-4a43-a6ca-59c1a85af345
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212072185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4212072185
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1547290843
Short name T444
Test name
Test status
Simulation time 3173971147 ps
CPU time 8.26 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:09 PM PDT 24
Peak memory 202568 kb
Host smart-0a34d4ef-4e2a-49a5-b7e3-06323f19b430
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1547290843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1547290843
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2015638364
Short name T300
Test name
Test status
Simulation time 8998537 ps
CPU time 1.19 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:03 PM PDT 24
Peak memory 202456 kb
Host smart-9c24dc58-4621-4e63-a69a-e89a15b42ba7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015638364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2015638364
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1942737389
Short name T806
Test name
Test status
Simulation time 304556439 ps
CPU time 31.06 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 203416 kb
Host smart-b92ddd1d-709d-4c4f-9310-3701ba2428c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1942737389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1942737389
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.173662912
Short name T180
Test name
Test status
Simulation time 2580702998 ps
CPU time 39.14 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202500 kb
Host smart-90f5de4a-b94e-4218-9734-7846c1818f01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=173662912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.173662912
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4198683988
Short name T39
Test name
Test status
Simulation time 634082709 ps
CPU time 114.57 seconds
Started Mar 10 02:10:04 PM PDT 24
Finished Mar 10 02:11:58 PM PDT 24
Peak memory 204536 kb
Host smart-aa31a9de-b0b8-49f4-a3d7-d008f38e884f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4198683988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.4198683988
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4172453252
Short name T599
Test name
Test status
Simulation time 11179164349 ps
CPU time 149.36 seconds
Started Mar 10 02:10:04 PM PDT 24
Finished Mar 10 02:12:33 PM PDT 24
Peak memory 204168 kb
Host smart-f4f026fa-2b27-49c9-b4d5-1b1cd76287e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4172453252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.4172453252
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2630994018
Short name T843
Test name
Test status
Simulation time 3686641244 ps
CPU time 11.49 seconds
Started Mar 10 02:10:03 PM PDT 24
Finished Mar 10 02:10:14 PM PDT 24
Peak memory 202548 kb
Host smart-1e7f0692-1c9d-4365-bce3-f986d1b3f38c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2630994018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2630994018
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3703538788
Short name T76
Test name
Test status
Simulation time 1094100382 ps
CPU time 4.26 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 202388 kb
Host smart-dfd8b871-356b-4335-be8b-cbf35bab75cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3703538788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3703538788
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1729488745
Short name T150
Test name
Test status
Simulation time 55291189665 ps
CPU time 276.8 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:14:45 PM PDT 24
Peak memory 203748 kb
Host smart-527b547d-befa-45cd-b437-6ae4e704664f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1729488745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1729488745
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1618703201
Short name T797
Test name
Test status
Simulation time 1317482147 ps
CPU time 11.58 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:10:19 PM PDT 24
Peak memory 202456 kb
Host smart-a35d2957-0ad2-49d7-bd29-4d7a56ad37e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1618703201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1618703201
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1957297145
Short name T861
Test name
Test status
Simulation time 2124327942 ps
CPU time 9.02 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:10:17 PM PDT 24
Peak memory 202448 kb
Host smart-8a3d842b-6825-4a05-b436-67b3a32e75c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1957297145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1957297145
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.1349896018
Short name T452
Test name
Test status
Simulation time 9559934 ps
CPU time 1.18 seconds
Started Mar 10 02:10:10 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 202304 kb
Host smart-bac2c97f-df19-426c-819e-fa6375d76b2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1349896018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1349896018
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3755458371
Short name T627
Test name
Test status
Simulation time 13872645787 ps
CPU time 16.38 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:10:24 PM PDT 24
Peak memory 202512 kb
Host smart-b1bd7873-b8e8-4a03-a50c-f2062f641902
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755458371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3755458371
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2724883765
Short name T105
Test name
Test status
Simulation time 13782167334 ps
CPU time 53.26 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 202552 kb
Host smart-bfe9cc54-5856-4e64-ad4e-02fdbbb141e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2724883765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2724883765
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1010053028
Short name T451
Test name
Test status
Simulation time 18098683 ps
CPU time 1.59 seconds
Started Mar 10 02:10:06 PM PDT 24
Finished Mar 10 02:10:08 PM PDT 24
Peak memory 202376 kb
Host smart-5f3d694b-e4cb-4fb8-bd81-99a895346cfa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010053028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1010053028
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.3200119930
Short name T132
Test name
Test status
Simulation time 164000013 ps
CPU time 4.5 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:10:12 PM PDT 24
Peak memory 202424 kb
Host smart-c53cfd40-7805-4530-a673-974afa66b410
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3200119930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3200119930
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1908784863
Short name T298
Test name
Test status
Simulation time 10169504 ps
CPU time 1.25 seconds
Started Mar 10 02:10:04 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 202392 kb
Host smart-1964eddd-4b3b-4717-ad2a-cfbf20b136a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1908784863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1908784863
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3460754766
Short name T729
Test name
Test status
Simulation time 2010826734 ps
CPU time 9.28 seconds
Started Mar 10 02:10:01 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 202452 kb
Host smart-f827154a-39c5-42d0-97bc-8d8ea4085c84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460754766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3460754766
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.585394552
Short name T792
Test name
Test status
Simulation time 834063656 ps
CPU time 6.24 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:10:13 PM PDT 24
Peak memory 202464 kb
Host smart-c2d2f804-d7cc-4fd5-969e-6bc3577d9dd9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=585394552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.585394552
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2811664261
Short name T48
Test name
Test status
Simulation time 12432939 ps
CPU time 1.17 seconds
Started Mar 10 02:10:00 PM PDT 24
Finished Mar 10 02:10:01 PM PDT 24
Peak memory 202452 kb
Host smart-ae45c72a-d9ec-4b3f-b7f0-059868fe25cf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811664261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2811664261
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3209823837
Short name T746
Test name
Test status
Simulation time 5090802574 ps
CPU time 79.3 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:11:27 PM PDT 24
Peak memory 203584 kb
Host smart-0fdfd96a-b94d-4327-9a7d-94b3872c5361
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3209823837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3209823837
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.109378119
Short name T837
Test name
Test status
Simulation time 40898063 ps
CPU time 3.81 seconds
Started Mar 10 02:10:07 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 202464 kb
Host smart-b0a81b74-702b-4cf4-b1c5-300535491e0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109378119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.109378119
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2916160793
Short name T160
Test name
Test status
Simulation time 171806109 ps
CPU time 17.29 seconds
Started Mar 10 02:10:10 PM PDT 24
Finished Mar 10 02:10:28 PM PDT 24
Peak memory 203388 kb
Host smart-c9ee3e3e-97aa-4cab-8f73-bc91478bdca7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2916160793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2916160793
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.475594294
Short name T97
Test name
Test status
Simulation time 2070336543 ps
CPU time 87.75 seconds
Started Mar 10 02:10:06 PM PDT 24
Finished Mar 10 02:11:33 PM PDT 24
Peak memory 205960 kb
Host smart-551a5b78-61eb-4297-ad8c-44aeaa217756
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=475594294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res
et_error.475594294
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1744693701
Short name T753
Test name
Test status
Simulation time 442669474 ps
CPU time 7.93 seconds
Started Mar 10 02:10:09 PM PDT 24
Finished Mar 10 02:10:17 PM PDT 24
Peak memory 202432 kb
Host smart-b909a794-6aba-4559-b469-a92ce738e27b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744693701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1744693701
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.779811363
Short name T879
Test name
Test status
Simulation time 106312102 ps
CPU time 7.48 seconds
Started Mar 10 02:10:17 PM PDT 24
Finished Mar 10 02:10:25 PM PDT 24
Peak memory 202444 kb
Host smart-c2fd14e2-69e7-4a5b-9d7c-2b6144aca097
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=779811363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.779811363
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.548748163
Short name T119
Test name
Test status
Simulation time 41744289240 ps
CPU time 195.08 seconds
Started Mar 10 02:10:17 PM PDT 24
Finished Mar 10 02:13:32 PM PDT 24
Peak memory 203592 kb
Host smart-21c1a106-3a3f-4d18-aa23-e7596e28423c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=548748163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo
w_rsp.548748163
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3812541972
Short name T577
Test name
Test status
Simulation time 74550539 ps
CPU time 4.54 seconds
Started Mar 10 02:10:12 PM PDT 24
Finished Mar 10 02:10:17 PM PDT 24
Peak memory 202372 kb
Host smart-7c07b2a8-8628-47d8-8fa3-9371b021390a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812541972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3812541972
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.346667301
Short name T199
Test name
Test status
Simulation time 1713439367 ps
CPU time 6.7 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:10:21 PM PDT 24
Peak memory 202440 kb
Host smart-637843d0-f7ed-45d6-855c-1e97f1a0435d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=346667301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.346667301
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3409914375
Short name T633
Test name
Test status
Simulation time 48737338 ps
CPU time 7.44 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:10:22 PM PDT 24
Peak memory 202388 kb
Host smart-2b396382-ae23-4d6d-83d1-6d66c5058faa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3409914375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3409914375
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.501661811
Short name T502
Test name
Test status
Simulation time 54269814413 ps
CPU time 103.82 seconds
Started Mar 10 02:10:14 PM PDT 24
Finished Mar 10 02:11:58 PM PDT 24
Peak memory 202512 kb
Host smart-66a85d4d-d4e6-4a51-a3ac-7d68e6e809c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=501661811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.501661811
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3475786498
Short name T488
Test name
Test status
Simulation time 38667573015 ps
CPU time 170.37 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:13:05 PM PDT 24
Peak memory 202568 kb
Host smart-d9056807-54fe-4d94-a260-7b39d3005ca5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3475786498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3475786498
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.702350011
Short name T442
Test name
Test status
Simulation time 91872943 ps
CPU time 4.63 seconds
Started Mar 10 02:10:14 PM PDT 24
Finished Mar 10 02:10:19 PM PDT 24
Peak memory 202452 kb
Host smart-e9d5c7bd-06cf-47d6-9808-37dea4d9c487
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702350011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.702350011
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1750015040
Short name T4
Test name
Test status
Simulation time 158225847 ps
CPU time 6.21 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:10:20 PM PDT 24
Peak memory 202412 kb
Host smart-e0f3c399-eac3-473f-b208-796d03c5ce62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1750015040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1750015040
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3836255303
Short name T841
Test name
Test status
Simulation time 264950388 ps
CPU time 1.7 seconds
Started Mar 10 02:10:09 PM PDT 24
Finished Mar 10 02:10:11 PM PDT 24
Peak memory 202360 kb
Host smart-68d0633e-1adb-4958-a828-fc04ecbb8f91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3836255303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3836255303
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1539020696
Short name T551
Test name
Test status
Simulation time 3668872526 ps
CPU time 8.8 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:10:17 PM PDT 24
Peak memory 202540 kb
Host smart-dab3a0a3-dd13-4205-bc74-a11a15412bda
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539020696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1539020696
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1463071000
Short name T756
Test name
Test status
Simulation time 1644927810 ps
CPU time 5.63 seconds
Started Mar 10 02:10:18 PM PDT 24
Finished Mar 10 02:10:24 PM PDT 24
Peak memory 202456 kb
Host smart-843576d8-de7c-49a5-b928-65233bcbcff9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1463071000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1463071000
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.422569614
Short name T248
Test name
Test status
Simulation time 10983106 ps
CPU time 1.1 seconds
Started Mar 10 02:10:08 PM PDT 24
Finished Mar 10 02:10:10 PM PDT 24
Peak memory 202368 kb
Host smart-e86f5299-1d6b-40f0-8d3c-62db861078fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422569614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.422569614
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.202336134
Short name T232
Test name
Test status
Simulation time 13315008015 ps
CPU time 93.49 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:11:48 PM PDT 24
Peak memory 204596 kb
Host smart-817efec3-1db5-4ff0-917c-4a0cc63b975a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=202336134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.202336134
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2004803476
Short name T457
Test name
Test status
Simulation time 420457907 ps
CPU time 6.06 seconds
Started Mar 10 02:10:18 PM PDT 24
Finished Mar 10 02:10:24 PM PDT 24
Peak memory 202452 kb
Host smart-fdd88cb6-23be-44f8-817d-dcf3cc553261
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2004803476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2004803476
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.23588687
Short name T141
Test name
Test status
Simulation time 862359966 ps
CPU time 71.99 seconds
Started Mar 10 02:10:19 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 205104 kb
Host smart-ab13babf-de37-454a-ae47-24f4f3389e32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23588687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rese
t_error.23588687
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2480229601
Short name T296
Test name
Test status
Simulation time 36974930 ps
CPU time 3.83 seconds
Started Mar 10 02:10:13 PM PDT 24
Finished Mar 10 02:10:18 PM PDT 24
Peak memory 202444 kb
Host smart-37d8890e-0c00-4285-9c54-9005df6ebf29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2480229601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2480229601
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.4048107577
Short name T162
Test name
Test status
Simulation time 178316475 ps
CPU time 1.74 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:29 PM PDT 24
Peak memory 202432 kb
Host smart-452fae55-7608-489e-93c1-3ac4477a50e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048107577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4048107577
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3273724381
Short name T326
Test name
Test status
Simulation time 1745554202 ps
CPU time 14.21 seconds
Started Mar 10 02:10:22 PM PDT 24
Finished Mar 10 02:10:36 PM PDT 24
Peak memory 202392 kb
Host smart-36813326-687b-4421-b5f8-15c85f06bf8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3273724381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.3273724381
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.842493345
Short name T244
Test name
Test status
Simulation time 253921316 ps
CPU time 5.18 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:10:25 PM PDT 24
Peak memory 202444 kb
Host smart-772b3f4c-a5c7-4c0f-8da2-7c60b709ce57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842493345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.842493345
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.963779034
Short name T585
Test name
Test status
Simulation time 71557464 ps
CPU time 7.17 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:10:27 PM PDT 24
Peak memory 202440 kb
Host smart-03340e6d-bef0-4392-884f-3a230f299942
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=963779034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.963779034
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.178657711
Short name T865
Test name
Test status
Simulation time 1353084288 ps
CPU time 13.65 seconds
Started Mar 10 02:10:18 PM PDT 24
Finished Mar 10 02:10:33 PM PDT 24
Peak memory 202360 kb
Host smart-22317de7-4381-4c6d-94db-a5984b20cce5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178657711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.178657711
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1859003071
Short name T730
Test name
Test status
Simulation time 18179271914 ps
CPU time 65.22 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 202564 kb
Host smart-e7001ce4-1f87-49c9-b3f9-0aa92a8293d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859003071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1859003071
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3381611388
Short name T620
Test name
Test status
Simulation time 75152593457 ps
CPU time 202.84 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:13:44 PM PDT 24
Peak memory 202572 kb
Host smart-428d0ead-ade0-4f12-ad2e-1e4eb893c9e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3381611388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3381611388
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1080910965
Short name T263
Test name
Test status
Simulation time 235267804 ps
CPU time 5.55 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:26 PM PDT 24
Peak memory 202400 kb
Host smart-24a2793e-18e1-464c-a3f3-e19195a0c393
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080910965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1080910965
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.1367550335
Short name T22
Test name
Test status
Simulation time 1808571424 ps
CPU time 12.74 seconds
Started Mar 10 02:10:18 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 202404 kb
Host smart-1db69e94-b009-4787-88a8-4f35b6639b77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1367550335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1367550335
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.2094290768
Short name T138
Test name
Test status
Simulation time 64299549 ps
CPU time 1.63 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:10:22 PM PDT 24
Peak memory 202412 kb
Host smart-31d5af69-ae8a-458f-b392-5052f0b9824f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2094290768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2094290768
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1615311428
Short name T268
Test name
Test status
Simulation time 1826450127 ps
CPU time 8.6 seconds
Started Mar 10 02:10:18 PM PDT 24
Finished Mar 10 02:10:27 PM PDT 24
Peak memory 202428 kb
Host smart-6cae3b9c-c6ce-42d6-99b1-07c92c86369e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615311428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1615311428
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.210017031
Short name T187
Test name
Test status
Simulation time 1331492813 ps
CPU time 8.53 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:30 PM PDT 24
Peak memory 202436 kb
Host smart-13f3b299-02f6-48c5-b2c8-5d1c0b161b3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=210017031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.210017031
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3886937425
Short name T409
Test name
Test status
Simulation time 11948971 ps
CPU time 1.04 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:22 PM PDT 24
Peak memory 202472 kb
Host smart-ad83ec58-32ec-480e-9835-9f9d55b941a1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886937425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3886937425
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.643997645
Short name T104
Test name
Test status
Simulation time 17003720227 ps
CPU time 80.02 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:11:41 PM PDT 24
Peak memory 202504 kb
Host smart-1647c5e1-a7b0-4ffb-afba-e6851d143094
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=643997645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.643997645
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3479570473
Short name T479
Test name
Test status
Simulation time 8457612670 ps
CPU time 42.16 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 202588 kb
Host smart-ccc2acd6-f4bf-44dc-9d45-818068e9b9dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3479570473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3479570473
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.4165361002
Short name T360
Test name
Test status
Simulation time 540914307 ps
CPU time 48.37 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:11:09 PM PDT 24
Peak memory 204480 kb
Host smart-97b285ab-bb22-429e-a04b-2ea03b6e7f51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4165361002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.4165361002
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.694491811
Short name T112
Test name
Test status
Simulation time 3674209723 ps
CPU time 40.37 seconds
Started Mar 10 02:10:22 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 204588 kb
Host smart-d849ee3c-8b5e-4b46-9127-01037ba507df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=694491811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res
et_error.694491811
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3708098035
Short name T371
Test name
Test status
Simulation time 9555949 ps
CPU time 1.15 seconds
Started Mar 10 02:10:19 PM PDT 24
Finished Mar 10 02:10:20 PM PDT 24
Peak memory 202436 kb
Host smart-75f434aa-d7f7-4c45-983a-83b7f7f0568d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3708098035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3708098035
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3609718324
Short name T392
Test name
Test status
Simulation time 16132197 ps
CPU time 2.21 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:10:26 PM PDT 24
Peak memory 202436 kb
Host smart-3fc9e3c7-9116-4679-9d3b-a22ba80c19ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3609718324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3609718324
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3889439401
Short name T885
Test name
Test status
Simulation time 54709857012 ps
CPU time 369.62 seconds
Started Mar 10 02:10:25 PM PDT 24
Finished Mar 10 02:16:35 PM PDT 24
Peak memory 203592 kb
Host smart-db620982-becb-4554-805a-022452e76e95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3889439401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.3889439401
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1077626447
Short name T892
Test name
Test status
Simulation time 1484855198 ps
CPU time 8.13 seconds
Started Mar 10 02:10:23 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 202376 kb
Host smart-3c3a0764-1477-469f-a825-29144273b856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077626447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1077626447
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1871348386
Short name T749
Test name
Test status
Simulation time 36216537 ps
CPU time 3.35 seconds
Started Mar 10 02:10:25 PM PDT 24
Finished Mar 10 02:10:29 PM PDT 24
Peak memory 202360 kb
Host smart-33fc8d1b-c57c-4194-8e32-ebc19c5f7453
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1871348386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1871348386
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.1544813890
Short name T69
Test name
Test status
Simulation time 1261579060 ps
CPU time 5.63 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:27 PM PDT 24
Peak memory 202344 kb
Host smart-c8f3ddc4-37cd-4538-8852-38f27596d79c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1544813890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1544813890
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2065699519
Short name T81
Test name
Test status
Simulation time 141766230600 ps
CPU time 90.15 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:11:54 PM PDT 24
Peak memory 202540 kb
Host smart-bada8ae0-9f28-4cac-a3cd-f4d804503436
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065699519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2065699519
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.502370135
Short name T250
Test name
Test status
Simulation time 21536360686 ps
CPU time 134.7 seconds
Started Mar 10 02:10:26 PM PDT 24
Finished Mar 10 02:12:41 PM PDT 24
Peak memory 202540 kb
Host smart-a6884ec0-459f-4674-94ca-c016d6c577ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=502370135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.502370135
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3094174526
Short name T727
Test name
Test status
Simulation time 15349605 ps
CPU time 1.87 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:10:22 PM PDT 24
Peak memory 202432 kb
Host smart-e8b60eec-9543-4260-b329-4c16762d7c14
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094174526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3094174526
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.2847288144
Short name T850
Test name
Test status
Simulation time 1033009629 ps
CPU time 13.16 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:10:37 PM PDT 24
Peak memory 202396 kb
Host smart-b3edf2e5-0e72-4a08-a9ec-61f8e1f57941
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2847288144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2847288144
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.182943149
Short name T741
Test name
Test status
Simulation time 35934945 ps
CPU time 1.29 seconds
Started Mar 10 02:10:19 PM PDT 24
Finished Mar 10 02:10:20 PM PDT 24
Peak memory 202392 kb
Host smart-2af939ae-b151-4194-8774-eebb7e1730a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=182943149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.182943149
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2726825560
Short name T303
Test name
Test status
Simulation time 19006828890 ps
CPU time 12.07 seconds
Started Mar 10 02:10:20 PM PDT 24
Finished Mar 10 02:10:32 PM PDT 24
Peak memory 202576 kb
Host smart-c98d07df-2ee2-44c6-beeb-63215e0a726a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726825560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2726825560
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2754080443
Short name T374
Test name
Test status
Simulation time 5868777616 ps
CPU time 9.01 seconds
Started Mar 10 02:10:22 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 202556 kb
Host smart-120ac2e7-a5f1-4b97-9410-fa1bfd02ec59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2754080443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2754080443
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.893559210
Short name T33
Test name
Test status
Simulation time 14546114 ps
CPU time 1.34 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:23 PM PDT 24
Peak memory 202404 kb
Host smart-ebe95301-50c2-43fe-b7b8-4c0e3aecd805
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893559210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.893559210
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2399682759
Short name T468
Test name
Test status
Simulation time 1478244453 ps
CPU time 17.75 seconds
Started Mar 10 02:10:23 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202448 kb
Host smart-60f8a922-bd63-4929-8028-ab590c684ac2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2399682759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2399682759
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2110478848
Short name T404
Test name
Test status
Simulation time 7588833646 ps
CPU time 59.63 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:11:24 PM PDT 24
Peak memory 202556 kb
Host smart-9f154937-2c90-4f92-95f0-f74dbc981b7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2110478848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2110478848
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.488903922
Short name T354
Test name
Test status
Simulation time 1388430690 ps
CPU time 110.64 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:12:18 PM PDT 24
Peak memory 204344 kb
Host smart-ff9289a6-f3f3-42b3-9528-6af7286191ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=488903922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand
_reset.488903922
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3968895748
Short name T800
Test name
Test status
Simulation time 6693479142 ps
CPU time 146.61 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:12:51 PM PDT 24
Peak memory 207184 kb
Host smart-76fb091a-889f-4ea2-b38a-e22251882319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3968895748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3968895748
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.542389338
Short name T275
Test name
Test status
Simulation time 172001623 ps
CPU time 7.03 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:10:31 PM PDT 24
Peak memory 202428 kb
Host smart-3a6fddea-742b-4b6b-b0c5-1e277ce39ed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=542389338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.542389338
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.4260498592
Short name T210
Test name
Test status
Simulation time 20896267015 ps
CPU time 156.32 seconds
Started Mar 10 02:10:23 PM PDT 24
Finished Mar 10 02:12:59 PM PDT 24
Peak memory 203508 kb
Host smart-9d6cd406-01fa-4b5c-b3cb-a33cacf8d4c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4260498592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.4260498592
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2615355492
Short name T857
Test name
Test status
Simulation time 42036937 ps
CPU time 5.1 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:33 PM PDT 24
Peak memory 202452 kb
Host smart-22e59506-b3bd-4391-8a50-41eb0f609220
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615355492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2615355492
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.3042235564
Short name T245
Test name
Test status
Simulation time 955375409 ps
CPU time 11.19 seconds
Started Mar 10 02:10:26 PM PDT 24
Finished Mar 10 02:10:38 PM PDT 24
Peak memory 202480 kb
Host smart-10504f3e-d86b-4a30-874c-8fa3828feccc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3042235564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3042235564
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.1012243001
Short name T129
Test name
Test status
Simulation time 39526723 ps
CPU time 5.87 seconds
Started Mar 10 02:10:21 PM PDT 24
Finished Mar 10 02:10:27 PM PDT 24
Peak memory 202412 kb
Host smart-5dec5fca-1382-408f-a6a9-5593b31a4e44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012243001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1012243001
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1589113025
Short name T874
Test name
Test status
Simulation time 63493294280 ps
CPU time 159.17 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:13:04 PM PDT 24
Peak memory 202488 kb
Host smart-7a2f2c0d-8120-4602-a925-565fa78349fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589113025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1589113025
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3069779191
Short name T540
Test name
Test status
Simulation time 8358942532 ps
CPU time 44.68 seconds
Started Mar 10 02:10:22 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202504 kb
Host smart-76eae006-07ad-42c6-994a-662cae952e35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3069779191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3069779191
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3943090131
Short name T124
Test name
Test status
Simulation time 14274699 ps
CPU time 1.64 seconds
Started Mar 10 02:10:24 PM PDT 24
Finished Mar 10 02:10:26 PM PDT 24
Peak memory 202448 kb
Host smart-c2ba0e81-219f-400c-936d-e4d06541b2f6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943090131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3943090131
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.4011516288
Short name T118
Test name
Test status
Simulation time 56403129 ps
CPU time 3.92 seconds
Started Mar 10 02:10:25 PM PDT 24
Finished Mar 10 02:10:29 PM PDT 24
Peak memory 202352 kb
Host smart-9567bbb6-c8a1-4033-9475-9c38067bc9d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4011516288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4011516288
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.683145875
Short name T340
Test name
Test status
Simulation time 14061390 ps
CPU time 1.18 seconds
Started Mar 10 02:10:31 PM PDT 24
Finished Mar 10 02:10:33 PM PDT 24
Peak memory 202332 kb
Host smart-4a193e12-c4df-44a3-9437-dbf46091e9b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=683145875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.683145875
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3142381627
Short name T864
Test name
Test status
Simulation time 2202936500 ps
CPU time 8.97 seconds
Started Mar 10 02:10:26 PM PDT 24
Finished Mar 10 02:10:35 PM PDT 24
Peak memory 202548 kb
Host smart-5bf3a2b8-7f7e-4694-b4da-5905f5081789
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142381627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3142381627
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.865314573
Short name T26
Test name
Test status
Simulation time 946139653 ps
CPU time 5.57 seconds
Started Mar 10 02:10:22 PM PDT 24
Finished Mar 10 02:10:28 PM PDT 24
Peak memory 202460 kb
Host smart-f71309e2-a8f0-46bc-8bb2-274e2e47384c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=865314573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.865314573
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2347619526
Short name T306
Test name
Test status
Simulation time 11557037 ps
CPU time 1.09 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:29 PM PDT 24
Peak memory 202228 kb
Host smart-9cad5bc2-88dc-4a9b-9dab-07d1926c162c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347619526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2347619526
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.37291687
Short name T28
Test name
Test status
Simulation time 679492193 ps
CPU time 10.14 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:38 PM PDT 24
Peak memory 202396 kb
Host smart-4fcfafd7-a400-473b-a8a9-d2437d29b3b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37291687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.37291687
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1699272084
Short name T693
Test name
Test status
Simulation time 4063137571 ps
CPU time 57.45 seconds
Started Mar 10 02:10:28 PM PDT 24
Finished Mar 10 02:11:26 PM PDT 24
Peak memory 202556 kb
Host smart-0f8206c6-c17d-4ef2-958c-3d411553f261
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1699272084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1699272084
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3357148133
Short name T586
Test name
Test status
Simulation time 517460772 ps
CPU time 42.66 seconds
Started Mar 10 02:10:26 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 204660 kb
Host smart-3f3bd8e4-a6b8-4595-8256-764047aeaecb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3357148133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.3357148133
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4275150901
Short name T230
Test name
Test status
Simulation time 6717989593 ps
CPU time 98.19 seconds
Started Mar 10 02:10:28 PM PDT 24
Finished Mar 10 02:12:07 PM PDT 24
Peak memory 205568 kb
Host smart-050cc06c-9eae-41c1-a425-705355397255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4275150901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.4275150901
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.168857939
Short name T522
Test name
Test status
Simulation time 945611190 ps
CPU time 12.51 seconds
Started Mar 10 02:10:29 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202368 kb
Host smart-2685dab4-628d-430a-9ab6-053ba5aaea9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=168857939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.168857939
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2883220962
Short name T389
Test name
Test status
Simulation time 111950064 ps
CPU time 10.09 seconds
Started Mar 10 02:10:32 PM PDT 24
Finished Mar 10 02:10:42 PM PDT 24
Peak memory 202444 kb
Host smart-d293b7bb-66e2-4202-9da8-67a3d0813153
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2883220962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2883220962
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2013940244
Short name T213
Test name
Test status
Simulation time 48143911263 ps
CPU time 196.32 seconds
Started Mar 10 02:10:33 PM PDT 24
Finished Mar 10 02:13:50 PM PDT 24
Peak memory 203552 kb
Host smart-257459be-9dba-44f7-a4a2-f7182869ecb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2013940244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.2013940244
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1362510719
Short name T774
Test name
Test status
Simulation time 56524942 ps
CPU time 2.79 seconds
Started Mar 10 02:10:37 PM PDT 24
Finished Mar 10 02:10:40 PM PDT 24
Peak memory 202448 kb
Host smart-ea78ab03-07a8-410b-9a56-3cf105ccb7bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1362510719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1362510719
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.3157824423
Short name T342
Test name
Test status
Simulation time 179210912 ps
CPU time 2.93 seconds
Started Mar 10 02:10:37 PM PDT 24
Finished Mar 10 02:10:40 PM PDT 24
Peak memory 202440 kb
Host smart-854e7290-784f-488f-9e90-60d3d09c0a59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3157824423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3157824423
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.3185166589
Short name T640
Test name
Test status
Simulation time 113477138 ps
CPU time 5.45 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:10:33 PM PDT 24
Peak memory 202416 kb
Host smart-9ec43bbb-0692-4a11-b22d-893788b34382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3185166589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3185166589
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.682642671
Short name T526
Test name
Test status
Simulation time 41153589045 ps
CPU time 148.06 seconds
Started Mar 10 02:10:27 PM PDT 24
Finished Mar 10 02:12:56 PM PDT 24
Peak memory 202548 kb
Host smart-c210fc7e-adae-4503-a290-f34eba8914a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=682642671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.682642671
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2527518436
Short name T21
Test name
Test status
Simulation time 36069170163 ps
CPU time 180.82 seconds
Started Mar 10 02:10:37 PM PDT 24
Finished Mar 10 02:13:38 PM PDT 24
Peak memory 202572 kb
Host smart-1c601111-529b-4cf7-a4d8-cd72381ea573
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2527518436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2527518436
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2824630414
Short name T534
Test name
Test status
Simulation time 30952470 ps
CPU time 4.15 seconds
Started Mar 10 02:10:29 PM PDT 24
Finished Mar 10 02:10:34 PM PDT 24
Peak memory 202216 kb
Host smart-53c42185-3699-4e8f-9986-1e125ec138d5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824630414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2824630414
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.1272539575
Short name T780
Test name
Test status
Simulation time 53523453 ps
CPU time 6.36 seconds
Started Mar 10 02:10:34 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202440 kb
Host smart-debe1802-fc28-412e-bc52-23900457712e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1272539575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1272539575
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.294831918
Short name T376
Test name
Test status
Simulation time 17915270 ps
CPU time 1.2 seconds
Started Mar 10 02:10:31 PM PDT 24
Finished Mar 10 02:10:32 PM PDT 24
Peak memory 202420 kb
Host smart-733e5bd7-4322-4818-9c22-97e7b8569714
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294831918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.294831918
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.4168120344
Short name T349
Test name
Test status
Simulation time 1467255018 ps
CPU time 8.3 seconds
Started Mar 10 02:10:26 PM PDT 24
Finished Mar 10 02:10:36 PM PDT 24
Peak memory 202456 kb
Host smart-1c5c7c24-7c63-4697-bcbe-005f15f2c315
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4168120344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4168120344
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4252501492
Short name T591
Test name
Test status
Simulation time 10931176 ps
CPU time 1.35 seconds
Started Mar 10 02:10:29 PM PDT 24
Finished Mar 10 02:10:30 PM PDT 24
Peak memory 202464 kb
Host smart-7d8c884a-8bbd-435b-bf1f-2c13dfda16e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252501492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4252501492
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2359513435
Short name T515
Test name
Test status
Simulation time 5693721801 ps
CPU time 93.02 seconds
Started Mar 10 02:10:33 PM PDT 24
Finished Mar 10 02:12:07 PM PDT 24
Peak memory 204992 kb
Host smart-26895c45-80db-49f7-b0bf-47ac45602dad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359513435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2359513435
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.248274458
Short name T471
Test name
Test status
Simulation time 6219541979 ps
CPU time 69.85 seconds
Started Mar 10 02:10:34 PM PDT 24
Finished Mar 10 02:11:44 PM PDT 24
Peak memory 203584 kb
Host smart-beca5be5-1247-4c3b-9948-41d5d6576c33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=248274458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.248274458
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1075125058
Short name T712
Test name
Test status
Simulation time 182935627 ps
CPU time 42.32 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:11:22 PM PDT 24
Peak memory 204552 kb
Host smart-39fee302-6ebd-4174-b8dd-e8a2ab37b29d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1075125058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1075125058
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4176659945
Short name T897
Test name
Test status
Simulation time 1767980771 ps
CPU time 80.58 seconds
Started Mar 10 02:10:32 PM PDT 24
Finished Mar 10 02:11:53 PM PDT 24
Peak memory 204644 kb
Host smart-fa3b4b06-4584-418d-be89-0742a83228c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4176659945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.4176659945
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.983126223
Short name T498
Test name
Test status
Simulation time 42460840 ps
CPU time 3.76 seconds
Started Mar 10 02:10:32 PM PDT 24
Finished Mar 10 02:10:36 PM PDT 24
Peak memory 202428 kb
Host smart-14d62b68-417a-4b14-839b-63eec962ff3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983126223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.983126223
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2068215480
Short name T299
Test name
Test status
Simulation time 217460674 ps
CPU time 1.8 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202444 kb
Host smart-67c5194a-4638-4cac-bb64-0399d362302f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2068215480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2068215480
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3614082454
Short name T873
Test name
Test status
Simulation time 3195917084 ps
CPU time 21.43 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:11:00 PM PDT 24
Peak memory 202572 kb
Host smart-ee001d0e-91cc-48b8-be89-576bd579bc01
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3614082454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3614082454
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3332281681
Short name T177
Test name
Test status
Simulation time 565739347 ps
CPU time 9.26 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:10:48 PM PDT 24
Peak memory 202392 kb
Host smart-b85842a0-b627-41cb-ab7d-0d15b0739dfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3332281681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3332281681
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2403282483
Short name T290
Test name
Test status
Simulation time 57282517 ps
CPU time 4.13 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:10:43 PM PDT 24
Peak memory 202484 kb
Host smart-5e3e025c-3a25-4215-b2e0-bcd393fa025e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2403282483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2403282483
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.679017704
Short name T890
Test name
Test status
Simulation time 20215219 ps
CPU time 1.36 seconds
Started Mar 10 02:10:32 PM PDT 24
Finished Mar 10 02:10:34 PM PDT 24
Peak memory 202328 kb
Host smart-2e0eb6e7-9c57-492b-88c2-4db329e0c1ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=679017704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.679017704
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.692613527
Short name T154
Test name
Test status
Simulation time 3754082613 ps
CPU time 11.26 seconds
Started Mar 10 02:10:41 PM PDT 24
Finished Mar 10 02:10:53 PM PDT 24
Peak memory 202580 kb
Host smart-c4e5bc3b-7c30-4d49-9f6c-ce40433fef00
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=692613527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.692613527
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2176577229
Short name T225
Test name
Test status
Simulation time 24775897121 ps
CPU time 116.87 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:12:38 PM PDT 24
Peak memory 202492 kb
Host smart-d5dc7760-e85b-4299-a4e0-11c2252f3b57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2176577229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2176577229
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3350986104
Short name T675
Test name
Test status
Simulation time 15913857 ps
CPU time 2.33 seconds
Started Mar 10 02:10:33 PM PDT 24
Finished Mar 10 02:10:35 PM PDT 24
Peak memory 202432 kb
Host smart-7bc51d5b-d4e4-418c-a843-9689fb3d0ed1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350986104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3350986104
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.4291003951
Short name T477
Test name
Test status
Simulation time 2207529801 ps
CPU time 7.42 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:10:46 PM PDT 24
Peak memory 202544 kb
Host smart-c3bade91-2083-471e-818b-d105898f1978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4291003951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4291003951
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.1742191654
Short name T554
Test name
Test status
Simulation time 108812151 ps
CPU time 1.41 seconds
Started Mar 10 02:10:33 PM PDT 24
Finished Mar 10 02:10:34 PM PDT 24
Peak memory 202368 kb
Host smart-84a7a743-e2e2-422f-b27a-ac812cc61047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1742191654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1742191654
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2594274514
Short name T569
Test name
Test status
Simulation time 2266565271 ps
CPU time 8.34 seconds
Started Mar 10 02:10:35 PM PDT 24
Finished Mar 10 02:10:43 PM PDT 24
Peak memory 202500 kb
Host smart-9fb46cf9-f381-4aa7-bc29-8b6adce29215
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594274514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2594274514
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3324008636
Short name T312
Test name
Test status
Simulation time 1642137664 ps
CPU time 8.71 seconds
Started Mar 10 02:10:33 PM PDT 24
Finished Mar 10 02:10:42 PM PDT 24
Peak memory 202444 kb
Host smart-2e84d57a-c368-46ad-9b33-40341d3c5435
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3324008636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3324008636
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1317698359
Short name T823
Test name
Test status
Simulation time 9040836 ps
CPU time 1.14 seconds
Started Mar 10 02:10:34 PM PDT 24
Finished Mar 10 02:10:36 PM PDT 24
Peak memory 202464 kb
Host smart-e2f47a82-7054-4777-b998-6bf75a91618c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317698359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1317698359
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1866796107
Short name T98
Test name
Test status
Simulation time 7685914163 ps
CPU time 66.3 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:11:45 PM PDT 24
Peak memory 203560 kb
Host smart-b2bc3eee-9654-42bb-a2f4-ff1b9c44122a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1866796107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1866796107
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2262878807
Short name T435
Test name
Test status
Simulation time 326037918 ps
CPU time 39.13 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:11:19 PM PDT 24
Peak memory 202456 kb
Host smart-c0336822-e612-4760-a564-4f5e22da25dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2262878807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2262878807
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2218184614
Short name T192
Test name
Test status
Simulation time 7989023128 ps
CPU time 141.74 seconds
Started Mar 10 02:10:41 PM PDT 24
Finished Mar 10 02:13:04 PM PDT 24
Peak memory 205968 kb
Host smart-71e144f1-6a9f-40c1-ad55-940f37997630
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2218184614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2218184614
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1317768577
Short name T772
Test name
Test status
Simulation time 459493693 ps
CPU time 36.31 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:11:15 PM PDT 24
Peak memory 204036 kb
Host smart-df280221-4ebe-4b63-91c5-19e55af0c74a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1317768577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.1317768577
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3091026877
Short name T309
Test name
Test status
Simulation time 226239030 ps
CPU time 4.51 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:44 PM PDT 24
Peak memory 202220 kb
Host smart-e8f48b0f-8159-4fe0-ab9e-a6509a3ab22e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091026877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3091026877
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1496782487
Short name T197
Test name
Test status
Simulation time 103357229 ps
CPU time 10.35 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:51 PM PDT 24
Peak memory 202436 kb
Host smart-4f16934d-50a8-4420-b0f7-049e6d98cc11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1496782487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1496782487
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.892170272
Short name T711
Test name
Test status
Simulation time 28559260241 ps
CPU time 104.52 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:12:24 PM PDT 24
Peak memory 202520 kb
Host smart-aab09ece-114f-40d6-a01b-87d960fe595e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=892170272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.892170272
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1825296422
Short name T249
Test name
Test status
Simulation time 32806137 ps
CPU time 3.87 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:44 PM PDT 24
Peak memory 202220 kb
Host smart-b2552f9a-8744-4fce-aa21-32a8eacccde9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1825296422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1825296422
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.1567635270
Short name T229
Test name
Test status
Simulation time 599558031 ps
CPU time 5.5 seconds
Started Mar 10 02:10:41 PM PDT 24
Finished Mar 10 02:10:48 PM PDT 24
Peak memory 202452 kb
Host smart-9581d58d-522d-4495-8518-05ef350d0fe9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1567635270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1567635270
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.2389833821
Short name T294
Test name
Test status
Simulation time 89860743 ps
CPU time 4.75 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:10:44 PM PDT 24
Peak memory 202392 kb
Host smart-0fbbb3c9-bd0a-42ff-b41c-72487d686299
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2389833821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2389833821
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2224396044
Short name T608
Test name
Test status
Simulation time 77351658300 ps
CPU time 171.79 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:13:30 PM PDT 24
Peak memory 202548 kb
Host smart-13e8c8b1-2f6d-4b2c-9c2c-da50ec504e78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224396044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2224396044
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.404096665
Short name T877
Test name
Test status
Simulation time 54248123615 ps
CPU time 136.58 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:12:56 PM PDT 24
Peak memory 202560 kb
Host smart-7f10a138-6935-44d6-8333-4cf73570fdea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=404096665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.404096665
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3047787708
Short name T384
Test name
Test status
Simulation time 112640979 ps
CPU time 8.38 seconds
Started Mar 10 02:10:39 PM PDT 24
Finished Mar 10 02:10:47 PM PDT 24
Peak memory 202452 kb
Host smart-fc717f8b-0c84-43f9-ac18-c3ea30ea049b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047787708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3047787708
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.26752580
Short name T781
Test name
Test status
Simulation time 249246716 ps
CPU time 3.82 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:45 PM PDT 24
Peak memory 202360 kb
Host smart-c55bb107-2e74-4340-9f8c-e6a2cf184ccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26752580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.26752580
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3598187160
Short name T356
Test name
Test status
Simulation time 8440973 ps
CPU time 1.23 seconds
Started Mar 10 02:10:37 PM PDT 24
Finished Mar 10 02:10:40 PM PDT 24
Peak memory 202400 kb
Host smart-cf5d27da-9f10-485f-89a2-f818f4aa1ef0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598187160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3598187160
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2046699094
Short name T854
Test name
Test status
Simulation time 2770724742 ps
CPU time 11.36 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:10:50 PM PDT 24
Peak memory 202528 kb
Host smart-9f7ffde7-87b5-4a6d-9ff3-1f40d2b24566
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046699094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2046699094
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3685132932
Short name T417
Test name
Test status
Simulation time 1057935647 ps
CPU time 8.43 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:49 PM PDT 24
Peak memory 202456 kb
Host smart-18523a40-9db8-43ec-9541-e7c73a6e35e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3685132932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3685132932
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.425817108
Short name T264
Test name
Test status
Simulation time 8311975 ps
CPU time 1.04 seconds
Started Mar 10 02:10:40 PM PDT 24
Finished Mar 10 02:10:41 PM PDT 24
Peak memory 202436 kb
Host smart-17f30801-e8eb-45c7-b95f-6d1d26359005
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425817108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.425817108
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3082482825
Short name T461
Test name
Test status
Simulation time 5154175775 ps
CPU time 81.31 seconds
Started Mar 10 02:10:38 PM PDT 24
Finished Mar 10 02:12:00 PM PDT 24
Peak memory 202604 kb
Host smart-29c3e22d-13a0-4a70-9a1b-d23dcef82233
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3082482825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3082482825
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.241550681
Short name T217
Test name
Test status
Simulation time 5258384512 ps
CPU time 76.16 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:12:01 PM PDT 24
Peak memory 203656 kb
Host smart-d263747c-83a7-4827-8e1e-622e73a7c4c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=241550681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.241550681
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1428515787
Short name T207
Test name
Test status
Simulation time 8269221973 ps
CPU time 153.91 seconds
Started Mar 10 02:10:44 PM PDT 24
Finished Mar 10 02:13:18 PM PDT 24
Peak memory 204940 kb
Host smart-cca2c096-3d79-4d95-8c0a-ef145a9853b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1428515787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.1428515787
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4144877244
Short name T92
Test name
Test status
Simulation time 525184436 ps
CPU time 52.15 seconds
Started Mar 10 02:10:44 PM PDT 24
Finished Mar 10 02:11:37 PM PDT 24
Peak memory 205244 kb
Host smart-8392a3b8-4de7-49e7-bf9e-daeebf481fb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4144877244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.4144877244
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3102960382
Short name T429
Test name
Test status
Simulation time 6183646775 ps
CPU time 17.46 seconds
Started Mar 10 02:07:26 PM PDT 24
Finished Mar 10 02:07:45 PM PDT 24
Peak memory 202560 kb
Host smart-e3127f0e-022c-4c00-8d9e-0174c6cc1175
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3102960382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3102960382
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.424707596
Short name T134
Test name
Test status
Simulation time 75828702809 ps
CPU time 240.86 seconds
Started Mar 10 02:07:26 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 204892 kb
Host smart-d682e38b-03fc-4ad7-9978-c7ea555a60db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=424707596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow
_rsp.424707596
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3100837600
Short name T562
Test name
Test status
Simulation time 12658211 ps
CPU time 1.05 seconds
Started Mar 10 02:07:25 PM PDT 24
Finished Mar 10 02:07:27 PM PDT 24
Peak memory 202440 kb
Host smart-e64f0ff7-fd86-42d9-990d-694a4b784a7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3100837600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3100837600
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3800415665
Short name T745
Test name
Test status
Simulation time 98255152 ps
CPU time 7.07 seconds
Started Mar 10 02:07:25 PM PDT 24
Finished Mar 10 02:07:33 PM PDT 24
Peak memory 202420 kb
Host smart-d5a0c3df-c697-4a57-9cdb-30320712e170
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3800415665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3800415665
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2264796237
Short name T271
Test name
Test status
Simulation time 46675679 ps
CPU time 2.34 seconds
Started Mar 10 02:07:20 PM PDT 24
Finished Mar 10 02:07:22 PM PDT 24
Peak memory 202376 kb
Host smart-820b0008-85b3-4a31-b42f-0eec2952f0d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2264796237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2264796237
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2270312835
Short name T734
Test name
Test status
Simulation time 34379017414 ps
CPU time 144.9 seconds
Started Mar 10 02:07:26 PM PDT 24
Finished Mar 10 02:09:52 PM PDT 24
Peak memory 202584 kb
Host smart-b7e824e3-98af-452c-b1a3-afa0fba92899
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270312835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2270312835
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3831606366
Short name T641
Test name
Test status
Simulation time 7244209565 ps
CPU time 49.81 seconds
Started Mar 10 02:07:25 PM PDT 24
Finished Mar 10 02:08:16 PM PDT 24
Peak memory 202560 kb
Host smart-2acc2b1c-0e47-4ada-8d3a-4bd656ef12ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3831606366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3831606366
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.650936341
Short name T364
Test name
Test status
Simulation time 45493499 ps
CPU time 5.67 seconds
Started Mar 10 02:07:25 PM PDT 24
Finished Mar 10 02:07:32 PM PDT 24
Peak memory 202444 kb
Host smart-c60b18aa-0768-478a-a649-c9a08ebb4230
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650936341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.650936341
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3461098384
Short name T367
Test name
Test status
Simulation time 45900452 ps
CPU time 4.39 seconds
Started Mar 10 02:07:24 PM PDT 24
Finished Mar 10 02:07:29 PM PDT 24
Peak memory 202372 kb
Host smart-e13386a2-97c5-4276-ae39-df4f0fca6eab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3461098384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3461098384
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.708184724
Short name T55
Test name
Test status
Simulation time 63154460 ps
CPU time 1.35 seconds
Started Mar 10 02:07:20 PM PDT 24
Finished Mar 10 02:07:22 PM PDT 24
Peak memory 202392 kb
Host smart-e34ffd48-008e-4154-807e-f27f4ffa869f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708184724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.708184724
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2280568975
Short name T378
Test name
Test status
Simulation time 1270526001 ps
CPU time 6.58 seconds
Started Mar 10 02:07:21 PM PDT 24
Finished Mar 10 02:07:29 PM PDT 24
Peak memory 202376 kb
Host smart-82089af2-b1b0-4fa4-bcf9-58bcf4040662
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280568975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2280568975
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2313459495
Short name T24
Test name
Test status
Simulation time 1044028293 ps
CPU time 7.62 seconds
Started Mar 10 02:07:18 PM PDT 24
Finished Mar 10 02:07:26 PM PDT 24
Peak memory 202444 kb
Host smart-db476e2e-329d-4155-afbb-c978523dd40d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2313459495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2313459495
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2890794816
Short name T196
Test name
Test status
Simulation time 18480172 ps
CPU time 1.1 seconds
Started Mar 10 02:07:19 PM PDT 24
Finished Mar 10 02:07:21 PM PDT 24
Peak memory 202360 kb
Host smart-391520ea-c682-4ce5-82de-adb36b681308
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890794816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2890794816
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.952823609
Short name T529
Test name
Test status
Simulation time 198590223 ps
CPU time 9.53 seconds
Started Mar 10 02:07:34 PM PDT 24
Finished Mar 10 02:07:45 PM PDT 24
Peak memory 202412 kb
Host smart-97ba5f22-7720-4cef-a65f-3402072392aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952823609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.952823609
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1702527701
Short name T421
Test name
Test status
Simulation time 3287373926 ps
CPU time 14.78 seconds
Started Mar 10 02:07:31 PM PDT 24
Finished Mar 10 02:07:47 PM PDT 24
Peak memory 202560 kb
Host smart-3edd4937-8574-48a7-9ac4-e7a8237a8361
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1702527701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1702527701
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4150584824
Short name T67
Test name
Test status
Simulation time 589942705 ps
CPU time 61.94 seconds
Started Mar 10 02:07:35 PM PDT 24
Finished Mar 10 02:08:37 PM PDT 24
Peak memory 204764 kb
Host smart-9e7f3bdc-88c2-4d57-a014-fcd6782fda20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4150584824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.4150584824
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4030372728
Short name T647
Test name
Test status
Simulation time 2126999902 ps
CPU time 54.49 seconds
Started Mar 10 02:07:31 PM PDT 24
Finished Mar 10 02:08:26 PM PDT 24
Peak memory 203372 kb
Host smart-703980e7-bfb8-4ee0-b330-83c72b5eed7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4030372728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.4030372728
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2136495804
Short name T652
Test name
Test status
Simulation time 28284682 ps
CPU time 3.82 seconds
Started Mar 10 02:07:26 PM PDT 24
Finished Mar 10 02:07:31 PM PDT 24
Peak memory 202368 kb
Host smart-d0c1dbc9-4bb4-4f94-8423-81a6a362021d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2136495804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2136495804
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1003034863
Short name T438
Test name
Test status
Simulation time 1110995497 ps
CPU time 10.18 seconds
Started Mar 10 02:10:45 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202440 kb
Host smart-e3433c89-25ca-4514-85f1-9e5bca637655
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1003034863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1003034863
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2611694442
Short name T148
Test name
Test status
Simulation time 84476389 ps
CPU time 1.95 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:10:46 PM PDT 24
Peak memory 202420 kb
Host smart-c0642411-ed59-4967-b550-ba3273db78e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2611694442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2611694442
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.1672046922
Short name T407
Test name
Test status
Simulation time 42535177 ps
CPU time 3.4 seconds
Started Mar 10 02:10:45 PM PDT 24
Finished Mar 10 02:10:50 PM PDT 24
Peak memory 202440 kb
Host smart-f6759065-2aeb-41f7-8a9c-468b7358a0ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1672046922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1672046922
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.3729327702
Short name T845
Test name
Test status
Simulation time 13999419 ps
CPU time 1.67 seconds
Started Mar 10 02:10:42 PM PDT 24
Finished Mar 10 02:10:46 PM PDT 24
Peak memory 202352 kb
Host smart-bff0ba5e-01d9-4c63-8ddc-f51d92bd4c19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3729327702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3729327702
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3171422290
Short name T274
Test name
Test status
Simulation time 4235807962 ps
CPU time 16.29 seconds
Started Mar 10 02:10:45 PM PDT 24
Finished Mar 10 02:11:02 PM PDT 24
Peak memory 202572 kb
Host smart-997b5fea-c7e8-4c40-9414-579b475f1447
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171422290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3171422290
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2262458924
Short name T697
Test name
Test status
Simulation time 67784932835 ps
CPU time 196.35 seconds
Started Mar 10 02:10:49 PM PDT 24
Finished Mar 10 02:14:06 PM PDT 24
Peak memory 202504 kb
Host smart-b6267a5b-0d53-4b83-b52d-321ec3004224
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2262458924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2262458924
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1916933514
Short name T812
Test name
Test status
Simulation time 116445153 ps
CPU time 7.38 seconds
Started Mar 10 02:10:44 PM PDT 24
Finished Mar 10 02:10:53 PM PDT 24
Peak memory 202356 kb
Host smart-a53587e3-b5ab-4f56-ae88-5cb28b1b1d8a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916933514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1916933514
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.3215009652
Short name T696
Test name
Test status
Simulation time 36150307 ps
CPU time 3.5 seconds
Started Mar 10 02:10:44 PM PDT 24
Finished Mar 10 02:10:48 PM PDT 24
Peak memory 202372 kb
Host smart-d7e35bde-e7d3-4972-a19f-a4a20aed8963
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3215009652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3215009652
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.1560286810
Short name T543
Test name
Test status
Simulation time 11726946 ps
CPU time 1.37 seconds
Started Mar 10 02:10:45 PM PDT 24
Finished Mar 10 02:10:47 PM PDT 24
Peak memory 202412 kb
Host smart-796e9bab-e828-401a-8008-3a81250b3133
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1560286810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1560286810
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1910648280
Short name T447
Test name
Test status
Simulation time 2314888877 ps
CPU time 11.22 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202568 kb
Host smart-20befef0-1b7f-474e-a9e5-9630e820e133
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910648280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1910648280
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1684569876
Short name T397
Test name
Test status
Simulation time 675442596 ps
CPU time 6.28 seconds
Started Mar 10 02:10:42 PM PDT 24
Finished Mar 10 02:10:50 PM PDT 24
Peak memory 202496 kb
Host smart-3d2de7a0-45f6-4209-ba4e-efb3b7bc2e9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1684569876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1684569876
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2155541733
Short name T699
Test name
Test status
Simulation time 11523727 ps
CPU time 1.14 seconds
Started Mar 10 02:10:42 PM PDT 24
Finished Mar 10 02:10:45 PM PDT 24
Peak memory 202404 kb
Host smart-a6ae407c-f8b4-4b90-a564-520e6b9e2692
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155541733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2155541733
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1605236298
Short name T202
Test name
Test status
Simulation time 1526907436 ps
CPU time 23.21 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:11:08 PM PDT 24
Peak memory 202412 kb
Host smart-f80a1b93-24b2-4dfe-b20f-f4ac93166681
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1605236298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1605236298
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.637321124
Short name T410
Test name
Test status
Simulation time 23984990305 ps
CPU time 43.17 seconds
Started Mar 10 02:10:44 PM PDT 24
Finished Mar 10 02:11:29 PM PDT 24
Peak memory 202556 kb
Host smart-2bf0281c-515f-4492-a26d-5ca0225df45b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=637321124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.637321124
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4188372238
Short name T624
Test name
Test status
Simulation time 9788652573 ps
CPU time 140.74 seconds
Started Mar 10 02:10:50 PM PDT 24
Finished Mar 10 02:13:10 PM PDT 24
Peak memory 207292 kb
Host smart-0aa6a82d-9cda-4dd1-a4a6-978ea65ffd96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4188372238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.4188372238
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4053419271
Short name T536
Test name
Test status
Simulation time 218112860 ps
CPU time 43.34 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 203444 kb
Host smart-58602134-bc19-4dbf-9a7b-8de16b07e11a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4053419271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.4053419271
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.443519374
Short name T41
Test name
Test status
Simulation time 49725641 ps
CPU time 6.44 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:10:51 PM PDT 24
Peak memory 202440 kb
Host smart-d48355d6-d8db-4dbd-9920-a4fba949dfc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=443519374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.443519374
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.149488395
Short name T546
Test name
Test status
Simulation time 545050532 ps
CPU time 9.58 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 202452 kb
Host smart-0f230772-8a30-4177-ab13-d39b9d23928c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=149488395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.149488395
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1980086070
Short name T670
Test name
Test status
Simulation time 60203522562 ps
CPU time 171.46 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:13:44 PM PDT 24
Peak memory 203512 kb
Host smart-d0f99845-b2f5-49e9-9519-4cf9ae5560ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1980086070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.1980086070
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2582785438
Short name T888
Test name
Test status
Simulation time 21899601 ps
CPU time 2.71 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202448 kb
Host smart-60220338-f783-4e70-b133-b6caa03e0acb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2582785438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2582785438
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3227673660
Short name T379
Test name
Test status
Simulation time 254293744 ps
CPU time 6.31 seconds
Started Mar 10 02:10:51 PM PDT 24
Finished Mar 10 02:10:57 PM PDT 24
Peak memory 202448 kb
Host smart-21cc6a00-985a-4348-9b03-a82209fabcba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227673660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3227673660
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2037602990
Short name T42
Test name
Test status
Simulation time 727884306 ps
CPU time 12.55 seconds
Started Mar 10 02:10:47 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 202364 kb
Host smart-763e4faa-fed8-4506-91f5-51e8ac3daf52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037602990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2037602990
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.468644380
Short name T678
Test name
Test status
Simulation time 31088558567 ps
CPU time 142.49 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:13:10 PM PDT 24
Peak memory 202552 kb
Host smart-abc084ef-e53a-49fb-bc5d-99df5f42969b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=468644380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.468644380
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.225554000
Short name T85
Test name
Test status
Simulation time 25824994303 ps
CPU time 187.33 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:13:55 PM PDT 24
Peak memory 202516 kb
Host smart-5cd303ae-1d78-4376-93af-36aaf7e1d117
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=225554000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.225554000
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.4099099712
Short name T437
Test name
Test status
Simulation time 142790248 ps
CPU time 6.81 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202452 kb
Host smart-d3bd3d8f-5a2e-41fa-afb1-5bd873a82f76
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099099712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.4099099712
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.697195742
Short name T817
Test name
Test status
Simulation time 1110853564 ps
CPU time 13.22 seconds
Started Mar 10 02:10:49 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 202424 kb
Host smart-bcb49121-6f03-403f-915c-b3e9d764767e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=697195742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.697195742
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.912965657
Short name T188
Test name
Test status
Simulation time 61036534 ps
CPU time 1.4 seconds
Started Mar 10 02:10:43 PM PDT 24
Finished Mar 10 02:10:46 PM PDT 24
Peak memory 202388 kb
Host smart-2a7569e3-4b62-4d54-be3d-c3d70d878e67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912965657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.912965657
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3877213438
Short name T140
Test name
Test status
Simulation time 6273431589 ps
CPU time 11.72 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:11:00 PM PDT 24
Peak memory 202508 kb
Host smart-145740b1-b647-4ceb-8f81-1fedea85a678
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877213438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3877213438
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2957619467
Short name T276
Test name
Test status
Simulation time 944521588 ps
CPU time 5.58 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:10:53 PM PDT 24
Peak memory 202436 kb
Host smart-48448757-79cf-4758-842c-d4bd47023cf5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2957619467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2957619467
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2797688295
Short name T330
Test name
Test status
Simulation time 8916571 ps
CPU time 1.15 seconds
Started Mar 10 02:10:50 PM PDT 24
Finished Mar 10 02:10:51 PM PDT 24
Peak memory 202400 kb
Host smart-d95aa28d-3cda-4329-bb0d-0bbe6fdfbe27
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797688295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2797688295
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.4234741538
Short name T329
Test name
Test status
Simulation time 266933607 ps
CPU time 34.06 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:11:23 PM PDT 24
Peak memory 203504 kb
Host smart-9b730063-7b90-4ca3-9c20-b490a04aafe6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4234741538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4234741538
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1472792275
Short name T286
Test name
Test status
Simulation time 1153320044 ps
CPU time 14.01 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 202416 kb
Host smart-e8a37446-712c-4ba9-9234-4591cc1f80c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1472792275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1472792275
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2394827431
Short name T871
Test name
Test status
Simulation time 531076623 ps
CPU time 95.24 seconds
Started Mar 10 02:10:49 PM PDT 24
Finished Mar 10 02:12:25 PM PDT 24
Peak memory 204800 kb
Host smart-fe31b758-d4ff-4738-ba66-2e9c7b4ed884
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2394827431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.2394827431
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3461399666
Short name T231
Test name
Test status
Simulation time 2955171547 ps
CPU time 92.6 seconds
Started Mar 10 02:10:50 PM PDT 24
Finished Mar 10 02:12:23 PM PDT 24
Peak memory 205792 kb
Host smart-106daffe-59ae-4a0e-a22e-8f0b6df4a672
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3461399666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.3461399666
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1677421092
Short name T23
Test name
Test status
Simulation time 2482184289 ps
CPU time 7.11 seconds
Started Mar 10 02:10:48 PM PDT 24
Finished Mar 10 02:10:56 PM PDT 24
Peak memory 202504 kb
Host smart-e4f2b208-333f-4f33-bd4a-b20e603cd7b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1677421092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1677421092
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1304894007
Short name T370
Test name
Test status
Simulation time 570572238 ps
CPU time 7.79 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:11:08 PM PDT 24
Peak memory 202436 kb
Host smart-257686a2-a455-4be2-afc2-8cdac3fb2e14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1304894007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1304894007
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4191329820
Short name T406
Test name
Test status
Simulation time 27453051491 ps
CPU time 55.7 seconds
Started Mar 10 02:10:56 PM PDT 24
Finished Mar 10 02:11:52 PM PDT 24
Peak memory 202564 kb
Host smart-a509b50a-78f6-4e10-b709-ebc452cbac85
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4191329820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.4191329820
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.823652472
Short name T310
Test name
Test status
Simulation time 2131975697 ps
CPU time 5.62 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:11:00 PM PDT 24
Peak memory 202444 kb
Host smart-03032fd1-2038-40bf-8903-d1f47cb88e48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823652472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.823652472
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3340410058
Short name T283
Test name
Test status
Simulation time 64470028 ps
CPU time 6.62 seconds
Started Mar 10 02:10:55 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 202436 kb
Host smart-b1ac132d-78fb-4635-9b32-dd0122c956c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3340410058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3340410058
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2465323392
Short name T135
Test name
Test status
Simulation time 698413040 ps
CPU time 13.31 seconds
Started Mar 10 02:10:49 PM PDT 24
Finished Mar 10 02:11:02 PM PDT 24
Peak memory 202352 kb
Host smart-0708cfe4-c131-43bc-8501-140ca8963550
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2465323392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2465323392
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1146233119
Short name T72
Test name
Test status
Simulation time 45694906841 ps
CPU time 138.41 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:13:13 PM PDT 24
Peak memory 202492 kb
Host smart-8e14e5b1-f620-48e5-b26a-8747d01d836f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146233119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1146233119
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1375807493
Short name T484
Test name
Test status
Simulation time 7293452135 ps
CPU time 38.58 seconds
Started Mar 10 02:10:57 PM PDT 24
Finished Mar 10 02:11:36 PM PDT 24
Peak memory 201848 kb
Host smart-4827ac05-7a8c-435c-8763-9ff31757037c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1375807493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1375807493
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.4291235145
Short name T208
Test name
Test status
Simulation time 69782562 ps
CPU time 6.12 seconds
Started Mar 10 02:10:55 PM PDT 24
Finished Mar 10 02:11:02 PM PDT 24
Peak memory 202412 kb
Host smart-412df678-64b5-4d86-8cf7-c8c9011f7c5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291235145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.4291235145
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.964932280
Short name T345
Test name
Test status
Simulation time 95105856 ps
CPU time 5.62 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:10:59 PM PDT 24
Peak memory 202440 kb
Host smart-0fff3514-10f2-4e74-9944-c982383ac004
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964932280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.964932280
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2587318781
Short name T638
Test name
Test status
Simulation time 64410541 ps
CPU time 1.59 seconds
Started Mar 10 02:10:50 PM PDT 24
Finished Mar 10 02:10:52 PM PDT 24
Peak memory 202396 kb
Host smart-af965a5c-e5d3-4bd4-8d77-0a0942102eb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587318781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2587318781
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1796760113
Short name T74
Test name
Test status
Simulation time 1136012005 ps
CPU time 6.12 seconds
Started Mar 10 02:10:47 PM PDT 24
Finished Mar 10 02:10:54 PM PDT 24
Peak memory 202428 kb
Host smart-5269e52f-3ef6-4c16-9d01-00c4327dc2e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796760113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1796760113
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1338564955
Short name T255
Test name
Test status
Simulation time 1167741504 ps
CPU time 7.53 seconds
Started Mar 10 02:10:51 PM PDT 24
Finished Mar 10 02:10:58 PM PDT 24
Peak memory 202448 kb
Host smart-58a47279-92df-4b6d-88a0-3f8b6ebc0610
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1338564955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1338564955
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4052975390
Short name T17
Test name
Test status
Simulation time 10698549 ps
CPU time 1.07 seconds
Started Mar 10 02:10:47 PM PDT 24
Finished Mar 10 02:10:49 PM PDT 24
Peak memory 202420 kb
Host smart-4eff097f-b122-4619-a509-9358a4f2a4db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052975390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4052975390
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1129492047
Short name T660
Test name
Test status
Simulation time 96345033 ps
CPU time 9.96 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:11:04 PM PDT 24
Peak memory 202440 kb
Host smart-6821bdc1-5461-435d-8b47-966ea4543d85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1129492047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1129492047
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2314376204
Short name T137
Test name
Test status
Simulation time 9316389652 ps
CPU time 38.48 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:11:32 PM PDT 24
Peak memory 202580 kb
Host smart-30f80610-260b-4be1-b751-cd9e8f789d5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2314376204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2314376204
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1342838796
Short name T77
Test name
Test status
Simulation time 5711873987 ps
CPU time 152.57 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:13:26 PM PDT 24
Peak memory 205736 kb
Host smart-a40ebf6f-34d4-4348-b00f-84d25e5ba031
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1342838796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1342838796
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2819293919
Short name T594
Test name
Test status
Simulation time 4426449986 ps
CPU time 123.28 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:12:57 PM PDT 24
Peak memory 206612 kb
Host smart-759d9dc3-1f67-4610-855d-cb114be8b2f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819293919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2819293919
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1046438258
Short name T572
Test name
Test status
Simulation time 69927917 ps
CPU time 6.52 seconds
Started Mar 10 02:10:57 PM PDT 24
Finished Mar 10 02:11:04 PM PDT 24
Peak memory 202436 kb
Host smart-e5c2864f-0305-479a-bbd1-6d6d1cebc695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1046438258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1046438258
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2263738003
Short name T788
Test name
Test status
Simulation time 915699409 ps
CPU time 15.52 seconds
Started Mar 10 02:10:56 PM PDT 24
Finished Mar 10 02:11:12 PM PDT 24
Peak memory 202216 kb
Host smart-780fea03-3641-4c07-8567-91443a047e50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2263738003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2263738003
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3137393529
Short name T133
Test name
Test status
Simulation time 7977832565 ps
CPU time 37.85 seconds
Started Mar 10 02:10:56 PM PDT 24
Finished Mar 10 02:11:34 PM PDT 24
Peak memory 202564 kb
Host smart-121cc67f-fce0-44f9-b0a7-bf08b8a97545
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3137393529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.3137393529
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2542414612
Short name T674
Test name
Test status
Simulation time 595618486 ps
CPU time 7.51 seconds
Started Mar 10 02:10:59 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202664 kb
Host smart-e7213339-956e-445c-a046-27846331e140
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2542414612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2542414612
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1882308495
Short name T816
Test name
Test status
Simulation time 733371865 ps
CPU time 11.99 seconds
Started Mar 10 02:11:07 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202432 kb
Host smart-383119c3-aa72-414e-93e5-010e9943d23d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1882308495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1882308495
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.3309328751
Short name T849
Test name
Test status
Simulation time 90527210 ps
CPU time 8.67 seconds
Started Mar 10 02:10:56 PM PDT 24
Finished Mar 10 02:11:05 PM PDT 24
Peak memory 202344 kb
Host smart-405f13b3-2219-4fc3-90b2-35297ad9b93f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3309328751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3309328751
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1472060739
Short name T530
Test name
Test status
Simulation time 14500787626 ps
CPU time 46.04 seconds
Started Mar 10 02:10:55 PM PDT 24
Finished Mar 10 02:11:41 PM PDT 24
Peak memory 202564 kb
Host smart-86913e06-e643-4695-84a2-961bac7fa448
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472060739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1472060739
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1355862810
Short name T775
Test name
Test status
Simulation time 151647908044 ps
CPU time 174.78 seconds
Started Mar 10 02:10:54 PM PDT 24
Finished Mar 10 02:13:49 PM PDT 24
Peak memory 202588 kb
Host smart-246cb263-db78-4e3f-8d94-44041c8f82d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1355862810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1355862810
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.303880729
Short name T425
Test name
Test status
Simulation time 50473675 ps
CPU time 6.49 seconds
Started Mar 10 02:10:57 PM PDT 24
Finished Mar 10 02:11:04 PM PDT 24
Peak memory 202448 kb
Host smart-c42bc813-bc4b-4717-8e80-666b43357881
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303880729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.303880729
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.2870699098
Short name T362
Test name
Test status
Simulation time 647198371 ps
CPU time 8.97 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:11:09 PM PDT 24
Peak memory 202436 kb
Host smart-8a5af238-2c96-41a1-b6fa-88470c328d0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2870699098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2870699098
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.2147964176
Short name T386
Test name
Test status
Simulation time 12576372 ps
CPU time 1.13 seconds
Started Mar 10 02:10:53 PM PDT 24
Finished Mar 10 02:10:54 PM PDT 24
Peak memory 202416 kb
Host smart-34662dec-3e20-4f03-9ace-437b2efdfb1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2147964176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2147964176
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2969223383
Short name T601
Test name
Test status
Simulation time 9549765416 ps
CPU time 12.44 seconds
Started Mar 10 02:10:57 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 201956 kb
Host smart-6cb7c7e0-a516-4866-a870-dc82c5f55646
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969223383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2969223383
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2796784127
Short name T436
Test name
Test status
Simulation time 1959715915 ps
CPU time 7.85 seconds
Started Mar 10 02:10:55 PM PDT 24
Finished Mar 10 02:11:03 PM PDT 24
Peak memory 202440 kb
Host smart-668810da-cc24-45d3-a9e1-cd33df2b51a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2796784127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2796784127
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2315182647
Short name T798
Test name
Test status
Simulation time 9598273 ps
CPU time 1.39 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 202432 kb
Host smart-1bb898fd-c2d0-4586-817d-807c1dd77d5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315182647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2315182647
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1828035692
Short name T748
Test name
Test status
Simulation time 1590241035 ps
CPU time 27.59 seconds
Started Mar 10 02:11:02 PM PDT 24
Finished Mar 10 02:11:30 PM PDT 24
Peak memory 202400 kb
Host smart-739c1806-b07c-4b38-9ae0-a5dd8c585b87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828035692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1828035692
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2054286115
Short name T420
Test name
Test status
Simulation time 18661635579 ps
CPU time 64.4 seconds
Started Mar 10 02:11:07 PM PDT 24
Finished Mar 10 02:12:12 PM PDT 24
Peak memory 202556 kb
Host smart-284f2ca1-cb1a-4f18-84d6-79cd8ad41ffa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2054286115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2054286115
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1182725811
Short name T8
Test name
Test status
Simulation time 5175857557 ps
CPU time 158.35 seconds
Started Mar 10 02:11:08 PM PDT 24
Finished Mar 10 02:13:47 PM PDT 24
Peak memory 205840 kb
Host smart-9a245957-35ec-4e09-ac82-fe5f158a92e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1182725811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1182725811
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1943109846
Short name T856
Test name
Test status
Simulation time 237931897 ps
CPU time 28.89 seconds
Started Mar 10 02:10:59 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 203436 kb
Host smart-10218505-141d-423b-b7f6-7b9c7d431535
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1943109846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1943109846
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2149183648
Short name T182
Test name
Test status
Simulation time 130559193 ps
CPU time 1.97 seconds
Started Mar 10 02:10:59 PM PDT 24
Finished Mar 10 02:11:01 PM PDT 24
Peak memory 202376 kb
Host smart-4423dadd-e98c-4854-8c0e-affc51769f8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2149183648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2149183648
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.835990423
Short name T185
Test name
Test status
Simulation time 536949245 ps
CPU time 12.66 seconds
Started Mar 10 02:11:01 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202436 kb
Host smart-dab36a14-88b6-4aa1-9d38-c1a55113455a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=835990423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.835990423
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2872059341
Short name T211
Test name
Test status
Simulation time 133354562078 ps
CPU time 227.42 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:14:48 PM PDT 24
Peak memory 203592 kb
Host smart-1a73756f-9f22-4e5c-8b97-2079cf813481
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2872059341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.2872059341
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.666180662
Short name T278
Test name
Test status
Simulation time 53390049 ps
CPU time 1.61 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202664 kb
Host smart-612795a0-11db-479c-bc74-1f15d1f44908
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=666180662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.666180662
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.2555431615
Short name T590
Test name
Test status
Simulation time 10530414 ps
CPU time 1.22 seconds
Started Mar 10 02:11:05 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202484 kb
Host smart-0120fbde-2a87-4e9f-ace5-7a87956c2507
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555431615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2555431615
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.4224572019
Short name T791
Test name
Test status
Simulation time 984460412 ps
CPU time 11.75 seconds
Started Mar 10 02:10:59 PM PDT 24
Finished Mar 10 02:11:11 PM PDT 24
Peak memory 202412 kb
Host smart-0b682496-60d5-4a54-a4d7-47b27ad9fc91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4224572019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.4224572019
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.624245657
Short name T327
Test name
Test status
Simulation time 5948644774 ps
CPU time 9.84 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 202500 kb
Host smart-92babeb5-549e-49c9-90f6-a9339ee80107
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=624245657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.624245657
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3886574557
Short name T664
Test name
Test status
Simulation time 19501702949 ps
CPU time 109.86 seconds
Started Mar 10 02:11:09 PM PDT 24
Finished Mar 10 02:12:59 PM PDT 24
Peak memory 202564 kb
Host smart-17f744ae-a1ae-4e96-ad0a-f6ba7e37bb65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3886574557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3886574557
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.502363179
Short name T832
Test name
Test status
Simulation time 62987681 ps
CPU time 7.22 seconds
Started Mar 10 02:11:00 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202392 kb
Host smart-7425703b-eff8-4eb7-9f0c-d03dc1b0ccc9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502363179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.502363179
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.2163359618
Short name T284
Test name
Test status
Simulation time 396956720 ps
CPU time 4.15 seconds
Started Mar 10 02:11:01 PM PDT 24
Finished Mar 10 02:11:05 PM PDT 24
Peak memory 202440 kb
Host smart-45868b5c-733e-4978-8bfb-8385bd99e775
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2163359618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2163359618
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1779892508
Short name T636
Test name
Test status
Simulation time 8971274 ps
CPU time 1.12 seconds
Started Mar 10 02:11:08 PM PDT 24
Finished Mar 10 02:11:09 PM PDT 24
Peak memory 202376 kb
Host smart-a7f6b117-50ad-47b3-b033-d37fe183dcc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1779892508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1779892508
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1091339998
Short name T872
Test name
Test status
Simulation time 7599758791 ps
CPU time 11.3 seconds
Started Mar 10 02:11:03 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202488 kb
Host smart-65005f00-75d4-4879-afb5-0df0151ff40b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091339998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1091339998
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1536464432
Short name T113
Test name
Test status
Simulation time 14600565567 ps
CPU time 12.25 seconds
Started Mar 10 02:11:01 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202580 kb
Host smart-eb68ce31-7837-4262-a9c7-0841c1936aa4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1536464432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1536464432
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.400664177
Short name T428
Test name
Test status
Simulation time 8404307 ps
CPU time 1.03 seconds
Started Mar 10 02:10:58 PM PDT 24
Finished Mar 10 02:10:59 PM PDT 24
Peak memory 202444 kb
Host smart-e32bd1f4-39f0-4c52-9d5f-7cbf2a088a7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400664177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.400664177
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3296166379
Short name T491
Test name
Test status
Simulation time 6660807104 ps
CPU time 93.57 seconds
Started Mar 10 02:11:09 PM PDT 24
Finished Mar 10 02:12:43 PM PDT 24
Peak memory 202436 kb
Host smart-877f4ade-deaf-4f71-a494-fae9b5caf021
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296166379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3296166379
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2418458418
Short name T715
Test name
Test status
Simulation time 4099482403 ps
CPU time 32.82 seconds
Started Mar 10 02:11:07 PM PDT 24
Finished Mar 10 02:11:40 PM PDT 24
Peak memory 202560 kb
Host smart-3321255b-3426-4e63-8399-4c174d3c9e3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2418458418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2418458418
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3445184647
Short name T494
Test name
Test status
Simulation time 444883625 ps
CPU time 38.89 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:46 PM PDT 24
Peak memory 204500 kb
Host smart-f87454fd-ec36-4482-ac23-95712e69eb69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3445184647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3445184647
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1529779905
Short name T884
Test name
Test status
Simulation time 5877464385 ps
CPU time 165.85 seconds
Started Mar 10 02:11:07 PM PDT 24
Finished Mar 10 02:13:53 PM PDT 24
Peak memory 205316 kb
Host smart-25805eb0-0872-4de6-a009-3ee8de13a104
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529779905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.1529779905
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2379493452
Short name T301
Test name
Test status
Simulation time 440525157 ps
CPU time 6.81 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202432 kb
Host smart-666ee63b-fa76-4b05-b9a8-427b93ed3633
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2379493452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2379493452
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2352951421
Short name T289
Test name
Test status
Simulation time 44721587 ps
CPU time 9.28 seconds
Started Mar 10 02:11:05 PM PDT 24
Finished Mar 10 02:11:15 PM PDT 24
Peak memory 202452 kb
Host smart-b96e8c9d-c6a5-4a42-85a7-1d92679f307c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2352951421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2352951421
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1849768413
Short name T629
Test name
Test status
Simulation time 8650702657 ps
CPU time 68.14 seconds
Started Mar 10 02:11:09 PM PDT 24
Finished Mar 10 02:12:17 PM PDT 24
Peak memory 202532 kb
Host smart-6cd0e5a1-3d4d-4533-89e2-9862dc573970
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1849768413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1849768413
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4109086331
Short name T592
Test name
Test status
Simulation time 1543614100 ps
CPU time 5.44 seconds
Started Mar 10 02:11:04 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 202432 kb
Host smart-45410ba9-b67b-4052-b188-1c9a829c6cc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4109086331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4109086331
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2329308096
Short name T828
Test name
Test status
Simulation time 155318563 ps
CPU time 2.2 seconds
Started Mar 10 02:11:04 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202440 kb
Host smart-9dd2b416-b12c-4f0f-855a-cee50fd62ec9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2329308096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2329308096
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.3847998101
Short name T542
Test name
Test status
Simulation time 3932048035 ps
CPU time 8.58 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202740 kb
Host smart-d1f2e335-7919-4613-93df-d9cee77091e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3847998101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3847998101
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1125227308
Short name T126
Test name
Test status
Simulation time 20219428543 ps
CPU time 41 seconds
Started Mar 10 02:11:04 PM PDT 24
Finished Mar 10 02:11:45 PM PDT 24
Peak memory 202584 kb
Host smart-c2726460-cad2-4845-9a67-c9c9f47f64a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125227308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1125227308
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.109237816
Short name T827
Test name
Test status
Simulation time 16166401916 ps
CPU time 103.78 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:12:50 PM PDT 24
Peak memory 202540 kb
Host smart-fa05e614-8faa-41e8-a14f-927ddb4f5716
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=109237816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.109237816
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.976529663
Short name T716
Test name
Test status
Simulation time 25116384 ps
CPU time 2.12 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202656 kb
Host smart-46744836-ced8-467d-8485-d58441a1f662
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976529663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.976529663
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.489087515
Short name T155
Test name
Test status
Simulation time 2079445469 ps
CPU time 8.19 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:15 PM PDT 24
Peak memory 202224 kb
Host smart-7205aa11-1bbc-46fa-9758-7dab93e2e3b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=489087515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.489087515
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.1654771802
Short name T839
Test name
Test status
Simulation time 12561238 ps
CPU time 0.99 seconds
Started Mar 10 02:11:05 PM PDT 24
Finished Mar 10 02:11:07 PM PDT 24
Peak memory 202392 kb
Host smart-d306f2e9-cdc6-44aa-ae7a-19f554499156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1654771802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1654771802
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1797482018
Short name T336
Test name
Test status
Simulation time 3210774617 ps
CPU time 7.41 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202560 kb
Host smart-df867dbc-849f-439f-8575-a1f615c89ff0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797482018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1797482018
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.62562666
Short name T419
Test name
Test status
Simulation time 3442064765 ps
CPU time 12.54 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:19 PM PDT 24
Peak memory 202572 kb
Host smart-318eb9f0-c9e0-4a41-8f0d-4bfe03c1726c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=62562666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.62562666
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1342518470
Short name T287
Test name
Test status
Simulation time 9348491 ps
CPU time 1.27 seconds
Started Mar 10 02:11:09 PM PDT 24
Finished Mar 10 02:11:10 PM PDT 24
Peak memory 202224 kb
Host smart-462cd536-7ad3-47e6-977d-d9037be20ba3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342518470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1342518470
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2549771460
Short name T145
Test name
Test status
Simulation time 9295434476 ps
CPU time 46.4 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:59 PM PDT 24
Peak memory 203792 kb
Host smart-0ae40247-3e83-4e3a-82e4-d6817ee784aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2549771460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2549771460
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2214581094
Short name T223
Test name
Test status
Simulation time 7893376900 ps
CPU time 53.63 seconds
Started Mar 10 02:11:05 PM PDT 24
Finished Mar 10 02:12:00 PM PDT 24
Peak memory 203504 kb
Host smart-9b278cee-cc62-4460-8ba8-6273c4cf3ffe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2214581094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2214581094
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2933416796
Short name T54
Test name
Test status
Simulation time 505405959 ps
CPU time 45.67 seconds
Started Mar 10 02:11:07 PM PDT 24
Finished Mar 10 02:11:53 PM PDT 24
Peak memory 204712 kb
Host smart-70a0cde0-a85a-4eec-a3f3-73b74b66aa69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2933416796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.2933416796
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3911085932
Short name T507
Test name
Test status
Simulation time 175674780 ps
CPU time 24.08 seconds
Started Mar 10 02:11:08 PM PDT 24
Finished Mar 10 02:11:32 PM PDT 24
Peak memory 203464 kb
Host smart-7a353804-3af9-4a2f-a393-620c94b56efe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3911085932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.3911085932
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.451609643
Short name T635
Test name
Test status
Simulation time 455139280 ps
CPU time 2.7 seconds
Started Mar 10 02:11:08 PM PDT 24
Finished Mar 10 02:11:11 PM PDT 24
Peak memory 202360 kb
Host smart-5809b44f-cdfe-4071-a0a9-166c694239cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=451609643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.451609643
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.203256590
Short name T492
Test name
Test status
Simulation time 123206743 ps
CPU time 15.81 seconds
Started Mar 10 02:11:10 PM PDT 24
Finished Mar 10 02:11:26 PM PDT 24
Peak memory 202408 kb
Host smart-428b434b-ef33-4936-b7b4-595098239d3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=203256590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.203256590
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4225716879
Short name T107
Test name
Test status
Simulation time 25500575231 ps
CPU time 194.86 seconds
Started Mar 10 02:11:10 PM PDT 24
Finished Mar 10 02:14:25 PM PDT 24
Peak memory 203784 kb
Host smart-ccf8e7c6-423e-464a-82ba-59311ffbc0a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4225716879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.4225716879
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1615112502
Short name T311
Test name
Test status
Simulation time 238344902 ps
CPU time 5.79 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:18 PM PDT 24
Peak memory 202440 kb
Host smart-01c1345c-f675-4f85-b2d4-ec7938e1c6b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1615112502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1615112502
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1930482750
Short name T418
Test name
Test status
Simulation time 107432607 ps
CPU time 5.04 seconds
Started Mar 10 02:11:09 PM PDT 24
Finished Mar 10 02:11:15 PM PDT 24
Peak memory 202384 kb
Host smart-e5b74b4f-bc8d-4e31-8291-49f62e04e13b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1930482750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1930482750
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2156386048
Short name T50
Test name
Test status
Simulation time 261490162 ps
CPU time 2.36 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202348 kb
Host smart-2da3b349-dc0f-4808-852a-15297dff7e91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2156386048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2156386048
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3632115935
Short name T427
Test name
Test status
Simulation time 18915319465 ps
CPU time 18.22 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 202504 kb
Host smart-923f4eb5-7d11-4e10-83aa-fa70bfd17370
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632115935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3632115935
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3638506286
Short name T401
Test name
Test status
Simulation time 24950051959 ps
CPU time 114.65 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:13:06 PM PDT 24
Peak memory 202560 kb
Host smart-56eea9d4-6013-48ed-a140-88f7c96b7989
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3638506286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3638506286
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1054994945
Short name T440
Test name
Test status
Simulation time 34419676 ps
CPU time 1.24 seconds
Started Mar 10 02:11:13 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202432 kb
Host smart-9df0f61b-8e80-4b6a-b07b-91c13ddc9608
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054994945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1054994945
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2134645103
Short name T805
Test name
Test status
Simulation time 1489416354 ps
CPU time 3.16 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202452 kb
Host smart-4ff23b22-147c-4748-8eae-ce211a0104ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2134645103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2134645103
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.3776863159
Short name T110
Test name
Test status
Simulation time 67376208 ps
CPU time 1.66 seconds
Started Mar 10 02:11:06 PM PDT 24
Finished Mar 10 02:11:08 PM PDT 24
Peak memory 202352 kb
Host smart-21138a26-8314-41f3-8c4c-87ca9eaf9c51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3776863159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3776863159
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3487895410
Short name T254
Test name
Test status
Simulation time 1813363931 ps
CPU time 9.61 seconds
Started Mar 10 02:11:10 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202384 kb
Host smart-73b2c90a-6af0-483d-bf83-e43e9e4c8ab8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487895410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3487895410
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4131998139
Short name T25
Test name
Test status
Simulation time 1008412136 ps
CPU time 8.07 seconds
Started Mar 10 02:11:14 PM PDT 24
Finished Mar 10 02:11:22 PM PDT 24
Peak memory 202216 kb
Host smart-25bb4bf2-b502-4f8b-8bb8-8b0237e008d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4131998139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4131998139
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.332123698
Short name T18
Test name
Test status
Simulation time 10200527 ps
CPU time 1.1 seconds
Started Mar 10 02:11:08 PM PDT 24
Finished Mar 10 02:11:09 PM PDT 24
Peak memory 202356 kb
Host smart-02da8cfa-cb51-42b5-9e4c-29099479cc46
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332123698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.332123698
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3882243012
Short name T519
Test name
Test status
Simulation time 379853392 ps
CPU time 16.2 seconds
Started Mar 10 02:11:13 PM PDT 24
Finished Mar 10 02:11:29 PM PDT 24
Peak memory 202428 kb
Host smart-5562ab2e-3feb-4004-a809-ad20f997a0b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3882243012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3882243012
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2234180470
Short name T754
Test name
Test status
Simulation time 12576318692 ps
CPU time 41.82 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:54 PM PDT 24
Peak memory 202588 kb
Host smart-a999c56a-1a4d-4f2e-a086-d0b0e7ec21ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2234180470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2234180470
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4014999679
Short name T205
Test name
Test status
Simulation time 196872540 ps
CPU time 28.43 seconds
Started Mar 10 02:11:13 PM PDT 24
Finished Mar 10 02:11:42 PM PDT 24
Peak memory 204484 kb
Host smart-0f8cda3d-aa0c-4e4b-bc06-6b1fbd9f92bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4014999679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.4014999679
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3481261942
Short name T359
Test name
Test status
Simulation time 169187568 ps
CPU time 16.61 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:11:33 PM PDT 24
Peak memory 202428 kb
Host smart-a200a20e-7483-4d6f-af89-6ad99c69dda0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3481261942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.3481261942
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1200010693
Short name T441
Test name
Test status
Simulation time 36398515 ps
CPU time 4.7 seconds
Started Mar 10 02:11:11 PM PDT 24
Finished Mar 10 02:11:16 PM PDT 24
Peak memory 202428 kb
Host smart-08fcee25-bf20-4dec-984d-715dddf9b90c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1200010693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1200010693
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.4109461136
Short name T88
Test name
Test status
Simulation time 976252713 ps
CPU time 23.06 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:11:39 PM PDT 24
Peak memory 202456 kb
Host smart-fe0a1878-ab94-41b9-b262-1eea57ff342a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4109461136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4109461136
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2771605555
Short name T285
Test name
Test status
Simulation time 40248590 ps
CPU time 1.33 seconds
Started Mar 10 02:11:18 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202444 kb
Host smart-45b3bfa5-b848-449a-9486-1691f80aa25b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2771605555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2771605555
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2885804132
Short name T490
Test name
Test status
Simulation time 8296124 ps
CPU time 1.03 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:11:18 PM PDT 24
Peak memory 202448 kb
Host smart-41c625a6-54bd-48a9-ac44-e0f457088c05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2885804132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2885804132
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1385693754
Short name T882
Test name
Test status
Simulation time 394239052 ps
CPU time 6.29 seconds
Started Mar 10 02:11:18 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 202404 kb
Host smart-f938f75c-0873-4e97-8e1b-34633151ec96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1385693754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1385693754
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.164831235
Short name T80
Test name
Test status
Simulation time 77195456576 ps
CPU time 82.27 seconds
Started Mar 10 02:11:15 PM PDT 24
Finished Mar 10 02:12:37 PM PDT 24
Peak memory 202556 kb
Host smart-4dda7c98-a324-4744-b678-3c8d08050871
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=164831235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.164831235
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3217044634
Short name T73
Test name
Test status
Simulation time 51188984965 ps
CPU time 162.26 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:13:59 PM PDT 24
Peak memory 202520 kb
Host smart-16d9d7f5-bd36-41d7-b014-e2c5f9ddf317
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3217044634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3217044634
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.859400545
Short name T505
Test name
Test status
Simulation time 16038869 ps
CPU time 1.7 seconds
Started Mar 10 02:11:20 PM PDT 24
Finished Mar 10 02:11:21 PM PDT 24
Peak memory 202404 kb
Host smart-fe11f23c-9674-4f4a-85a9-bc7ae6b56b69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859400545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.859400545
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.4029460222
Short name T709
Test name
Test status
Simulation time 1557790774 ps
CPU time 11.01 seconds
Started Mar 10 02:11:18 PM PDT 24
Finished Mar 10 02:11:29 PM PDT 24
Peak memory 202408 kb
Host smart-45d2ae0a-f714-43d4-a3a7-92cd39feb0b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029460222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.4029460222
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.3624291860
Short name T552
Test name
Test status
Simulation time 9871663 ps
CPU time 1.39 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:14 PM PDT 24
Peak memory 202364 kb
Host smart-2942aa38-3267-4e9e-8db3-d537bad0655b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3624291860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3624291860
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.199306717
Short name T65
Test name
Test status
Simulation time 1636549726 ps
CPU time 7.15 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202392 kb
Host smart-eaa00bd3-63ad-43cd-845e-783579511b6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=199306717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.199306717
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3105678392
Short name T659
Test name
Test status
Simulation time 3526234578 ps
CPU time 9.3 seconds
Started Mar 10 02:11:10 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202488 kb
Host smart-45334d87-5e2c-4cfd-a072-fe89425969d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3105678392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3105678392
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.736410691
Short name T886
Test name
Test status
Simulation time 8226519 ps
CPU time 1.03 seconds
Started Mar 10 02:11:12 PM PDT 24
Finished Mar 10 02:11:13 PM PDT 24
Peak memory 202408 kb
Host smart-7314d58b-3892-4b5f-a3b7-c245398b75f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736410691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.736410691
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1035894148
Short name T518
Test name
Test status
Simulation time 685831103 ps
CPU time 47.21 seconds
Started Mar 10 02:11:18 PM PDT 24
Finished Mar 10 02:12:05 PM PDT 24
Peak memory 203408 kb
Host smart-43622dc3-b0d6-4904-96eb-fa1692ab8ed2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1035894148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1035894148
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.791247946
Short name T737
Test name
Test status
Simulation time 291258134 ps
CPU time 7.56 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 202412 kb
Host smart-91342c37-9cda-44f8-9e9a-1257d3c433eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=791247946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.791247946
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.243962654
Short name T894
Test name
Test status
Simulation time 141772002 ps
CPU time 13.5 seconds
Started Mar 10 02:11:18 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 203468 kb
Host smart-9b819166-5950-472d-9bc4-080dfa23b7d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=243962654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.243962654
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3140266800
Short name T639
Test name
Test status
Simulation time 568950502 ps
CPU time 46.88 seconds
Started Mar 10 02:11:19 PM PDT 24
Finished Mar 10 02:12:05 PM PDT 24
Peak memory 204268 kb
Host smart-a98924b9-85bb-4a6f-b203-ca92056741cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3140266800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.3140266800
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2448004916
Short name T750
Test name
Test status
Simulation time 83343899 ps
CPU time 4.79 seconds
Started Mar 10 02:11:15 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202436 kb
Host smart-82ec5b52-7d2f-4c8e-ad20-30d3c89153fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2448004916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2448004916
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3660610941
Short name T277
Test name
Test status
Simulation time 102073315 ps
CPU time 13.13 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:36 PM PDT 24
Peak memory 202404 kb
Host smart-f292b3af-eabd-4be5-a4ef-b6944b0f94ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3660610941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3660610941
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3983205396
Short name T215
Test name
Test status
Simulation time 118475750007 ps
CPU time 327.19 seconds
Started Mar 10 02:11:24 PM PDT 24
Finished Mar 10 02:16:51 PM PDT 24
Peak memory 203592 kb
Host smart-c798cc8e-3e01-4c13-b260-8e8fc6074f37
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3983205396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.3983205396
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.939700754
Short name T247
Test name
Test status
Simulation time 6036611794 ps
CPU time 12.79 seconds
Started Mar 10 02:11:21 PM PDT 24
Finished Mar 10 02:11:34 PM PDT 24
Peak memory 202576 kb
Host smart-49b0ee04-4a76-4273-9ee5-bd305652cf1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=939700754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.939700754
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.1487349988
Short name T251
Test name
Test status
Simulation time 24289056 ps
CPU time 1.22 seconds
Started Mar 10 02:11:24 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 202220 kb
Host smart-dad38511-0bd8-4c84-95f2-be92624e7386
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487349988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1487349988
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.2011620750
Short name T12
Test name
Test status
Simulation time 184237145 ps
CPU time 4.24 seconds
Started Mar 10 02:11:16 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202388 kb
Host smart-807c0453-1334-40fa-9fa6-b1cea9d19f0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2011620750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2011620750
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.202411279
Short name T350
Test name
Test status
Simulation time 38261761124 ps
CPU time 156.83 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:14:00 PM PDT 24
Peak memory 202548 kb
Host smart-67c60a72-d534-45db-903a-daa65d9bf249
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=202411279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.202411279
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1814872159
Short name T692
Test name
Test status
Simulation time 11630613765 ps
CPU time 80.09 seconds
Started Mar 10 02:11:17 PM PDT 24
Finished Mar 10 02:12:37 PM PDT 24
Peak memory 202568 kb
Host smart-7a26f9cb-aff7-4e28-a1cd-e9003a70356b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1814872159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1814872159
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.559420665
Short name T40
Test name
Test status
Simulation time 44517295 ps
CPU time 5.23 seconds
Started Mar 10 02:11:22 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 202420 kb
Host smart-1fc5ef3f-0b87-4882-9968-4bece47a1b32
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559420665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.559420665
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.2409174868
Short name T751
Test name
Test status
Simulation time 90305163 ps
CPU time 1.68 seconds
Started Mar 10 02:11:21 PM PDT 24
Finished Mar 10 02:11:23 PM PDT 24
Peak memory 202436 kb
Host smart-019f04e3-e16e-4eca-8748-a72b32941c68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2409174868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2409174868
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.691091501
Short name T506
Test name
Test status
Simulation time 52579769 ps
CPU time 1.25 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:24 PM PDT 24
Peak memory 202360 kb
Host smart-58f1dea1-8dcf-4476-81c0-e2d9fe5c8584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=691091501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.691091501
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2016066897
Short name T175
Test name
Test status
Simulation time 1588000861 ps
CPU time 7.92 seconds
Started Mar 10 02:11:24 PM PDT 24
Finished Mar 10 02:11:32 PM PDT 24
Peak memory 202420 kb
Host smart-54977ab4-1881-4e8e-97c2-a7f28af90fa3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016066897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2016066897
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1322061854
Short name T830
Test name
Test status
Simulation time 776506758 ps
CPU time 5.84 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 202428 kb
Host smart-13c12263-30e6-4a9d-94aa-9ba91e028cd6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1322061854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1322061854
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1226279424
Short name T252
Test name
Test status
Simulation time 8978822 ps
CPU time 1.11 seconds
Started Mar 10 02:11:19 PM PDT 24
Finished Mar 10 02:11:20 PM PDT 24
Peak memory 202420 kb
Host smart-abbab815-b0d0-46a3-a82b-b8eaf3cb4bbe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226279424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1226279424
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1063403761
Short name T174
Test name
Test status
Simulation time 4589991574 ps
CPU time 34.48 seconds
Started Mar 10 02:11:22 PM PDT 24
Finished Mar 10 02:11:56 PM PDT 24
Peak memory 202536 kb
Host smart-8056f864-85c8-4d92-9909-0f3cd47569ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1063403761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1063403761
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2102013775
Short name T198
Test name
Test status
Simulation time 3564515780 ps
CPU time 42.48 seconds
Started Mar 10 02:11:22 PM PDT 24
Finished Mar 10 02:12:04 PM PDT 24
Peak memory 202540 kb
Host smart-2a30f0ba-f2f1-48e5-b80f-b5d79897b848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2102013775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2102013775
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3740400778
Short name T855
Test name
Test status
Simulation time 3191471768 ps
CPU time 133.78 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:13:36 PM PDT 24
Peak memory 207704 kb
Host smart-42591c90-a1a3-4758-b0ca-4cd4b0b05da5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3740400778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.3740400778
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1584781023
Short name T840
Test name
Test status
Simulation time 195348649 ps
CPU time 18.03 seconds
Started Mar 10 02:11:21 PM PDT 24
Finished Mar 10 02:11:39 PM PDT 24
Peak memory 202372 kb
Host smart-bea3d58c-aec9-463b-aebb-d24134db9d52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1584781023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1584781023
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.518586258
Short name T514
Test name
Test status
Simulation time 823556181 ps
CPU time 4.25 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:27 PM PDT 24
Peak memory 202424 kb
Host smart-c787a68c-f19c-4570-be3e-6e0f54a682e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518586258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.518586258
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1985203277
Short name T209
Test name
Test status
Simulation time 1056586336 ps
CPU time 18.61 seconds
Started Mar 10 02:11:27 PM PDT 24
Finished Mar 10 02:11:46 PM PDT 24
Peak memory 202404 kb
Host smart-26ab40d7-ced9-47de-8ade-2aa46a5da965
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1985203277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1985203277
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3695091944
Short name T212
Test name
Test status
Simulation time 34301588490 ps
CPU time 204.55 seconds
Started Mar 10 02:11:28 PM PDT 24
Finished Mar 10 02:14:52 PM PDT 24
Peak memory 202600 kb
Host smart-183549b1-f887-46b7-a137-03a667b9aa9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3695091944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3695091944
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4027907211
Short name T743
Test name
Test status
Simulation time 24642457 ps
CPU time 3.02 seconds
Started Mar 10 02:11:27 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 202452 kb
Host smart-40b9d17f-f4f3-4926-ba96-fc01ffd324e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4027907211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4027907211
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.1445261929
Short name T655
Test name
Test status
Simulation time 38187921 ps
CPU time 3.26 seconds
Started Mar 10 02:11:26 PM PDT 24
Finished Mar 10 02:11:29 PM PDT 24
Peak memory 202436 kb
Host smart-2a701e62-5ad0-4c31-80cf-2794b1edc48f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445261929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1445261929
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.3325879777
Short name T355
Test name
Test status
Simulation time 231663572 ps
CPU time 3.48 seconds
Started Mar 10 02:11:22 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 202368 kb
Host smart-42ff49e2-e123-4a31-b0d0-dac3378f8d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3325879777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3325879777
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.825278188
Short name T149
Test name
Test status
Simulation time 48420041272 ps
CPU time 150.83 seconds
Started Mar 10 02:11:24 PM PDT 24
Finished Mar 10 02:13:55 PM PDT 24
Peak memory 202340 kb
Host smart-184be28f-fe79-4408-8626-4ab2d016d0e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=825278188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.825278188
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.905526289
Short name T525
Test name
Test status
Simulation time 77464582770 ps
CPU time 105.46 seconds
Started Mar 10 02:11:21 PM PDT 24
Finished Mar 10 02:13:07 PM PDT 24
Peak memory 202528 kb
Host smart-3920b0ea-8b55-4f78-88fd-2f51585f9bfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=905526289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.905526289
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3715316471
Short name T571
Test name
Test status
Simulation time 137483857 ps
CPU time 8.55 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 202420 kb
Host smart-c5295704-9417-4a6e-8501-592950b2e1bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715316471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3715316471
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.419246262
Short name T527
Test name
Test status
Simulation time 1424221883 ps
CPU time 7.56 seconds
Started Mar 10 02:11:28 PM PDT 24
Finished Mar 10 02:11:36 PM PDT 24
Peak memory 202448 kb
Host smart-2b9acb39-60d8-4566-b160-69e0af457d19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419246262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.419246262
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.485893184
Short name T504
Test name
Test status
Simulation time 24090166 ps
CPU time 1.34 seconds
Started Mar 10 02:11:23 PM PDT 24
Finished Mar 10 02:11:25 PM PDT 24
Peak memory 202404 kb
Host smart-f72cc173-db22-42b7-a580-e92ebffb234d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485893184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.485893184
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1439993447
Short name T60
Test name
Test status
Simulation time 2700727138 ps
CPU time 9.75 seconds
Started Mar 10 02:11:25 PM PDT 24
Finished Mar 10 02:11:34 PM PDT 24
Peak memory 202544 kb
Host smart-c1197be6-6aef-42f7-bb82-0550f1209701
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439993447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1439993447
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.120696087
Short name T794
Test name
Test status
Simulation time 935771621 ps
CPU time 5.64 seconds
Started Mar 10 02:11:24 PM PDT 24
Finished Mar 10 02:11:30 PM PDT 24
Peak memory 202452 kb
Host smart-3246f534-bda5-475b-91e8-54e550c6851d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=120696087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.120696087
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2405209802
Short name T808
Test name
Test status
Simulation time 10797153 ps
CPU time 1.32 seconds
Started Mar 10 02:11:26 PM PDT 24
Finished Mar 10 02:11:28 PM PDT 24
Peak memory 202440 kb
Host smart-1fc9adf7-5f52-4e02-860e-b38f7aa09a5a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405209802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2405209802
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.881952056
Short name T304
Test name
Test status
Simulation time 6738106580 ps
CPU time 84.62 seconds
Started Mar 10 02:11:26 PM PDT 24
Finished Mar 10 02:12:51 PM PDT 24
Peak memory 203520 kb
Host smart-b8078720-5b54-4f02-96bf-471941992a5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=881952056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.881952056
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4112166473
Short name T531
Test name
Test status
Simulation time 45746829 ps
CPU time 3.15 seconds
Started Mar 10 02:11:27 PM PDT 24
Finished Mar 10 02:11:30 PM PDT 24
Peak memory 202448 kb
Host smart-c995851e-801a-4f5b-be43-b06a591fc29f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4112166473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4112166473
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.400465948
Short name T405
Test name
Test status
Simulation time 2085608664 ps
CPU time 238.42 seconds
Started Mar 10 02:11:27 PM PDT 24
Finished Mar 10 02:15:25 PM PDT 24
Peak memory 209432 kb
Host smart-8625f2ab-9dfb-4d87-8625-965d6938a740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=400465948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.400465948
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2114717715
Short name T43
Test name
Test status
Simulation time 104166366 ps
CPU time 2.52 seconds
Started Mar 10 02:11:27 PM PDT 24
Finished Mar 10 02:11:29 PM PDT 24
Peak memory 202436 kb
Host smart-c0aa6b39-ea05-4972-ac54-4d7842e1f17b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2114717715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2114717715
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3088062095
Short name T818
Test name
Test status
Simulation time 147256339 ps
CPU time 10.09 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:07:48 PM PDT 24
Peak memory 202388 kb
Host smart-8a61186a-9b42-4816-b427-195576000ed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3088062095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3088062095
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2602705090
Short name T824
Test name
Test status
Simulation time 55794011433 ps
CPU time 132.17 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:09:49 PM PDT 24
Peak memory 202580 kb
Host smart-3fdcb7ba-eb2e-43f3-a0ad-06992af6abe7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2602705090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.2602705090
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4240937190
Short name T731
Test name
Test status
Simulation time 85270079 ps
CPU time 5.18 seconds
Started Mar 10 02:07:34 PM PDT 24
Finished Mar 10 02:07:40 PM PDT 24
Peak memory 202488 kb
Host smart-ee41b5b8-73e0-4433-bf1e-16ef9a36daf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4240937190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4240937190
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.4044862617
Short name T353
Test name
Test status
Simulation time 5145246001 ps
CPU time 17.42 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:07:54 PM PDT 24
Peak memory 202500 kb
Host smart-788309bb-9109-41f6-b7ff-62c7522906c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4044862617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4044862617
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.4288290000
Short name T13
Test name
Test status
Simulation time 98784578 ps
CPU time 6.22 seconds
Started Mar 10 02:07:40 PM PDT 24
Finished Mar 10 02:07:46 PM PDT 24
Peak memory 202328 kb
Host smart-58963007-94df-4c70-946a-fb3c04e2599c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4288290000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4288290000
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3376663911
Short name T439
Test name
Test status
Simulation time 13463209054 ps
CPU time 44.24 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202488 kb
Host smart-f813a2dc-65a2-45c1-a062-f7ff4eeb5dd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376663911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3376663911
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.115118956
Short name T739
Test name
Test status
Simulation time 24403075351 ps
CPU time 159.57 seconds
Started Mar 10 02:07:33 PM PDT 24
Finished Mar 10 02:10:13 PM PDT 24
Peak memory 202512 kb
Host smart-ab712b42-5199-40b4-b9cb-8e6fa4ba5d60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=115118956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.115118956
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1455028867
Short name T702
Test name
Test status
Simulation time 208568844 ps
CPU time 6.74 seconds
Started Mar 10 02:07:34 PM PDT 24
Finished Mar 10 02:07:42 PM PDT 24
Peak memory 202468 kb
Host smart-5a60c0dc-7af5-40c5-83b2-5cca31c42e1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455028867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1455028867
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.328317077
Short name T337
Test name
Test status
Simulation time 229444144 ps
CPU time 3.08 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:07:41 PM PDT 24
Peak memory 202452 kb
Host smart-a440970a-f168-439b-b968-475238c346e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328317077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.328317077
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.3555344619
Short name T170
Test name
Test status
Simulation time 19819020 ps
CPU time 1.07 seconds
Started Mar 10 02:07:30 PM PDT 24
Finished Mar 10 02:07:32 PM PDT 24
Peak memory 202384 kb
Host smart-636192d3-2dce-4f57-9ac1-5dda14b0ec5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3555344619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3555344619
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2178220962
Short name T256
Test name
Test status
Simulation time 2659769154 ps
CPU time 9.72 seconds
Started Mar 10 02:07:32 PM PDT 24
Finished Mar 10 02:07:43 PM PDT 24
Peak memory 202492 kb
Host smart-7a1cfd27-71db-4503-9731-c15f5e6adfeb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178220962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2178220962
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3836022073
Short name T509
Test name
Test status
Simulation time 1634601932 ps
CPU time 10.75 seconds
Started Mar 10 02:07:31 PM PDT 24
Finished Mar 10 02:07:42 PM PDT 24
Peak memory 202460 kb
Host smart-b618c7a4-ac6f-4942-bf29-97befdb81bf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3836022073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3836022073
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2302298380
Short name T90
Test name
Test status
Simulation time 8148096 ps
CPU time 1.04 seconds
Started Mar 10 02:07:33 PM PDT 24
Finished Mar 10 02:07:34 PM PDT 24
Peak memory 202444 kb
Host smart-54c83525-3520-453d-946b-b9a729fe378e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302298380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2302298380
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1690540594
Short name T152
Test name
Test status
Simulation time 4844430479 ps
CPU time 67.05 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 203572 kb
Host smart-7df23823-cc18-430c-bf9a-1d61b33f3ddb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690540594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1690540594
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2623388742
Short name T295
Test name
Test status
Simulation time 173656844 ps
CPU time 26.24 seconds
Started Mar 10 02:07:39 PM PDT 24
Finished Mar 10 02:08:05 PM PDT 24
Peak memory 202416 kb
Host smart-1b033665-d7c3-45dd-93ee-d6ef83e0f1e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2623388742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2623388742
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.502822105
Short name T385
Test name
Test status
Simulation time 7616450 ps
CPU time 8.61 seconds
Started Mar 10 02:07:35 PM PDT 24
Finished Mar 10 02:07:45 PM PDT 24
Peak memory 202444 kb
Host smart-11a8c161-dc7e-4f8c-97f0-bb1da816df14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502822105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_
reset.502822105
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1018182928
Short name T239
Test name
Test status
Simulation time 949378352 ps
CPU time 65.19 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 204920 kb
Host smart-19129cc9-d8b6-4ec0-8ff8-6d6716a5d04b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1018182928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.1018182928
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.451281853
Short name T20
Test name
Test status
Simulation time 557232313 ps
CPU time 11.88 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:07:49 PM PDT 24
Peak memory 202448 kb
Host smart-60004e13-5d53-42fe-ae8a-e11094231b91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=451281853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.451281853
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3159773623
Short name T38
Test name
Test status
Simulation time 44124493 ps
CPU time 6.01 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:07:43 PM PDT 24
Peak memory 202452 kb
Host smart-322af1de-0b7d-4b03-b390-b21a442ac445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3159773623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3159773623
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.530397414
Short name T630
Test name
Test status
Simulation time 54472461434 ps
CPU time 88.61 seconds
Started Mar 10 02:07:35 PM PDT 24
Finished Mar 10 02:09:04 PM PDT 24
Peak memory 202572 kb
Host smart-3607deee-7c71-4415-8fba-7ddc36c113a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=530397414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow
_rsp.530397414
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2629135280
Short name T15
Test name
Test status
Simulation time 96685784 ps
CPU time 2.48 seconds
Started Mar 10 02:07:40 PM PDT 24
Finished Mar 10 02:07:43 PM PDT 24
Peak memory 202452 kb
Host smart-fd29733d-7ca2-4cf3-b340-05654891c355
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2629135280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2629135280
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.3534944654
Short name T265
Test name
Test status
Simulation time 430833942 ps
CPU time 5.9 seconds
Started Mar 10 02:07:41 PM PDT 24
Finished Mar 10 02:07:47 PM PDT 24
Peak memory 202436 kb
Host smart-f209f7b6-6988-4896-9cc2-65e3af6dc082
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3534944654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3534944654
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.1298996857
Short name T51
Test name
Test status
Simulation time 272824507 ps
CPU time 6.41 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:07:42 PM PDT 24
Peak memory 202392 kb
Host smart-9af8f261-6393-4331-8a58-4543f116ff95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1298996857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1298996857
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.758514763
Short name T70
Test name
Test status
Simulation time 35331830634 ps
CPU time 65.37 seconds
Started Mar 10 02:07:37 PM PDT 24
Finished Mar 10 02:08:43 PM PDT 24
Peak memory 202576 kb
Host smart-54118100-0f1e-4742-af60-3f7f19d457ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=758514763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.758514763
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2600837020
Short name T375
Test name
Test status
Simulation time 4624779850 ps
CPU time 29.46 seconds
Started Mar 10 02:07:39 PM PDT 24
Finished Mar 10 02:08:09 PM PDT 24
Peak memory 202508 kb
Host smart-889946fb-93b8-471f-9ba7-2507afc26973
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2600837020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2600837020
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2269320986
Short name T685
Test name
Test status
Simulation time 82518422 ps
CPU time 2.07 seconds
Started Mar 10 02:07:35 PM PDT 24
Finished Mar 10 02:07:38 PM PDT 24
Peak memory 202408 kb
Host smart-b30e8801-3b85-4f8a-8e1f-48296b770356
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269320986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2269320986
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.510110607
Short name T789
Test name
Test status
Simulation time 347631046 ps
CPU time 3.92 seconds
Started Mar 10 02:07:38 PM PDT 24
Finished Mar 10 02:07:43 PM PDT 24
Peak memory 202432 kb
Host smart-2d9649e5-488b-4b5b-a4a9-82142c0661a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510110607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.510110607
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2024382571
Short name T176
Test name
Test status
Simulation time 58437371 ps
CPU time 1.99 seconds
Started Mar 10 02:07:34 PM PDT 24
Finished Mar 10 02:07:37 PM PDT 24
Peak memory 202400 kb
Host smart-7844bfc7-d900-4d56-8787-eb82ccf5d971
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2024382571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2024382571
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3725974540
Short name T555
Test name
Test status
Simulation time 2765376009 ps
CPU time 11.44 seconds
Started Mar 10 02:07:39 PM PDT 24
Finished Mar 10 02:07:51 PM PDT 24
Peak memory 202508 kb
Host smart-6574f341-d6b0-4340-9422-22455ef605bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725974540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3725974540
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2069261500
Short name T722
Test name
Test status
Simulation time 861933197 ps
CPU time 5.94 seconds
Started Mar 10 02:07:34 PM PDT 24
Finished Mar 10 02:07:41 PM PDT 24
Peak memory 202456 kb
Host smart-fc225279-65f6-4163-b835-4ee8d1dabad8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2069261500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2069261500
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.706072514
Short name T728
Test name
Test status
Simulation time 8033986 ps
CPU time 1.05 seconds
Started Mar 10 02:07:36 PM PDT 24
Finished Mar 10 02:07:38 PM PDT 24
Peak memory 202452 kb
Host smart-af109583-f7d4-451f-ac50-d970842a7745
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706072514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.706072514
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2479863679
Short name T825
Test name
Test status
Simulation time 3269419017 ps
CPU time 37.06 seconds
Started Mar 10 02:07:42 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 202552 kb
Host smart-0f41a391-99a9-4c85-aa76-d6dce09abd7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2479863679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2479863679
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.81890079
Short name T89
Test name
Test status
Simulation time 567575103 ps
CPU time 38.13 seconds
Started Mar 10 02:07:42 PM PDT 24
Finished Mar 10 02:08:20 PM PDT 24
Peak memory 203412 kb
Host smart-97489efa-19ab-412d-9d5c-9bc207a221cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81890079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.81890079
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1037889104
Short name T887
Test name
Test status
Simulation time 6896178470 ps
CPU time 116.97 seconds
Started Mar 10 02:07:43 PM PDT 24
Finished Mar 10 02:09:40 PM PDT 24
Peak memory 206616 kb
Host smart-e59d09c8-2150-4db0-a5f2-dc40f3f31833
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037889104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1037889104
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3810435549
Short name T561
Test name
Test status
Simulation time 775930592 ps
CPU time 13.96 seconds
Started Mar 10 02:07:41 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202388 kb
Host smart-ef7505ae-47bc-419c-b313-f41f7e14c888
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810435549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3810435549
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1268662484
Short name T46
Test name
Test status
Simulation time 55425505 ps
CPU time 9.88 seconds
Started Mar 10 02:07:48 PM PDT 24
Finished Mar 10 02:07:58 PM PDT 24
Peak memory 202352 kb
Host smart-0a75aabf-dd23-4283-bf86-a86f5c6034b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1268662484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1268662484
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3689867191
Short name T769
Test name
Test status
Simulation time 76529506976 ps
CPU time 301.47 seconds
Started Mar 10 02:07:45 PM PDT 24
Finished Mar 10 02:12:47 PM PDT 24
Peak memory 203592 kb
Host smart-79fdc77b-7eb3-44b7-9e0b-b81f53e08cd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3689867191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.3689867191
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.626869329
Short name T596
Test name
Test status
Simulation time 202417044 ps
CPU time 2.78 seconds
Started Mar 10 02:07:47 PM PDT 24
Finished Mar 10 02:07:50 PM PDT 24
Peak memory 202436 kb
Host smart-f47ce231-a92f-43d2-9235-d28e41752fb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=626869329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.626869329
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3315175859
Short name T465
Test name
Test status
Simulation time 2095938550 ps
CPU time 9.01 seconds
Started Mar 10 02:07:46 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202352 kb
Host smart-dba67088-413b-4af0-94e5-9088a082d8ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3315175859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3315175859
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.1851165315
Short name T508
Test name
Test status
Simulation time 765297550 ps
CPU time 18.27 seconds
Started Mar 10 02:07:48 PM PDT 24
Finished Mar 10 02:08:06 PM PDT 24
Peak memory 202360 kb
Host smart-9d621763-1bea-4027-a9b0-dbf22eb0568f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1851165315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1851165315
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3651681473
Short name T464
Test name
Test status
Simulation time 32280230109 ps
CPU time 108.58 seconds
Started Mar 10 02:07:47 PM PDT 24
Finished Mar 10 02:09:36 PM PDT 24
Peak memory 202576 kb
Host smart-45f9840b-73b3-4850-a84b-7cf877389945
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651681473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3651681473
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.741807743
Short name T650
Test name
Test status
Simulation time 21217895525 ps
CPU time 69.6 seconds
Started Mar 10 02:07:45 PM PDT 24
Finished Mar 10 02:08:55 PM PDT 24
Peak memory 202568 kb
Host smart-cf1e01ce-fc36-4753-82c7-273bb3d01378
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=741807743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.741807743
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3888844184
Short name T450
Test name
Test status
Simulation time 67413947 ps
CPU time 6.11 seconds
Started Mar 10 02:07:47 PM PDT 24
Finished Mar 10 02:07:53 PM PDT 24
Peak memory 202468 kb
Host smart-184e66cf-0fc4-4191-9bdf-0ee0045ff096
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888844184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3888844184
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.3605857872
Short name T628
Test name
Test status
Simulation time 892669925 ps
CPU time 12.78 seconds
Started Mar 10 02:07:46 PM PDT 24
Finished Mar 10 02:07:59 PM PDT 24
Peak memory 202448 kb
Host smart-5b3abab8-ebf3-43e2-9279-432bdd576385
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3605857872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3605857872
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2626847937
Short name T580
Test name
Test status
Simulation time 236574937 ps
CPU time 1.62 seconds
Started Mar 10 02:07:42 PM PDT 24
Finished Mar 10 02:07:44 PM PDT 24
Peak memory 202312 kb
Host smart-4d2cb6cb-f1a9-4df7-8943-16e0ab760cce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2626847937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2626847937
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1418429343
Short name T779
Test name
Test status
Simulation time 2568394611 ps
CPU time 9.14 seconds
Started Mar 10 02:07:42 PM PDT 24
Finished Mar 10 02:07:51 PM PDT 24
Peak memory 202572 kb
Host smart-78eb550c-9cd1-4a48-bb2b-689c7ddbbd25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418429343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1418429343
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2925514548
Short name T503
Test name
Test status
Simulation time 1868607171 ps
CPU time 8.72 seconds
Started Mar 10 02:07:42 PM PDT 24
Finished Mar 10 02:07:51 PM PDT 24
Peak memory 202376 kb
Host smart-778f4636-08e3-4825-86ee-edcd02178579
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2925514548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2925514548
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.4283884399
Short name T317
Test name
Test status
Simulation time 23083268 ps
CPU time 1.05 seconds
Started Mar 10 02:07:41 PM PDT 24
Finished Mar 10 02:07:43 PM PDT 24
Peak memory 202452 kb
Host smart-47c84bb0-1795-4a3a-b9ff-23faadcc5f09
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283884399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4283884399
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2087007097
Short name T101
Test name
Test status
Simulation time 21414536775 ps
CPU time 115.04 seconds
Started Mar 10 02:07:47 PM PDT 24
Finished Mar 10 02:09:42 PM PDT 24
Peak memory 205960 kb
Host smart-7bf60a60-e1bd-4d7c-938d-d6a242e3b85d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2087007097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2087007097
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.183694761
Short name T332
Test name
Test status
Simulation time 432896647 ps
CPU time 31.1 seconds
Started Mar 10 02:07:46 PM PDT 24
Finished Mar 10 02:08:17 PM PDT 24
Peak memory 202436 kb
Host smart-73b18b14-ba9c-44e3-b5ff-1694198c101e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=183694761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.183694761
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1452745682
Short name T584
Test name
Test status
Simulation time 706060712 ps
CPU time 103.59 seconds
Started Mar 10 02:07:46 PM PDT 24
Finished Mar 10 02:09:29 PM PDT 24
Peak memory 204636 kb
Host smart-5f053714-c6fd-4223-b5c1-a58f90f6b4aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1452745682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1452745682
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.676130885
Short name T532
Test name
Test status
Simulation time 3433977590 ps
CPU time 71.68 seconds
Started Mar 10 02:07:49 PM PDT 24
Finished Mar 10 02:09:00 PM PDT 24
Peak memory 204688 kb
Host smart-27dd3045-1b6f-4e30-8285-cb6934847d74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=676130885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese
t_error.676130885
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3677949158
Short name T671
Test name
Test status
Simulation time 184948309 ps
CPU time 6.75 seconds
Started Mar 10 02:07:48 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202412 kb
Host smart-6a45ea97-aa1e-4767-9798-78bf1c1a01bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3677949158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3677949158
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.875037351
Short name T878
Test name
Test status
Simulation time 47830559 ps
CPU time 11.9 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:08:04 PM PDT 24
Peak memory 202432 kb
Host smart-10ac3d9d-a833-46ca-8209-b22218b4ce74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=875037351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.875037351
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2522206043
Short name T220
Test name
Test status
Simulation time 22083682180 ps
CPU time 108.31 seconds
Started Mar 10 02:07:51 PM PDT 24
Finished Mar 10 02:09:40 PM PDT 24
Peak memory 202576 kb
Host smart-2536fd5b-e84b-47b9-b78f-17c7a925c636
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2522206043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2522206043
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.870519277
Short name T64
Test name
Test status
Simulation time 90121405 ps
CPU time 2.16 seconds
Started Mar 10 02:07:54 PM PDT 24
Finished Mar 10 02:07:57 PM PDT 24
Peak memory 202432 kb
Host smart-686205b1-60b2-4c8a-926b-d1625e4dbfd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=870519277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.870519277
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.707268639
Short name T793
Test name
Test status
Simulation time 116336402 ps
CPU time 9.65 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:08:02 PM PDT 24
Peak memory 202444 kb
Host smart-39400ebd-f7ea-4cf5-a418-ed3658ac3ebc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=707268639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.707268639
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1467532079
Short name T833
Test name
Test status
Simulation time 163165706 ps
CPU time 3.56 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:07:56 PM PDT 24
Peak memory 202392 kb
Host smart-6c9bd127-2ba7-402d-b1a5-003edac377c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1467532079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1467532079
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1776876351
Short name T836
Test name
Test status
Simulation time 30698941756 ps
CPU time 73.6 seconds
Started Mar 10 02:07:50 PM PDT 24
Finished Mar 10 02:09:03 PM PDT 24
Peak memory 202580 kb
Host smart-bbdeadab-17e0-470a-8d5e-264f0f190a12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776876351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1776876351
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.15917435
Short name T487
Test name
Test status
Simulation time 16791367624 ps
CPU time 84.05 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:09:17 PM PDT 24
Peak memory 202520 kb
Host smart-db51ef9b-7b3d-4acc-a678-d1c22c3d7fe0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15917435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.15917435
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1816854489
Short name T858
Test name
Test status
Simulation time 8410911 ps
CPU time 1.03 seconds
Started Mar 10 02:07:54 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202424 kb
Host smart-d1f936c4-e608-47cb-82b2-f507f69a6ae2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816854489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1816854489
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.4271415670
Short name T466
Test name
Test status
Simulation time 12144853 ps
CPU time 1.09 seconds
Started Mar 10 02:07:53 PM PDT 24
Finished Mar 10 02:07:54 PM PDT 24
Peak memory 202452 kb
Host smart-8c7d1946-da9a-4ce6-b97c-052580ff9a5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4271415670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4271415670
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.457359984
Short name T426
Test name
Test status
Simulation time 99559351 ps
CPU time 1.26 seconds
Started Mar 10 02:07:50 PM PDT 24
Finished Mar 10 02:07:51 PM PDT 24
Peak memory 202328 kb
Host smart-ee13b787-64db-49be-8e41-e20fc3637a54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457359984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.457359984
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2173674501
Short name T496
Test name
Test status
Simulation time 1989855553 ps
CPU time 9.64 seconds
Started Mar 10 02:07:48 PM PDT 24
Finished Mar 10 02:07:58 PM PDT 24
Peak memory 202456 kb
Host smart-25fe5451-f659-4288-874a-5bbedf473016
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173674501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2173674501
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.985786083
Short name T123
Test name
Test status
Simulation time 3421378348 ps
CPU time 9.53 seconds
Started Mar 10 02:07:45 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202500 kb
Host smart-38db4a72-800d-44f1-a32d-f775b2332fbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=985786083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.985786083
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2614594072
Short name T615
Test name
Test status
Simulation time 9247740 ps
CPU time 1.1 seconds
Started Mar 10 02:07:47 PM PDT 24
Finished Mar 10 02:07:48 PM PDT 24
Peak memory 202388 kb
Host smart-41d62227-543a-4e29-82ef-af9fa08e3117
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614594072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2614594072
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1836405614
Short name T747
Test name
Test status
Simulation time 516193796 ps
CPU time 38.08 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:08:30 PM PDT 24
Peak memory 202488 kb
Host smart-b3dcb781-b405-4163-b681-95f8db1496cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1836405614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1836405614
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1115490512
Short name T431
Test name
Test status
Simulation time 3618869039 ps
CPU time 50.61 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:08:49 PM PDT 24
Peak memory 202316 kb
Host smart-1e4224ca-b73f-464b-890e-6fd4e4df05da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1115490512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1115490512
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1997105906
Short name T352
Test name
Test status
Simulation time 88247329 ps
CPU time 2.93 seconds
Started Mar 10 02:07:52 PM PDT 24
Finished Mar 10 02:07:55 PM PDT 24
Peak memory 202452 kb
Host smart-556d8dfe-be14-4033-bd38-f6f5f9164e72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1997105906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.1997105906
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3467325523
Short name T623
Test name
Test status
Simulation time 791798504 ps
CPU time 103.16 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:09:41 PM PDT 24
Peak memory 206940 kb
Host smart-1a45e245-974e-4268-9f53-88f8ba631c63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3467325523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.3467325523
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3812881071
Short name T604
Test name
Test status
Simulation time 1187542120 ps
CPU time 8.24 seconds
Started Mar 10 02:07:53 PM PDT 24
Finished Mar 10 02:08:01 PM PDT 24
Peak memory 202452 kb
Host smart-0ec649e9-c95a-476e-ade2-0b7be2e2d285
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812881071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3812881071
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2358986651
Short name T183
Test name
Test status
Simulation time 237854811 ps
CPU time 3.88 seconds
Started Mar 10 02:07:59 PM PDT 24
Finished Mar 10 02:08:03 PM PDT 24
Peak memory 202432 kb
Host smart-073ca872-53de-4a20-9f4e-4327cc8359f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2358986651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2358986651
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2699301924
Short name T226
Test name
Test status
Simulation time 33021561687 ps
CPU time 248.73 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:12:07 PM PDT 24
Peak memory 203788 kb
Host smart-b0f87579-8977-42a8-8bca-9fd30c6866b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2699301924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.2699301924
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3970094994
Short name T351
Test name
Test status
Simulation time 172051139 ps
CPU time 5.13 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:08:03 PM PDT 24
Peak memory 202436 kb
Host smart-8e2a0129-fdc1-4bd9-8a02-580a0d28c1a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3970094994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3970094994
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2456330006
Short name T189
Test name
Test status
Simulation time 89735416 ps
CPU time 10.18 seconds
Started Mar 10 02:07:56 PM PDT 24
Finished Mar 10 02:08:06 PM PDT 24
Peak memory 202432 kb
Host smart-cc9df48e-4296-4080-8ce3-e6194f1cc23b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2456330006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2456330006
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1212652806
Short name T66
Test name
Test status
Simulation time 1735183751 ps
CPU time 15.78 seconds
Started Mar 10 02:07:59 PM PDT 24
Finished Mar 10 02:08:16 PM PDT 24
Peak memory 202384 kb
Host smart-144d9670-907d-43fe-b453-53d6e99259f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1212652806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1212652806
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1408778079
Short name T320
Test name
Test status
Simulation time 22383162482 ps
CPU time 82.76 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:09:21 PM PDT 24
Peak memory 202272 kb
Host smart-b48f30c2-3f7d-4225-85f3-17ad1723a9c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408778079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1408778079
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1707376695
Short name T700
Test name
Test status
Simulation time 26189997126 ps
CPU time 42.26 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:40 PM PDT 24
Peak memory 202504 kb
Host smart-7cadebe6-eff9-45f1-918f-8d32e7c4eb64
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1707376695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1707376695
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1791650688
Short name T867
Test name
Test status
Simulation time 46420177 ps
CPU time 6.46 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:03 PM PDT 24
Peak memory 202416 kb
Host smart-46a19dd6-7612-4083-8f6d-f1aaf6765ff3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791650688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1791650688
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.2488020799
Short name T273
Test name
Test status
Simulation time 79948598 ps
CPU time 2.97 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:00 PM PDT 24
Peak memory 202380 kb
Host smart-5660679e-e4c4-4704-be60-c313cd50cfa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2488020799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2488020799
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.2934142879
Short name T52
Test name
Test status
Simulation time 40162262 ps
CPU time 1.41 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:07:58 PM PDT 24
Peak memory 202396 kb
Host smart-9c51791f-bb98-453f-8f18-a7daa2abf419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2934142879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2934142879
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1083330376
Short name T179
Test name
Test status
Simulation time 2055156974 ps
CPU time 8.15 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:05 PM PDT 24
Peak memory 202428 kb
Host smart-485a4e74-02ae-4822-b2df-a3308dcd3e50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083330376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1083330376
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.206976111
Short name T760
Test name
Test status
Simulation time 3077283947 ps
CPU time 5.79 seconds
Started Mar 10 02:07:57 PM PDT 24
Finished Mar 10 02:08:03 PM PDT 24
Peak memory 202560 kb
Host smart-1d4f292e-5228-49a0-8125-25a99c398c33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=206976111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.206976111
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3851851627
Short name T335
Test name
Test status
Simulation time 9534343 ps
CPU time 1.14 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:07:59 PM PDT 24
Peak memory 202360 kb
Host smart-c23004be-6e6b-4a4a-9b02-9380b97e40ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851851627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3851851627
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3407236368
Short name T11
Test name
Test status
Simulation time 772331834 ps
CPU time 21.44 seconds
Started Mar 10 02:08:03 PM PDT 24
Finished Mar 10 02:08:24 PM PDT 24
Peak memory 202436 kb
Host smart-d6a4a036-cc70-48e6-9d65-00008da0673d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3407236368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3407236368
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3661783479
Short name T846
Test name
Test status
Simulation time 967472727 ps
CPU time 93.53 seconds
Started Mar 10 02:07:58 PM PDT 24
Finished Mar 10 02:09:32 PM PDT 24
Peak memory 205904 kb
Host smart-831ab493-e93d-410c-93ff-5e74e2e367a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3661783479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.3661783479
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2336024745
Short name T235
Test name
Test status
Simulation time 712805963 ps
CPU time 88.17 seconds
Started Mar 10 02:08:06 PM PDT 24
Finished Mar 10 02:09:34 PM PDT 24
Peak memory 205568 kb
Host smart-ac8e27ae-4c1a-44c8-b515-554aebd56a19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2336024745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2336024745
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4254045299
Short name T673
Test name
Test status
Simulation time 843926851 ps
CPU time 12.21 seconds
Started Mar 10 02:07:55 PM PDT 24
Finished Mar 10 02:08:08 PM PDT 24
Peak memory 202372 kb
Host smart-5a4274ce-8f34-494f-869f-9707eb4bad0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254045299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4254045299
Directory /workspace/9.xbar_unmapped_addr/latest
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