Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 439 1 T2 1 T3 1 T5 4
all_values[1] 440 1 T5 2 T27 3 T42 1
all_values[2] 475 1 T2 1 T17 1 T5 3
all_values[3] 451 1 T5 6 T16 1 T53 1
all_values[4] 487 1 T5 4 T23 1 T16 1
all_values[5] 449 1 T17 1 T5 1 T16 1
all_values[6] 467 1 T5 5 T23 1 T238 1
all_values[7] 514 1 T2 2 T5 8 T23 1
all_values[8] 471 1 T17 1 T5 4 T29 1
all_values[9] 443 1 T17 1 T5 6 T16 1
all_values[10] 456 1 T5 3 T23 1 T69 1
all_values[11] 436 1 T5 1 T23 2 T16 1
all_values[12] 467 1 T17 2 T5 6 T16 1
all_values[13] 478 1 T17 3 T5 3 T23 1
all_values[14] 432 1 T5 6 T23 1 T46 2
all_values[15] 463 1 T5 2 T53 2 T29 1
all_values[16] 470 1 T2 1 T3 2 T17 3
all_values[17] 486 1 T2 1 T3 1 T17 1
all_values[18] 458 1 T17 1 T5 10 T16 3
all_values[19] 467 1 T3 2 T5 6 T23 1
all_values[20] 483 1 T2 2 T5 4 T27 1
all_values[21] 458 1 T3 1 T5 3 T16 1
all_values[22] 444 1 T5 5 T16 1 T29 1
all_values[23] 421 1 T5 8 T23 2 T16 2
all_values[24] 476 1 T17 1 T5 2 T23 1
all_values[25] 411 1 T2 1 T5 8 T23 1
all_values[26] 430 1 T17 2 T5 3 T29 1

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