Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.32 100.00 95.90 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T760 /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.682727878 Mar 12 12:55:56 PM PDT 24 Mar 12 12:59:17 PM PDT 24 179445447620 ps
T761 /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1860136808 Mar 12 12:56:58 PM PDT 24 Mar 12 12:56:59 PM PDT 24 11143830 ps
T762 /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2213147133 Mar 12 12:54:47 PM PDT 24 Mar 12 12:55:51 PM PDT 24 17482319492 ps
T763 /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1608232749 Mar 12 12:55:45 PM PDT 24 Mar 12 12:55:54 PM PDT 24 95080574 ps
T764 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1215046354 Mar 12 12:57:22 PM PDT 24 Mar 12 01:01:58 PM PDT 24 48874902036 ps
T765 /workspace/coverage/xbar_build_mode/14.xbar_error_random.2801680492 Mar 12 12:55:35 PM PDT 24 Mar 12 12:55:38 PM PDT 24 23201218 ps
T766 /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1468169056 Mar 12 12:57:00 PM PDT 24 Mar 12 12:57:03 PM PDT 24 26311144 ps
T767 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1681134300 Mar 12 12:54:56 PM PDT 24 Mar 12 12:55:13 PM PDT 24 157140488 ps
T768 /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3284447275 Mar 12 12:56:03 PM PDT 24 Mar 12 12:56:44 PM PDT 24 422781499 ps
T769 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.880529583 Mar 12 12:55:24 PM PDT 24 Mar 12 12:56:22 PM PDT 24 41897743742 ps
T770 /workspace/coverage/xbar_build_mode/48.xbar_same_source.3061091623 Mar 12 12:57:27 PM PDT 24 Mar 12 12:57:32 PM PDT 24 52433251 ps
T771 /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3421950628 Mar 12 12:56:54 PM PDT 24 Mar 12 12:57:01 PM PDT 24 3274234039 ps
T772 /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2858425203 Mar 12 12:57:25 PM PDT 24 Mar 12 12:57:33 PM PDT 24 2280372173 ps
T773 /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3254229258 Mar 12 12:57:17 PM PDT 24 Mar 12 12:57:24 PM PDT 24 52839550 ps
T774 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.715226265 Mar 12 12:55:41 PM PDT 24 Mar 12 12:55:45 PM PDT 24 92728295 ps
T775 /workspace/coverage/xbar_build_mode/26.xbar_error_random.2148675620 Mar 12 12:55:55 PM PDT 24 Mar 12 12:56:02 PM PDT 24 1579609293 ps
T776 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3335601724 Mar 12 12:57:16 PM PDT 24 Mar 12 12:57:21 PM PDT 24 197989899 ps
T777 /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1441665410 Mar 12 12:55:00 PM PDT 24 Mar 12 12:55:48 PM PDT 24 2818147740 ps
T778 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.928408798 Mar 12 12:55:35 PM PDT 24 Mar 12 12:56:13 PM PDT 24 157996466 ps
T779 /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1373172469 Mar 12 12:57:15 PM PDT 24 Mar 12 12:57:19 PM PDT 24 810293252 ps
T780 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2335322539 Mar 12 12:56:54 PM PDT 24 Mar 12 12:56:58 PM PDT 24 48402490 ps
T781 /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3983158992 Mar 12 12:54:51 PM PDT 24 Mar 12 12:55:30 PM PDT 24 9537160729 ps
T782 /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1363745697 Mar 12 12:56:54 PM PDT 24 Mar 12 12:57:03 PM PDT 24 2730336817 ps
T783 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3868135402 Mar 12 12:55:40 PM PDT 24 Mar 12 12:57:19 PM PDT 24 9533151888 ps
T784 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.702873556 Mar 12 12:57:16 PM PDT 24 Mar 12 12:58:17 PM PDT 24 7051174787 ps
T785 /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2435896787 Mar 12 12:57:23 PM PDT 24 Mar 12 12:57:24 PM PDT 24 40126612 ps
T13 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4750780 Mar 12 12:56:56 PM PDT 24 Mar 12 01:00:13 PM PDT 24 1499423320 ps
T786 /workspace/coverage/xbar_build_mode/8.xbar_same_source.731238062 Mar 12 12:55:00 PM PDT 24 Mar 12 12:55:06 PM PDT 24 340496229 ps
T787 /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3272346080 Mar 12 12:55:50 PM PDT 24 Mar 12 12:55:53 PM PDT 24 8603709 ps
T272 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.358448322 Mar 12 12:56:54 PM PDT 24 Mar 12 01:01:59 PM PDT 24 67118829472 ps
T788 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.619225756 Mar 12 12:54:56 PM PDT 24 Mar 12 12:54:58 PM PDT 24 27694755 ps
T789 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.572015621 Mar 12 12:54:53 PM PDT 24 Mar 12 12:54:55 PM PDT 24 21297486 ps
T790 /workspace/coverage/xbar_build_mode/17.xbar_same_source.1909012839 Mar 12 12:55:33 PM PDT 24 Mar 12 12:55:35 PM PDT 24 164261133 ps
T791 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3847383264 Mar 12 12:55:44 PM PDT 24 Mar 12 12:56:25 PM PDT 24 5062044887 ps
T792 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3286858008 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:29 PM PDT 24 1132039827 ps
T793 /workspace/coverage/xbar_build_mode/16.xbar_smoke.4248264083 Mar 12 12:55:25 PM PDT 24 Mar 12 12:55:27 PM PDT 24 65001094 ps
T794 /workspace/coverage/xbar_build_mode/8.xbar_smoke.3624891698 Mar 12 12:55:00 PM PDT 24 Mar 12 12:55:01 PM PDT 24 47114341 ps
T795 /workspace/coverage/xbar_build_mode/13.xbar_same_source.2286792744 Mar 12 12:55:13 PM PDT 24 Mar 12 12:55:15 PM PDT 24 16536854 ps
T796 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1297535052 Mar 12 12:54:46 PM PDT 24 Mar 12 12:54:47 PM PDT 24 9803814 ps
T797 /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1311373035 Mar 12 12:57:07 PM PDT 24 Mar 12 12:57:35 PM PDT 24 3701534347 ps
T798 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2137724915 Mar 12 12:56:56 PM PDT 24 Mar 12 12:59:17 PM PDT 24 143823614778 ps
T799 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.53582904 Mar 12 12:55:11 PM PDT 24 Mar 12 12:55:53 PM PDT 24 2644103248 ps
T800 /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2371451336 Mar 12 12:55:38 PM PDT 24 Mar 12 12:55:43 PM PDT 24 1155193640 ps
T131 /workspace/coverage/xbar_build_mode/21.xbar_stress_all.46248334 Mar 12 12:55:42 PM PDT 24 Mar 12 12:57:08 PM PDT 24 7864121466 ps
T801 /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.820984698 Mar 12 12:56:03 PM PDT 24 Mar 12 12:56:08 PM PDT 24 300590088 ps
T802 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1971850967 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:36 PM PDT 24 89868995 ps
T803 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.729133775 Mar 12 12:55:37 PM PDT 24 Mar 12 12:57:21 PM PDT 24 1054656977 ps
T804 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3596399988 Mar 12 12:55:18 PM PDT 24 Mar 12 12:56:30 PM PDT 24 823173656 ps
T805 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.960479339 Mar 12 12:54:50 PM PDT 24 Mar 12 12:55:39 PM PDT 24 2132992638 ps
T806 /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.187381584 Mar 12 12:57:18 PM PDT 24 Mar 12 12:57:23 PM PDT 24 170504541 ps
T807 /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.297198516 Mar 12 12:55:42 PM PDT 24 Mar 12 12:55:46 PM PDT 24 314836169 ps
T808 /workspace/coverage/xbar_build_mode/45.xbar_error_random.2755933562 Mar 12 12:57:25 PM PDT 24 Mar 12 12:57:30 PM PDT 24 166828227 ps
T809 /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.115910201 Mar 12 12:57:20 PM PDT 24 Mar 12 12:58:39 PM PDT 24 12208223502 ps
T810 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2935379116 Mar 12 12:57:15 PM PDT 24 Mar 12 12:58:42 PM PDT 24 737909152 ps
T124 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3089190387 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:31 PM PDT 24 572452784 ps
T811 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1200701763 Mar 12 12:55:58 PM PDT 24 Mar 12 12:56:09 PM PDT 24 3040485259 ps
T812 /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3694103313 Mar 12 12:57:16 PM PDT 24 Mar 12 12:57:25 PM PDT 24 1796622302 ps
T813 /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2515255940 Mar 12 12:55:04 PM PDT 24 Mar 12 12:55:43 PM PDT 24 5650240898 ps
T814 /workspace/coverage/xbar_build_mode/27.xbar_same_source.2787990614 Mar 12 12:56:06 PM PDT 24 Mar 12 12:56:09 PM PDT 24 17876500 ps
T815 /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.467489282 Mar 12 12:56:53 PM PDT 24 Mar 12 12:56:55 PM PDT 24 14009885 ps
T816 /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3857236804 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:28 PM PDT 24 60721175 ps
T817 /workspace/coverage/xbar_build_mode/15.xbar_error_random.3095241832 Mar 12 12:55:24 PM PDT 24 Mar 12 12:55:30 PM PDT 24 247864002 ps
T818 /workspace/coverage/xbar_build_mode/0.xbar_random.3686902661 Mar 12 12:54:44 PM PDT 24 Mar 12 12:54:49 PM PDT 24 2737880723 ps
T819 /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2220138040 Mar 12 12:57:17 PM PDT 24 Mar 12 12:57:26 PM PDT 24 455345757 ps
T125 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2874021979 Mar 12 12:57:20 PM PDT 24 Mar 12 12:57:34 PM PDT 24 1320742662 ps
T820 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3717900648 Mar 12 12:54:52 PM PDT 24 Mar 12 12:55:29 PM PDT 24 616529864 ps
T821 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.150821615 Mar 12 12:56:54 PM PDT 24 Mar 12 12:57:28 PM PDT 24 8229071920 ps
T822 /workspace/coverage/xbar_build_mode/26.xbar_same_source.3841194084 Mar 12 12:55:57 PM PDT 24 Mar 12 12:56:00 PM PDT 24 450622667 ps
T823 /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.599780558 Mar 12 12:57:14 PM PDT 24 Mar 12 12:58:45 PM PDT 24 14255106760 ps
T824 /workspace/coverage/xbar_build_mode/47.xbar_smoke.2784155331 Mar 12 12:57:18 PM PDT 24 Mar 12 12:57:19 PM PDT 24 9372269 ps
T825 /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1077498837 Mar 12 12:55:02 PM PDT 24 Mar 12 12:55:09 PM PDT 24 392352950 ps
T826 /workspace/coverage/xbar_build_mode/11.xbar_random.1776283004 Mar 12 12:55:00 PM PDT 24 Mar 12 12:55:04 PM PDT 24 312104858 ps
T827 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3247415830 Mar 12 12:57:16 PM PDT 24 Mar 12 01:00:52 PM PDT 24 30155105746 ps
T828 /workspace/coverage/xbar_build_mode/30.xbar_stress_all.30750112 Mar 12 12:56:10 PM PDT 24 Mar 12 12:56:15 PM PDT 24 625294737 ps
T829 /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2502698304 Mar 12 12:55:13 PM PDT 24 Mar 12 12:55:18 PM PDT 24 446628015 ps
T830 /workspace/coverage/xbar_build_mode/35.xbar_random.902309485 Mar 12 12:56:55 PM PDT 24 Mar 12 12:56:57 PM PDT 24 70527821 ps
T831 /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.447140567 Mar 12 12:55:16 PM PDT 24 Mar 12 12:55:17 PM PDT 24 12803062 ps
T832 /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.4070025034 Mar 12 12:55:31 PM PDT 24 Mar 12 12:55:33 PM PDT 24 9127325 ps
T833 /workspace/coverage/xbar_build_mode/22.xbar_error_random.1287600262 Mar 12 12:55:42 PM PDT 24 Mar 12 12:55:51 PM PDT 24 2234288121 ps
T126 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3453607071 Mar 12 12:54:55 PM PDT 24 Mar 12 12:55:03 PM PDT 24 521290198 ps
T834 /workspace/coverage/xbar_build_mode/10.xbar_same_source.1926793851 Mar 12 12:55:02 PM PDT 24 Mar 12 12:55:08 PM PDT 24 1163908076 ps
T835 /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.959173718 Mar 12 12:57:19 PM PDT 24 Mar 12 12:57:22 PM PDT 24 22488529 ps
T211 /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3537163794 Mar 12 12:57:13 PM PDT 24 Mar 12 12:57:49 PM PDT 24 5356836701 ps
T836 /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1864619442 Mar 12 12:55:14 PM PDT 24 Mar 12 12:55:18 PM PDT 24 212870364 ps
T837 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3788347793 Mar 12 12:57:15 PM PDT 24 Mar 12 01:00:39 PM PDT 24 1255188325 ps
T838 /workspace/coverage/xbar_build_mode/28.xbar_error_random.1291090335 Mar 12 12:55:59 PM PDT 24 Mar 12 12:56:05 PM PDT 24 62606327 ps
T839 /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1721952101 Mar 12 12:55:33 PM PDT 24 Mar 12 12:57:00 PM PDT 24 79712131169 ps
T840 /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2518983999 Mar 12 12:57:22 PM PDT 24 Mar 12 12:58:51 PM PDT 24 40140963418 ps
T841 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.963070138 Mar 12 12:55:29 PM PDT 24 Mar 12 12:56:25 PM PDT 24 4065555237 ps
T842 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.4258620185 Mar 12 12:57:27 PM PDT 24 Mar 12 12:58:02 PM PDT 24 8080585079 ps
T843 /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3010280976 Mar 12 12:57:15 PM PDT 24 Mar 12 12:59:06 PM PDT 24 9494906792 ps
T844 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.686089711 Mar 12 12:55:49 PM PDT 24 Mar 12 01:01:01 PM PDT 24 161845442985 ps
T845 /workspace/coverage/xbar_build_mode/13.xbar_error_random.2041781016 Mar 12 12:55:15 PM PDT 24 Mar 12 12:55:22 PM PDT 24 501971688 ps
T846 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1471743554 Mar 12 12:55:45 PM PDT 24 Mar 12 12:56:24 PM PDT 24 4206454839 ps
T847 /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.934608264 Mar 12 12:55:16 PM PDT 24 Mar 12 12:55:25 PM PDT 24 1727515429 ps
T848 /workspace/coverage/xbar_build_mode/38.xbar_smoke.2785657098 Mar 12 12:57:14 PM PDT 24 Mar 12 12:57:16 PM PDT 24 75007133 ps
T849 /workspace/coverage/xbar_build_mode/23.xbar_same_source.1205175873 Mar 12 12:55:47 PM PDT 24 Mar 12 12:55:58 PM PDT 24 1374688785 ps
T850 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.84561979 Mar 12 12:57:20 PM PDT 24 Mar 12 01:02:10 PM PDT 24 76761792295 ps
T851 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.452105329 Mar 12 12:57:16 PM PDT 24 Mar 12 12:57:29 PM PDT 24 113694073 ps
T852 /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1195897194 Mar 12 12:56:52 PM PDT 24 Mar 12 12:57:43 PM PDT 24 9322551032 ps
T853 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.742453724 Mar 12 12:57:22 PM PDT 24 Mar 12 12:57:28 PM PDT 24 67927622 ps
T854 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1791554305 Mar 12 12:56:56 PM PDT 24 Mar 12 12:57:01 PM PDT 24 52141320 ps
T855 /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.428625065 Mar 12 12:54:51 PM PDT 24 Mar 12 12:55:02 PM PDT 24 2466255666 ps
T856 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3760632038 Mar 12 12:55:46 PM PDT 24 Mar 12 12:59:30 PM PDT 24 49109533068 ps
T857 /workspace/coverage/xbar_build_mode/16.xbar_random.1831057369 Mar 12 12:55:25 PM PDT 24 Mar 12 12:55:30 PM PDT 24 94220516 ps
T858 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.762602691 Mar 12 12:56:02 PM PDT 24 Mar 12 12:57:01 PM PDT 24 441681300 ps
T859 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2552680282 Mar 12 12:57:19 PM PDT 24 Mar 12 12:58:23 PM PDT 24 12047574580 ps
T860 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2841283012 Mar 12 12:57:25 PM PDT 24 Mar 12 12:57:26 PM PDT 24 9166194 ps
T861 /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1401874728 Mar 12 12:57:19 PM PDT 24 Mar 12 12:57:21 PM PDT 24 9834661 ps
T862 /workspace/coverage/xbar_build_mode/1.xbar_same_source.575279091 Mar 12 12:54:46 PM PDT 24 Mar 12 12:54:51 PM PDT 24 1233011453 ps
T863 /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4205103711 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:22 PM PDT 24 9463349 ps
T864 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2474253123 Mar 12 12:57:18 PM PDT 24 Mar 12 12:57:45 PM PDT 24 10233727262 ps
T865 /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1002776057 Mar 12 12:55:49 PM PDT 24 Mar 12 12:55:57 PM PDT 24 2238553295 ps
T866 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3667960052 Mar 12 12:55:23 PM PDT 24 Mar 12 12:56:27 PM PDT 24 600634169 ps
T867 /workspace/coverage/xbar_build_mode/43.xbar_error_random.2725090959 Mar 12 12:57:17 PM PDT 24 Mar 12 12:57:24 PM PDT 24 3610357424 ps
T868 /workspace/coverage/xbar_build_mode/29.xbar_error_random.552538256 Mar 12 12:56:06 PM PDT 24 Mar 12 12:56:11 PM PDT 24 475143880 ps
T869 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.290567187 Mar 12 12:57:17 PM PDT 24 Mar 12 12:57:24 PM PDT 24 72393272 ps
T870 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.119573765 Mar 12 12:54:58 PM PDT 24 Mar 12 12:56:10 PM PDT 24 8656773181 ps
T871 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1465184840 Mar 12 12:56:58 PM PDT 24 Mar 12 12:57:23 PM PDT 24 323245655 ps
T872 /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3197050413 Mar 12 12:54:55 PM PDT 24 Mar 12 12:55:00 PM PDT 24 581446857 ps
T873 /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3471241746 Mar 12 12:54:56 PM PDT 24 Mar 12 12:54:59 PM PDT 24 26338759 ps
T874 /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.484225298 Mar 12 12:55:14 PM PDT 24 Mar 12 12:55:16 PM PDT 24 11826982 ps
T875 /workspace/coverage/xbar_build_mode/41.xbar_same_source.1472165260 Mar 12 12:57:21 PM PDT 24 Mar 12 12:57:24 PM PDT 24 236201264 ps
T876 /workspace/coverage/xbar_build_mode/19.xbar_smoke.2049168634 Mar 12 12:55:36 PM PDT 24 Mar 12 12:55:37 PM PDT 24 42387864 ps
T877 /workspace/coverage/xbar_build_mode/15.xbar_random.3369540976 Mar 12 12:55:24 PM PDT 24 Mar 12 12:55:27 PM PDT 24 244998640 ps
T878 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2764884216 Mar 12 12:55:27 PM PDT 24 Mar 12 12:56:12 PM PDT 24 604857370 ps
T879 /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3636372554 Mar 12 12:55:45 PM PDT 24 Mar 12 12:55:48 PM PDT 24 83593975 ps
T880 /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.4222985989 Mar 12 12:56:12 PM PDT 24 Mar 12 12:58:28 PM PDT 24 197462744835 ps
T881 /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.600955928 Mar 12 12:56:06 PM PDT 24 Mar 12 12:56:08 PM PDT 24 81424250 ps
T882 /workspace/coverage/xbar_build_mode/21.xbar_same_source.1436300530 Mar 12 12:55:44 PM PDT 24 Mar 12 12:55:50 PM PDT 24 814678065 ps
T127 /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4033764811 Mar 12 12:55:37 PM PDT 24 Mar 12 12:56:28 PM PDT 24 12358271405 ps
T883 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3148447322 Mar 12 12:55:54 PM PDT 24 Mar 12 12:56:02 PM PDT 24 2878997026 ps
T884 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1668539337 Mar 12 12:56:10 PM PDT 24 Mar 12 12:57:12 PM PDT 24 920798883 ps
T885 /workspace/coverage/xbar_build_mode/49.xbar_smoke.4201691757 Mar 12 12:57:22 PM PDT 24 Mar 12 12:57:24 PM PDT 24 60603490 ps
T886 /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2658303702 Mar 12 12:55:17 PM PDT 24 Mar 12 12:57:43 PM PDT 24 97069247805 ps
T887 /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.268562098 Mar 12 12:54:52 PM PDT 24 Mar 12 12:55:03 PM PDT 24 3384480318 ps
T243 /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.961452486 Mar 12 12:57:14 PM PDT 24 Mar 12 12:57:21 PM PDT 24 1348715539 ps
T888 /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.99134614 Mar 12 12:55:34 PM PDT 24 Mar 12 12:55:41 PM PDT 24 107375647 ps
T889 /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.479405132 Mar 12 12:55:28 PM PDT 24 Mar 12 12:55:40 PM PDT 24 10259270634 ps
T890 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1969567611 Mar 12 12:57:11 PM PDT 24 Mar 12 12:58:48 PM PDT 24 36226789594 ps
T891 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2022763934 Mar 12 12:55:43 PM PDT 24 Mar 12 12:56:10 PM PDT 24 232457749 ps
T892 /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1501618613 Mar 12 12:55:45 PM PDT 24 Mar 12 12:55:51 PM PDT 24 376702215 ps
T893 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3885077167 Mar 12 12:54:48 PM PDT 24 Mar 12 12:55:40 PM PDT 24 364484957 ps
T894 /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.639952951 Mar 12 12:56:04 PM PDT 24 Mar 12 12:56:16 PM PDT 24 4232304144 ps
T895 /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.251736248 Mar 12 12:54:56 PM PDT 24 Mar 12 12:54:59 PM PDT 24 82315469 ps
T896 /workspace/coverage/xbar_build_mode/46.xbar_random.2876982836 Mar 12 12:57:22 PM PDT 24 Mar 12 12:57:24 PM PDT 24 17905163 ps
T897 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2954864044 Mar 12 12:54:51 PM PDT 24 Mar 12 12:55:14 PM PDT 24 158149684 ps
T898 /workspace/coverage/xbar_build_mode/17.xbar_error_random.912437559 Mar 12 12:55:37 PM PDT 24 Mar 12 12:55:44 PM PDT 24 354982257 ps
T899 /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.4079370920 Mar 12 12:55:26 PM PDT 24 Mar 12 12:55:38 PM PDT 24 16659566274 ps
T900 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3281593693 Mar 12 12:55:38 PM PDT 24 Mar 12 12:55:48 PM PDT 24 787854982 ps

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1663143178
Short name T5
Test name
Test status
Simulation time 4289300868 ps
CPU time 101.18 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:56:42 PM PDT 24
Peak memory 204032 kb
Host smart-76cf9d22-128e-47b9-917a-ed8d5fa4d47c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663143178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1663143178
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2533340492
Short name T90
Test name
Test status
Simulation time 111747925044 ps
CPU time 306.05 seconds
Started Mar 12 12:55:21 PM PDT 24
Finished Mar 12 01:00:27 PM PDT 24
Peak memory 203724 kb
Host smart-e95091e4-9de4-4b11-89a2-5dc5688fd086
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2533340492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.2533340492
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1603866945
Short name T252
Test name
Test status
Simulation time 56073269040 ps
CPU time 333.76 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 01:00:28 PM PDT 24
Peak memory 203044 kb
Host smart-b1a47225-e988-4b1f-ad61-4579667ab2f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1603866945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1603866945
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2981662661
Short name T17
Test name
Test status
Simulation time 186544144583 ps
CPU time 278.69 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:59:27 PM PDT 24
Peak memory 203356 kb
Host smart-3cda43aa-31b0-4ea3-addb-66fe29f12f40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2981662661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.2981662661
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2816631463
Short name T262
Test name
Test status
Simulation time 41585489872 ps
CPU time 313.09 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 01:00:50 PM PDT 24
Peak memory 203336 kb
Host smart-42bdea69-62bc-4152-9a13-3818f5e70086
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2816631463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.2816631463
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.626893470
Short name T16
Test name
Test status
Simulation time 5244335638 ps
CPU time 40.22 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:56:20 PM PDT 24
Peak memory 202076 kb
Host smart-a11716bc-a16f-40c4-8978-e573ea1ab1f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=626893470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.626893470
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3292016509
Short name T78
Test name
Test status
Simulation time 20530882885 ps
CPU time 152.29 seconds
Started Mar 12 12:56:06 PM PDT 24
Finished Mar 12 12:58:39 PM PDT 24
Peak memory 202076 kb
Host smart-78e0b217-b120-4f0f-8e52-8828264ae1b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3292016509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.3292016509
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.886435218
Short name T269
Test name
Test status
Simulation time 97739285530 ps
CPU time 333.7 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 01:02:50 PM PDT 24
Peak memory 203544 kb
Host smart-7b3f0beb-711f-4da5-a9dd-ac573fb2ea4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=886435218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo
w_rsp.886435218
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3227361132
Short name T46
Test name
Test status
Simulation time 1829355048 ps
CPU time 18.2 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:36 PM PDT 24
Peak memory 201956 kb
Host smart-f3888ac2-b8d2-4ab3-bbdd-d699c5829938
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227361132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3227361132
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3956324078
Short name T20
Test name
Test status
Simulation time 56328222 ps
CPU time 3.54 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:56 PM PDT 24
Peak memory 200732 kb
Host smart-7742e86e-6b49-40db-bb17-af7c1ec07935
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3956324078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3956324078
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.559941728
Short name T25
Test name
Test status
Simulation time 54818385633 ps
CPU time 149.05 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 202028 kb
Host smart-7284ffe3-204f-4078-842b-cb5922cddec5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=559941728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.559941728
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3180499428
Short name T207
Test name
Test status
Simulation time 9160627466 ps
CPU time 96.87 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:58:32 PM PDT 24
Peak memory 204652 kb
Host smart-7742cfdf-2bad-44aa-90f0-4d052d34d769
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3180499428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.3180499428
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2855143091
Short name T60
Test name
Test status
Simulation time 69634839801 ps
CPU time 163.17 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:58:35 PM PDT 24
Peak memory 203108 kb
Host smart-160b586c-1341-478b-b2bf-953914ec4c99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2855143091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.2855143091
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.4239676300
Short name T77
Test name
Test status
Simulation time 133079549154 ps
CPU time 156.64 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:59:59 PM PDT 24
Peak memory 201700 kb
Host smart-5f7d26d0-dac8-461f-ba8f-66ac05ce633f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239676300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4239676300
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.446108120
Short name T9
Test name
Test status
Simulation time 266447523 ps
CPU time 39.2 seconds
Started Mar 12 12:55:46 PM PDT 24
Finished Mar 12 12:56:26 PM PDT 24
Peak memory 203260 kb
Host smart-cd5fa55c-55db-45e2-b2f0-4784e08f1893
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=446108120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res
et_error.446108120
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3247415830
Short name T827
Test name
Test status
Simulation time 30155105746 ps
CPU time 215.71 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 01:00:52 PM PDT 24
Peak memory 203032 kb
Host smart-57852499-27ff-4447-94ac-d8be3de2aad6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3247415830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.3247415830
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3514276547
Short name T7
Test name
Test status
Simulation time 3139246027 ps
CPU time 208.69 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 206388 kb
Host smart-118ee07d-2a4a-4ea8-a6d9-84afd326713f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3514276547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.3514276547
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1600434387
Short name T12
Test name
Test status
Simulation time 308166721 ps
CPU time 39.29 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 203300 kb
Host smart-277a1a4d-6141-4870-be3c-c3e843b83f69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1600434387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1600434387
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1368221787
Short name T6
Test name
Test status
Simulation time 477590739 ps
CPU time 63.46 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:57:13 PM PDT 24
Peak memory 203984 kb
Host smart-373a1740-4e16-4569-ad02-13bbc94bd773
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1368221787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.1368221787
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.3523201982
Short name T11
Test name
Test status
Simulation time 2187045563 ps
CPU time 14.25 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 202064 kb
Host smart-cbd945cd-cc1a-4640-966b-6038a0538ca0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3523201982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3523201982
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.248440297
Short name T253
Test name
Test status
Simulation time 82175925962 ps
CPU time 166.62 seconds
Started Mar 12 12:55:55 PM PDT 24
Finished Mar 12 12:58:42 PM PDT 24
Peak memory 201980 kb
Host smart-7bf9efc0-990d-4f26-bc1e-090dcc6c5ac8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=248440297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo
w_rsp.248440297
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.2494002587
Short name T30
Test name
Test status
Simulation time 2507796888 ps
CPU time 8.58 seconds
Started Mar 12 12:55:25 PM PDT 24
Finished Mar 12 12:55:34 PM PDT 24
Peak memory 201804 kb
Host smart-36861117-fae2-437e-91d8-5e500c5600f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2494002587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2494002587
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.246654185
Short name T116
Test name
Test status
Simulation time 14309128505 ps
CPU time 50.67 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 203144 kb
Host smart-e6cc83fd-0839-44fb-b5f2-e13f36c63a6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=246654185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.246654185
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.358448322
Short name T272
Test name
Test status
Simulation time 67118829472 ps
CPU time 305.4 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 01:01:59 PM PDT 24
Peak memory 204088 kb
Host smart-990b49dd-cb98-4d7b-881e-b4a4a79ac74c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=358448322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo
w_rsp.358448322
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1928469251
Short name T87
Test name
Test status
Simulation time 1696651878 ps
CPU time 85.71 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 204344 kb
Host smart-9da206f5-67ef-4ad3-8c0d-d62f4a258d68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1928469251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.1928469251
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3254430149
Short name T120
Test name
Test status
Simulation time 70870280575 ps
CPU time 170.01 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 201776 kb
Host smart-b16c7cc6-360b-4302-8481-58d686195e3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3254430149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3254430149
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3193264580
Short name T204
Test name
Test status
Simulation time 826232134 ps
CPU time 91.83 seconds
Started Mar 12 12:56:01 PM PDT 24
Finished Mar 12 12:57:33 PM PDT 24
Peak memory 204556 kb
Host smart-abed8ae1-e1ea-4938-a324-05588bf869ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193264580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3193264580
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1023763525
Short name T135
Test name
Test status
Simulation time 26231104535 ps
CPU time 94.94 seconds
Started Mar 12 12:55:15 PM PDT 24
Finished Mar 12 12:56:51 PM PDT 24
Peak memory 202072 kb
Host smart-f38a0bae-1abb-4932-a3a1-b47bfe7b61a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1023763525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.1023763525
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3944158529
Short name T608
Test name
Test status
Simulation time 3751263529 ps
CPU time 116.34 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 204472 kb
Host smart-6562bf81-3e1e-40dc-8e59-6efe1408754c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3944158529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3944158529
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1161043871
Short name T189
Test name
Test status
Simulation time 2392671859 ps
CPU time 21.44 seconds
Started Mar 12 12:55:31 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 202000 kb
Host smart-46bcee73-1d90-4d9c-96ba-e534b48e17ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1161043871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1161043871
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2705535373
Short name T674
Test name
Test status
Simulation time 16166314 ps
CPU time 2.24 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 201892 kb
Host smart-ddd156fe-fc87-4739-8355-cb6b6f385cdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2705535373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2705535373
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2213147133
Short name T762
Test name
Test status
Simulation time 17482319492 ps
CPU time 63.64 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 202020 kb
Host smart-d36176f8-7127-435c-b334-ad702902d847
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2213147133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2213147133
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2963701884
Short name T347
Test name
Test status
Simulation time 908662254 ps
CPU time 10.14 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201940 kb
Host smart-12ab818f-6991-4ba7-bfdd-7cc83474f68a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2963701884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2963701884
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.248397390
Short name T655
Test name
Test status
Simulation time 729206340 ps
CPU time 11.39 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:55:01 PM PDT 24
Peak memory 201872 kb
Host smart-cbf471cd-187f-45bc-bf2a-f3d9ae2c2d73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=248397390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.248397390
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3686902661
Short name T818
Test name
Test status
Simulation time 2737880723 ps
CPU time 5.08 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 201976 kb
Host smart-333a5b98-bea7-4973-ad17-fcbdb196995c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3686902661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3686902661
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4158731943
Short name T395
Test name
Test status
Simulation time 109498195353 ps
CPU time 127.59 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:56:58 PM PDT 24
Peak memory 202024 kb
Host smart-4ee65c5c-e2e4-4dbb-91f5-860ad486e5a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158731943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4158731943
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2368248711
Short name T197
Test name
Test status
Simulation time 141965116989 ps
CPU time 148.07 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 202052 kb
Host smart-45d67da7-49a2-4f0b-9101-89389001f02e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2368248711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2368248711
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1972023749
Short name T472
Test name
Test status
Simulation time 23444074 ps
CPU time 2.57 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 201832 kb
Host smart-74eb84e1-12da-400b-958a-fcb30bed5b6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972023749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1972023749
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.2283838295
Short name T224
Test name
Test status
Simulation time 35106551 ps
CPU time 3.31 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 201948 kb
Host smart-4d3fd303-cdea-43ea-ba56-71bd19104ef5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2283838295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2283838295
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.4181670657
Short name T602
Test name
Test status
Simulation time 190020381 ps
CPU time 1.32 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 201792 kb
Host smart-a619b013-1157-4c84-af41-55967aa24390
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4181670657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4181670657
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.268562098
Short name T887
Test name
Test status
Simulation time 3384480318 ps
CPU time 10.9 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 202028 kb
Host smart-15a9ee51-9731-4192-b251-1316ff1225cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=268562098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.268562098
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3214072369
Short name T400
Test name
Test status
Simulation time 3192567800 ps
CPU time 7.04 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 202060 kb
Host smart-899ad860-0e4c-42bb-993b-1cf409e68b5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3214072369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3214072369
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2113158284
Short name T579
Test name
Test status
Simulation time 7796174 ps
CPU time 1.09 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 201928 kb
Host smart-fb46a401-f646-4625-9a70-5c60f0869617
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113158284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2113158284
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3640788325
Short name T591
Test name
Test status
Simulation time 491400900 ps
CPU time 42.98 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 202936 kb
Host smart-23e17f63-3102-41dd-babc-8d7a25c3823e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3640788325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3640788325
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3717900648
Short name T820
Test name
Test status
Simulation time 616529864 ps
CPU time 36.96 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:29 PM PDT 24
Peak memory 201860 kb
Host smart-12170097-bd1c-4b6b-95f3-6392bf934056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3717900648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3717900648
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2762010574
Short name T155
Test name
Test status
Simulation time 408170305 ps
CPU time 74.33 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 204620 kb
Host smart-0c2f2b2c-67b9-471a-b47a-ea3ce1e08be0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2762010574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.2762010574
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2116192046
Short name T251
Test name
Test status
Simulation time 143327351 ps
CPU time 16.76 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 201900 kb
Host smart-ffd2e29c-6ad4-4e89-939b-e2b233ac3b0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116192046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.2116192046
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3641005950
Short name T57
Test name
Test status
Simulation time 491334832 ps
CPU time 5.55 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201908 kb
Host smart-7a90eac5-2332-4f27-ab64-970b45e65247
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641005950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3641005950
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1838086381
Short name T749
Test name
Test status
Simulation time 7240953086 ps
CPU time 24.25 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:55:11 PM PDT 24
Peak memory 202000 kb
Host smart-df6ce872-7094-4e87-b56e-8379194d9dfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1838086381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1838086381
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.329302008
Short name T261
Test name
Test status
Simulation time 60545723949 ps
CPU time 271.19 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 203436 kb
Host smart-c751b233-262d-4f97-a46d-71aab27f638c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=329302008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow
_rsp.329302008
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2020515905
Short name T236
Test name
Test status
Simulation time 11119587 ps
CPU time 1.41 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201892 kb
Host smart-90538e27-5320-408a-95b4-76149eb0115c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2020515905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2020515905
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.4082375171
Short name T487
Test name
Test status
Simulation time 3990923722 ps
CPU time 13.93 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:08 PM PDT 24
Peak memory 201988 kb
Host smart-c3e5b7dd-043c-46db-b9d2-b224731c212c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4082375171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4082375171
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.242979008
Short name T745
Test name
Test status
Simulation time 1322426766 ps
CPU time 10.26 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201876 kb
Host smart-35235ae1-5727-44dd-886a-ea8dc5df2ac2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=242979008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.242979008
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1449395244
Short name T408
Test name
Test status
Simulation time 37420642599 ps
CPU time 109.93 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:56:38 PM PDT 24
Peak memory 202072 kb
Host smart-35f8e853-b8ef-4e5f-bc22-d92031649e1d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449395244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1449395244
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.124933542
Short name T299
Test name
Test status
Simulation time 18441000995 ps
CPU time 56.29 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201956 kb
Host smart-511b9278-7815-454d-9c20-69a84a9b3b3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=124933542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.124933542
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3098059339
Short name T686
Test name
Test status
Simulation time 33980552 ps
CPU time 1.79 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 201952 kb
Host smart-1836b57d-b220-4c98-ac1b-402c7cd21b06
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098059339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3098059339
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.575279091
Short name T862
Test name
Test status
Simulation time 1233011453 ps
CPU time 4.41 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:51 PM PDT 24
Peak memory 201868 kb
Host smart-cc30ec1d-5115-4b7e-b4e6-3f19b5ada734
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=575279091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.575279091
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1979989871
Short name T58
Test name
Test status
Simulation time 288497028 ps
CPU time 1.42 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 201848 kb
Host smart-51513362-0c54-43f3-8b8e-5218f2eb44a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979989871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1979989871
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.483606646
Short name T720
Test name
Test status
Simulation time 2419202914 ps
CPU time 7.79 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:54:59 PM PDT 24
Peak memory 202008 kb
Host smart-992d97f2-0674-4401-991d-54d469f1b4dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=483606646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.483606646
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2752384298
Short name T638
Test name
Test status
Simulation time 1362099981 ps
CPU time 5.58 seconds
Started Mar 12 12:54:40 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 201924 kb
Host smart-2ba62a3b-93f5-43b9-aae4-9670f38f6c4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2752384298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2752384298
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2944433465
Short name T695
Test name
Test status
Simulation time 12629183 ps
CPU time 1.34 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201948 kb
Host smart-3d97954d-c7ac-425c-9af0-265993c27908
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944433465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2944433465
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2954864044
Short name T897
Test name
Test status
Simulation time 158149684 ps
CPU time 22.88 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:14 PM PDT 24
Peak memory 202484 kb
Host smart-443ece9e-4be5-4130-a75d-dc265196b9ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2954864044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2954864044
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1828514952
Short name T504
Test name
Test status
Simulation time 6640086846 ps
CPU time 80.03 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 202020 kb
Host smart-591876eb-b611-4ee8-b14b-79ada6253770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828514952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1828514952
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1093771120
Short name T213
Test name
Test status
Simulation time 10712739256 ps
CPU time 87.94 seconds
Started Mar 12 12:55:08 PM PDT 24
Finished Mar 12 12:56:37 PM PDT 24
Peak memory 205160 kb
Host smart-bbf53e8d-f397-4d20-951a-c2fdc73bf556
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1093771120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.1093771120
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.960479339
Short name T805
Test name
Test status
Simulation time 2132992638 ps
CPU time 47.96 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:55:39 PM PDT 24
Peak memory 203692 kb
Host smart-976f0d49-dc1c-4833-8815-e5c2d2fcedac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=960479339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.960479339
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1401507512
Short name T241
Test name
Test status
Simulation time 803199627 ps
CPU time 12.01 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201904 kb
Host smart-737d5291-4434-4d5a-bde2-2f9aaf725496
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1401507512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1401507512
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1446488598
Short name T3
Test name
Test status
Simulation time 879828147 ps
CPU time 8.35 seconds
Started Mar 12 12:55:07 PM PDT 24
Finished Mar 12 12:55:15 PM PDT 24
Peak memory 201944 kb
Host smart-0f54e49b-58bc-422c-916d-a3cd63f71c00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1446488598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1446488598
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2487094183
Short name T138
Test name
Test status
Simulation time 21993867919 ps
CPU time 124.57 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:57:16 PM PDT 24
Peak memory 203828 kb
Host smart-a1a7fab5-8ecc-4bdf-8fce-99cd0b726988
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2487094183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.2487094183
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1394758219
Short name T333
Test name
Test status
Simulation time 239163394 ps
CPU time 5.61 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:20 PM PDT 24
Peak memory 201892 kb
Host smart-47746693-e624-4c22-a640-1ebb43494202
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394758219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1394758219
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3431112634
Short name T362
Test name
Test status
Simulation time 793158499 ps
CPU time 8.59 seconds
Started Mar 12 12:55:12 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 201940 kb
Host smart-5ad8e305-5977-4356-b892-4cd1fb66e7ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3431112634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3431112634
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.1234022206
Short name T142
Test name
Test status
Simulation time 1317500507 ps
CPU time 9.66 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 201828 kb
Host smart-ef36e7b8-0d42-4e22-81a7-7457a389d9d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1234022206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1234022206
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1346919853
Short name T65
Test name
Test status
Simulation time 56482464420 ps
CPU time 121.17 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:57:11 PM PDT 24
Peak memory 202276 kb
Host smart-bc4fc45c-8c93-4ede-a7be-ab4df3d3a4fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346919853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1346919853
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3449986789
Short name T574
Test name
Test status
Simulation time 18047014467 ps
CPU time 117.28 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:57:09 PM PDT 24
Peak memory 202016 kb
Host smart-e9068121-44f1-4beb-b8dd-9b56555c0e58
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3449986789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3449986789
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1649835109
Short name T342
Test name
Test status
Simulation time 523507804 ps
CPU time 8.56 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:06 PM PDT 24
Peak memory 201928 kb
Host smart-1bb5a078-0068-4fb8-a1d4-28b9090f3ed5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649835109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1649835109
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.1926793851
Short name T834
Test name
Test status
Simulation time 1163908076 ps
CPU time 6.74 seconds
Started Mar 12 12:55:02 PM PDT 24
Finished Mar 12 12:55:08 PM PDT 24
Peak memory 201892 kb
Host smart-4ae4924e-cd11-4e57-89ed-de66bff1cf1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1926793851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1926793851
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3189572454
Short name T592
Test name
Test status
Simulation time 51518674 ps
CPU time 1.58 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201872 kb
Host smart-84c46648-bf07-4f99-bdf3-bd5e168a51ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3189572454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3189572454
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2660045529
Short name T616
Test name
Test status
Simulation time 3246826538 ps
CPU time 11.62 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 201968 kb
Host smart-aca392dd-29c4-41d9-abed-08b4bda17345
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660045529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2660045529
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.304358621
Short name T658
Test name
Test status
Simulation time 3623737655 ps
CPU time 12.04 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 202040 kb
Host smart-2a92d1d4-4bf0-4929-9795-2c04409a9cc3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=304358621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.304358621
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2766435708
Short name T302
Test name
Test status
Simulation time 12224408 ps
CPU time 1.19 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201904 kb
Host smart-6c7b3bd7-90df-4712-b72e-34e981d4d12c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766435708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2766435708
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.694495598
Short name T680
Test name
Test status
Simulation time 1533699635 ps
CPU time 18.05 seconds
Started Mar 12 12:55:03 PM PDT 24
Finished Mar 12 12:55:22 PM PDT 24
Peak memory 201904 kb
Host smart-c4728b24-a624-46d2-b43e-cf3984605cb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=694495598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.694495598
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1377987889
Short name T442
Test name
Test status
Simulation time 22330929905 ps
CPU time 87.78 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:56:29 PM PDT 24
Peak memory 202280 kb
Host smart-fd519a18-9d68-41d7-83fd-99c34b48d816
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1377987889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1377987889
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1606702936
Short name T743
Test name
Test status
Simulation time 1127123566 ps
CPU time 117.2 seconds
Started Mar 12 12:55:06 PM PDT 24
Finished Mar 12 12:57:04 PM PDT 24
Peak memory 204320 kb
Host smart-c6834ef6-ec5f-47d9-b9f7-b395bda4fe36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1606702936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.1606702936
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3886705938
Short name T593
Test name
Test status
Simulation time 2802245341 ps
CPU time 93.19 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:56:43 PM PDT 24
Peak memory 204584 kb
Host smart-02f4ded6-6fdc-4eb4-8fda-39cc2d4c20f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3886705938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.3886705938
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3188806170
Short name T557
Test name
Test status
Simulation time 531693927 ps
CPU time 9.45 seconds
Started Mar 12 12:55:13 PM PDT 24
Finished Mar 12 12:55:22 PM PDT 24
Peak memory 201936 kb
Host smart-6b54f880-1d64-4162-b351-20025ea832db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3188806170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3188806170
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2878060765
Short name T730
Test name
Test status
Simulation time 1297650879 ps
CPU time 20.12 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:34 PM PDT 24
Peak memory 202140 kb
Host smart-f59abd13-9478-487b-82d3-6cb0ec4138a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2878060765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2878060765
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1077498837
Short name T825
Test name
Test status
Simulation time 392352950 ps
CPU time 6.31 seconds
Started Mar 12 12:55:02 PM PDT 24
Finished Mar 12 12:55:09 PM PDT 24
Peak memory 201944 kb
Host smart-35864c0c-bccf-4889-8d16-22da890fb721
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077498837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1077498837
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2982998234
Short name T373
Test name
Test status
Simulation time 671083327 ps
CPU time 6.31 seconds
Started Mar 12 12:55:03 PM PDT 24
Finished Mar 12 12:55:09 PM PDT 24
Peak memory 201948 kb
Host smart-6171323e-927b-4d4e-830c-c966ed81c101
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2982998234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2982998234
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1776283004
Short name T826
Test name
Test status
Simulation time 312104858 ps
CPU time 3.06 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:04 PM PDT 24
Peak memory 201840 kb
Host smart-b1578683-3b5a-4a35-8fc2-1e9786cd6e3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1776283004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1776283004
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3515919296
Short name T37
Test name
Test status
Simulation time 180488435923 ps
CPU time 119.64 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 202040 kb
Host smart-101712c3-5c24-424d-b5b9-46c70547a88f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515919296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3515919296
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1359743256
Short name T531
Test name
Test status
Simulation time 5917705027 ps
CPU time 39.49 seconds
Started Mar 12 12:55:07 PM PDT 24
Finished Mar 12 12:55:47 PM PDT 24
Peak memory 202076 kb
Host smart-aa664e28-3bed-482a-aee3-4b5e5579f346
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1359743256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1359743256
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2799989869
Short name T338
Test name
Test status
Simulation time 226111596 ps
CPU time 7.38 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 201860 kb
Host smart-6f51b5f9-65d9-4717-9ef6-e0d9dc3e059a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799989869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2799989869
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3756097557
Short name T227
Test name
Test status
Simulation time 19082901 ps
CPU time 1.9 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201880 kb
Host smart-bebeed46-42e5-4fac-853d-8a776ec4f767
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3756097557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3756097557
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.51078817
Short name T300
Test name
Test status
Simulation time 14502268 ps
CPU time 1.38 seconds
Started Mar 12 12:55:08 PM PDT 24
Finished Mar 12 12:55:10 PM PDT 24
Peak memory 201880 kb
Host smart-1978f042-ded5-4c2c-b57a-e26b81260993
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51078817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.51078817
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.934608264
Short name T847
Test name
Test status
Simulation time 1727515429 ps
CPU time 8.08 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:25 PM PDT 24
Peak memory 201948 kb
Host smart-19841751-f024-4776-bf12-9b198b389873
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=934608264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.934608264
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.615409092
Short name T752
Test name
Test status
Simulation time 2428777181 ps
CPU time 11.91 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:09 PM PDT 24
Peak memory 202024 kb
Host smart-48d0c6b6-7cbf-4f4c-a905-2576f9a36039
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=615409092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.615409092
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4098274837
Short name T26
Test name
Test status
Simulation time 11192179 ps
CPU time 1.45 seconds
Started Mar 12 12:55:13 PM PDT 24
Finished Mar 12 12:55:14 PM PDT 24
Peak memory 201940 kb
Host smart-dd848874-375d-4058-9ead-f627da124307
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098274837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4098274837
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1441665410
Short name T777
Test name
Test status
Simulation time 2818147740 ps
CPU time 47.02 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 203076 kb
Host smart-5c1d0484-0e04-4957-b7eb-267667b57905
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1441665410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1441665410
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1832149414
Short name T488
Test name
Test status
Simulation time 908744489 ps
CPU time 30.78 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201936 kb
Host smart-a865d496-d4db-4de9-b236-61bc6c4d3498
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1832149414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1832149414
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2664577767
Short name T238
Test name
Test status
Simulation time 88856533 ps
CPU time 4.72 seconds
Started Mar 12 12:55:12 PM PDT 24
Finished Mar 12 12:55:17 PM PDT 24
Peak memory 201860 kb
Host smart-cc925c8f-1bac-4e31-9974-9620beb50d5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2664577767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2664577767
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1864619442
Short name T836
Test name
Test status
Simulation time 212870364 ps
CPU time 3.38 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:18 PM PDT 24
Peak memory 201840 kb
Host smart-9c4eddd3-29b8-4248-997d-c795a3bcbfd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1864619442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1864619442
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2925420452
Short name T595
Test name
Test status
Simulation time 4310005195 ps
CPU time 12.79 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 202020 kb
Host smart-a94e5bf8-caf2-47a8-806c-505381fee1d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2925420452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2925420452
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4243889329
Short name T704
Test name
Test status
Simulation time 83790937269 ps
CPU time 193.92 seconds
Started Mar 12 12:55:17 PM PDT 24
Finished Mar 12 12:58:31 PM PDT 24
Peak memory 203056 kb
Host smart-5d7a6506-0ec0-4a8e-80d7-89d2c9bd9b7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4243889329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.4243889329
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2745387117
Short name T705
Test name
Test status
Simulation time 240787561 ps
CPU time 3.69 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:20 PM PDT 24
Peak memory 201880 kb
Host smart-a3e856a0-50cf-408a-b5d6-22b5fc173d04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2745387117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2745387117
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1227875550
Short name T411
Test name
Test status
Simulation time 1269656314 ps
CPU time 13.07 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201888 kb
Host smart-0d1a30f8-6ec4-4b22-9615-703b5f2e2c3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1227875550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1227875550
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.4128185269
Short name T703
Test name
Test status
Simulation time 57593062 ps
CPU time 5.72 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:55:32 PM PDT 24
Peak memory 201836 kb
Host smart-0b76b06b-596d-4bc5-be95-55b754497d89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128185269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4128185269
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2894571977
Short name T67
Test name
Test status
Simulation time 13811344464 ps
CPU time 24.43 seconds
Started Mar 12 12:55:25 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 202036 kb
Host smart-8a754bbe-9c7b-4886-9007-f1b31bc5e2f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894571977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2894571977
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1475255870
Short name T250
Test name
Test status
Simulation time 27991848836 ps
CPU time 52.54 seconds
Started Mar 12 12:55:13 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 202044 kb
Host smart-a4fa3eb3-3c12-405e-b46a-835438af3873
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1475255870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1475255870
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1589864350
Short name T430
Test name
Test status
Simulation time 42470787 ps
CPU time 1.95 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:16 PM PDT 24
Peak memory 201924 kb
Host smart-67cfdd5d-b8e0-4718-b12a-4b0a2079a9dc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589864350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1589864350
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.842675789
Short name T538
Test name
Test status
Simulation time 575975030 ps
CPU time 6.09 seconds
Started Mar 12 12:55:19 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 201816 kb
Host smart-faeab652-abdb-4c0d-94e1-e117aac2710c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842675789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.842675789
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.1417310124
Short name T111
Test name
Test status
Simulation time 91900370 ps
CPU time 1.74 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:19 PM PDT 24
Peak memory 201876 kb
Host smart-8e4ce415-5fc0-4972-85fc-3aa95677bf8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1417310124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1417310124
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3984457128
Short name T682
Test name
Test status
Simulation time 2320718672 ps
CPU time 10.72 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:39 PM PDT 24
Peak memory 202028 kb
Host smart-cfba17b0-346f-4969-ac10-08959250830a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984457128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3984457128
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.909881236
Short name T676
Test name
Test status
Simulation time 4415947328 ps
CPU time 7.13 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 202016 kb
Host smart-280498ce-8d97-47dc-a5b8-2ce81111b93a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=909881236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.909881236
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.484225298
Short name T874
Test name
Test status
Simulation time 11826982 ps
CPU time 1.08 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:16 PM PDT 24
Peak memory 201892 kb
Host smart-f5bc67c6-b7a8-41a4-aba1-681db01516f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484225298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.484225298
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2242308090
Short name T397
Test name
Test status
Simulation time 117735436 ps
CPU time 6.45 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:55:29 PM PDT 24
Peak memory 201780 kb
Host smart-a87ad7e7-eae1-47a2-9f94-04cb1cabec90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2242308090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2242308090
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2678627821
Short name T417
Test name
Test status
Simulation time 3806624383 ps
CPU time 59.27 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 202052 kb
Host smart-9f5b4e93-52fa-46de-9d6c-4951605da8e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2678627821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2678627821
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3963786295
Short name T62
Test name
Test status
Simulation time 541190292 ps
CPU time 56.92 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 204228 kb
Host smart-9629376a-e33f-416e-a4fc-093a6faaf581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3963786295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.3963786295
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2187702206
Short name T69
Test name
Test status
Simulation time 6371730344 ps
CPU time 44.69 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 203776 kb
Host smart-3d04d647-589c-46bb-86b8-aa275a9307cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2187702206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2187702206
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3698556386
Short name T601
Test name
Test status
Simulation time 1960840195 ps
CPU time 12.06 seconds
Started Mar 12 12:55:15 PM PDT 24
Finished Mar 12 12:55:28 PM PDT 24
Peak memory 201904 kb
Host smart-b8f98ad1-2826-424e-b45d-11d436c36a98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3698556386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3698556386
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3027993256
Short name T683
Test name
Test status
Simulation time 51821422 ps
CPU time 7.13 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:32 PM PDT 24
Peak memory 201932 kb
Host smart-c526bc43-6eae-4532-bdd5-c53318177f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3027993256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3027993256
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3320505425
Short name T264
Test name
Test status
Simulation time 238486314948 ps
CPU time 198.82 seconds
Started Mar 12 12:55:19 PM PDT 24
Finished Mar 12 12:58:39 PM PDT 24
Peak memory 201984 kb
Host smart-1b106d43-836d-422c-813e-4f4d911f22ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3320505425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3320505425
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2849001855
Short name T144
Test name
Test status
Simulation time 19768274 ps
CPU time 2.24 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:18 PM PDT 24
Peak memory 201900 kb
Host smart-222da036-dacd-4276-aa19-386b1f2f30b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2849001855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2849001855
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.2041781016
Short name T845
Test name
Test status
Simulation time 501971688 ps
CPU time 6.53 seconds
Started Mar 12 12:55:15 PM PDT 24
Finished Mar 12 12:55:22 PM PDT 24
Peak memory 201924 kb
Host smart-b26fe614-3fd0-4865-836a-88c5e17a8c63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2041781016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2041781016
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.337242444
Short name T280
Test name
Test status
Simulation time 763119547 ps
CPU time 11.5 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201680 kb
Host smart-18e15100-c4d8-4e1c-80c9-bba83f07955a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337242444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.337242444
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2658303702
Short name T886
Test name
Test status
Simulation time 97069247805 ps
CPU time 146.26 seconds
Started Mar 12 12:55:17 PM PDT 24
Finished Mar 12 12:57:43 PM PDT 24
Peak memory 202008 kb
Host smart-f30dca3b-ef85-4faa-b4ee-8b09864c9afd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658303702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2658303702
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.880529583
Short name T769
Test name
Test status
Simulation time 41897743742 ps
CPU time 56.85 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:56:22 PM PDT 24
Peak memory 202076 kb
Host smart-68439a37-57f1-4e1d-8180-ee070f162021
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=880529583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.880529583
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.426481646
Short name T569
Test name
Test status
Simulation time 34311520 ps
CPU time 1.25 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:17 PM PDT 24
Peak memory 201932 kb
Host smart-d809d3a5-6a88-4be0-bd89-777daf2451ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426481646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.426481646
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.2286792744
Short name T795
Test name
Test status
Simulation time 16536854 ps
CPU time 1.54 seconds
Started Mar 12 12:55:13 PM PDT 24
Finished Mar 12 12:55:15 PM PDT 24
Peak memory 201928 kb
Host smart-298ef97f-fe4e-4bf5-a28a-9a790d950992
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2286792744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2286792744
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1848980988
Short name T718
Test name
Test status
Simulation time 47775157 ps
CPU time 1.61 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:19 PM PDT 24
Peak memory 201896 kb
Host smart-8c071b3f-20f0-425d-9bef-ec013bb77bdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1848980988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1848980988
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2987098554
Short name T156
Test name
Test status
Simulation time 1900497986 ps
CPU time 9.39 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 201948 kb
Host smart-e03b6d50-3483-4bfa-8220-12c47dae2e81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987098554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2987098554
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1074163972
Short name T598
Test name
Test status
Simulation time 1164664036 ps
CPU time 8.58 seconds
Started Mar 12 12:55:17 PM PDT 24
Finished Mar 12 12:55:26 PM PDT 24
Peak memory 201880 kb
Host smart-36f7444a-f468-4232-af0f-dd87aab37249
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1074163972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1074163972
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.447140567
Short name T831
Test name
Test status
Simulation time 12803062 ps
CPU time 1.42 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:17 PM PDT 24
Peak memory 201856 kb
Host smart-51706ff2-2164-4ebc-aaa0-347154173802
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447140567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.447140567
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.223418290
Short name T572
Test name
Test status
Simulation time 1542202926 ps
CPU time 24.66 seconds
Started Mar 12 12:55:16 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 202900 kb
Host smart-104dfca1-670d-4cc7-b022-08188ccdd832
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223418290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.223418290
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2819193249
Short name T459
Test name
Test status
Simulation time 2139385551 ps
CPU time 32.04 seconds
Started Mar 12 12:55:14 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 201900 kb
Host smart-f521a92f-c6a9-464f-9e4d-7bee4099320c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819193249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2819193249
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3987772705
Short name T61
Test name
Test status
Simulation time 301406057 ps
CPU time 56.25 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:56:21 PM PDT 24
Peak memory 203780 kb
Host smart-449c6780-d8f0-4b33-9026-5ded6c0043cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3987772705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.3987772705
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1254436283
Short name T407
Test name
Test status
Simulation time 739095645 ps
CPU time 56.17 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:56:23 PM PDT 24
Peak memory 204360 kb
Host smart-df3165a9-4d44-46d1-bcb9-79229035d4de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1254436283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.1254436283
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2502698304
Short name T829
Test name
Test status
Simulation time 446628015 ps
CPU time 3.97 seconds
Started Mar 12 12:55:13 PM PDT 24
Finished Mar 12 12:55:18 PM PDT 24
Peak memory 201916 kb
Host smart-3f7b5c37-67b9-4ac8-be42-b62dfda52ee5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2502698304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2502698304
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.4266538530
Short name T649
Test name
Test status
Simulation time 62273298 ps
CPU time 5.08 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201936 kb
Host smart-30066b03-b21d-4bf6-a085-8d06f68f14d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4266538530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4266538530
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1835074471
Short name T265
Test name
Test status
Simulation time 7556961458 ps
CPU time 38.61 seconds
Started Mar 12 12:55:18 PM PDT 24
Finished Mar 12 12:55:57 PM PDT 24
Peak memory 201936 kb
Host smart-ab6b326e-6fbb-46bf-85a2-a2943558eea9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1835074471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.1835074471
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3483311454
Short name T15
Test name
Test status
Simulation time 276487701 ps
CPU time 6.3 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201928 kb
Host smart-8b68f1b9-211e-4e69-baaf-cdf49232fbc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3483311454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3483311454
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2801680492
Short name T765
Test name
Test status
Simulation time 23201218 ps
CPU time 2.65 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:55:38 PM PDT 24
Peak memory 201900 kb
Host smart-44643b3f-1990-4e99-86f9-8e8eac70912a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2801680492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2801680492
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1360256505
Short name T119
Test name
Test status
Simulation time 43430926581 ps
CPU time 106.85 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 202016 kb
Host smart-f9a7adc6-29c1-4e3c-a8e2-3af6aa080ec8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360256505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1360256505
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1125721835
Short name T637
Test name
Test status
Simulation time 98489481778 ps
CPU time 88.97 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 202040 kb
Host smart-bffb4644-c57a-405e-940e-665e81e16dfb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1125721835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1125721835
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.99134614
Short name T888
Test name
Test status
Simulation time 107375647 ps
CPU time 7.56 seconds
Started Mar 12 12:55:34 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201916 kb
Host smart-5d5b85c3-7eb1-493b-add3-ba64e8fae30b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99134614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.99134614
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.3499057314
Short name T522
Test name
Test status
Simulation time 75753016 ps
CPU time 5.4 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201820 kb
Host smart-62146b7b-3a96-41dd-84a9-38e49da8e012
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3499057314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3499057314
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.544753592
Short name T571
Test name
Test status
Simulation time 10645611 ps
CPU time 1.24 seconds
Started Mar 12 12:55:12 PM PDT 24
Finished Mar 12 12:55:14 PM PDT 24
Peak memory 201832 kb
Host smart-54a7bc87-a134-424e-9f42-efdb9ab6aa0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=544753592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.544753592
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.4079370920
Short name T899
Test name
Test status
Simulation time 16659566274 ps
CPU time 11.42 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:55:38 PM PDT 24
Peak memory 201976 kb
Host smart-5544606a-7aa3-475d-aeb3-880dfad795f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079370920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4079370920
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.503718615
Short name T184
Test name
Test status
Simulation time 877696056 ps
CPU time 4.92 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:33 PM PDT 24
Peak memory 201936 kb
Host smart-b3b1b647-0efa-4df7-937e-4ee88256e4c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=503718615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.503718615
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1809685891
Short name T724
Test name
Test status
Simulation time 8777878 ps
CPU time 1.24 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:55:25 PM PDT 24
Peak memory 201920 kb
Host smart-965b7376-4f87-4d29-803b-e6a20fdbea80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809685891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1809685891
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1460070543
Short name T669
Test name
Test status
Simulation time 3338253386 ps
CPU time 30.96 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 203040 kb
Host smart-1d545d11-6747-4b94-8713-c48c57b9fbd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460070543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1460070543
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1228973264
Short name T256
Test name
Test status
Simulation time 6687023189 ps
CPU time 51.59 seconds
Started Mar 12 12:55:32 PM PDT 24
Finished Mar 12 12:56:24 PM PDT 24
Peak memory 201972 kb
Host smart-75067a13-0533-4d0f-88d5-897fe77a4f4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1228973264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1228973264
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3596399988
Short name T804
Test name
Test status
Simulation time 823173656 ps
CPU time 72.24 seconds
Started Mar 12 12:55:18 PM PDT 24
Finished Mar 12 12:56:30 PM PDT 24
Peak memory 206040 kb
Host smart-f55b0097-7992-4d48-8c12-c733e7c4d693
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3596399988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3596399988
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3868135402
Short name T783
Test name
Test status
Simulation time 9533151888 ps
CPU time 98.96 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 203948 kb
Host smart-55b38ae1-9e77-4990-a375-5589e5c027ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3868135402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3868135402
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.615857117
Short name T678
Test name
Test status
Simulation time 791280144 ps
CPU time 10.62 seconds
Started Mar 12 12:55:31 PM PDT 24
Finished Mar 12 12:55:42 PM PDT 24
Peak memory 201596 kb
Host smart-f0db74da-dc20-4377-b665-7d77e13f9c85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=615857117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.615857117
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.212478355
Short name T481
Test name
Test status
Simulation time 819048743 ps
CPU time 15.95 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201948 kb
Host smart-30067056-95ba-4353-b220-0309208e4c03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=212478355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.212478355
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1948691296
Short name T219
Test name
Test status
Simulation time 18644258424 ps
CPU time 131.43 seconds
Started Mar 12 12:55:21 PM PDT 24
Finished Mar 12 12:57:33 PM PDT 24
Peak memory 203092 kb
Host smart-33495759-503c-4b2b-a4d4-bcd27e5470ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1948691296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1948691296
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.4185063507
Short name T435
Test name
Test status
Simulation time 7878609 ps
CPU time 1.07 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 201952 kb
Host smart-d5a99184-53dc-418a-8267-3b4b178d71e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4185063507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4185063507
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3095241832
Short name T817
Test name
Test status
Simulation time 247864002 ps
CPU time 5.79 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 201896 kb
Host smart-6eb0d2a4-cf05-4d09-9a3f-cafba1adcbec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3095241832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3095241832
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.3369540976
Short name T877
Test name
Test status
Simulation time 244998640 ps
CPU time 2.7 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:27 PM PDT 24
Peak memory 201852 kb
Host smart-4cc98e36-58dd-4130-831c-0dd083698d4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3369540976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3369540976
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.361766899
Short name T209
Test name
Test status
Simulation time 32009294708 ps
CPU time 85.9 seconds
Started Mar 12 12:55:18 PM PDT 24
Finished Mar 12 12:56:44 PM PDT 24
Peak memory 202044 kb
Host smart-97b9a0b2-2fc7-4fd4-8062-24da9d6a3dc9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=361766899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.361766899
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.981296531
Short name T726
Test name
Test status
Simulation time 12201314630 ps
CPU time 81.69 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:56:46 PM PDT 24
Peak memory 202036 kb
Host smart-7417db10-cadd-496b-879a-8dad9a66e752
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=981296531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.981296531
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2008557043
Short name T49
Test name
Test status
Simulation time 72656827 ps
CPU time 8.26 seconds
Started Mar 12 12:55:22 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201924 kb
Host smart-8353cdaf-694c-40d0-b902-a127272df3f0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008557043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2008557043
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.118878640
Short name T689
Test name
Test status
Simulation time 148992691 ps
CPU time 4.64 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201900 kb
Host smart-8519dad3-0668-40c6-add2-832dd81da6c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=118878640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.118878640
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3902048901
Short name T566
Test name
Test status
Simulation time 16869194 ps
CPU time 1.02 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:55:27 PM PDT 24
Peak memory 201848 kb
Host smart-afd68958-ac64-472c-ba75-c7eddbf54ffa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3902048901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3902048901
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3285389098
Short name T580
Test name
Test status
Simulation time 1228302482 ps
CPU time 6.29 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201928 kb
Host smart-cc3ac6ec-3d4a-4386-b584-bfc898fcba59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285389098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3285389098
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3174473885
Short name T740
Test name
Test status
Simulation time 868533842 ps
CPU time 6.52 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201936 kb
Host smart-508fc6e8-c8c6-4949-95c2-0f8b2e856303
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3174473885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3174473885
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4150484037
Short name T367
Test name
Test status
Simulation time 12676053 ps
CPU time 1.18 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 201884 kb
Host smart-329e081a-13a9-4fc4-895d-2603c25c658e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150484037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.4150484037
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4137538392
Short name T321
Test name
Test status
Simulation time 262817424 ps
CPU time 30.1 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 203040 kb
Host smart-68c92833-20fd-4983-a453-f2cfff2cd21e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4137538392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4137538392
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2064530561
Short name T53
Test name
Test status
Simulation time 112850106 ps
CPU time 13.21 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 201868 kb
Host smart-8ad16d57-5cd9-46bf-8151-0771372b34c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2064530561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2064530561
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3879022088
Short name T103
Test name
Test status
Simulation time 14231419461 ps
CPU time 109.28 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:57:14 PM PDT 24
Peak memory 204464 kb
Host smart-e6dab512-f3aa-44ad-a798-71beea134fa2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3879022088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.3879022088
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2239271426
Short name T129
Test name
Test status
Simulation time 154447251 ps
CPU time 3.44 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201728 kb
Host smart-fbac2629-ae09-4755-9df4-bad31dea18dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2239271426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2239271426
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1111395433
Short name T141
Test name
Test status
Simulation time 532119567 ps
CPU time 6.12 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 201864 kb
Host smart-95166a54-614d-4151-a293-282935523b34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1111395433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1111395433
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3917491556
Short name T560
Test name
Test status
Simulation time 2176697200 ps
CPU time 9.55 seconds
Started Mar 12 12:55:20 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201912 kb
Host smart-a1805511-de53-4b54-8ebf-a7637710905e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3917491556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3917491556
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1767792610
Short name T418
Test name
Test status
Simulation time 655657557 ps
CPU time 12.5 seconds
Started Mar 12 12:55:24 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 201932 kb
Host smart-3b00f966-71d2-4c52-8af7-7f2eec5226ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1767792610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1767792610
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.1831057369
Short name T857
Test name
Test status
Simulation time 94220516 ps
CPU time 4.51 seconds
Started Mar 12 12:55:25 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 201860 kb
Host smart-93377f05-c77b-4ebf-9b3c-c0e8e5882782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1831057369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1831057369
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1721952101
Short name T839
Test name
Test status
Simulation time 79712131169 ps
CPU time 87.4 seconds
Started Mar 12 12:55:33 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 202016 kb
Host smart-1174063b-c1c1-43de-8df6-6b8e94400d2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721952101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1721952101
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2980967632
Short name T132
Test name
Test status
Simulation time 67986699301 ps
CPU time 117.17 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 202084 kb
Host smart-5399d720-1bde-4ee8-97ee-01ba732fa26c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2980967632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2980967632
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4267761317
Short name T358
Test name
Test status
Simulation time 205891047 ps
CPU time 6.88 seconds
Started Mar 12 12:55:25 PM PDT 24
Finished Mar 12 12:55:32 PM PDT 24
Peak memory 201924 kb
Host smart-33466cd2-46f8-4055-b16b-93f5a833789d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267761317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4267761317
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3226044972
Short name T375
Test name
Test status
Simulation time 1519133964 ps
CPU time 6.21 seconds
Started Mar 12 12:55:33 PM PDT 24
Finished Mar 12 12:55:39 PM PDT 24
Peak memory 201880 kb
Host smart-0e0f274f-57a9-4203-a6a1-3dd2965d5e46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3226044972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3226044972
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.4248264083
Short name T793
Test name
Test status
Simulation time 65001094 ps
CPU time 1.59 seconds
Started Mar 12 12:55:25 PM PDT 24
Finished Mar 12 12:55:27 PM PDT 24
Peak memory 201856 kb
Host smart-770b6f90-fc3e-4bda-bf29-3ed765eb63b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4248264083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4248264083
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.479405132
Short name T889
Test name
Test status
Simulation time 10259270634 ps
CPU time 11.64 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 201996 kb
Host smart-15253b43-e8da-4f96-91dd-ef136e5687e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=479405132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.479405132
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1580256442
Short name T355
Test name
Test status
Simulation time 918202110 ps
CPU time 5.45 seconds
Started Mar 12 12:55:21 PM PDT 24
Finished Mar 12 12:55:27 PM PDT 24
Peak memory 201936 kb
Host smart-c9b77886-ec03-47c0-abde-af0603f8267d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1580256442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1580256442
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3250704006
Short name T558
Test name
Test status
Simulation time 32049838 ps
CPU time 1.36 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:32 PM PDT 24
Peak memory 201852 kb
Host smart-410e6472-0a1d-4632-bbb2-70520b082192
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250704006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3250704006
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1794145743
Short name T651
Test name
Test status
Simulation time 821842200 ps
CPU time 12.91 seconds
Started Mar 12 12:55:31 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201688 kb
Host smart-163a2e17-523d-46be-94ba-5e76f1964d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1794145743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1794145743
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3780413877
Short name T673
Test name
Test status
Simulation time 5002092010 ps
CPU time 65.7 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:56:32 PM PDT 24
Peak memory 201940 kb
Host smart-9f314c2c-6778-4acc-b088-b683b6c1f6d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3780413877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3780413877
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3667960052
Short name T866
Test name
Test status
Simulation time 600634169 ps
CPU time 62.89 seconds
Started Mar 12 12:55:23 PM PDT 24
Finished Mar 12 12:56:27 PM PDT 24
Peak memory 204256 kb
Host smart-a1796757-7d9a-46e6-8edd-45ad48f6a4e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3667960052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3667960052
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3553785235
Short name T753
Test name
Test status
Simulation time 12645010035 ps
CPU time 110.56 seconds
Started Mar 12 12:55:26 PM PDT 24
Finished Mar 12 12:57:17 PM PDT 24
Peak memory 207420 kb
Host smart-a7f26a86-e8cb-4abd-b756-2591d45b676a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3553785235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.3553785235
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.729975715
Short name T586
Test name
Test status
Simulation time 100715334 ps
CPU time 3.96 seconds
Started Mar 12 12:55:19 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 201904 kb
Host smart-e549b705-8686-4705-bd1e-1fcd679c3b82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=729975715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.729975715
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2345667632
Short name T427
Test name
Test status
Simulation time 1107740815 ps
CPU time 13.82 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201948 kb
Host smart-967aa26f-a424-49bd-8543-42d44c187d57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2345667632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2345667632
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3906113791
Short name T671
Test name
Test status
Simulation time 72053205 ps
CPU time 3.49 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201896 kb
Host smart-e0eb30bd-12d9-4c38-a839-aaff9e241a7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906113791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3906113791
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.912437559
Short name T898
Test name
Test status
Simulation time 354982257 ps
CPU time 6.78 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201928 kb
Host smart-1601a1e9-c69b-4a18-90d3-d53be91ff29b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912437559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.912437559
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.441425096
Short name T446
Test name
Test status
Simulation time 77752599 ps
CPU time 7.15 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201792 kb
Host smart-95504066-ded5-415e-8cb0-20c1eb354d38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=441425096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.441425096
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.404608960
Short name T102
Test name
Test status
Simulation time 62294119456 ps
CPU time 156.17 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 201976 kb
Host smart-25e7a88a-2d15-4a03-b45a-bff277678bd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=404608960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.404608960
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2667970794
Short name T221
Test name
Test status
Simulation time 30081341125 ps
CPU time 151.57 seconds
Started Mar 12 12:55:32 PM PDT 24
Finished Mar 12 12:58:04 PM PDT 24
Peak memory 202028 kb
Host smart-c3598481-f99e-4303-8af6-649fabf86cd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2667970794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2667970794
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3902762167
Short name T554
Test name
Test status
Simulation time 76375089 ps
CPU time 6.6 seconds
Started Mar 12 12:55:34 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201900 kb
Host smart-ff6f2904-ce8e-483f-9f7d-85c3cd31dd7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902762167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3902762167
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.1909012839
Short name T790
Test name
Test status
Simulation time 164261133 ps
CPU time 1.79 seconds
Started Mar 12 12:55:33 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201900 kb
Host smart-20b110f4-0eae-42c4-90d6-cfb9e3cf89a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1909012839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1909012839
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2281800191
Short name T437
Test name
Test status
Simulation time 12567684 ps
CPU time 1.27 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201896 kb
Host smart-91e3d1f4-c2ba-4fe3-bb02-ef1c2b92d81a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2281800191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2281800191
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3139546894
Short name T559
Test name
Test status
Simulation time 11802551339 ps
CPU time 9.91 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:39 PM PDT 24
Peak memory 202040 kb
Host smart-268b548d-3644-4a91-b89f-f2ca209ae96a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139546894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3139546894
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.32369579
Short name T217
Test name
Test status
Simulation time 2649622628 ps
CPU time 9.04 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 202072 kb
Host smart-316e47c8-9d89-40a3-b732-bf63ba5e0fe8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=32369579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.32369579
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.4070025034
Short name T832
Test name
Test status
Simulation time 9127325 ps
CPU time 1.12 seconds
Started Mar 12 12:55:31 PM PDT 24
Finished Mar 12 12:55:33 PM PDT 24
Peak memory 201948 kb
Host smart-67df0f1e-eaed-4341-bc57-deba8d4b7589
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070025034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.4070025034
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1779555268
Short name T365
Test name
Test status
Simulation time 6872762235 ps
CPU time 71.27 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:56:48 PM PDT 24
Peak memory 203052 kb
Host smart-37377ab1-8819-4414-8b92-83c71fbfef6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1779555268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1779555268
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.729133775
Short name T803
Test name
Test status
Simulation time 1054656977 ps
CPU time 103.48 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 204068 kb
Host smart-16b71e21-f2d5-4b41-9145-f62a3163f1df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=729133775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand
_reset.729133775
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.928408798
Short name T778
Test name
Test status
Simulation time 157996466 ps
CPU time 37.79 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:56:13 PM PDT 24
Peak memory 203432 kb
Host smart-01e44814-7029-4d64-85d4-91c70db4f8e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928408798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res
et_error.928408798
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.344846481
Short name T292
Test name
Test status
Simulation time 1230741202 ps
CPU time 10.23 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 201932 kb
Host smart-c09df3e9-95bb-4284-9daa-98381056ad6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=344846481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.344846481
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3871353270
Short name T259
Test name
Test status
Simulation time 1923273220 ps
CPU time 9.64 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:49 PM PDT 24
Peak memory 201840 kb
Host smart-8efbceec-18d4-434a-89b4-c1a8296efe73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3871353270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3871353270
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.840107117
Short name T96
Test name
Test status
Simulation time 28071974649 ps
CPU time 147.94 seconds
Started Mar 12 12:55:34 PM PDT 24
Finished Mar 12 12:58:03 PM PDT 24
Peak memory 203144 kb
Host smart-a6920fbd-3eb7-40a7-b272-a573de32eafb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=840107117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.840107117
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3456584887
Short name T423
Test name
Test status
Simulation time 760262476 ps
CPU time 10.77 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201900 kb
Host smart-d9d621e4-6d4d-4f86-9706-496ee86bb4d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3456584887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3456584887
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.925924498
Short name T218
Test name
Test status
Simulation time 3336101069 ps
CPU time 9.57 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 202032 kb
Host smart-045610be-3a68-46ea-8775-54762781b14e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925924498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.925924498
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1979103033
Short name T754
Test name
Test status
Simulation time 76020502 ps
CPU time 2.91 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201808 kb
Host smart-334c1d4f-1dd9-441b-8c92-5cef3e0cb232
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979103033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1979103033
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.79925599
Short name T287
Test name
Test status
Simulation time 74518877911 ps
CPU time 52.23 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:56:28 PM PDT 24
Peak memory 201920 kb
Host smart-e683fc94-8b9b-4cfe-b866-4f60531e1f1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=79925599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.79925599
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3524447658
Short name T326
Test name
Test status
Simulation time 18861668983 ps
CPU time 61.3 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:56:39 PM PDT 24
Peak memory 201980 kb
Host smart-ce5d2ccf-104f-4734-96cf-d1d0ff1e36bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3524447658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3524447658
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1327037756
Short name T433
Test name
Test status
Simulation time 75342977 ps
CPU time 7.41 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201924 kb
Host smart-c9890967-7300-4a0e-abde-7ed228431a54
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327037756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1327037756
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.211003116
Short name T59
Test name
Test status
Simulation time 786900002 ps
CPU time 10.81 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:38 PM PDT 24
Peak memory 201888 kb
Host smart-a9d88882-afeb-4a8c-ac42-86e8079fddb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=211003116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.211003116
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.4003706623
Short name T697
Test name
Test status
Simulation time 50368965 ps
CPU time 1.51 seconds
Started Mar 12 12:55:34 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201876 kb
Host smart-4e9b352a-6805-4e4d-80c6-e7c0243a4ec3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003706623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.4003706623
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2126411186
Short name T199
Test name
Test status
Simulation time 1537289828 ps
CPU time 7.27 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 201912 kb
Host smart-b531e69e-a0c7-448f-a868-de8f7d5a32c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126411186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2126411186
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3534564034
Short name T81
Test name
Test status
Simulation time 1409281024 ps
CPU time 10.37 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201868 kb
Host smart-e9edeae2-0b59-4a20-b276-6cc6864a99eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3534564034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3534564034
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1778681726
Short name T301
Test name
Test status
Simulation time 11542027 ps
CPU time 1.14 seconds
Started Mar 12 12:55:30 PM PDT 24
Finished Mar 12 12:55:31 PM PDT 24
Peak memory 201924 kb
Host smart-0143bdde-a9dd-444c-8e9b-a6bf5f56a502
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778681726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1778681726
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4033764811
Short name T127
Test name
Test status
Simulation time 12358271405 ps
CPU time 50.45 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:56:28 PM PDT 24
Peak memory 203040 kb
Host smart-a2682057-ce38-4d9a-b858-ca5089dd0a77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4033764811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4033764811
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1471743554
Short name T846
Test name
Test status
Simulation time 4206454839 ps
CPU time 38.54 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:56:24 PM PDT 24
Peak memory 201912 kb
Host smart-719987d1-dedd-4b0a-b288-d9c6e612891d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1471743554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1471743554
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1955398141
Short name T180
Test name
Test status
Simulation time 253112009 ps
CPU time 25.78 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:56:01 PM PDT 24
Peak memory 202916 kb
Host smart-e2642c4b-fcff-4ec3-a47e-7070692d8a35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1955398141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.1955398141
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2764884216
Short name T878
Test name
Test status
Simulation time 604857370 ps
CPU time 45.1 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 203800 kb
Host smart-b50e6c20-c09e-401e-ad72-7b9a4888a035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2764884216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2764884216
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3636372554
Short name T879
Test name
Test status
Simulation time 83593975 ps
CPU time 1.95 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201852 kb
Host smart-ec6f8ed0-3072-44fd-8c86-b693ac8f800a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3636372554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3636372554
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3088151067
Short name T520
Test name
Test status
Simulation time 109492778 ps
CPU time 6.53 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:55:42 PM PDT 24
Peak memory 201924 kb
Host smart-00bfc7c3-a954-4d60-a3d1-6761d0739728
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3088151067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3088151067
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1315370055
Short name T115
Test name
Test status
Simulation time 97485301612 ps
CPU time 131.41 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:57:41 PM PDT 24
Peak memory 202048 kb
Host smart-f103a19e-0a2c-4f04-805c-546b4b4359b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1315370055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.1315370055
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2371451336
Short name T800
Test name
Test status
Simulation time 1155193640 ps
CPU time 4.68 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 201844 kb
Host smart-0d007320-1f27-4c55-8b93-10f963647a8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371451336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2371451336
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.1347897683
Short name T719
Test name
Test status
Simulation time 1024238020 ps
CPU time 11.88 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201904 kb
Host smart-022d6996-0172-4086-aa7d-e194f37f9270
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1347897683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1347897683
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3336062280
Short name T185
Test name
Test status
Simulation time 134716729 ps
CPU time 2.04 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 201804 kb
Host smart-984223c8-7000-41ee-b669-9b4a91baa5f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3336062280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3336062280
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1628577678
Short name T118
Test name
Test status
Simulation time 60390572408 ps
CPU time 151.18 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:58:06 PM PDT 24
Peak memory 202048 kb
Host smart-897c1b82-3144-4406-a5d5-6b249e183922
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628577678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1628577678
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3324589645
Short name T482
Test name
Test status
Simulation time 6552852106 ps
CPU time 15.39 seconds
Started Mar 12 12:55:35 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 202004 kb
Host smart-c7f13be4-819d-4211-9ed5-f8e72384319d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3324589645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3324589645
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3840768603
Short name T148
Test name
Test status
Simulation time 72036831 ps
CPU time 7.97 seconds
Started Mar 12 12:55:32 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 201892 kb
Host smart-36092bb2-dc40-438d-8d02-e74c29e89b4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840768603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3840768603
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.294876993
Short name T577
Test name
Test status
Simulation time 28042493 ps
CPU time 1.88 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:55:39 PM PDT 24
Peak memory 201828 kb
Host smart-31a5569a-6c10-4f12-8778-dfeb6cf64188
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294876993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.294876993
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2049168634
Short name T876
Test name
Test status
Simulation time 42387864 ps
CPU time 1.36 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 201872 kb
Host smart-e54a9ac9-4b78-4caf-93c1-860b6aff61b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049168634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2049168634
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3472457746
Short name T546
Test name
Test status
Simulation time 6597670197 ps
CPU time 9.03 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 202064 kb
Host smart-94c606d5-566e-448f-ba7b-17756f1c7e3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472457746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3472457746
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3940646989
Short name T556
Test name
Test status
Simulation time 4834377170 ps
CPU time 12.46 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:55:42 PM PDT 24
Peak memory 202036 kb
Host smart-0b6792eb-3aad-45fa-b61d-93dc824de68c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3940646989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3940646989
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.831384864
Short name T727
Test name
Test status
Simulation time 9693912 ps
CPU time 1.33 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201792 kb
Host smart-93bb8a1b-1755-4b0f-aeaa-e9bf28e905e0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831384864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.831384864
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1320045557
Short name T205
Test name
Test status
Simulation time 2421276690 ps
CPU time 20.42 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:59 PM PDT 24
Peak memory 201912 kb
Host smart-23be0ba9-1c57-454b-8fac-36e221d2b5d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320045557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1320045557
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.963070138
Short name T841
Test name
Test status
Simulation time 4065555237 ps
CPU time 56.35 seconds
Started Mar 12 12:55:29 PM PDT 24
Finished Mar 12 12:56:25 PM PDT 24
Peak memory 202004 kb
Host smart-b22f7f76-c6d3-46b3-a7f3-5e8c0bfb99ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=963070138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.963070138
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4277685864
Short name T350
Test name
Test status
Simulation time 7054401145 ps
CPU time 87.94 seconds
Started Mar 12 12:55:37 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 205216 kb
Host smart-5a5e0226-ebdd-4301-943d-a091c2580f7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4277685864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.4277685864
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.715226265
Short name T774
Test name
Test status
Simulation time 92728295 ps
CPU time 4.71 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201888 kb
Host smart-ea247b49-4ed7-459d-94ea-205347b22419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=715226265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res
et_error.715226265
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2474924603
Short name T479
Test name
Test status
Simulation time 9218125 ps
CPU time 1.08 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 201888 kb
Host smart-591367ed-61b7-43ae-8c54-96457ed6734e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2474924603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2474924603
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3138463324
Short name T182
Test name
Test status
Simulation time 68242086 ps
CPU time 8.46 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201900 kb
Host smart-c8e1f376-7370-4128-acaf-9e6a2a479a42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3138463324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3138463324
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3946250082
Short name T274
Test name
Test status
Simulation time 7631643755 ps
CPU time 49.6 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 202052 kb
Host smart-16a0c86f-50f4-4665-a651-c9bfec6efe10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3946250082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.3946250082
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2925435901
Short name T691
Test name
Test status
Simulation time 78658228 ps
CPU time 4.68 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 201952 kb
Host smart-d34b7886-9753-4c43-a7d2-89fb6776e18c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2925435901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2925435901
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.943721548
Short name T751
Test name
Test status
Simulation time 594209196 ps
CPU time 5.82 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201872 kb
Host smart-1ca81ad8-1852-4d45-ba3c-5ee9e8319bc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=943721548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.943721548
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1221129829
Short name T43
Test name
Test status
Simulation time 702076520 ps
CPU time 9.77 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201856 kb
Host smart-b5f749b9-8c16-436a-8502-03953a9e238d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1221129829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1221129829
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.966130437
Short name T38
Test name
Test status
Simulation time 26982397632 ps
CPU time 78.9 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:56:05 PM PDT 24
Peak memory 202072 kb
Host smart-0269aa55-abc8-4098-a873-b074fe0714a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=966130437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.966130437
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4107700957
Short name T341
Test name
Test status
Simulation time 166534055 ps
CPU time 3.24 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 201844 kb
Host smart-af3c0294-6d2b-45f4-a3cd-f9c1685312f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107700957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4107700957
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.3804487065
Short name T201
Test name
Test status
Simulation time 188447442 ps
CPU time 3.15 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201900 kb
Host smart-a2e63080-26d2-4e10-bce5-b626589854bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3804487065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3804487065
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3691975113
Short name T166
Test name
Test status
Simulation time 228896903 ps
CPU time 1.42 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 201776 kb
Host smart-72f472a9-5aad-4b14-82ce-a4f8fddc93fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3691975113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3691975113
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3049079204
Short name T410
Test name
Test status
Simulation time 5323313320 ps
CPU time 10.26 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 202036 kb
Host smart-2e603cf9-a66f-4861-b1a4-50481bdff7ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049079204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3049079204
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1638022209
Short name T83
Test name
Test status
Simulation time 2357892523 ps
CPU time 7.75 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 202056 kb
Host smart-366562b2-149c-4870-b69f-d5b234afcc9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1638022209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1638022209
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1297535052
Short name T796
Test name
Test status
Simulation time 9803814 ps
CPU time 1.32 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 201884 kb
Host smart-10808afb-7f70-47e8-91be-c805bca5b469
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297535052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1297535052
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2150076588
Short name T351
Test name
Test status
Simulation time 14278660776 ps
CPU time 80.24 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 203964 kb
Host smart-ecbc5032-0908-4d52-9a86-11e701f62c9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2150076588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2150076588
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2930766001
Short name T419
Test name
Test status
Simulation time 8234331922 ps
CPU time 50.08 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:55:38 PM PDT 24
Peak memory 202072 kb
Host smart-b88a0d41-8484-4e7f-8f73-aba9c681530e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2930766001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2930766001
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.674658171
Short name T76
Test name
Test status
Simulation time 5089735386 ps
CPU time 117.91 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:56:44 PM PDT 24
Peak memory 204408 kb
Host smart-1ec39f04-b84e-4f82-9d9b-f6ca33a8fb05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=674658171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_
reset.674658171
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3885077167
Short name T893
Test name
Test status
Simulation time 364484957 ps
CPU time 51.18 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 203416 kb
Host smart-25fa7ba1-752a-4ced-94d0-9d451ee0e6ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3885077167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.3885077167
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.605652151
Short name T561
Test name
Test status
Simulation time 114827066 ps
CPU time 3.05 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 201904 kb
Host smart-66f06cdc-5b3f-4a9d-8c04-3711b39be376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=605652151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.605652151
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1985878611
Short name T153
Test name
Test status
Simulation time 38604208 ps
CPU time 7.69 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:55:59 PM PDT 24
Peak memory 201868 kb
Host smart-e590ee1f-c6ce-4196-8514-5213840283b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1985878611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1985878611
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3355991326
Short name T27
Test name
Test status
Simulation time 20614222463 ps
CPU time 148.77 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 203060 kb
Host smart-a849ad2d-a32e-48f2-a2d3-b33fabd5c75b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3355991326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3355991326
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2346927918
Short name T284
Test name
Test status
Simulation time 44154231 ps
CPU time 4.16 seconds
Started Mar 12 12:55:48 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201908 kb
Host smart-6e4a36bf-515c-4b6f-ae3d-2a2a45a174db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346927918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2346927918
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.2532109485
Short name T110
Test name
Test status
Simulation time 853164901 ps
CPU time 11.71 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201904 kb
Host smart-d7470817-d7a9-45a7-80ce-bd0c67ee7201
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2532109485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2532109485
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1844264140
Short name T733
Test name
Test status
Simulation time 63050762 ps
CPU time 1.57 seconds
Started Mar 12 12:55:34 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 201784 kb
Host smart-9fad492b-94a2-4cc4-b73b-0a693fe2932d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1844264140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1844264140
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.56191434
Short name T684
Test name
Test status
Simulation time 23651761020 ps
CPU time 31.37 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 202028 kb
Host smart-d981db63-0d3b-4e87-b61e-90285fc416bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=56191434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.56191434
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1216382788
Short name T436
Test name
Test status
Simulation time 17387587032 ps
CPU time 64.29 seconds
Started Mar 12 12:55:36 PM PDT 24
Finished Mar 12 12:56:41 PM PDT 24
Peak memory 202072 kb
Host smart-f0afeaf7-db05-4bca-9004-dd6828201d9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1216382788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1216382788
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2441232594
Short name T44
Test name
Test status
Simulation time 20559545 ps
CPU time 1.81 seconds
Started Mar 12 12:55:33 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201868 kb
Host smart-aadab262-5787-4a8e-a91f-8a4de6479594
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441232594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2441232594
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.641114812
Short name T758
Test name
Test status
Simulation time 118565742 ps
CPU time 5.95 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201924 kb
Host smart-8826a204-fbdd-41b0-8191-552f85fcf4e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=641114812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.641114812
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.1581246467
Short name T731
Test name
Test status
Simulation time 107989491 ps
CPU time 1.57 seconds
Started Mar 12 12:55:27 PM PDT 24
Finished Mar 12 12:55:28 PM PDT 24
Peak memory 201820 kb
Host smart-2a8b5d5c-9969-4dc2-a1fb-75e8ac80480d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1581246467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1581246467
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.4009894779
Short name T521
Test name
Test status
Simulation time 13871892802 ps
CPU time 12.98 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 201988 kb
Host smart-cd14f7cd-6832-40f7-82b8-88e0fc991215
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009894779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4009894779
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.689708203
Short name T349
Test name
Test status
Simulation time 1299087036 ps
CPU time 8.19 seconds
Started Mar 12 12:55:28 PM PDT 24
Finished Mar 12 12:55:37 PM PDT 24
Peak memory 201880 kb
Host smart-f7b26448-658a-4931-9c40-25215d75f579
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=689708203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.689708203
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1064591612
Short name T512
Test name
Test status
Simulation time 8506622 ps
CPU time 1.13 seconds
Started Mar 12 12:55:46 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201860 kb
Host smart-c81abbde-6530-4729-869a-54e821454400
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064591612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1064591612
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3847383264
Short name T791
Test name
Test status
Simulation time 5062044887 ps
CPU time 39.58 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:56:25 PM PDT 24
Peak memory 203052 kb
Host smart-a8daef96-bfe7-487e-ab96-1a118f3852d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3847383264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3847383264
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.536230674
Short name T309
Test name
Test status
Simulation time 525395177 ps
CPU time 40.96 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:56:25 PM PDT 24
Peak memory 202924 kb
Host smart-be734c70-882a-437d-a61f-dab509bde407
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=536230674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.536230674
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4223596873
Short name T162
Test name
Test status
Simulation time 246592953 ps
CPU time 44.57 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:56:23 PM PDT 24
Peak memory 204192 kb
Host smart-105c608c-0e17-498e-9dc3-f25ac6e6bee8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4223596873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.4223596873
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.649980300
Short name T107
Test name
Test status
Simulation time 1120210804 ps
CPU time 127.71 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:57:56 PM PDT 24
Peak memory 209212 kb
Host smart-eedad5a1-4870-4921-99dc-a6b2ace21c66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649980300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.649980300
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3123652009
Short name T654
Test name
Test status
Simulation time 131180170 ps
CPU time 2.37 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 201952 kb
Host smart-d55fd02d-a632-41bf-ba17-938de08288ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3123652009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3123652009
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3454772370
Short name T714
Test name
Test status
Simulation time 4170113129 ps
CPU time 16.33 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:56:08 PM PDT 24
Peak memory 202028 kb
Host smart-c94c85e6-e855-4f48-9eee-6d5091a6581a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454772370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3454772370
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2573766755
Short name T42
Test name
Test status
Simulation time 103916249806 ps
CPU time 110.83 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 202080 kb
Host smart-99f1c032-539d-4016-9307-cf32684a7564
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2573766755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2573766755
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2326310655
Short name T625
Test name
Test status
Simulation time 26549649 ps
CPU time 2.72 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201840 kb
Host smart-f4fb720c-5562-4b60-ab1f-f1d5911cd27e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2326310655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2326310655
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3653104960
Short name T281
Test name
Test status
Simulation time 107093441 ps
CPU time 5.17 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201868 kb
Host smart-f197de3c-95d8-42ee-baa3-5795d668bca9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3653104960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3653104960
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.24793055
Short name T438
Test name
Test status
Simulation time 70372554 ps
CPU time 6.7 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201876 kb
Host smart-736a7c23-48e1-4d62-85dd-89c87046273a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24793055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.24793055
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1175894600
Short name T716
Test name
Test status
Simulation time 56883328573 ps
CPU time 140.58 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:58:06 PM PDT 24
Peak memory 202048 kb
Host smart-5dabab0d-89d4-4cea-bb09-26e8abb9c504
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175894600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1175894600
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1664916852
Short name T18
Test name
Test status
Simulation time 30018399635 ps
CPU time 63.1 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:56:45 PM PDT 24
Peak memory 202020 kb
Host smart-68b508af-9672-4b05-a1e0-8e37ef0a9b3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1664916852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1664916852
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2494553232
Short name T500
Test name
Test status
Simulation time 102265761 ps
CPU time 7.32 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:55:59 PM PDT 24
Peak memory 201904 kb
Host smart-bb0c9d01-3da9-4537-8721-0eca3e02af93
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494553232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2494553232
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.1436300530
Short name T882
Test name
Test status
Simulation time 814678065 ps
CPU time 4.11 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201888 kb
Host smart-27c21084-95e1-44df-a54b-4276bd310f20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1436300530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1436300530
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.299762764
Short name T662
Test name
Test status
Simulation time 123837994 ps
CPU time 1.27 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:47 PM PDT 24
Peak memory 201828 kb
Host smart-6da1efc3-c8bd-4802-8ba0-592d59bed1d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=299762764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.299762764
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.133892766
Short name T687
Test name
Test status
Simulation time 8286423669 ps
CPU time 6.85 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 202012 kb
Host smart-c8ddecbd-932e-4af3-8018-f13ab9acdae4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=133892766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.133892766
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2653582752
Short name T550
Test name
Test status
Simulation time 6087667595 ps
CPU time 10.87 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:52 PM PDT 24
Peak memory 202044 kb
Host smart-b01d5de6-4588-40a2-91ac-cd63fe4e4eb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2653582752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2653582752
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3131525771
Short name T600
Test name
Test status
Simulation time 9436610 ps
CPU time 1.19 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201904 kb
Host smart-a7b46527-a0e4-48a5-b0df-27d361e939c0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131525771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3131525771
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.46248334
Short name T131
Test name
Test status
Simulation time 7864121466 ps
CPU time 85.75 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:57:08 PM PDT 24
Peak memory 203440 kb
Host smart-975df49b-50ae-4cf0-9699-c49b36f9aa5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46248334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.46248334
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4181123843
Short name T200
Test name
Test status
Simulation time 1172311429 ps
CPU time 134.27 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:57:58 PM PDT 24
Peak memory 206452 kb
Host smart-dfcd0d66-d677-48ec-8e5b-1c5f900d829c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4181123843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.4181123843
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1963551376
Short name T474
Test name
Test status
Simulation time 112180962 ps
CPU time 10.1 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201904 kb
Host smart-bc165048-5dba-4997-bf12-95e474a5a9f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1963551376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1963551376
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.242193211
Short name T159
Test name
Test status
Simulation time 953007819 ps
CPU time 10.07 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201880 kb
Host smart-5915530b-fbae-4c72-8d3d-eb34faa438f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=242193211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.242193211
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3572770057
Short name T742
Test name
Test status
Simulation time 457565889 ps
CPU time 11.73 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201880 kb
Host smart-55117eb1-9f24-45e7-9163-c2f0f1a3c259
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572770057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3572770057
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3760632038
Short name T856
Test name
Test status
Simulation time 49109533068 ps
CPU time 222.25 seconds
Started Mar 12 12:55:46 PM PDT 24
Finished Mar 12 12:59:30 PM PDT 24
Peak memory 204088 kb
Host smart-6219d272-f1fa-48e7-89c4-244dc7f2db2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3760632038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3760632038
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1501618613
Short name T892
Test name
Test status
Simulation time 376702215 ps
CPU time 4.96 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201900 kb
Host smart-ee803f06-333a-4df1-a233-aa9b6bb90c16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1501618613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1501618613
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1287600262
Short name T833
Test name
Test status
Simulation time 2234288121 ps
CPU time 8.29 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 202064 kb
Host smart-def7396c-0180-47f5-8b0f-17f85e2281e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1287600262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1287600262
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.1643848951
Short name T346
Test name
Test status
Simulation time 66532235 ps
CPU time 3.71 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:49 PM PDT 24
Peak memory 201856 kb
Host smart-d3576298-597d-418b-806c-73347ad7507e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1643848951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1643848951
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.120671040
Short name T582
Test name
Test status
Simulation time 26850214705 ps
CPU time 121.54 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:57:44 PM PDT 24
Peak memory 202048 kb
Host smart-5d69b6d5-8188-46a1-a7e5-754e49c59904
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=120671040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.120671040
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3080680762
Short name T39
Test name
Test status
Simulation time 52258289555 ps
CPU time 89.88 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:57:13 PM PDT 24
Peak memory 202032 kb
Host smart-7ef9a980-4ff3-4673-b9e2-e02189b91aa4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3080680762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3080680762
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1608232749
Short name T763
Test name
Test status
Simulation time 95080574 ps
CPU time 8.26 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201888 kb
Host smart-dafdc41e-a909-454c-b811-fb5521a39152
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608232749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1608232749
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.432226343
Short name T469
Test name
Test status
Simulation time 206699531 ps
CPU time 6.17 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:52 PM PDT 24
Peak memory 201884 kb
Host smart-d18463b1-ee5c-4ec0-96bd-a738ee737389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=432226343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.432226343
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.2622702229
Short name T328
Test name
Test status
Simulation time 87697757 ps
CPU time 1.22 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 201892 kb
Host smart-aa245248-73b4-43a2-917b-368b91dac6f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622702229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2622702229
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1002776057
Short name T865
Test name
Test status
Simulation time 2238553295 ps
CPU time 7.62 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 12:55:57 PM PDT 24
Peak memory 202016 kb
Host smart-0a0576ec-3394-4b90-b9ee-2fbe20209c2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002776057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1002776057
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3660428949
Short name T339
Test name
Test status
Simulation time 978785224 ps
CPU time 6.57 seconds
Started Mar 12 12:55:46 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201920 kb
Host smart-e5cf4235-8a3f-469c-ab61-ba2e5af7e8b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3660428949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3660428949
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3503796895
Short name T316
Test name
Test status
Simulation time 11479386 ps
CPU time 1.2 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:55:44 PM PDT 24
Peak memory 201936 kb
Host smart-fedea45b-f544-44ff-a9be-cfc26081260b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503796895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3503796895
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.4151092615
Short name T330
Test name
Test status
Simulation time 92598232 ps
CPU time 8.06 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:47 PM PDT 24
Peak memory 201860 kb
Host smart-9634e15e-db7b-491b-8ab9-1e3876647cd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151092615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4151092615
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3281593693
Short name T900
Test name
Test status
Simulation time 787854982 ps
CPU time 10.13 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201848 kb
Host smart-6d535545-8fde-4196-85c1-8294c33792fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281593693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3281593693
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3319605426
Short name T178
Test name
Test status
Simulation time 6955175969 ps
CPU time 146.75 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:58:09 PM PDT 24
Peak memory 204732 kb
Host smart-9b34f627-16e6-4224-bd93-141f2cd868f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3319605426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.3319605426
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.241073704
Short name T390
Test name
Test status
Simulation time 36272738 ps
CPU time 1.6 seconds
Started Mar 12 12:55:45 PM PDT 24
Finished Mar 12 12:55:47 PM PDT 24
Peak memory 201904 kb
Host smart-ede8cf9c-4644-4882-ad24-a9345d062bee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=241073704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.241073704
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1476488986
Short name T359
Test name
Test status
Simulation time 994283597 ps
CPU time 10.79 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201476 kb
Host smart-6f0b2db9-51e7-4eb2-a1c3-929ebb7f3850
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476488986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1476488986
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1532213902
Short name T170
Test name
Test status
Simulation time 22527255167 ps
CPU time 39.76 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:56:28 PM PDT 24
Peak memory 202020 kb
Host smart-7e5eea63-eefb-4cb2-8800-79bde23827f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1532213902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.1532213902
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.297198516
Short name T807
Test name
Test status
Simulation time 314836169 ps
CPU time 3.43 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 201912 kb
Host smart-64bacfb7-2a87-4809-ad3a-6062afc002c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=297198516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.297198516
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.2547165465
Short name T496
Test name
Test status
Simulation time 645558223 ps
CPU time 6.85 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 12:55:56 PM PDT 24
Peak memory 201892 kb
Host smart-764e2f4e-ec2c-4488-819c-d2680a287e91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2547165465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2547165465
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3060133274
Short name T190
Test name
Test status
Simulation time 137338525 ps
CPU time 2.71 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 201904 kb
Host smart-f7715789-24b4-4a52-8760-c5de811072a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3060133274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3060133274
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1969289400
Short name T696
Test name
Test status
Simulation time 20028684108 ps
CPU time 97.84 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 202024 kb
Host smart-aa304f6a-6d18-4be2-9682-97e7fc10dc9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969289400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1969289400
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3601679266
Short name T466
Test name
Test status
Simulation time 22998740173 ps
CPU time 71.69 seconds
Started Mar 12 12:55:38 PM PDT 24
Finished Mar 12 12:56:50 PM PDT 24
Peak memory 202052 kb
Host smart-443f505a-3e4f-4079-8939-21312cda1d70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3601679266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3601679266
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.703139506
Short name T315
Test name
Test status
Simulation time 99687293 ps
CPU time 3.32 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201896 kb
Host smart-e2f81fd6-6688-405f-a090-adfaf3cc4d13
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703139506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.703139506
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1205175873
Short name T849
Test name
Test status
Simulation time 1374688785 ps
CPU time 9.86 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:55:58 PM PDT 24
Peak memory 201916 kb
Host smart-5cb75178-2e53-4719-9420-82e5e83430c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1205175873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1205175873
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2472751954
Short name T327
Test name
Test status
Simulation time 11188356 ps
CPU time 1.24 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 201860 kb
Host smart-91ae1468-793e-4698-851d-c36dfd478bff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2472751954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2472751954
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1545598783
Short name T40
Test name
Test status
Simulation time 2052966006 ps
CPU time 7.47 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201888 kb
Host smart-0b0af2f5-8063-4e7a-b66b-8e037c6d4af8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545598783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1545598783
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3848289211
Short name T668
Test name
Test status
Simulation time 1231878886 ps
CPU time 7.73 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:55:48 PM PDT 24
Peak memory 201500 kb
Host smart-856f107a-d34c-4468-bcec-6dd20c4b97d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3848289211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3848289211
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3421800002
Short name T498
Test name
Test status
Simulation time 10014880 ps
CPU time 1.08 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:42 PM PDT 24
Peak memory 201868 kb
Host smart-22e5a603-9b44-45d0-a02b-64ff334546e0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421800002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3421800002
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3809086267
Short name T273
Test name
Test status
Simulation time 3272686946 ps
CPU time 47.81 seconds
Started Mar 12 12:55:42 PM PDT 24
Finished Mar 12 12:56:30 PM PDT 24
Peak memory 202060 kb
Host smart-3535d921-9009-44a4-bcfd-92e3c9e74acb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809086267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3809086267
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.742618542
Short name T285
Test name
Test status
Simulation time 1987339377 ps
CPU time 27.99 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:56:08 PM PDT 24
Peak memory 201896 kb
Host smart-2e32c30e-70d8-4b88-811e-49885edd179a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742618542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.742618542
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2022763934
Short name T891
Test name
Test status
Simulation time 232457749 ps
CPU time 26.78 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 203992 kb
Host smart-0755f3b4-c47a-4b9e-8711-fef8757310c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2022763934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2022763934
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.437161711
Short name T210
Test name
Test status
Simulation time 77110860 ps
CPU time 6.47 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201872 kb
Host smart-e689f204-c80b-4104-b50e-10ecdf6493b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=437161711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res
et_error.437161711
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1448844941
Short name T518
Test name
Test status
Simulation time 402545655 ps
CPU time 4.67 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201936 kb
Host smart-cd7af741-06c0-4dba-86b6-a16cf85b6243
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448844941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1448844941
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1686571699
Short name T202
Test name
Test status
Simulation time 18365562 ps
CPU time 2.07 seconds
Started Mar 12 12:55:48 PM PDT 24
Finished Mar 12 12:55:52 PM PDT 24
Peak memory 201848 kb
Host smart-0c8668b1-5c21-4581-94fc-2d9d09052499
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1686571699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1686571699
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.686089711
Short name T844
Test name
Test status
Simulation time 161845442985 ps
CPU time 309.85 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 01:01:01 PM PDT 24
Peak memory 203084 kb
Host smart-cdb45b7e-69da-4cdd-87e9-2cd048e0a2f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=686089711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo
w_rsp.686089711
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3588293791
Short name T244
Test name
Test status
Simulation time 302786664 ps
CPU time 4.41 seconds
Started Mar 12 12:55:55 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 201900 kb
Host smart-c8855ac0-e9b0-4c4d-8afb-7cbac378cc6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3588293791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3588293791
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1802739021
Short name T208
Test name
Test status
Simulation time 53581459 ps
CPU time 4.89 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:57 PM PDT 24
Peak memory 201932 kb
Host smart-32a9a844-d537-4219-a3ea-b411ba93e084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1802739021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1802739021
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2174638414
Short name T640
Test name
Test status
Simulation time 810563289 ps
CPU time 9.04 seconds
Started Mar 12 12:55:40 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201864 kb
Host smart-435aa66a-3bb9-4ca3-91c1-070d2e121aa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2174638414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2174638414
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2306541763
Short name T661
Test name
Test status
Simulation time 14635316124 ps
CPU time 36.82 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:56:34 PM PDT 24
Peak memory 201928 kb
Host smart-3a833570-5233-4e99-85fd-4599d6da18fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306541763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2306541763
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3451321868
Short name T715
Test name
Test status
Simulation time 10659754751 ps
CPU time 37 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:56:34 PM PDT 24
Peak memory 202036 kb
Host smart-7421f26d-6670-414f-969d-97bd3bd28b02
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3451321868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3451321868
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.820984698
Short name T801
Test name
Test status
Simulation time 300590088 ps
CPU time 4.71 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:08 PM PDT 24
Peak memory 201792 kb
Host smart-ec7cf9b5-5938-4397-a98c-b6682531edfe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820984698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.820984698
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.499313846
Short name T377
Test name
Test status
Simulation time 255338878 ps
CPU time 6.01 seconds
Started Mar 12 12:55:56 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201900 kb
Host smart-7d6d19e7-85a3-4a9f-8058-2b46a2a72ef1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=499313846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.499313846
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.818520085
Short name T393
Test name
Test status
Simulation time 92256000 ps
CPU time 1.83 seconds
Started Mar 12 12:55:43 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201908 kb
Host smart-502ec7a9-f31f-40b3-9851-78d976746372
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=818520085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.818520085
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.490013875
Short name T471
Test name
Test status
Simulation time 1941792043 ps
CPU time 8.94 seconds
Started Mar 12 12:55:41 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 201884 kb
Host smart-a8ae51d5-f72a-4b31-8881-4851cdd39c42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=490013875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.490013875
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.595937644
Short name T495
Test name
Test status
Simulation time 1171019446 ps
CPU time 6.88 seconds
Started Mar 12 12:55:44 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 201928 kb
Host smart-99ec8b33-3fcf-476a-af09-f596bda11da7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=595937644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.595937644
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1245263663
Short name T615
Test name
Test status
Simulation time 11080628 ps
CPU time 1.27 seconds
Started Mar 12 12:55:39 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 201868 kb
Host smart-12d3b419-64e3-4762-86f6-f4eba4da0f62
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245263663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1245263663
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2601028251
Short name T195
Test name
Test status
Simulation time 1431837575 ps
CPU time 10.11 seconds
Started Mar 12 12:55:54 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201908 kb
Host smart-1f66aea6-8f8f-4d64-9693-07f4cb0c4e5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2601028251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2601028251
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3385439617
Short name T404
Test name
Test status
Simulation time 15351677453 ps
CPU time 48.06 seconds
Started Mar 12 12:55:48 PM PDT 24
Finished Mar 12 12:56:37 PM PDT 24
Peak memory 202068 kb
Host smart-bf73b735-1d8c-423a-ada7-3f35b767abd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3385439617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3385439617
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2045731994
Short name T652
Test name
Test status
Simulation time 2224940381 ps
CPU time 90.77 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 204076 kb
Host smart-008f0cfa-f9c3-4429-88c3-9a30df1114f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045731994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.2045731994
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4194853595
Short name T356
Test name
Test status
Simulation time 1516544227 ps
CPU time 204.23 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 210020 kb
Host smart-5f1219f3-a916-4d9f-90fc-39cdb4820ed3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4194853595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.4194853595
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.4261321945
Short name T722
Test name
Test status
Simulation time 393840623 ps
CPU time 6.98 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 201908 kb
Host smart-af0a0e70-9e96-44fc-b410-a82dcb3f529b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4261321945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.4261321945
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2188896585
Short name T626
Test name
Test status
Simulation time 1002334285 ps
CPU time 4.77 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:57 PM PDT 24
Peak memory 201928 kb
Host smart-fd2ed7bb-8d8e-4068-9d81-22d3324bc6c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188896585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2188896585
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1713019796
Short name T708
Test name
Test status
Simulation time 21626308060 ps
CPU time 66.82 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 202008 kb
Host smart-44907efc-1393-4874-a54d-30ae448e0545
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1713019796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.1713019796
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3148447322
Short name T883
Test name
Test status
Simulation time 2878997026 ps
CPU time 7.11 seconds
Started Mar 12 12:55:54 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 202016 kb
Host smart-340f6032-5fa8-419b-8418-6bd151503e40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3148447322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3148447322
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.3959771977
Short name T187
Test name
Test status
Simulation time 400051180 ps
CPU time 6.66 seconds
Started Mar 12 12:55:56 PM PDT 24
Finished Mar 12 12:56:03 PM PDT 24
Peak memory 201784 kb
Host smart-57e7811c-7e4f-4d7a-802b-a15ced707033
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3959771977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3959771977
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2938975702
Short name T173
Test name
Test status
Simulation time 10166716503 ps
CPU time 18.03 seconds
Started Mar 12 12:55:47 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 202000 kb
Host smart-0f6d4e26-980a-4e0b-8f19-39db1e76cd33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938975702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2938975702
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1897497165
Short name T82
Test name
Test status
Simulation time 3793933077 ps
CPU time 22.88 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:56:20 PM PDT 24
Peak memory 202004 kb
Host smart-af0d76c1-a0af-415f-8be3-1af1c1179c50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1897497165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1897497165
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1556283987
Short name T405
Test name
Test status
Simulation time 95721248 ps
CPU time 4.24 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 201792 kb
Host smart-6b239ac1-8a18-40ef-b922-7ef134b34407
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556283987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1556283987
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.2289711676
Short name T230
Test name
Test status
Simulation time 27450303 ps
CPU time 2.53 seconds
Started Mar 12 12:55:48 PM PDT 24
Finished Mar 12 12:55:52 PM PDT 24
Peak memory 201892 kb
Host smart-59b9aa06-9a2d-4f59-ade9-59fb77ea7f4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2289711676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2289711676
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.3208054554
Short name T670
Test name
Test status
Simulation time 10519091 ps
CPU time 0.98 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201824 kb
Host smart-d9a6de38-4f39-433f-8756-e53f339dc68a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3208054554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3208054554
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3667445507
Short name T88
Test name
Test status
Simulation time 2817465309 ps
CPU time 9.07 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:56:01 PM PDT 24
Peak memory 201972 kb
Host smart-9cc6b2b9-55d6-4410-b8b4-f748bb728ace
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667445507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3667445507
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.768440546
Short name T647
Test name
Test status
Simulation time 1029670125 ps
CPU time 8.39 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 201944 kb
Host smart-c0bdce8e-659e-4fee-8832-8614b8b19ff8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=768440546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.768440546
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3272346080
Short name T787
Test name
Test status
Simulation time 8603709 ps
CPU time 1.16 seconds
Started Mar 12 12:55:50 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201816 kb
Host smart-898bddd8-2373-4dd3-96e7-bdef555ecaf8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272346080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3272346080
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.832328951
Short name T526
Test name
Test status
Simulation time 229405060 ps
CPU time 30.32 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:56:22 PM PDT 24
Peak memory 203304 kb
Host smart-d2d43cc2-cc18-4bb3-97b2-89898fee6daf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=832328951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.832328951
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3595720531
Short name T627
Test name
Test status
Simulation time 227185684 ps
CPU time 13.98 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 201888 kb
Host smart-00e0ed84-b23d-4580-b220-342fcd80f174
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3595720531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3595720531
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2911870631
Short name T226
Test name
Test status
Simulation time 2367751259 ps
CPU time 64.49 seconds
Started Mar 12 12:55:48 PM PDT 24
Finished Mar 12 12:56:54 PM PDT 24
Peak memory 204108 kb
Host smart-74596e92-c9c4-4052-b3c6-9e2689dbe3f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2911870631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.2911870631
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2200763077
Short name T492
Test name
Test status
Simulation time 17945912 ps
CPU time 3.29 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 201888 kb
Host smart-91173893-b496-41b7-8163-7fe547213e3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2200763077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.2200763077
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.862632502
Short name T33
Test name
Test status
Simulation time 831850282 ps
CPU time 6.72 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:55:58 PM PDT 24
Peak memory 201656 kb
Host smart-0813bb73-e1bd-418d-b828-072175600d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862632502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.862632502
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3522062410
Short name T464
Test name
Test status
Simulation time 1043862204 ps
CPU time 16.82 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:56:09 PM PDT 24
Peak memory 201932 kb
Host smart-b8d0251c-3ab6-4518-baf9-02a07033e90f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3522062410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3522062410
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1370390113
Short name T174
Test name
Test status
Simulation time 226039157 ps
CPU time 3.99 seconds
Started Mar 12 12:56:37 PM PDT 24
Finished Mar 12 12:56:42 PM PDT 24
Peak memory 201888 kb
Host smart-03b49592-e35e-4ef6-8ac9-81ee3f378d0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370390113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1370390113
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2148675620
Short name T775
Test name
Test status
Simulation time 1579609293 ps
CPU time 6.85 seconds
Started Mar 12 12:55:55 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201912 kb
Host smart-0a4ed9ac-8940-4fe0-9b23-112abe21783c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148675620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2148675620
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.4189484431
Short name T31
Test name
Test status
Simulation time 1838104182 ps
CPU time 13.76 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 201860 kb
Host smart-0f38959d-7b28-4d18-b597-6b6370893bf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4189484431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4189484431
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.682727878
Short name T760
Test name
Test status
Simulation time 179445447620 ps
CPU time 200.86 seconds
Started Mar 12 12:55:56 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 202004 kb
Host smart-176279f8-e490-49bc-9339-a56d4690c7ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=682727878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.682727878
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2614753391
Short name T634
Test name
Test status
Simulation time 46761728659 ps
CPU time 74.13 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:57:07 PM PDT 24
Peak memory 202040 kb
Host smart-2dcfd2f0-045f-400b-b7bd-5c34dcb84b69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2614753391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2614753391
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2974742112
Short name T617
Test name
Test status
Simulation time 61065820 ps
CPU time 5.41 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:58 PM PDT 24
Peak memory 200596 kb
Host smart-83308a3c-afa1-4d76-ad97-56eb094646fd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974742112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2974742112
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.3841194084
Short name T822
Test name
Test status
Simulation time 450622667 ps
CPU time 2.96 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 201848 kb
Host smart-b211a44e-96f4-496a-b392-59953980f604
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3841194084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3841194084
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.3038836705
Short name T509
Test name
Test status
Simulation time 59944145 ps
CPU time 1.43 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201872 kb
Host smart-63181f72-e748-455f-be4d-e9492bd315da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3038836705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3038836705
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1618841574
Short name T701
Test name
Test status
Simulation time 1743124448 ps
CPU time 6.17 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:55:58 PM PDT 24
Peak memory 201508 kb
Host smart-243a8eb0-236b-487b-99b9-16424080759d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618841574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1618841574
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.698945249
Short name T725
Test name
Test status
Simulation time 1775757236 ps
CPU time 12.17 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201840 kb
Host smart-18eab105-e8b3-421e-8a61-4de3ba1d358f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=698945249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.698945249
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1811647349
Short name T583
Test name
Test status
Simulation time 9261222 ps
CPU time 1.34 seconds
Started Mar 12 12:55:49 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201884 kb
Host smart-83325945-73b8-415c-a63d-fca2922df21e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811647349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1811647349
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3284447275
Short name T768
Test name
Test status
Simulation time 422781499 ps
CPU time 40.65 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:44 PM PDT 24
Peak memory 202816 kb
Host smart-87a73f88-9e2c-4453-ae26-d4b6b6f89638
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3284447275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3284447275
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2665120445
Short name T462
Test name
Test status
Simulation time 250499232 ps
CPU time 1.54 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201928 kb
Host smart-d4e6e13e-4777-4e84-9339-bce92e454da9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2665120445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2665120445
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2420229973
Short name T666
Test name
Test status
Simulation time 917105400 ps
CPU time 114.9 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:57:52 PM PDT 24
Peak memory 205276 kb
Host smart-d69003e9-7e17-4d10-800c-6f424ded08d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2420229973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.2420229973
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.4286707980
Short name T164
Test name
Test status
Simulation time 4184853947 ps
CPU time 77.66 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:57:10 PM PDT 24
Peak memory 203580 kb
Host smart-cb334424-3eb3-477c-8a45-8cf58aec0151
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4286707980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.4286707980
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3855873308
Short name T447
Test name
Test status
Simulation time 34035798 ps
CPU time 3.04 seconds
Started Mar 12 12:55:51 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 201836 kb
Host smart-77429812-6a6a-4949-ad6e-5dbc2a44c67d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855873308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3855873308
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.4144255626
Short name T86
Test name
Test status
Simulation time 5693831659 ps
CPU time 18.09 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:17 PM PDT 24
Peak memory 202056 kb
Host smart-79bd86f6-4d69-4a40-9fe5-4ae6db696fd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4144255626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.4144255626
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.717696234
Short name T268
Test name
Test status
Simulation time 57819148235 ps
CPU time 315.9 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 01:01:16 PM PDT 24
Peak memory 204068 kb
Host smart-9fec304f-22e6-44d1-8828-5284be269e72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=717696234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo
w_rsp.717696234
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.882779420
Short name T613
Test name
Test status
Simulation time 148227421 ps
CPU time 3.12 seconds
Started Mar 12 12:56:01 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201876 kb
Host smart-9f401788-1f84-42cf-a144-63a743641978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=882779420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.882779420
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.1616460585
Short name T741
Test name
Test status
Simulation time 956916875 ps
CPU time 12.23 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 201884 kb
Host smart-537c6644-369a-41e7-a64f-af060aecdd46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1616460585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1616460585
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.1529416486
Short name T325
Test name
Test status
Simulation time 38846017 ps
CPU time 2.61 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 201836 kb
Host smart-72b40393-ffe3-42a8-a62c-a309c0a54956
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529416486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1529416486
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.4100225258
Short name T240
Test name
Test status
Simulation time 129940366776 ps
CPU time 102.58 seconds
Started Mar 12 12:56:02 PM PDT 24
Finished Mar 12 12:57:45 PM PDT 24
Peak memory 202028 kb
Host smart-b53bf26d-e865-441e-af98-ef9ac00cd81a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100225258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4100225258
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3928700330
Short name T711
Test name
Test status
Simulation time 23209066661 ps
CPU time 110.79 seconds
Started Mar 12 12:56:01 PM PDT 24
Finished Mar 12 12:57:52 PM PDT 24
Peak memory 202048 kb
Host smart-8466438d-7ec7-4bf2-abff-a954e989a493
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3928700330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3928700330
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2996176096
Short name T756
Test name
Test status
Simulation time 52173378 ps
CPU time 3.26 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:03 PM PDT 24
Peak memory 201876 kb
Host smart-fd1bf9a6-cab4-46b5-bf0d-8bde546b7aed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996176096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2996176096
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.2787990614
Short name T814
Test name
Test status
Simulation time 17876500 ps
CPU time 1.96 seconds
Started Mar 12 12:56:06 PM PDT 24
Finished Mar 12 12:56:09 PM PDT 24
Peak memory 201952 kb
Host smart-05310bf7-04a7-461a-8b0e-c77a7ad06e76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2787990614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2787990614
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.71900107
Short name T401
Test name
Test status
Simulation time 89612175 ps
CPU time 1.42 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 201848 kb
Host smart-b7b111a9-0179-4c23-b085-03bd7d3ca9eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71900107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.71900107
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1200701763
Short name T811
Test name
Test status
Simulation time 3040485259 ps
CPU time 10.05 seconds
Started Mar 12 12:55:58 PM PDT 24
Finished Mar 12 12:56:09 PM PDT 24
Peak memory 202044 kb
Host smart-a5a22a83-e92f-4ca4-b3d4-5b3c135b1425
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200701763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1200701763
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1505641264
Short name T157
Test name
Test status
Simulation time 2552915657 ps
CPU time 8.56 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:09 PM PDT 24
Peak memory 202032 kb
Host smart-5c68cf58-2542-4eed-8b95-8d2646273486
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1505641264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1505641264
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3426316871
Short name T314
Test name
Test status
Simulation time 8725366 ps
CPU time 1.12 seconds
Started Mar 12 12:55:52 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201908 kb
Host smart-dd25995b-bfcb-4225-9a4d-48b1797795ab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426316871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3426316871
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1619786018
Short name T366
Test name
Test status
Simulation time 21502315 ps
CPU time 2 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:01 PM PDT 24
Peak memory 201884 kb
Host smart-7437bcc9-07f1-42a5-9e25-f3538a43caa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1619786018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1619786018
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1504447287
Short name T169
Test name
Test status
Simulation time 682788963 ps
CPU time 25.64 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:25 PM PDT 24
Peak memory 201928 kb
Host smart-4a093d62-cb49-4c30-86a8-fdf8e9756ad0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1504447287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1504447287
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.762602691
Short name T858
Test name
Test status
Simulation time 441681300 ps
CPU time 58.81 seconds
Started Mar 12 12:56:02 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 204144 kb
Host smart-172f4a34-1887-46c3-ae3e-08ccb3e1d26e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=762602691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.762602691
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2241724671
Short name T415
Test name
Test status
Simulation time 521738430 ps
CPU time 66.1 seconds
Started Mar 12 12:56:04 PM PDT 24
Finished Mar 12 12:57:10 PM PDT 24
Peak memory 203512 kb
Host smart-ad0098b0-020f-4b9b-a293-335e93b6ac08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2241724671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.2241724671
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2563849014
Short name T548
Test name
Test status
Simulation time 282929614 ps
CPU time 5.97 seconds
Started Mar 12 12:56:01 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 201912 kb
Host smart-158af43b-2ac3-40e0-8682-033f829cf2b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2563849014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2563849014
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.214672202
Short name T635
Test name
Test status
Simulation time 1468253780 ps
CPU time 17.6 seconds
Started Mar 12 12:55:57 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 201788 kb
Host smart-1fdf484c-cfbb-4c26-831a-26d36c46b50d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=214672202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.214672202
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3549942192
Short name T145
Test name
Test status
Simulation time 323686789 ps
CPU time 4.85 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:05 PM PDT 24
Peak memory 201848 kb
Host smart-39bda431-9fb7-499a-aaaa-c363b4e0e694
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549942192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3549942192
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.1291090335
Short name T838
Test name
Test status
Simulation time 62606327 ps
CPU time 6.06 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:05 PM PDT 24
Peak memory 201932 kb
Host smart-2871a59a-95bb-483d-8642-3fdac6285a03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291090335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1291090335
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.1816636009
Short name T318
Test name
Test status
Simulation time 401560380 ps
CPU time 7 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 201908 kb
Host smart-9b1bc11f-fe89-45a4-802f-45a166d220c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1816636009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1816636009
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.482784854
Short name T448
Test name
Test status
Simulation time 49792752717 ps
CPU time 88.55 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 202056 kb
Host smart-47839575-b167-419a-b304-50a635647b39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=482784854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.482784854
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2089570015
Short name T100
Test name
Test status
Simulation time 12213328519 ps
CPU time 66.22 seconds
Started Mar 12 12:55:58 PM PDT 24
Finished Mar 12 12:57:05 PM PDT 24
Peak memory 202064 kb
Host smart-eb11b4f3-56f6-40cc-8b95-44c212b20d46
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2089570015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2089570015
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.82934113
Short name T134
Test name
Test status
Simulation time 23257465 ps
CPU time 2.27 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201924 kb
Host smart-353dd1f4-ae43-4838-ba89-00b5e5f009a8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82934113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.82934113
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.2805196392
Short name T528
Test name
Test status
Simulation time 45547944 ps
CPU time 4.38 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201836 kb
Host smart-8584584b-7ddc-4325-a1d0-e92449683251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2805196392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2805196392
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.457768077
Short name T149
Test name
Test status
Simulation time 170697121 ps
CPU time 1.65 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201820 kb
Host smart-bf8f6287-e5b0-4ed9-b804-b0ad2d87693f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457768077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.457768077
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.639952951
Short name T894
Test name
Test status
Simulation time 4232304144 ps
CPU time 11.77 seconds
Started Mar 12 12:56:04 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 202016 kb
Host smart-557bce27-f327-4d9e-b677-c70dc3cd4904
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=639952951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.639952951
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4292654472
Short name T642
Test name
Test status
Simulation time 3732445053 ps
CPU time 7.17 seconds
Started Mar 12 12:56:07 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 202072 kb
Host smart-7176b544-66b4-44c0-aa2a-e12960f1dbb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4292654472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4292654472
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4117830500
Short name T52
Test name
Test status
Simulation time 39236132 ps
CPU time 1.32 seconds
Started Mar 12 12:56:02 PM PDT 24
Finished Mar 12 12:56:03 PM PDT 24
Peak memory 201872 kb
Host smart-c8a0b769-e6f1-48f5-9a49-25bb2ffc1388
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117830500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4117830500
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.704912803
Short name T463
Test name
Test status
Simulation time 535392831 ps
CPU time 27.8 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:26 PM PDT 24
Peak memory 203124 kb
Host smart-c1db4ce3-f4a6-4cb4-a160-7a9585520363
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=704912803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.704912803
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.900378300
Short name T220
Test name
Test status
Simulation time 1038354861 ps
CPU time 26.61 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:26 PM PDT 24
Peak memory 201892 kb
Host smart-a31fd96b-c8b0-4ea9-a73f-ea74c5835c86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=900378300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.900378300
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2950180089
Short name T298
Test name
Test status
Simulation time 48369696 ps
CPU time 8.58 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:09 PM PDT 24
Peak memory 201900 kb
Host smart-0226289c-81e0-4ae2-918d-7abf46c94126
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2950180089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.2950180089
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2687060447
Short name T165
Test name
Test status
Simulation time 856010677 ps
CPU time 7.61 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:08 PM PDT 24
Peak memory 201892 kb
Host smart-26d6e695-f269-4319-a89c-d3939dcca26a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2687060447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2687060447
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3990794600
Short name T117
Test name
Test status
Simulation time 432817916 ps
CPU time 10.15 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 201888 kb
Host smart-b05de036-d414-43ba-b9a5-3360dbdcf0c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3990794600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3990794600
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.327700385
Short name T723
Test name
Test status
Simulation time 61622406 ps
CPU time 5.07 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 201876 kb
Host smart-48fbd577-0e94-4931-b460-638d0606f4db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=327700385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.327700385
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.552538256
Short name T868
Test name
Test status
Simulation time 475143880 ps
CPU time 4.17 seconds
Started Mar 12 12:56:06 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 201944 kb
Host smart-27d19877-f94b-40a7-87fc-18b6e8365d63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=552538256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.552538256
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.402261962
Short name T312
Test name
Test status
Simulation time 41282250 ps
CPU time 2.55 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201860 kb
Host smart-07f1da90-206b-452c-9037-bb745c4d9ed8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=402261962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.402261962
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.113805324
Short name T123
Test name
Test status
Simulation time 51711990279 ps
CPU time 91.11 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 202028 kb
Host smart-68ef6f81-2c6e-4773-a06e-52a601a1ccb4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=113805324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.113805324
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.922823491
Short name T497
Test name
Test status
Simulation time 10018771032 ps
CPU time 67.99 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:57:11 PM PDT 24
Peak memory 202056 kb
Host smart-9e3301eb-b564-4ffc-aee2-7c6c785a41ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=922823491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.922823491
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.434051145
Short name T480
Test name
Test status
Simulation time 128030159 ps
CPU time 5.63 seconds
Started Mar 12 12:56:06 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 201956 kb
Host smart-611363fd-d7ff-48dc-a851-165e0b2bffbb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434051145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.434051145
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.4011924520
Short name T540
Test name
Test status
Simulation time 38248699 ps
CPU time 4.32 seconds
Started Mar 12 12:55:59 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201956 kb
Host smart-c93fd5e3-76e0-446c-b0ae-d928d9bd8ed0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4011924520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4011924520
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.4118175265
Short name T172
Test name
Test status
Simulation time 17051878 ps
CPU time 1.05 seconds
Started Mar 12 12:56:00 PM PDT 24
Finished Mar 12 12:56:01 PM PDT 24
Peak memory 201796 kb
Host smart-5a6d6052-5308-4606-81b9-1567a37ba1e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4118175265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4118175265
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1989478298
Short name T336
Test name
Test status
Simulation time 1665201784 ps
CPU time 8.64 seconds
Started Mar 12 12:56:03 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 201800 kb
Host smart-1809a498-0745-4b99-b734-3da7fb59073c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989478298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1989478298
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2749718009
Short name T576
Test name
Test status
Simulation time 2604443175 ps
CPU time 8.06 seconds
Started Mar 12 12:56:02 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 202032 kb
Host smart-2649c349-ceff-4dae-9b06-01e6868220d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2749718009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2749718009
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2963845955
Short name T748
Test name
Test status
Simulation time 15740880 ps
CPU time 1.02 seconds
Started Mar 12 12:56:01 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 201944 kb
Host smart-a949378f-9dce-46a0-b61f-3603acec7573
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963845955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2963845955
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1754818135
Short name T524
Test name
Test status
Simulation time 1778225728 ps
CPU time 7.53 seconds
Started Mar 12 12:56:12 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 201868 kb
Host smart-faf6e9ce-4ce5-4079-8b82-ff3caac88e51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1754818135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1754818135
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3059350788
Short name T614
Test name
Test status
Simulation time 146428368 ps
CPU time 10.31 seconds
Started Mar 12 12:56:12 PM PDT 24
Finished Mar 12 12:56:23 PM PDT 24
Peak memory 201928 kb
Host smart-332b5d15-4603-475d-a5b3-980d8044366c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3059350788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3059350788
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1553862507
Short name T713
Test name
Test status
Simulation time 369443517 ps
CPU time 16.99 seconds
Started Mar 12 12:56:12 PM PDT 24
Finished Mar 12 12:56:30 PM PDT 24
Peak memory 203860 kb
Host smart-b3ad41c0-3e8b-4f6d-9020-b11e61b00fa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1553862507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1553862507
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2730157222
Short name T677
Test name
Test status
Simulation time 10445068041 ps
CPU time 149.32 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:58:41 PM PDT 24
Peak memory 206976 kb
Host smart-ac8025fb-fcf9-4fd7-83b2-e4deea12f231
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2730157222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.2730157222
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.600955928
Short name T881
Test name
Test status
Simulation time 81424250 ps
CPU time 2.31 seconds
Started Mar 12 12:56:06 PM PDT 24
Finished Mar 12 12:56:08 PM PDT 24
Peak memory 201956 kb
Host smart-9bd6153c-0624-4318-98d3-c59756c2b6e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=600955928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.600955928
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1376227309
Short name T710
Test name
Test status
Simulation time 916292453 ps
CPU time 14.48 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 201820 kb
Host smart-7afe7e08-d0d9-406f-bff5-686a98e8fd43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1376227309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1376227309
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2401953699
Short name T270
Test name
Test status
Simulation time 14761844884 ps
CPU time 68.06 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 202056 kb
Host smart-8a8bbd9e-9775-485e-95fe-510344fd6a2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2401953699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.2401953699
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1565163399
Short name T364
Test name
Test status
Simulation time 22263534 ps
CPU time 2.51 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201792 kb
Host smart-30c437d1-5199-4a38-a9d5-b0d1da8162c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1565163399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1565163399
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.230491358
Short name T246
Test name
Test status
Simulation time 1254252118 ps
CPU time 11.83 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201872 kb
Host smart-9111f4ac-e83b-4d52-9364-f2635aa22881
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=230491358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.230491358
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.2828672679
Short name T147
Test name
Test status
Simulation time 1548041331 ps
CPU time 7.62 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201844 kb
Host smart-f3af270f-2f0f-4e05-a3bc-493d2f47be29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2828672679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2828672679
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3983158992
Short name T781
Test name
Test status
Simulation time 9537160729 ps
CPU time 38.83 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 201912 kb
Host smart-1f37a6c6-704f-4819-9a7f-ef64087211a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983158992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3983158992
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4085306622
Short name T319
Test name
Test status
Simulation time 13397868292 ps
CPU time 89.35 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:56:20 PM PDT 24
Peak memory 202056 kb
Host smart-d06defd7-67b7-4112-a07b-4996918a70b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4085306622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4085306622
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2068688295
Short name T549
Test name
Test status
Simulation time 86576245 ps
CPU time 4.28 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:51 PM PDT 24
Peak memory 201840 kb
Host smart-b92f5ca3-808f-4209-9544-bb284919aca5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068688295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2068688295
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.831758089
Short name T323
Test name
Test status
Simulation time 1387015744 ps
CPU time 6.2 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201920 kb
Host smart-12d08cef-24f3-4653-ae2c-ff5b0bfaa366
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=831758089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.831758089
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.218528317
Short name T458
Test name
Test status
Simulation time 104215275 ps
CPU time 1.41 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 201780 kb
Host smart-652b7ed3-cd2d-427b-b4df-4f37445162ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=218528317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.218528317
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.306755908
Short name T286
Test name
Test status
Simulation time 4192014603 ps
CPU time 6.32 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 202024 kb
Host smart-893d1b0c-d27d-4d5b-8e14-d8c30d4c2efa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=306755908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.306755908
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2632873334
Short name T294
Test name
Test status
Simulation time 1267342541 ps
CPU time 9.22 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201892 kb
Host smart-25db3105-88ab-4f76-9e61-4eb3a514957a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2632873334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2632873334
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2989502512
Short name T310
Test name
Test status
Simulation time 10282308 ps
CPU time 1.34 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:54 PM PDT 24
Peak memory 201916 kb
Host smart-04f28c69-16ea-4025-bfd6-d308f9067c4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989502512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2989502512
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2987827390
Short name T451
Test name
Test status
Simulation time 230069297 ps
CPU time 26.5 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:55:16 PM PDT 24
Peak memory 204480 kb
Host smart-66039c24-d6d5-4ce2-9ed7-35b45f186b00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2987827390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2987827390
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3512044501
Short name T570
Test name
Test status
Simulation time 1636452916 ps
CPU time 28.83 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:55:17 PM PDT 24
Peak memory 201952 kb
Host smart-01347e0f-2643-4c79-8318-064b7735710a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3512044501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3512044501
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2247639671
Short name T130
Test name
Test status
Simulation time 674417557 ps
CPU time 71.95 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:56:05 PM PDT 24
Peak memory 204296 kb
Host smart-8de4812c-4237-4029-8dad-8e1ac5a8262e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2247639671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.2247639671
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3785226852
Short name T276
Test name
Test status
Simulation time 605914820 ps
CPU time 78.94 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 205480 kb
Host smart-25c0b11e-dce5-41ec-a65d-8b48e2acb22c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3785226852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3785226852
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3016160320
Short name T460
Test name
Test status
Simulation time 84006239 ps
CPU time 5.17 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 201896 kb
Host smart-a80141f7-39dd-48c7-a0b7-077849b8a644
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3016160320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3016160320
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2380573924
Short name T494
Test name
Test status
Simulation time 667933000 ps
CPU time 14.09 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:26 PM PDT 24
Peak memory 201908 kb
Host smart-753deb38-c3f1-480e-b936-a187598a9975
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2380573924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2380573924
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3236419127
Short name T660
Test name
Test status
Simulation time 9168432668 ps
CPU time 69.74 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 202044 kb
Host smart-122a645e-12a6-4d0a-bb4d-63f4a33aa3df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3236419127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3236419127
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2590320866
Short name T353
Test name
Test status
Simulation time 394418773 ps
CPU time 5.82 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 201860 kb
Host smart-e1e4eee3-7459-434f-b564-8ef7b4748bfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590320866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2590320866
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.877405285
Short name T605
Test name
Test status
Simulation time 728424175 ps
CPU time 10.67 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 201924 kb
Host smart-7379d2bf-4ce7-4650-9adb-2f2c0c5bc218
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=877405285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.877405285
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.428111348
Short name T581
Test name
Test status
Simulation time 199944012 ps
CPU time 3.49 seconds
Started Mar 12 12:56:14 PM PDT 24
Finished Mar 12 12:56:17 PM PDT 24
Peak memory 201680 kb
Host smart-4053f96a-d05c-4aa2-969d-4abc727243e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=428111348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.428111348
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.4222985989
Short name T880
Test name
Test status
Simulation time 197462744835 ps
CPU time 135.7 seconds
Started Mar 12 12:56:12 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 201956 kb
Host smart-06426b21-e05f-4b71-974f-1b6fa51f294e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222985989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4222985989
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3463007165
Short name T194
Test name
Test status
Simulation time 33186275709 ps
CPU time 222.54 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 201920 kb
Host smart-944b95a5-589a-4f0e-b5a3-72f1de902096
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3463007165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3463007165
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2427787752
Short name T530
Test name
Test status
Simulation time 20082437 ps
CPU time 2.44 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 201900 kb
Host smart-99be7bd5-2373-4bb5-aee0-698f09447421
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427787752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2427787752
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3729716278
Short name T293
Test name
Test status
Simulation time 848647764 ps
CPU time 9.05 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:18 PM PDT 24
Peak memory 201840 kb
Host smart-f1ad1273-a765-4851-930a-85a21a289be7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3729716278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3729716278
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.1659578364
Short name T465
Test name
Test status
Simulation time 72847919 ps
CPU time 1.5 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:13 PM PDT 24
Peak memory 201872 kb
Host smart-3e0ea878-127a-4822-9374-47c3d7591849
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1659578364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1659578364
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.826065653
Short name T340
Test name
Test status
Simulation time 7824418758 ps
CPU time 8.66 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:20 PM PDT 24
Peak memory 202072 kb
Host smart-af032dea-6163-45f0-930b-df33405baa57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=826065653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.826065653
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2107886175
Short name T4
Test name
Test status
Simulation time 4130566639 ps
CPU time 13.02 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:22 PM PDT 24
Peak memory 202036 kb
Host smart-10fd6e8f-804d-468f-bc57-547b456d44e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2107886175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2107886175
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1578793927
Short name T461
Test name
Test status
Simulation time 9049564 ps
CPU time 1.22 seconds
Started Mar 12 12:56:14 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 201884 kb
Host smart-b728e967-ec74-4fc8-9693-c464d9907412
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578793927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1578793927
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.30750112
Short name T828
Test name
Test status
Simulation time 625294737 ps
CPU time 5.62 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:15 PM PDT 24
Peak memory 201856 kb
Host smart-d7a83f9a-d3b3-47a4-9e8c-efbfc1ab24fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30750112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.30750112
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3545876786
Short name T515
Test name
Test status
Simulation time 991296182 ps
CPU time 13.43 seconds
Started Mar 12 12:56:14 PM PDT 24
Finished Mar 12 12:56:27 PM PDT 24
Peak memory 201724 kb
Host smart-65ea0840-12aa-44bf-af6e-b632af382d69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545876786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3545876786
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1668539337
Short name T884
Test name
Test status
Simulation time 920798883 ps
CPU time 61.32 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:57:12 PM PDT 24
Peak memory 203940 kb
Host smart-8ef6f45d-c96f-4c69-9e05-4721c4e744e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1668539337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1668539337
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1363481804
Short name T84
Test name
Test status
Simulation time 423237196 ps
CPU time 6.48 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:15 PM PDT 24
Peak memory 201788 kb
Host smart-add2fce0-27d1-4773-9cb5-c79af594e2ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1363481804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1363481804
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2105670033
Short name T154
Test name
Test status
Simulation time 74163518 ps
CPU time 7.21 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:18 PM PDT 24
Peak memory 201944 kb
Host smart-830eee1e-67ec-43f7-baaf-5abef21178aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2105670033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2105670033
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2217804411
Short name T255
Test name
Test status
Simulation time 69498463204 ps
CPU time 257.07 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 01:00:28 PM PDT 24
Peak memory 203256 kb
Host smart-df5d9e04-e242-4c27-b476-5de7bae45b1b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2217804411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.2217804411
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.4185421780
Short name T384
Test name
Test status
Simulation time 67432882 ps
CPU time 3.18 seconds
Started Mar 12 12:56:08 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 201924 kb
Host smart-c3773be5-4a07-4364-99bd-de441dd98ac9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4185421780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4185421780
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1049161434
Short name T231
Test name
Test status
Simulation time 365304785 ps
CPU time 6.34 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:17 PM PDT 24
Peak memory 201932 kb
Host smart-d4968da2-27bf-4890-b889-3c3d46d09b2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1049161434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1049161434
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.757818254
Short name T175
Test name
Test status
Simulation time 2293513597 ps
CPU time 5.39 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:15 PM PDT 24
Peak memory 201980 kb
Host smart-45daf217-5ed5-47ab-a819-0a5160f2548a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=757818254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.757818254
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1711630120
Short name T193
Test name
Test status
Simulation time 24166439405 ps
CPU time 61.83 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:57:12 PM PDT 24
Peak memory 201980 kb
Host smart-98cf5e00-5cb7-4efe-883c-8fb79468201a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711630120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1711630120
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2653140506
Short name T122
Test name
Test status
Simulation time 32628786594 ps
CPU time 80.24 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201976 kb
Host smart-5af71c9c-3315-498f-accb-da9592faa9d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2653140506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2653140506
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.452925354
Short name T394
Test name
Test status
Simulation time 266363701 ps
CPU time 4.16 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 201924 kb
Host smart-a1dc79a7-cc1e-4a2a-92b9-39a95d7a9a7f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452925354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.452925354
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.586319512
Short name T361
Test name
Test status
Simulation time 466207126 ps
CPU time 3.17 seconds
Started Mar 12 12:56:14 PM PDT 24
Finished Mar 12 12:56:18 PM PDT 24
Peak memory 201888 kb
Host smart-f3c4c39d-2b6b-4979-aaed-277b828b60eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=586319512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.586319512
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.2053769114
Short name T628
Test name
Test status
Simulation time 23216685 ps
CPU time 1.06 seconds
Started Mar 12 12:56:08 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 201840 kb
Host smart-bc4f0ea5-c396-43c7-a101-b0045d0ed9d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2053769114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2053769114
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1812641874
Short name T534
Test name
Test status
Simulation time 17885285130 ps
CPU time 9.69 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 202036 kb
Host smart-d5729c77-8fcf-4a77-8ddc-747fd9b76e7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812641874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1812641874
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1935931576
Short name T371
Test name
Test status
Simulation time 962358782 ps
CPU time 7.43 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 201936 kb
Host smart-a5b0ecde-4c34-4046-9d3e-b32246482056
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1935931576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1935931576
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3599196022
Short name T303
Test name
Test status
Simulation time 9430985 ps
CPU time 1.13 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 201896 kb
Host smart-b93a9021-7825-4941-a459-01ecd05752b2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599196022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3599196022
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2936088017
Short name T656
Test name
Test status
Simulation time 551895617 ps
CPU time 46.52 seconds
Started Mar 12 12:56:13 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 201736 kb
Host smart-6b5e6038-486e-46d0-86cf-47e22516446a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2936088017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2936088017
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2404484045
Short name T2
Test name
Test status
Simulation time 2038556442 ps
CPU time 14.17 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:25 PM PDT 24
Peak memory 201948 kb
Host smart-b250b883-558a-411b-9bae-d5df6a19e38a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2404484045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2404484045
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1700487028
Short name T675
Test name
Test status
Simulation time 668443660 ps
CPU time 51.88 seconds
Started Mar 12 12:56:15 PM PDT 24
Finished Mar 12 12:57:08 PM PDT 24
Peak memory 204260 kb
Host smart-92f12227-aedc-46dc-86f4-f7ecb9f1930b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1700487028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1700487028
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4012553045
Short name T624
Test name
Test status
Simulation time 637204730 ps
CPU time 3.17 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 201900 kb
Host smart-af261aab-4515-44a6-b611-0ed6c03de688
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4012553045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4012553045
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1425224503
Short name T612
Test name
Test status
Simulation time 1089294213 ps
CPU time 5.87 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 201828 kb
Host smart-53ca5de4-b036-4ec3-b982-c474137d46f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1425224503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1425224503
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.444718332
Short name T161
Test name
Test status
Simulation time 323890044 ps
CPU time 5.13 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 201944 kb
Host smart-f0ab789b-42e5-4056-87b5-be552a91b620
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=444718332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.444718332
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.2034984954
Short name T416
Test name
Test status
Simulation time 70896117 ps
CPU time 5.15 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201944 kb
Host smart-4ea31f60-d7d6-4d8a-88f0-7dfb204fd9df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2034984954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2034984954
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2732277581
Short name T645
Test name
Test status
Simulation time 322765577 ps
CPU time 4.82 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201904 kb
Host smart-049c5203-fbd8-44e5-b502-e4dd4b7f8e30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2732277581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2732277581
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.150821615
Short name T821
Test name
Test status
Simulation time 8229071920 ps
CPU time 33.18 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201848 kb
Host smart-f61a070d-7bdb-4922-9624-e41e6abc49c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=150821615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.150821615
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1195897194
Short name T852
Test name
Test status
Simulation time 9322551032 ps
CPU time 50.78 seconds
Started Mar 12 12:56:52 PM PDT 24
Finished Mar 12 12:57:43 PM PDT 24
Peak memory 202080 kb
Host smart-e49ed1de-1fd7-4bc0-a47c-b15022dc05a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1195897194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1195897194
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1791554305
Short name T854
Test name
Test status
Simulation time 52141320 ps
CPU time 4.8 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 201932 kb
Host smart-05b14bc1-02ea-4a91-8fe2-b7d2f6b2aece
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791554305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1791554305
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1334272264
Short name T311
Test name
Test status
Simulation time 47274122 ps
CPU time 3.44 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 201908 kb
Host smart-b8e0e082-2d01-4fbc-9a63-fe4fce67e95d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1334272264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1334272264
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1573440286
Short name T618
Test name
Test status
Simulation time 16514051 ps
CPU time 1.12 seconds
Started Mar 12 12:56:11 PM PDT 24
Finished Mar 12 12:56:12 PM PDT 24
Peak memory 201896 kb
Host smart-d47b4401-456b-44a8-8d04-bfa27faabe8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1573440286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1573440286
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4015655827
Short name T216
Test name
Test status
Simulation time 14662855373 ps
CPU time 10.12 seconds
Started Mar 12 12:56:13 PM PDT 24
Finished Mar 12 12:56:23 PM PDT 24
Peak memory 201956 kb
Host smart-22362685-1673-4b03-8e37-7459298ff9e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015655827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4015655827
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3760799905
Short name T431
Test name
Test status
Simulation time 1839234031 ps
CPU time 9.73 seconds
Started Mar 12 12:56:09 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 201904 kb
Host smart-7b04312f-0452-4ded-b9c8-3deaea17d45d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3760799905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3760799905
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3359465768
Short name T501
Test name
Test status
Simulation time 10149994 ps
CPU time 1.13 seconds
Started Mar 12 12:56:10 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 201900 kb
Host smart-88970b4c-c82c-4b9c-8eb4-df5abb29b8a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359465768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3359465768
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1663625823
Short name T688
Test name
Test status
Simulation time 3811166940 ps
CPU time 58.36 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:55 PM PDT 24
Peak memory 202036 kb
Host smart-18974b53-9e1e-4153-aa8c-8c6f4e3a66fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663625823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1663625823
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.925089816
Short name T434
Test name
Test status
Simulation time 1353095386 ps
CPU time 16.63 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:13 PM PDT 24
Peak memory 201764 kb
Host smart-3e7cfe46-22d9-4fc0-b8cd-701fa9255cba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925089816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.925089816
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2219943154
Short name T331
Test name
Test status
Simulation time 393006413 ps
CPU time 51.36 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 203944 kb
Host smart-09055073-5e48-4200-82bd-06400a30ff95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219943154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2219943154
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3584793169
Short name T398
Test name
Test status
Simulation time 955377912 ps
CPU time 7.73 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 201928 kb
Host smart-70f765bc-19aa-4aea-922d-a7d79efdae78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3584793169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3584793169
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1482622983
Short name T744
Test name
Test status
Simulation time 42840974 ps
CPU time 6.91 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201932 kb
Host smart-d673009e-c7a2-458a-90e6-ec2df1b53420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482622983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1482622983
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3842359737
Short name T71
Test name
Test status
Simulation time 4626461491 ps
CPU time 31.23 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 202076 kb
Host smart-74d7258c-076f-4b4c-886f-11a388ec2d1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3842359737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.3842359737
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1468169056
Short name T766
Test name
Test status
Simulation time 26311144 ps
CPU time 3 seconds
Started Mar 12 12:57:00 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 201472 kb
Host smart-91f2432a-8e59-4a11-8da8-0d789d0eeb12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468169056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1468169056
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.4219958542
Short name T288
Test name
Test status
Simulation time 35696768 ps
CPU time 3.81 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 201944 kb
Host smart-ed9ff25a-0803-4824-bcb8-94e10ef37857
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4219958542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4219958542
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.913301448
Short name T527
Test name
Test status
Simulation time 1330969306 ps
CPU time 7.65 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:04 PM PDT 24
Peak memory 201828 kb
Host smart-829a8c12-ab11-4037-9b17-2c20ba4ee081
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=913301448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.913301448
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2082014979
Short name T72
Test name
Test status
Simulation time 18353500917 ps
CPU time 87.91 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:58:25 PM PDT 24
Peak memory 202076 kb
Host smart-48877c2a-a8d4-462c-93e1-c97aa9fe7e16
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082014979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2082014979
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.634655098
Short name T483
Test name
Test status
Simulation time 4384934231 ps
CPU time 25.63 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:57:18 PM PDT 24
Peak memory 202000 kb
Host smart-9458616b-bf2c-4bfc-adc1-9d16ab4d264e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=634655098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.634655098
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2262272137
Short name T499
Test name
Test status
Simulation time 217644544 ps
CPU time 4.51 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 201852 kb
Host smart-6181650f-ad6f-4dce-af0e-1d926867e652
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262272137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2262272137
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.2091327183
Short name T313
Test name
Test status
Simulation time 154315487 ps
CPU time 5.46 seconds
Started Mar 12 12:56:52 PM PDT 24
Finished Mar 12 12:56:57 PM PDT 24
Peak memory 201940 kb
Host smart-926bc9b1-fbd1-41d0-aa8e-29ab0cdbd702
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2091327183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2091327183
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.818919313
Short name T136
Test name
Test status
Simulation time 9721034 ps
CPU time 1.12 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:56:58 PM PDT 24
Peak memory 201876 kb
Host smart-366ec6f7-e178-4d9b-96d1-bde6eb7b80b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=818919313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.818919313
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.511785730
Short name T667
Test name
Test status
Simulation time 1463588093 ps
CPU time 6.94 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 201944 kb
Host smart-65797479-949f-4130-b7f4-c2fe23b702df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=511785730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.511785730
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1946180727
Short name T1
Test name
Test status
Simulation time 1782100505 ps
CPU time 10.48 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 201920 kb
Host smart-633c9c2c-144e-4638-b87e-2164dcb4fc1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1946180727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1946180727
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.467489282
Short name T815
Test name
Test status
Simulation time 14009885 ps
CPU time 1.15 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:56:55 PM PDT 24
Peak memory 201944 kb
Host smart-c315485a-da5c-4c6b-958e-72b982e15198
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467489282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.467489282
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1752407687
Short name T587
Test name
Test status
Simulation time 248084201 ps
CPU time 20.3 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:15 PM PDT 24
Peak memory 201952 kb
Host smart-9af77c4e-806a-4510-813a-6ae70287016b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752407687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1752407687
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3817119675
Short name T374
Test name
Test status
Simulation time 3591928491 ps
CPU time 47.42 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:44 PM PDT 24
Peak memory 201892 kb
Host smart-a149f948-421b-46e4-a4b9-22bbc378c134
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3817119675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3817119675
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3275403815
Short name T152
Test name
Test status
Simulation time 6446996604 ps
CPU time 143.86 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 204608 kb
Host smart-fb7f3410-e55f-48e9-8c43-b056da02c1d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3275403815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3275403815
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3856125554
Short name T275
Test name
Test status
Simulation time 255652974 ps
CPU time 48.13 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:44 PM PDT 24
Peak memory 203536 kb
Host smart-77e82e61-3426-46a9-be61-7ab56dcedd71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3856125554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.3856125554
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2335322539
Short name T780
Test name
Test status
Simulation time 48402490 ps
CPU time 4.78 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:56:58 PM PDT 24
Peak memory 201944 kb
Host smart-65331608-5ebb-4f24-b347-da89b64a1ace
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2335322539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2335322539
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1771645020
Short name T578
Test name
Test status
Simulation time 47010858 ps
CPU time 2.89 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:00 PM PDT 24
Peak memory 201912 kb
Host smart-db4ff0cb-a146-44b5-a768-ec74b32bca66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1771645020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1771645020
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2631599733
Short name T263
Test name
Test status
Simulation time 50799359189 ps
CPU time 320.71 seconds
Started Mar 12 12:56:52 PM PDT 24
Finished Mar 12 01:02:13 PM PDT 24
Peak memory 203032 kb
Host smart-e9bd749b-83fe-416d-9ab8-8e84cb7e8d88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2631599733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2631599733
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2822632403
Short name T712
Test name
Test status
Simulation time 45680986 ps
CPU time 1.27 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:56 PM PDT 24
Peak memory 201904 kb
Host smart-47b5ed1e-9a45-4f21-a1e0-5875dad76ed9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822632403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2822632403
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2490400021
Short name T150
Test name
Test status
Simulation time 432660687 ps
CPU time 6.83 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 201872 kb
Host smart-14e73f68-b32a-4019-a63b-483728797344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490400021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2490400021
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.2744130248
Short name T305
Test name
Test status
Simulation time 197903078 ps
CPU time 6.35 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:04 PM PDT 24
Peak memory 201684 kb
Host smart-451d2a02-5482-4ec0-a6af-6c99b3519d34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2744130248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2744130248
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1999285610
Short name T80
Test name
Test status
Simulation time 31797340439 ps
CPU time 148.68 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:59:25 PM PDT 24
Peak memory 201740 kb
Host smart-5da13845-2c6a-4f7c-8553-f0e0c629dc33
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999285610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1999285610
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.266643816
Short name T604
Test name
Test status
Simulation time 20034959255 ps
CPU time 97.64 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:58:31 PM PDT 24
Peak memory 202028 kb
Host smart-93d0061d-1e4d-451e-bc3e-eef2e2c9689c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=266643816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.266643816
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1918553092
Short name T648
Test name
Test status
Simulation time 43977334 ps
CPU time 3.43 seconds
Started Mar 12 12:56:58 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201856 kb
Host smart-bd61db23-36a2-4ee1-8671-3e60585627af
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918553092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1918553092
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.882605679
Short name T709
Test name
Test status
Simulation time 259147442 ps
CPU time 2.38 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:56:55 PM PDT 24
Peak memory 201900 kb
Host smart-58ca9d06-6274-4af1-92d7-9121f2278662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=882605679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.882605679
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.4164499830
Short name T631
Test name
Test status
Simulation time 8446651 ps
CPU time 1.07 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:56:56 PM PDT 24
Peak memory 201876 kb
Host smart-8f866340-8618-49e9-a4ed-e4e09cbe9657
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4164499830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4164499830
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.73878417
Short name T214
Test name
Test status
Simulation time 2317157971 ps
CPU time 11.55 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:08 PM PDT 24
Peak memory 201804 kb
Host smart-3c4b66c4-630b-4f0f-91e3-22e02269d7ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=73878417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.73878417
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2255651466
Short name T513
Test name
Test status
Simulation time 1534366455 ps
CPU time 6.17 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201908 kb
Host smart-669cbcc2-45d8-44db-af42-9bbf6cf8bc59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2255651466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2255651466
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.550428950
Short name T93
Test name
Test status
Simulation time 17296209 ps
CPU time 1.06 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:56 PM PDT 24
Peak memory 201756 kb
Host smart-a4230d84-4155-43b2-82e1-b3c11a2ea416
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550428950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.550428950
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1986671113
Short name T139
Test name
Test status
Simulation time 1889587974 ps
CPU time 15.29 seconds
Started Mar 12 12:56:53 PM PDT 24
Finished Mar 12 12:57:09 PM PDT 24
Peak memory 201956 kb
Host smart-70165ed1-e9c1-46e2-aa02-4af8621d5c49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1986671113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1986671113
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2289404586
Short name T92
Test name
Test status
Simulation time 9527664182 ps
CPU time 64.89 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:58:00 PM PDT 24
Peak memory 201992 kb
Host smart-69031137-8bbb-4a5b-832d-f90e14569f1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2289404586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2289404586
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.40274468
Short name T85
Test name
Test status
Simulation time 573478818 ps
CPU time 68.15 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:58:03 PM PDT 24
Peak memory 204092 kb
Host smart-ffc076fd-9bec-47c1-bdd7-f43874660398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40274468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_
reset.40274468
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1161026011
Short name T10
Test name
Test status
Simulation time 148133499 ps
CPU time 18.51 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:15 PM PDT 24
Peak memory 202956 kb
Host smart-d7752e48-2d3a-46f2-81ca-f9ba96078173
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1161026011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1161026011
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3616181409
Short name T47
Test name
Test status
Simulation time 185303195 ps
CPU time 6.16 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 201840 kb
Host smart-9c4552e2-c4fe-4192-a4f8-9a7e6d85996a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3616181409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3616181409
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.416924568
Short name T396
Test name
Test status
Simulation time 27202874 ps
CPU time 3.97 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 201932 kb
Host smart-71184030-3c79-4ee8-ac5f-6f6d1d6e0e5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=416924568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.416924568
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2137724915
Short name T798
Test name
Test status
Simulation time 143823614778 ps
CPU time 141.19 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 203048 kb
Host smart-4f1a97e9-0bb5-43bc-9288-dc29aeedd882
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2137724915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2137724915
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3370116626
Short name T516
Test name
Test status
Simulation time 51573182 ps
CPU time 4.67 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 201840 kb
Host smart-4841ad87-13b6-4017-8e2b-ec043f91e980
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3370116626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3370116626
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1856814469
Short name T304
Test name
Test status
Simulation time 825864530 ps
CPU time 7.1 seconds
Started Mar 12 12:56:58 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 201820 kb
Host smart-3951262f-cd37-4202-8225-b1a9c1a09c09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1856814469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1856814469
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.902309485
Short name T830
Test name
Test status
Simulation time 70527821 ps
CPU time 1.72 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:56:57 PM PDT 24
Peak memory 201824 kb
Host smart-92a6dc00-bff8-4787-872f-b01bbfdcd56c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=902309485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.902309485
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2042027702
Short name T692
Test name
Test status
Simulation time 4886593315 ps
CPU time 22.59 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 202068 kb
Host smart-f20de74d-56af-4e2b-a267-bb795fa7cc3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042027702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2042027702
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.81645714
Short name T34
Test name
Test status
Simulation time 16210571255 ps
CPU time 100.75 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:58:37 PM PDT 24
Peak memory 201980 kb
Host smart-b74c834e-fbb4-4ac2-9d49-8dfe7c94f875
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=81645714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.81645714
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.297545719
Short name T757
Test name
Test status
Simulation time 128094221 ps
CPU time 4.57 seconds
Started Mar 12 12:57:00 PM PDT 24
Finished Mar 12 12:57:05 PM PDT 24
Peak memory 201420 kb
Host smart-15c6e27c-c58f-45b4-a36a-b1767b669f93
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297545719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.297545719
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.587795857
Short name T734
Test name
Test status
Simulation time 46721430 ps
CPU time 4.79 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 201888 kb
Host smart-05e9addc-e03d-4a9c-a3a7-6af9968a6dec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=587795857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.587795857
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.414452449
Short name T468
Test name
Test status
Simulation time 10880945 ps
CPU time 1.13 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:56:58 PM PDT 24
Peak memory 201900 kb
Host smart-4dd990de-fdf2-41ae-9e59-ceae2fa8418e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=414452449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.414452449
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3421950628
Short name T771
Test name
Test status
Simulation time 3274234039 ps
CPU time 5.84 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:01 PM PDT 24
Peak memory 202068 kb
Host smart-57c975bb-6cd5-4272-8172-9e4716b651d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421950628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3421950628
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1363745697
Short name T782
Test name
Test status
Simulation time 2730336817 ps
CPU time 7.95 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 202028 kb
Host smart-651d35dc-0f6d-4889-bf54-47ec0b219138
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1363745697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1363745697
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3823303987
Short name T553
Test name
Test status
Simulation time 11366043 ps
CPU time 1.12 seconds
Started Mar 12 12:56:54 PM PDT 24
Finished Mar 12 12:56:55 PM PDT 24
Peak memory 201936 kb
Host smart-cac451e3-4956-4f15-987c-0c6af98f37b3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823303987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3823303987
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1465184840
Short name T871
Test name
Test status
Simulation time 323245655 ps
CPU time 24.74 seconds
Started Mar 12 12:56:58 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201876 kb
Host smart-cac65a4c-5d94-48fd-b912-acf0fe6ee9ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465184840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1465184840
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3447072240
Short name T623
Test name
Test status
Simulation time 14464457388 ps
CPU time 56.25 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:52 PM PDT 24
Peak memory 202064 kb
Host smart-61d07940-bee3-4467-8113-c484011c2074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3447072240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3447072240
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4750780
Short name T13
Test name
Test status
Simulation time 1499423320 ps
CPU time 196.27 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 01:00:13 PM PDT 24
Peak memory 206852 kb
Host smart-831274e7-d255-4ca7-a4f2-a697a9df2f83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4750780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_r
eset.4750780
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.967237785
Short name T693
Test name
Test status
Simulation time 723398742 ps
CPU time 40.11 seconds
Started Mar 12 12:56:58 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 203916 kb
Host smart-5ec91c4b-95bc-425d-aad0-cf57dcdc9ac5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=967237785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res
et_error.967237785
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2462249491
Short name T225
Test name
Test status
Simulation time 413252122 ps
CPU time 7.95 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 201844 kb
Host smart-a847bc52-2258-40c9-9245-cf8dbd0ea90f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2462249491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2462249491
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2833692520
Short name T698
Test name
Test status
Simulation time 202148496 ps
CPU time 10.08 seconds
Started Mar 12 12:57:10 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201856 kb
Host smart-77052af7-48c4-48c7-8dd6-ff571b28072a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2833692520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2833692520
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2585247265
Short name T254
Test name
Test status
Simulation time 64536066332 ps
CPU time 212.48 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 01:00:46 PM PDT 24
Peak memory 202980 kb
Host smart-7fa896bd-51ff-4ad0-8b39-196544d42af5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2585247265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.2585247265
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4094171164
Short name T707
Test name
Test status
Simulation time 3309960527 ps
CPU time 7.55 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201764 kb
Host smart-49a22214-1b05-447e-ba1b-05955b1a7514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4094171164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4094171164
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.1370707753
Short name T308
Test name
Test status
Simulation time 137145321 ps
CPU time 5.4 seconds
Started Mar 12 12:56:56 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201844 kb
Host smart-eb86a5b5-0bea-4428-b3a1-1d7641cc5498
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370707753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1370707753
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1182251064
Short name T75
Test name
Test status
Simulation time 9074213571 ps
CPU time 34.27 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 202064 kb
Host smart-5fb00c4d-22a9-43f5-b91f-c98909c31262
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182251064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1182251064
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3451335908
Short name T335
Test name
Test status
Simulation time 24310214709 ps
CPU time 111.76 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 202040 kb
Host smart-f495790d-fd7a-40e1-91cf-78b36e5cef60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3451335908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3451335908
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.522992039
Short name T48
Test name
Test status
Simulation time 64476427 ps
CPU time 10.16 seconds
Started Mar 12 12:56:55 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 201900 kb
Host smart-4e550105-7f25-4752-8e27-3a26d68821a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522992039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.522992039
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.4151185109
Short name T198
Test name
Test status
Simulation time 1015946844 ps
CPU time 12.53 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201896 kb
Host smart-e2778b16-2729-45a0-bf84-4af006eb1575
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151185109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4151185109
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.847957556
Short name T228
Test name
Test status
Simulation time 8932747 ps
CPU time 1.13 seconds
Started Mar 12 12:57:00 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 201848 kb
Host smart-0713d618-c905-4a6e-956e-1ced443c44a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=847957556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.847957556
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.658084442
Short name T242
Test name
Test status
Simulation time 1252589544 ps
CPU time 6.88 seconds
Started Mar 12 12:56:59 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 201888 kb
Host smart-1820c923-e80e-450e-86ce-aa483ffdc567
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=658084442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.658084442
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.740645850
Short name T94
Test name
Test status
Simulation time 1920407789 ps
CPU time 9.13 seconds
Started Mar 12 12:56:57 PM PDT 24
Finished Mar 12 12:57:07 PM PDT 24
Peak memory 201948 kb
Host smart-46ec5419-743c-4aa3-9731-6e328ec973dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=740645850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.740645850
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1860136808
Short name T761
Test name
Test status
Simulation time 11143830 ps
CPU time 1.2 seconds
Started Mar 12 12:56:58 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 201900 kb
Host smart-7552f3d5-3930-40e5-8ee6-85efb6ff4940
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860136808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1860136808
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2403243306
Short name T505
Test name
Test status
Simulation time 564911684 ps
CPU time 23.48 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:42 PM PDT 24
Peak memory 203108 kb
Host smart-078d9c08-105a-4f32-a3d0-c1ae8bc574eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2403243306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2403243306
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.720757989
Short name T477
Test name
Test status
Simulation time 4014755040 ps
CPU time 26.56 seconds
Started Mar 12 12:57:09 PM PDT 24
Finished Mar 12 12:57:36 PM PDT 24
Peak memory 202068 kb
Host smart-4da5a79c-be9d-4628-bce7-fb1b4d87fd22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=720757989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.720757989
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3010280976
Short name T843
Test name
Test status
Simulation time 9494906792 ps
CPU time 110.1 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 205736 kb
Host smart-2b092631-3766-4242-8c5b-1d2bfd890f27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3010280976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.3010280976
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.102458574
Short name T476
Test name
Test status
Simulation time 844912118 ps
CPU time 109.64 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 203912 kb
Host smart-79028234-28c7-4fe5-8cd3-7041f4d66cad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102458574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res
et_error.102458574
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1311432579
Short name T700
Test name
Test status
Simulation time 910662693 ps
CPU time 11.61 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201836 kb
Host smart-0ae57fc4-d32b-45cb-8cb8-c77abf3636cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1311432579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1311432579
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.452105329
Short name T851
Test name
Test status
Simulation time 113694073 ps
CPU time 12.62 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201948 kb
Host smart-03544859-ac0c-4318-95a8-3ed4deaadb4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=452105329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.452105329
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2302262131
Short name T429
Test name
Test status
Simulation time 606897338 ps
CPU time 5.29 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201888 kb
Host smart-4e33f3ba-1533-4ad0-a9f6-e9a90ac3fe31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2302262131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2302262131
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.3865205587
Short name T443
Test name
Test status
Simulation time 47687878 ps
CPU time 2.92 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201672 kb
Host smart-d0e54bd3-95fd-4ffc-b587-199b9c288a7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3865205587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3865205587
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2484127415
Short name T290
Test name
Test status
Simulation time 49560653 ps
CPU time 3.79 seconds
Started Mar 12 12:57:11 PM PDT 24
Finished Mar 12 12:57:15 PM PDT 24
Peak memory 201884 kb
Host smart-c0826bd5-3d0b-41ae-aa1e-eb17dfbd2143
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2484127415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2484127415
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3907904102
Short name T192
Test name
Test status
Simulation time 31816852840 ps
CPU time 142 seconds
Started Mar 12 12:57:10 PM PDT 24
Finished Mar 12 12:59:32 PM PDT 24
Peak memory 201964 kb
Host smart-147241d3-ed7d-4b83-9048-5d5bed750c2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907904102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3907904102
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.4093987968
Short name T588
Test name
Test status
Simulation time 27563509393 ps
CPU time 170.23 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 01:00:06 PM PDT 24
Peak memory 202068 kb
Host smart-9181a928-a48d-4bc8-a65e-0a68b475a796
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4093987968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.4093987968
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2070872802
Short name T755
Test name
Test status
Simulation time 39000313 ps
CPU time 2.23 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:17 PM PDT 24
Peak memory 201828 kb
Host smart-69df0bd0-4b7c-4e7e-a166-517e90f4cee6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070872802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2070872802
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.4085765048
Short name T659
Test name
Test status
Simulation time 550899643 ps
CPU time 6.45 seconds
Started Mar 12 12:57:12 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201824 kb
Host smart-fe91388d-fd0b-4b2c-ba99-4b0bdf45b004
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4085765048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4085765048
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.1781335268
Short name T382
Test name
Test status
Simulation time 68155162 ps
CPU time 1.49 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:17 PM PDT 24
Peak memory 201832 kb
Host smart-1b329cd8-5098-4a60-b36b-6263b3f91e67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1781335268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1781335268
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1307581951
Short name T113
Test name
Test status
Simulation time 4191017387 ps
CPU time 6.98 seconds
Started Mar 12 12:57:12 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 202008 kb
Host smart-9fad2e95-c085-42b2-a1a4-e7c155abcdf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307581951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1307581951
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.320006104
Short name T389
Test name
Test status
Simulation time 2221163347 ps
CPU time 9.24 seconds
Started Mar 12 12:57:11 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 202000 kb
Host smart-98f067bb-0a9f-400a-bd78-cc4003c55367
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=320006104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.320006104
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2914463782
Short name T562
Test name
Test status
Simulation time 17445551 ps
CPU time 1.33 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:17 PM PDT 24
Peak memory 201892 kb
Host smart-2793dbaa-2427-4d03-a18e-2f46276f1dd0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914463782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2914463782
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1311373035
Short name T797
Test name
Test status
Simulation time 3701534347 ps
CPU time 27.28 seconds
Started Mar 12 12:57:07 PM PDT 24
Finished Mar 12 12:57:35 PM PDT 24
Peak memory 202052 kb
Host smart-b3676904-33f7-494a-9ec5-d54eb9bd5df2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1311373035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1311373035
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2406574370
Short name T223
Test name
Test status
Simulation time 3761754400 ps
CPU time 47.5 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:58:10 PM PDT 24
Peak memory 202036 kb
Host smart-ec83d13d-3a32-471b-a930-77469ca7bce4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2406574370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2406574370
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3788347793
Short name T837
Test name
Test status
Simulation time 1255188325 ps
CPU time 203.79 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 01:00:39 PM PDT 24
Peak memory 206664 kb
Host smart-e8a6e798-1480-4ef5-87fe-79a6f77008d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3788347793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.3788347793
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1755822304
Short name T329
Test name
Test status
Simulation time 53407956 ps
CPU time 8.17 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201848 kb
Host smart-91a2bde7-8d72-4bcb-a2e2-9aab9fceb77a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1755822304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.1755822304
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2256573146
Short name T414
Test name
Test status
Simulation time 80911606 ps
CPU time 1.42 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201832 kb
Host smart-12a2a5ef-a86d-433a-b497-d93c6014e9de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256573146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2256573146
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1393494585
Short name T212
Test name
Test status
Simulation time 73718554 ps
CPU time 1.92 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201932 kb
Host smart-b7b4c18c-30ca-4777-93e5-f34832d712c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1393494585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1393494585
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2889730369
Short name T191
Test name
Test status
Simulation time 5043627184 ps
CPU time 36.52 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:55 PM PDT 24
Peak memory 202024 kb
Host smart-01a46b0b-703a-4d98-83f2-09f672c03c47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2889730369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.2889730369
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3500102145
Short name T425
Test name
Test status
Simulation time 76332711 ps
CPU time 4.62 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201928 kb
Host smart-a6c7b552-b799-4bd0-9159-9b582e8f2755
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3500102145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3500102145
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3448967120
Short name T511
Test name
Test status
Simulation time 461360064 ps
CPU time 7.54 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201792 kb
Host smart-b560f653-e54b-4bf1-a74a-659abf1df20e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3448967120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3448967120
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.791363539
Short name T455
Test name
Test status
Simulation time 654112670 ps
CPU time 7.62 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 201856 kb
Host smart-e107f741-a1c1-4bf5-a0b5-97dc20d0027c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=791363539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.791363539
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.931415850
Short name T168
Test name
Test status
Simulation time 224101468070 ps
CPU time 167.41 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 201888 kb
Host smart-ca2571d3-2e5e-4e8e-bc80-d87c03278255
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=931415850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.931415850
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1395245244
Short name T54
Test name
Test status
Simulation time 3176969813 ps
CPU time 18.58 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:35 PM PDT 24
Peak memory 202028 kb
Host smart-817b29b8-a9aa-48a3-a58b-b1e9ea02f004
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1395245244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1395245244
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3254229258
Short name T773
Test name
Test status
Simulation time 52839550 ps
CPU time 6 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201932 kb
Host smart-1505e013-632e-4a1e-aea7-1fe4ef94f0c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254229258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3254229258
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.1997799649
Short name T439
Test name
Test status
Simulation time 492340510 ps
CPU time 5.32 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201904 kb
Host smart-00b12d39-71b4-4fec-8f64-232f45ba7b97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1997799649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1997799649
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.2785657098
Short name T848
Test name
Test status
Simulation time 75007133 ps
CPU time 1.62 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:16 PM PDT 24
Peak memory 201852 kb
Host smart-0849610d-92c7-4b45-b99a-68dd011d4b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2785657098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2785657098
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3893959241
Short name T370
Test name
Test status
Simulation time 1638367138 ps
CPU time 7.86 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201956 kb
Host smart-8fac3b48-7d8e-4d06-8abd-5ebd8bb76859
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893959241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3893959241
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.340073297
Short name T233
Test name
Test status
Simulation time 2425857564 ps
CPU time 6.21 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 202028 kb
Host smart-882db9e8-9f3d-4175-b764-4b28f7ff9569
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=340073297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.340073297
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1499669388
Short name T525
Test name
Test status
Simulation time 9522982 ps
CPU time 1.03 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201852 kb
Host smart-214ac4c4-aa13-409c-92df-60e460fc68b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499669388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1499669388
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3464016158
Short name T177
Test name
Test status
Simulation time 668398603 ps
CPU time 9.17 seconds
Started Mar 12 12:57:10 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 202140 kb
Host smart-de27003f-c60e-478e-9f33-3e6e2fa872d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3464016158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3464016158
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.4069214259
Short name T151
Test name
Test status
Simulation time 5207565242 ps
CPU time 64.02 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 201940 kb
Host smart-94292393-bf4b-432e-843c-d48c886adaf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4069214259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4069214259
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.216044257
Short name T51
Test name
Test status
Simulation time 258701514 ps
CPU time 33.36 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:53 PM PDT 24
Peak memory 204184 kb
Host smart-24c9bbd5-6af8-4990-bae3-3a053d43ef35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216044257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand
_reset.216044257
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1832294278
Short name T517
Test name
Test status
Simulation time 19010988 ps
CPU time 4.28 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201792 kb
Host smart-30d12e05-9eb0-4d11-8651-1bbe33135f11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1832294278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.1832294278
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.290567187
Short name T869
Test name
Test status
Simulation time 72393272 ps
CPU time 6.87 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201900 kb
Host smart-a3b464f9-e709-401c-9afb-845cd2496071
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=290567187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.290567187
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.587034546
Short name T372
Test name
Test status
Simulation time 318809813 ps
CPU time 9.89 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201840 kb
Host smart-8dd642f7-4a9e-4001-ae87-6e995ef34eca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=587034546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.587034546
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4054996285
Short name T143
Test name
Test status
Simulation time 83253864426 ps
CPU time 153.25 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:59:49 PM PDT 24
Peak memory 202000 kb
Host smart-696c96e1-ae2e-49c0-b009-09883c67e36f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4054996285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.4054996285
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1373172469
Short name T779
Test name
Test status
Simulation time 810293252 ps
CPU time 3.53 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201856 kb
Host smart-51e6a017-7e57-4226-a72a-7aa708ff39b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373172469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1373172469
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.211970404
Short name T21
Test name
Test status
Simulation time 76693971 ps
CPU time 6.14 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201960 kb
Host smart-8b0b198d-c818-4338-bffe-648b5f072137
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=211970404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.211970404
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.3227775240
Short name T137
Test name
Test status
Simulation time 38285081 ps
CPU time 2.88 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201848 kb
Host smart-98f62962-774f-4e08-ac99-837e59cafb13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227775240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3227775240
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.4059901930
Short name T307
Test name
Test status
Simulation time 8245773045 ps
CPU time 14.62 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201956 kb
Host smart-0ebb16ea-159a-4a30-b2e3-ad4f53f90284
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059901930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4059901930
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.329973228
Short name T422
Test name
Test status
Simulation time 53761760 ps
CPU time 4.91 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201896 kb
Host smart-c857e8f6-8114-40aa-91ce-e0b999b3287c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329973228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.329973228
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.3539257990
Short name T636
Test name
Test status
Simulation time 21239185 ps
CPU time 1.59 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:18 PM PDT 24
Peak memory 201888 kb
Host smart-95aae882-096b-4aa0-809f-964bd343e802
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3539257990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3539257990
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3765446427
Short name T45
Test name
Test status
Simulation time 11530280 ps
CPU time 1.15 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201816 kb
Host smart-43879d5c-b990-436b-8cb6-bc15f11bcf59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765446427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3765446427
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1348131719
Short name T24
Test name
Test status
Simulation time 2297972309 ps
CPU time 8.04 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 202028 kb
Host smart-bb185a78-944a-464b-8aed-ae87c5c2dfa1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348131719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1348131719
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.203830761
Short name T632
Test name
Test status
Simulation time 4205189752 ps
CPU time 6.85 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:33 PM PDT 24
Peak memory 202024 kb
Host smart-b60acf66-0620-4413-b490-2f1aa3033fc4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=203830761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.203830761
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4277836256
Short name T444
Test name
Test status
Simulation time 8512452 ps
CPU time 0.98 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201616 kb
Host smart-761c95f2-30a1-4c1b-b676-6a5e16d3cd22
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277836256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4277836256
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3537163794
Short name T211
Test name
Test status
Simulation time 5356836701 ps
CPU time 35.66 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 12:57:49 PM PDT 24
Peak memory 201960 kb
Host smart-29f78b9d-b35f-41b2-8410-d329b150d211
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3537163794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3537163794
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3059706738
Short name T533
Test name
Test status
Simulation time 1475477347 ps
CPU time 59.4 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:58:14 PM PDT 24
Peak memory 203620 kb
Host smart-2f3f062b-3b7b-48e0-a425-814636e747f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3059706738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3059706738
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3518743712
Short name T354
Test name
Test status
Simulation time 279150462 ps
CPU time 28.31 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:43 PM PDT 24
Peak memory 203912 kb
Host smart-e6e26372-ff02-4cd7-9541-2de38aea49df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3518743712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.3518743712
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.4115606494
Short name T759
Test name
Test status
Simulation time 688141865 ps
CPU time 56.23 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:58:15 PM PDT 24
Peak memory 204096 kb
Host smart-e3216dc4-3044-4543-b688-2e62ba956fff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115606494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.4115606494
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2553077323
Short name T56
Test name
Test status
Simulation time 163843425 ps
CPU time 3.46 seconds
Started Mar 12 12:57:04 PM PDT 24
Finished Mar 12 12:57:08 PM PDT 24
Peak memory 201892 kb
Host smart-34b57d75-a0e4-4c0f-a26b-af81075c6ad3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2553077323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2553077323
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3636027830
Short name T589
Test name
Test status
Simulation time 1094465858 ps
CPU time 22.6 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 201868 kb
Host smart-2d0d9aba-2b25-4762-9ae1-e10813a8b2fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3636027830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3636027830
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.572015621
Short name T789
Test name
Test status
Simulation time 21297486 ps
CPU time 1.33 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201864 kb
Host smart-98daa980-45ef-48c5-b838-ffa276cebb86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=572015621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.572015621
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.2451032600
Short name T717
Test name
Test status
Simulation time 566589394 ps
CPU time 7.61 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201864 kb
Host smart-3ae2938a-e092-4966-a6fb-ba56ae1b6e82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2451032600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2451032600
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2343502009
Short name T424
Test name
Test status
Simulation time 1205229553 ps
CPU time 6.06 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201836 kb
Host smart-4059351b-7340-4a4c-ad47-e94ea7f16109
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2343502009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2343502009
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1428568292
Short name T68
Test name
Test status
Simulation time 53122527506 ps
CPU time 149.96 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201924 kb
Host smart-bccde974-97a0-484f-a2a0-f9830ca2a195
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428568292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1428568292
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2596413776
Short name T452
Test name
Test status
Simulation time 48397143576 ps
CPU time 47.42 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:55:38 PM PDT 24
Peak memory 201968 kb
Host smart-ebc4364f-0c3a-486e-9df7-d16b27f361ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2596413776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2596413776
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3471241746
Short name T873
Test name
Test status
Simulation time 26338759 ps
CPU time 2.93 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:54:59 PM PDT 24
Peak memory 201888 kb
Host smart-7e7a8169-e8d6-4367-896a-455cb43ce7fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471241746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3471241746
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.777350279
Short name T536
Test name
Test status
Simulation time 329202335 ps
CPU time 3.85 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 201864 kb
Host smart-37059bd6-ae73-450a-b8ee-9aab13d5c6fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=777350279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.777350279
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.2198032277
Short name T650
Test name
Test status
Simulation time 42735762 ps
CPU time 1.21 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201840 kb
Host smart-188bc568-942c-4ba6-aef3-921610d70dee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2198032277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2198032277
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2991955250
Short name T541
Test name
Test status
Simulation time 1468604113 ps
CPU time 6.93 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201700 kb
Host smart-604644bd-374b-4bb1-980b-ee1531e4489d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991955250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2991955250
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.603502171
Short name T456
Test name
Test status
Simulation time 723843338 ps
CPU time 4.99 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201784 kb
Host smart-c680539e-b216-4703-aa38-cdb6c6fd5d0e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=603502171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.603502171
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.710874250
Short name T420
Test name
Test status
Simulation time 11817376 ps
CPU time 1.15 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:51 PM PDT 24
Peak memory 201820 kb
Host smart-ee673375-ac6a-41bc-a07f-82dd818f7f75
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710874250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.710874250
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.610945154
Short name T454
Test name
Test status
Simulation time 420290932 ps
CPU time 16.07 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:55:05 PM PDT 24
Peak memory 201824 kb
Host smart-997bc742-06a9-4c82-9c4e-bedfb3650018
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=610945154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.610945154
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1681134300
Short name T767
Test name
Test status
Simulation time 157140488 ps
CPU time 17 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 201640 kb
Host smart-7e540da9-30c8-404e-8790-e45594290c8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1681134300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1681134300
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1839040980
Short name T646
Test name
Test status
Simulation time 254948791 ps
CPU time 22.7 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:55:34 PM PDT 24
Peak memory 202956 kb
Host smart-8a7f68dc-a25a-4fb9-a375-0f02d0a5ddf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1839040980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1839040980
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1987182317
Short name T70
Test name
Test status
Simulation time 2825174185 ps
CPU time 48.44 seconds
Started Mar 12 12:55:07 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 203064 kb
Host smart-6882be10-a950-4179-9386-18c327b2fde9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1987182317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.1987182317
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.719189877
Short name T409
Test name
Test status
Simulation time 56751240 ps
CPU time 6.38 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 201896 kb
Host smart-4e2e6e69-336e-41b8-bb10-702fd4941804
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=719189877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.719189877
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3324005859
Short name T249
Test name
Test status
Simulation time 1616127464 ps
CPU time 14.81 seconds
Started Mar 12 12:57:10 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 202156 kb
Host smart-e387db81-4616-419c-80ef-cc8638224741
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3324005859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3324005859
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1969567611
Short name T890
Test name
Test status
Simulation time 36226789594 ps
CPU time 96.1 seconds
Started Mar 12 12:57:11 PM PDT 24
Finished Mar 12 12:58:48 PM PDT 24
Peak memory 202060 kb
Host smart-47b06873-5f4d-47b6-8115-ec9afcbddef3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1969567611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.1969567611
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2379323346
Short name T73
Test name
Test status
Simulation time 48282504 ps
CPU time 4.33 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201920 kb
Host smart-2d96a3ee-1b0a-4b11-ada8-0549f6c0ec99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2379323346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2379323346
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2346823839
Short name T633
Test name
Test status
Simulation time 557966980 ps
CPU time 4.17 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201896 kb
Host smart-12dec1a8-56aa-4b56-b705-66e9867be9d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346823839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2346823839
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.992436164
Short name T66
Test name
Test status
Simulation time 840882828 ps
CPU time 9.62 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201912 kb
Host smart-df0d4514-8be7-4b85-b4f6-9f72357795a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992436164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.992436164
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1229648667
Short name T490
Test name
Test status
Simulation time 61462631625 ps
CPU time 46.16 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:58:06 PM PDT 24
Peak memory 201820 kb
Host smart-214de264-b78c-447d-8b2f-9e3ebfc24de2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229648667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1229648667
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.115910201
Short name T809
Test name
Test status
Simulation time 12208223502 ps
CPU time 78.91 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:58:39 PM PDT 24
Peak memory 202036 kb
Host smart-6a8aaca6-4cbc-41ad-85d7-515e5c61262e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=115910201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.115910201
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2530111445
Short name T108
Test name
Test status
Simulation time 427989766 ps
CPU time 7.61 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201892 kb
Host smart-fa23b001-df13-47cc-8def-ac062f240aae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530111445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2530111445
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.1405028223
Short name T699
Test name
Test status
Simulation time 185956366 ps
CPU time 4.45 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201892 kb
Host smart-7fafeda1-64c8-40e0-8a3f-5fc9b6e9021c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1405028223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1405028223
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.3288938637
Short name T542
Test name
Test status
Simulation time 59406629 ps
CPU time 1.48 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:18 PM PDT 24
Peak memory 201552 kb
Host smart-c7cefb6d-2adb-4f6c-95a9-9add4280740b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3288938637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3288938637
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3396330535
Short name T413
Test name
Test status
Simulation time 6084016408 ps
CPU time 7.17 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 202084 kb
Host smart-f698e33f-2d80-4e0b-b4d8-8bc8acad85a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396330535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3396330535
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3491904472
Short name T386
Test name
Test status
Simulation time 8018721461 ps
CPU time 11.9 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201876 kb
Host smart-698a9300-6153-496f-8af9-28d4e71a4a91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3491904472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3491904472
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.254904964
Short name T532
Test name
Test status
Simulation time 22119838 ps
CPU time 1.01 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:16 PM PDT 24
Peak memory 201904 kb
Host smart-33f347b8-bd8d-45b3-96bc-43de6ec01017
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254904964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.254904964
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3779453021
Short name T621
Test name
Test status
Simulation time 7382239470 ps
CPU time 115.03 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 203016 kb
Host smart-7dbf7311-2405-4bd4-820c-c764c025da34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779453021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3779453021
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.702873556
Short name T784
Test name
Test status
Simulation time 7051174787 ps
CPU time 60.5 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 201968 kb
Host smart-099a5adb-7a37-41a2-9956-ea01c7166fd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=702873556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.702873556
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1668041216
Short name T478
Test name
Test status
Simulation time 336890915 ps
CPU time 61.66 seconds
Started Mar 12 12:57:09 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 203952 kb
Host smart-7d4056e4-189a-470c-8ab8-a576b39fadf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1668041216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.1668041216
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.386834077
Short name T555
Test name
Test status
Simulation time 763901282 ps
CPU time 47.87 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:58:03 PM PDT 24
Peak memory 203320 kb
Host smart-f21438ba-fffb-4e27-ace7-7548386aa746
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=386834077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.386834077
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3488428745
Short name T64
Test name
Test status
Simulation time 455984984 ps
CPU time 9.55 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201880 kb
Host smart-85fe3861-2094-41fb-b2ad-cad4b8b19e3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3488428745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3488428745
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.84561979
Short name T850
Test name
Test status
Simulation time 76761792295 ps
CPU time 290.46 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 01:02:10 PM PDT 24
Peak memory 204360 kb
Host smart-5ddb7eec-61cd-45b2-a5ec-821b176c8545
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=84561979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow
_rsp.84561979
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2097639885
Short name T644
Test name
Test status
Simulation time 79364764 ps
CPU time 3.17 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201912 kb
Host smart-81d9835d-093c-4b12-8b34-231084ff4a57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2097639885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2097639885
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.2006350240
Short name T484
Test name
Test status
Simulation time 397058589 ps
CPU time 6.37 seconds
Started Mar 12 12:57:13 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201880 kb
Host smart-212ca82c-28b1-4701-8aba-125c8c3dba74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2006350240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2006350240
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.824018294
Short name T706
Test name
Test status
Simulation time 151271409 ps
CPU time 9.24 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201856 kb
Host smart-ee032424-086b-4885-9eb5-3f839606fdbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=824018294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.824018294
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.4023528667
Short name T41
Test name
Test status
Simulation time 36140301485 ps
CPU time 40.92 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:58 PM PDT 24
Peak memory 202060 kb
Host smart-7ff43025-f2e3-4aca-be16-47056a9387d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023528667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4023528667
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2993145071
Short name T55
Test name
Test status
Simulation time 88601657307 ps
CPU time 115.1 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 202024 kb
Host smart-f48aab9a-929d-4b06-9bfc-086dde5346ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2993145071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2993145071
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3121905985
Short name T514
Test name
Test status
Simulation time 55216365 ps
CPU time 5.82 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201916 kb
Host smart-185571d5-ee6d-4211-b4d7-2eedd651e3c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121905985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3121905985
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.1472165260
Short name T875
Test name
Test status
Simulation time 236201264 ps
CPU time 2.7 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201892 kb
Host smart-044cc848-3e83-4784-96b3-2fb0d8b1f93b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1472165260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1472165260
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1059223588
Short name T35
Test name
Test status
Simulation time 92970339 ps
CPU time 1.55 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201852 kb
Host smart-333ddb4a-cc7d-4abf-8743-4ac3690993a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1059223588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1059223588
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3620143930
Short name T685
Test name
Test status
Simulation time 9635277584 ps
CPU time 9.19 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:35 PM PDT 24
Peak memory 202028 kb
Host smart-7bf0a3e3-35de-4b77-b981-3911be03eb77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620143930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3620143930
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.502191486
Short name T426
Test name
Test status
Simulation time 2501486233 ps
CPU time 5.34 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 202024 kb
Host smart-dd78c550-0745-4de9-a865-0ec3c668f610
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=502191486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.502191486
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2214141562
Short name T470
Test name
Test status
Simulation time 17931851 ps
CPU time 1.25 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201880 kb
Host smart-0352adcb-30b4-4f74-8a01-8a81cf896059
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214141562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2214141562
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1877943236
Short name T95
Test name
Test status
Simulation time 4976987240 ps
CPU time 72.45 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:58:30 PM PDT 24
Peak memory 203040 kb
Host smart-7983a170-c578-4115-8742-8c068a6dc00e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1877943236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1877943236
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.195957002
Short name T539
Test name
Test status
Simulation time 10849216465 ps
CPU time 64.91 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:58:25 PM PDT 24
Peak memory 202032 kb
Host smart-50d3100b-d2f1-4603-ae25-e36e378c5fc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=195957002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.195957002
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2863473206
Short name T564
Test name
Test status
Simulation time 191749875 ps
CPU time 27.78 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:45 PM PDT 24
Peak memory 203948 kb
Host smart-f2b86838-b91c-403c-bd83-cc85c2fbf302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2863473206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.2863473206
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.55461852
Short name T563
Test name
Test status
Simulation time 1086510347 ps
CPU time 68.27 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:58:27 PM PDT 24
Peak memory 204096 kb
Host smart-804338dc-b1d2-41eb-bfdf-03b0df56cf56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55461852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rese
t_error.55461852
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2220138040
Short name T819
Test name
Test status
Simulation time 455345757 ps
CPU time 7.59 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201932 kb
Host smart-b59d68b3-8a2f-41b8-9725-2ba40ec4f50e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2220138040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2220138040
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2874021979
Short name T125
Test name
Test status
Simulation time 1320742662 ps
CPU time 14.44 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 201924 kb
Host smart-e353530a-818e-4d18-8bd1-f01bebb14743
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2874021979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2874021979
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2552680282
Short name T859
Test name
Test status
Simulation time 12047574580 ps
CPU time 63.33 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:58:23 PM PDT 24
Peak memory 202036 kb
Host smart-e9bcedca-9540-4ebc-b593-d684f030f27d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2552680282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.2552680282
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2901412962
Short name T332
Test name
Test status
Simulation time 2640016622 ps
CPU time 7.87 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 202016 kb
Host smart-e94f5cfd-2966-41dd-b918-f9e716646003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2901412962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2901412962
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.4111599494
Short name T363
Test name
Test status
Simulation time 867425055 ps
CPU time 3.56 seconds
Started Mar 12 12:57:05 PM PDT 24
Finished Mar 12 12:57:08 PM PDT 24
Peak memory 201904 kb
Host smart-a1c90711-4e47-4b94-a86f-97db36a0fb8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111599494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4111599494
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2272771408
Short name T728
Test name
Test status
Simulation time 63265349 ps
CPU time 3.06 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 201820 kb
Host smart-9f2e380e-9b1c-4a6d-925d-64a075d3f391
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2272771408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2272771408
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.588261236
Short name T176
Test name
Test status
Simulation time 20667820784 ps
CPU time 109.41 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 202024 kb
Host smart-c7e9c7d0-97a2-4ce9-9916-988a8279191c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=588261236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.588261236
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3886687937
Short name T357
Test name
Test status
Simulation time 75295305 ps
CPU time 6.34 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 201920 kb
Host smart-dbb0aa04-6540-4699-8653-b8d2715b3793
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886687937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3886687937
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3284417497
Short name T746
Test name
Test status
Simulation time 137517793 ps
CPU time 2.41 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201636 kb
Host smart-f3d0d0ee-e486-47ce-ba02-6a91cdf0478f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3284417497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3284417497
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.4148870697
Short name T606
Test name
Test status
Simulation time 72552015 ps
CPU time 1.36 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201844 kb
Host smart-38c5bf9d-fd2a-49a2-b4af-59c8eb9aa90d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4148870697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4148870697
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.4036537923
Short name T453
Test name
Test status
Simulation time 4273070476 ps
CPU time 8.07 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 202044 kb
Host smart-6aff4940-0c3f-4da1-b95c-7299a227aac2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036537923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4036537923
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3365376924
Short name T467
Test name
Test status
Simulation time 945234678 ps
CPU time 8.03 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 201920 kb
Host smart-c81a2e1d-9e6e-4376-aa61-3ce66f58c668
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3365376924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3365376924
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2196539630
Short name T109
Test name
Test status
Simulation time 23155232 ps
CPU time 1.02 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201932 kb
Host smart-1d5c3d55-14c4-411f-96a9-fe5156fb65a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196539630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2196539630
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2580303406
Short name T376
Test name
Test status
Simulation time 1784270382 ps
CPU time 26.3 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 202936 kb
Host smart-59303d44-2dfd-4e3c-92da-b1162c3b0b51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2580303406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2580303406
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1916301970
Short name T590
Test name
Test status
Simulation time 5750337854 ps
CPU time 129.06 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:59:37 PM PDT 24
Peak memory 205748 kb
Host smart-65605b09-bb8b-4bf3-b7a8-5873cd5c8fcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916301970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1916301970
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2078143411
Short name T279
Test name
Test status
Simulation time 72098747 ps
CPU time 16.02 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:42 PM PDT 24
Peak memory 201888 kb
Host smart-d05898f8-071e-4267-b0d5-6477d2e0271e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2078143411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2078143411
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2040937208
Short name T552
Test name
Test status
Simulation time 64181729 ps
CPU time 5.23 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:57:33 PM PDT 24
Peak memory 201928 kb
Host smart-1a97b1b0-d420-4a19-9bd6-ed07ea63a259
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040937208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2040937208
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3443701468
Short name T502
Test name
Test status
Simulation time 29319504 ps
CPU time 3.56 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201880 kb
Host smart-239574ec-6a87-48d5-959f-4fc4c52c33ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3443701468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3443701468
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1215046354
Short name T764
Test name
Test status
Simulation time 48874902036 ps
CPU time 275.81 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 203068 kb
Host smart-355aa1f5-e4cc-4bb9-b31c-b915aedd4ef9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1215046354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1215046354
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.730601897
Short name T585
Test name
Test status
Simulation time 96830348 ps
CPU time 7.02 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:32 PM PDT 24
Peak memory 201848 kb
Host smart-064c2fc1-0cf2-44f3-945a-b989502c184f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=730601897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.730601897
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.2725090959
Short name T867
Test name
Test status
Simulation time 3610357424 ps
CPU time 7.05 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 202052 kb
Host smart-046348ae-f322-477d-80a3-82b79323673d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2725090959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2725090959
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1786442492
Short name T101
Test name
Test status
Simulation time 1595132846 ps
CPU time 14.99 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:37 PM PDT 24
Peak memory 201860 kb
Host smart-360463bf-ab97-49a7-abaa-88aed0c06e63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786442492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1786442492
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1456063696
Short name T324
Test name
Test status
Simulation time 32503931886 ps
CPU time 150.14 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 202032 kb
Host smart-68fbc614-d3d7-4c71-b4ce-842c619adc3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456063696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1456063696
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2086992599
Short name T584
Test name
Test status
Simulation time 12563628688 ps
CPU time 91.33 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 202012 kb
Host smart-9a5c63c1-1939-4c5f-a16e-954df7a3a2cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2086992599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2086992599
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.708898536
Short name T506
Test name
Test status
Simulation time 145988202 ps
CPU time 3.35 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201884 kb
Host smart-d4e0e6aa-2eff-462c-a2fb-8a716973ee92
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708898536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.708898536
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.889564333
Short name T232
Test name
Test status
Simulation time 398094854 ps
CPU time 4.08 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201908 kb
Host smart-2aae3576-354f-432c-bf47-2dfcbd7d38fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=889564333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.889564333
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.1173048110
Short name T237
Test name
Test status
Simulation time 55127694 ps
CPU time 1.43 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201876 kb
Host smart-7c042fc3-c217-41e5-b8e5-d178c98aa7c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1173048110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1173048110
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3338866066
Short name T98
Test name
Test status
Simulation time 2643193317 ps
CPU time 6.8 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 202008 kb
Host smart-a54bca72-bb9e-4617-878a-e8526747c3d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338866066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3338866066
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3286858008
Short name T792
Test name
Test status
Simulation time 1132039827 ps
CPU time 7.98 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201908 kb
Host smart-3b158d2c-7288-47a1-b8f3-ba1f3975c88e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3286858008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3286858008
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4205103711
Short name T863
Test name
Test status
Simulation time 9463349 ps
CPU time 1.19 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 201912 kb
Host smart-9afc0926-624f-4459-b7ee-79f5f6775a9a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205103711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4205103711
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3596808083
Short name T737
Test name
Test status
Simulation time 334275852 ps
CPU time 18.98 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:37 PM PDT 24
Peak memory 201888 kb
Host smart-ac5e4bef-097d-4153-a33f-03af224fd204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3596808083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3596808083
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.709877060
Short name T291
Test name
Test status
Simulation time 131930076 ps
CPU time 12 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201668 kb
Host smart-4522188e-7b64-4437-a54a-fb13fefebfd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=709877060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.709877060
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.33204936
Short name T421
Test name
Test status
Simulation time 2790646654 ps
CPU time 188.49 seconds
Started Mar 12 12:57:11 PM PDT 24
Finished Mar 12 01:00:20 PM PDT 24
Peak memory 207472 kb
Host smart-9fa342fd-d606-42bd-bb53-852927dee9b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33204936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_
reset.33204936
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2935379116
Short name T810
Test name
Test status
Simulation time 737909152 ps
CPU time 86.44 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:58:42 PM PDT 24
Peak memory 203612 kb
Host smart-452fe0e7-606e-417c-9d6e-46a25aa35e9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2935379116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.2935379116
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1111541498
Short name T622
Test name
Test status
Simulation time 49336721 ps
CPU time 3.13 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201900 kb
Host smart-5d7df86c-cb78-481b-93be-5d9aae19259b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1111541498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1111541498
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3089190387
Short name T124
Test name
Test status
Simulation time 572452784 ps
CPU time 10.12 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:31 PM PDT 24
Peak memory 201900 kb
Host smart-92190789-cddc-497b-bacb-5972f2fc21c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3089190387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3089190387
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.78011819
Short name T266
Test name
Test status
Simulation time 25334221375 ps
CPU time 65.51 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:58:28 PM PDT 24
Peak memory 201296 kb
Host smart-41b29043-42ac-46c6-ac7c-6613596fd038
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=78011819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow
_rsp.78011819
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.187381584
Short name T806
Test name
Test status
Simulation time 170504541 ps
CPU time 4.58 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201912 kb
Host smart-b7cd74b9-6f66-4b67-8e4e-a68990ed57dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=187381584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.187381584
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3777889837
Short name T544
Test name
Test status
Simulation time 1034985775 ps
CPU time 13.87 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 201900 kb
Host smart-b99c4f7c-434e-4e0e-9a52-6da27af94d74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3777889837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3777889837
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.72382437
Short name T368
Test name
Test status
Simulation time 1325829590 ps
CPU time 12.35 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201836 kb
Host smart-06b7b77c-34b4-4f2c-ab74-a57fb4ec29c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72382437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.72382437
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3620233713
Short name T63
Test name
Test status
Simulation time 17182991228 ps
CPU time 65.16 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:58:31 PM PDT 24
Peak memory 201948 kb
Host smart-5215cd29-9d11-4cf6-a807-6cbb85ad905b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620233713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3620233713
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2518983999
Short name T840
Test name
Test status
Simulation time 40140963418 ps
CPU time 88.05 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:58:51 PM PDT 24
Peak memory 202028 kb
Host smart-257cbf6f-f927-4e22-aa42-ef3bcc551a87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2518983999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2518983999
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2369403846
Short name T657
Test name
Test status
Simulation time 99524952 ps
CPU time 5.93 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201920 kb
Host smart-12406a85-e2aa-4f2d-8509-b09eddbcb44e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369403846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2369403846
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.225054300
Short name T163
Test name
Test status
Simulation time 33107294 ps
CPU time 2.48 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201912 kb
Host smart-47dded3d-a72d-4422-ab3e-a4c5b306eebd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=225054300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.225054300
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.3021946813
Short name T387
Test name
Test status
Simulation time 170256996 ps
CPU time 1.38 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201864 kb
Host smart-c69c2d02-4e31-4e5e-b9ae-70c44d673b8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3021946813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3021946813
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3609687952
Short name T535
Test name
Test status
Simulation time 3503721610 ps
CPU time 8.69 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201980 kb
Host smart-cef8af1c-6547-42b9-8ea6-ac9c6b557779
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609687952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3609687952
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2408892150
Short name T158
Test name
Test status
Simulation time 982715496 ps
CPU time 7.11 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201892 kb
Host smart-2eb72135-baf4-49cc-901e-1511aa09fc05
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2408892150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2408892150
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2772790229
Short name T247
Test name
Test status
Simulation time 16743730 ps
CPU time 1.12 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:18 PM PDT 24
Peak memory 201932 kb
Host smart-7f1992cd-f2b6-4100-8984-f6628112fe5b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772790229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2772790229
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1401874728
Short name T861
Test name
Test status
Simulation time 9834661 ps
CPU time 1.11 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201896 kb
Host smart-f0512ca3-e3b5-4216-9fcc-288734ac46b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1401874728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1401874728
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3281873459
Short name T609
Test name
Test status
Simulation time 1294495022 ps
CPU time 17.26 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:37 PM PDT 24
Peak memory 201820 kb
Host smart-5cee42d5-1d1e-4c7a-8b33-1aa5b5221696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281873459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3281873459
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.968858293
Short name T114
Test name
Test status
Simulation time 9320525871 ps
CPU time 27.09 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 204040 kb
Host smart-383281c5-4095-4428-8f26-85c3320d63bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=968858293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand
_reset.968858293
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.925462705
Short name T380
Test name
Test status
Simulation time 820102619 ps
CPU time 118.47 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 205580 kb
Host smart-77f1c173-6ea4-44dc-9613-8f2b0d22fdd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925462705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res
et_error.925462705
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1336063575
Short name T128
Test name
Test status
Simulation time 82658814 ps
CPU time 1.99 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201884 kb
Host smart-9e8b8d0f-d802-4f4e-800e-482d40d1e49b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1336063575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1336063575
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1351564635
Short name T432
Test name
Test status
Simulation time 44102664 ps
CPU time 2.93 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201912 kb
Host smart-0532ecf3-99ca-447e-8cdb-2b97cba71b90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1351564635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1351564635
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1653750448
Short name T258
Test name
Test status
Simulation time 15650247171 ps
CPU time 88.92 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:58:51 PM PDT 24
Peak memory 202044 kb
Host smart-b5b602a8-e006-460b-bfdd-328c599402b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1653750448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1653750448
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3296074993
Short name T653
Test name
Test status
Simulation time 204940327 ps
CPU time 4.71 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201904 kb
Host smart-a2794a7d-a63c-4e94-b166-64b6f55e52af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296074993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3296074993
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2755933562
Short name T808
Test name
Test status
Simulation time 166828227 ps
CPU time 4.52 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 201884 kb
Host smart-043c6e4b-991f-476c-a6ce-543f730c6994
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2755933562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2755933562
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.681210402
Short name T523
Test name
Test status
Simulation time 53104417 ps
CPU time 7.34 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201872 kb
Host smart-585f2531-dc8d-4f49-82c2-7308414f0bff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681210402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.681210402
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.4258620185
Short name T842
Test name
Test status
Simulation time 8080585079 ps
CPU time 35.09 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:58:02 PM PDT 24
Peak memory 202048 kb
Host smart-c00bf63b-1dcf-45bb-ac19-a07f3f91aaed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258620185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4258620185
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1710264360
Short name T74
Test name
Test status
Simulation time 62047457070 ps
CPU time 129.45 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:59:30 PM PDT 24
Peak memory 202028 kb
Host smart-a3fd78d8-c7b2-4f76-99b5-062a47305492
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1710264360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1710264360
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2398557384
Short name T639
Test name
Test status
Simulation time 126035387 ps
CPU time 9.02 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201928 kb
Host smart-d3e87c67-8a8b-4b26-98bc-587750b41dde
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398557384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2398557384
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.2771013534
Short name T97
Test name
Test status
Simulation time 4549605299 ps
CPU time 11.75 seconds
Started Mar 12 12:57:26 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 202012 kb
Host smart-b494586f-27ea-48af-b976-64d9ddbe7495
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2771013534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2771013534
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.2126088493
Short name T519
Test name
Test status
Simulation time 8744482 ps
CPU time 1.12 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201760 kb
Host smart-10eaac77-0b7b-4e24-84e9-f8c669c60ba3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2126088493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2126088493
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.340113230
Short name T679
Test name
Test status
Simulation time 3435190640 ps
CPU time 9.27 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 202036 kb
Host smart-1bd7e4bb-cbbd-4527-acf9-8f2b6cf22550
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=340113230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.340113230
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.583241023
Short name T428
Test name
Test status
Simulation time 1620808129 ps
CPU time 8.85 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 201904 kb
Host smart-4a235595-b7c4-43f5-a601-d25079c0652d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=583241023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.583241023
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1583143677
Short name T672
Test name
Test status
Simulation time 12846315 ps
CPU time 1.38 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201828 kb
Host smart-b86f4f4a-ba46-49d8-a67c-8320f74a8051
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583143677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1583143677
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.488704475
Short name T222
Test name
Test status
Simulation time 1635817064 ps
CPU time 32.08 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:53 PM PDT 24
Peak memory 202936 kb
Host smart-51edb752-02f0-4c70-9d9b-e133d4d8c536
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=488704475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.488704475
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1039099552
Short name T171
Test name
Test status
Simulation time 335771722 ps
CPU time 21.92 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:43 PM PDT 24
Peak memory 201932 kb
Host smart-97b85490-05fe-49a0-808f-b5f3b4353cb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1039099552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1039099552
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1931311737
Short name T392
Test name
Test status
Simulation time 520823753 ps
CPU time 33.39 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:55 PM PDT 24
Peak memory 203964 kb
Host smart-a00f3daa-a2b9-4a77-8e67-bce2531be9e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931311737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1931311737
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1971850967
Short name T802
Test name
Test status
Simulation time 89868995 ps
CPU time 14.8 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:36 PM PDT 24
Peak memory 201900 kb
Host smart-f7c8283d-ed1d-406c-80c3-c3e8ce14efb1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1971850967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1971850967
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2211030312
Short name T545
Test name
Test status
Simulation time 322311346 ps
CPU time 6.85 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201900 kb
Host smart-2eb4ef29-b85b-4b1f-981d-7b185d72e7b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2211030312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2211030312
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3335601724
Short name T776
Test name
Test status
Simulation time 197989899 ps
CPU time 4.45 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201908 kb
Host smart-e5487337-0893-47e8-a527-36b3765777c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335601724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3335601724
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1727632615
Short name T206
Test name
Test status
Simulation time 959237588 ps
CPU time 11.62 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201872 kb
Host smart-89ae2a75-120e-4a2f-996b-db6e87276c5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1727632615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1727632615
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.94081515
Short name T575
Test name
Test status
Simulation time 60930854 ps
CPU time 5.42 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201880 kb
Host smart-a3dd5856-ee59-4d83-87bc-c9a4bb6a8658
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94081515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.94081515
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2876982836
Short name T896
Test name
Test status
Simulation time 17905163 ps
CPU time 1.81 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201856 kb
Host smart-ea0dcf44-09d4-468b-91d8-6e28b4f927e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2876982836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2876982836
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.608655162
Short name T551
Test name
Test status
Simulation time 11312709357 ps
CPU time 37.81 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:54 PM PDT 24
Peak memory 201772 kb
Host smart-6fa56062-1d53-4c7f-a5a8-8216bf87c2e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=608655162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.608655162
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.599780558
Short name T823
Test name
Test status
Simulation time 14255106760 ps
CPU time 90.55 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:58:45 PM PDT 24
Peak memory 201916 kb
Host smart-a262779b-470f-41c6-ae4f-4adc4ce74e53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=599780558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.599780558
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1324311695
Short name T385
Test name
Test status
Simulation time 54605113 ps
CPU time 4.84 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 201852 kb
Host smart-302449f6-2950-46a9-9fb4-1153190c2020
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324311695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1324311695
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2188736348
Short name T735
Test name
Test status
Simulation time 117434059 ps
CPU time 5.14 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201884 kb
Host smart-317ff0f2-efc8-410b-94a5-274cbd560c87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188736348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2188736348
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.4127569092
Short name T295
Test name
Test status
Simulation time 247266222 ps
CPU time 1.76 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 201872 kb
Host smart-a1e181fe-a69c-4b3b-a11e-8be7507d2587
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4127569092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4127569092
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1693890667
Short name T573
Test name
Test status
Simulation time 3237676675 ps
CPU time 13.4 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 201968 kb
Host smart-876eb470-4d9d-4172-8f56-fffa803e3d3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693890667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1693890667
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2858425203
Short name T772
Test name
Test status
Simulation time 2280372173 ps
CPU time 7.3 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:33 PM PDT 24
Peak memory 201964 kb
Host smart-af648a12-b909-4f75-b54c-1bd2f77e934a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2858425203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2858425203
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2841283012
Short name T860
Test name
Test status
Simulation time 9166194 ps
CPU time 1.16 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201844 kb
Host smart-b804cf3f-0537-45fa-ae4c-f41dc83b048f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841283012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2841283012
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.4247451316
Short name T747
Test name
Test status
Simulation time 88216759 ps
CPU time 9.49 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201900 kb
Host smart-d5cf1446-c612-4f4f-bf7e-71950ea3dac8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4247451316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4247451316
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2011214481
Short name T547
Test name
Test status
Simulation time 143298073 ps
CPU time 19.83 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 201936 kb
Host smart-325a577a-496a-4b0c-9c4f-0fbe16cf1156
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2011214481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2011214481
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4211233227
Short name T594
Test name
Test status
Simulation time 399471839 ps
CPU time 50.57 seconds
Started Mar 12 12:57:15 PM PDT 24
Finished Mar 12 12:58:06 PM PDT 24
Peak memory 203880 kb
Host smart-38c2ab41-2e37-440d-9c43-a75a44c598be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4211233227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.4211233227
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2842016415
Short name T486
Test name
Test status
Simulation time 4695929763 ps
CPU time 103.74 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:59:05 PM PDT 24
Peak memory 204364 kb
Host smart-05bc6fbf-e820-4bf6-a6f9-2acf358c86db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2842016415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2842016415
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.961452486
Short name T243
Test name
Test status
Simulation time 1348715539 ps
CPU time 6.2 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201796 kb
Host smart-b9c7fe4e-7642-4d40-b2eb-c64457668870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=961452486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.961452486
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3857326925
Short name T105
Test name
Test status
Simulation time 1395808251 ps
CPU time 18.5 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:36 PM PDT 24
Peak memory 201900 kb
Host smart-4294814a-f85b-45fe-ba69-d7954444caaa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3857326925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3857326925
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2197616309
Short name T271
Test name
Test status
Simulation time 43074946839 ps
CPU time 247.87 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 01:01:26 PM PDT 24
Peak memory 203008 kb
Host smart-ab95a6fb-d0b7-437e-af74-e1deacb1c8ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2197616309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.2197616309
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.83683241
Short name T343
Test name
Test status
Simulation time 3166642746 ps
CPU time 7.92 seconds
Started Mar 12 12:57:10 PM PDT 24
Finished Mar 12 12:57:18 PM PDT 24
Peak memory 202020 kb
Host smart-b5e8c75d-2665-4fe6-bfb7-6b53a6883a30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83683241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.83683241
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.1680190701
Short name T603
Test name
Test status
Simulation time 980937628 ps
CPU time 9.33 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201896 kb
Host smart-99d0a98b-7cce-4bd1-bdfa-7cd9505d5513
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680190701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1680190701
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1454757252
Short name T215
Test name
Test status
Simulation time 48997306 ps
CPU time 1.51 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201852 kb
Host smart-63fc4003-2ae2-4e8e-a096-2f12ac1d214e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454757252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1454757252
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1014307421
Short name T729
Test name
Test status
Simulation time 19423128176 ps
CPU time 86.04 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:58:43 PM PDT 24
Peak memory 202004 kb
Host smart-acb3028e-0776-4769-8624-92ae4aa1791f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014307421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1014307421
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.972522268
Short name T32
Test name
Test status
Simulation time 8053107893 ps
CPU time 31.22 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:54 PM PDT 24
Peak memory 201408 kb
Host smart-1854fc5c-f8ac-425a-be6f-8750eac7ea47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=972522268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.972522268
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3777135960
Short name T183
Test name
Test status
Simulation time 104380075 ps
CPU time 8.71 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201768 kb
Host smart-a35368ec-89a3-4153-b499-0d4bc0703af4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777135960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3777135960
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.3791751017
Short name T732
Test name
Test status
Simulation time 930164988 ps
CPU time 9.74 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 201904 kb
Host smart-a99f356f-f585-4c8c-80e9-2f6983b80829
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3791751017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3791751017
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.2784155331
Short name T824
Test name
Test status
Simulation time 9372269 ps
CPU time 1.14 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201908 kb
Host smart-580e42cc-2407-479b-a0a2-3ab80a9af172
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2784155331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2784155331
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3694103313
Short name T812
Test name
Test status
Simulation time 1796622302 ps
CPU time 8.31 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201904 kb
Host smart-db4c1bd6-5afb-4640-b3a6-3a13e185b5fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694103313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3694103313
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1179424623
Short name T694
Test name
Test status
Simulation time 615620717 ps
CPU time 5.53 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201924 kb
Host smart-89743afb-ae41-4ca2-8e73-da2ba34ccfd1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1179424623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1179424623
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3332057464
Short name T289
Test name
Test status
Simulation time 9325160 ps
CPU time 1.24 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 201908 kb
Host smart-8aeac7ac-3280-4105-a118-fe58dc1d18cf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332057464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3332057464
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3498069099
Short name T248
Test name
Test status
Simulation time 369597055 ps
CPU time 23.39 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:46 PM PDT 24
Peak memory 201912 kb
Host smart-c901e085-2d99-43ce-8c11-5a791a59eef3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3498069099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3498069099
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1061200922
Short name T257
Test name
Test status
Simulation time 18523279582 ps
CPU time 85.58 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:58:45 PM PDT 24
Peak memory 201996 kb
Host smart-27a0f3ac-6e90-4ae7-b7a6-1cb67fd686ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1061200922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1061200922
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.31152646
Short name T104
Test name
Test status
Simulation time 4833378604 ps
CPU time 126.92 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:59:29 PM PDT 24
Peak memory 204580 kb
Host smart-755df4ae-f5ce-4c0f-b5d7-7dba7f90ea93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31152646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_
reset.31152646
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4202422985
Short name T619
Test name
Test status
Simulation time 414743606 ps
CPU time 18.32 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 202896 kb
Host smart-cb8c108f-e16c-492c-be90-224eb0cd90a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4202422985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.4202422985
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.69266116
Short name T565
Test name
Test status
Simulation time 44228190 ps
CPU time 5.48 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201788 kb
Host smart-edd7e514-b2a6-4616-9cb0-fe928aa6fb89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69266116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.69266116
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1904746116
Short name T596
Test name
Test status
Simulation time 216371028 ps
CPU time 6.62 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 201928 kb
Host smart-b75563a1-13a2-4cf6-8098-9c396a72a629
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1904746116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1904746116
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2381786402
Short name T537
Test name
Test status
Simulation time 2526279939 ps
CPU time 14.41 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 202040 kb
Host smart-6601ff0e-3e0e-47ae-aba4-0601074d013f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2381786402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2381786402
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2870971123
Short name T306
Test name
Test status
Simulation time 347252892 ps
CPU time 5.16 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201916 kb
Host smart-0e766fe1-7971-478a-aaf7-fc29537c999e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2870971123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2870971123
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.2136790492
Short name T412
Test name
Test status
Simulation time 54331958 ps
CPU time 1.59 seconds
Started Mar 12 12:57:25 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201892 kb
Host smart-82838741-9354-4b07-a3fc-1fb106b9f2e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2136790492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2136790492
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.2826285325
Short name T457
Test name
Test status
Simulation time 25560017 ps
CPU time 2.84 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 201712 kb
Host smart-564eaa87-993f-435f-8aff-b790fb4a3f14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2826285325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2826285325
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2051365098
Short name T403
Test name
Test status
Simulation time 5749487984 ps
CPU time 24.96 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 202024 kb
Host smart-2967d45c-3065-4cf7-969e-7a6007db76d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051365098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2051365098
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3512054309
Short name T179
Test name
Test status
Simulation time 30462211672 ps
CPU time 114 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 202068 kb
Host smart-2a1cf9ba-94b5-4a3d-a941-4cda7bc45c8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3512054309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3512054309
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3857236804
Short name T816
Test name
Test status
Simulation time 60721175 ps
CPU time 7.34 seconds
Started Mar 12 12:57:21 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201892 kb
Host smart-c5f5773c-30de-45fa-a292-122da383daa6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857236804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3857236804
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3061091623
Short name T770
Test name
Test status
Simulation time 52433251 ps
CPU time 4.99 seconds
Started Mar 12 12:57:27 PM PDT 24
Finished Mar 12 12:57:32 PM PDT 24
Peak memory 201928 kb
Host smart-78c8288d-7edf-4829-a1d3-675350c7e142
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3061091623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3061091623
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.3074394998
Short name T630
Test name
Test status
Simulation time 178944781 ps
CPU time 1.38 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:16 PM PDT 24
Peak memory 201848 kb
Host smart-965860f6-8451-4068-8ffa-eecc93eb7d02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3074394998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3074394998
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.835511316
Short name T383
Test name
Test status
Simulation time 3915773431 ps
CPU time 7.97 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201704 kb
Host smart-bf957a7d-fdbd-486f-ae4a-f3a85fa53ab3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=835511316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.835511316
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2556025768
Short name T369
Test name
Test status
Simulation time 6285625156 ps
CPU time 8.63 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:27 PM PDT 24
Peak memory 201928 kb
Host smart-f50e4087-00d1-4b40-960b-c89af7051b91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2556025768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2556025768
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2435896787
Short name T785
Test name
Test status
Simulation time 40126612 ps
CPU time 1.2 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201908 kb
Host smart-36cbdb20-c4ff-45f9-b9e8-a094a9976608
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435896787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2435896787
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1642982651
Short name T99
Test name
Test status
Simulation time 4819485390 ps
CPU time 115.69 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 204464 kb
Host smart-eda5bb47-2780-40fe-881f-13950f1d6db6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1642982651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1642982651
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2474253123
Short name T864
Test name
Test status
Simulation time 10233727262 ps
CPU time 26.28 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:45 PM PDT 24
Peak memory 202056 kb
Host smart-16c42c8e-7438-43c4-974f-04a67833db9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2474253123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2474253123
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.574653577
Short name T245
Test name
Test status
Simulation time 662977658 ps
CPU time 73.09 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:58:35 PM PDT 24
Peak memory 206408 kb
Host smart-18286b36-9908-41b4-838f-9010b59fae55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=574653577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand
_reset.574653577
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2786215172
Short name T690
Test name
Test status
Simulation time 7148351007 ps
CPU time 110.07 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:59:09 PM PDT 24
Peak memory 204680 kb
Host smart-92df2740-cf69-453e-a843-e483490e833a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2786215172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.2786215172
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.742453724
Short name T853
Test name
Test status
Simulation time 67927622 ps
CPU time 5.86 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201908 kb
Host smart-59b4308a-8bd0-4ec3-b2b0-d7d51f1fa2fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742453724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.742453724
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1589474681
Short name T317
Test name
Test status
Simulation time 1253367009 ps
CPU time 19.62 seconds
Started Mar 12 12:57:18 PM PDT 24
Finished Mar 12 12:57:38 PM PDT 24
Peak memory 201908 kb
Host smart-e9ba3c45-1477-4517-a703-e8dfcbefe71b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589474681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1589474681
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.482735486
Short name T23
Test name
Test status
Simulation time 79048285275 ps
CPU time 250.25 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 01:01:30 PM PDT 24
Peak memory 202920 kb
Host smart-f1ea2ad8-71ef-4a3a-a981-3e24e89e77b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=482735486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo
w_rsp.482735486
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3442421242
Short name T643
Test name
Test status
Simulation time 362016687 ps
CPU time 7.46 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:57:25 PM PDT 24
Peak memory 201928 kb
Host smart-f15ed989-f9d4-4f90-9fa4-b4f45338d779
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3442421242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3442421242
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.114075995
Short name T664
Test name
Test status
Simulation time 57589850 ps
CPU time 3.21 seconds
Started Mar 12 12:57:16 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 201788 kb
Host smart-35d4947a-e91e-4931-ac3c-fe3c7fc9d382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114075995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.114075995
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.3247895359
Short name T567
Test name
Test status
Simulation time 13254880 ps
CPU time 1.08 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:26 PM PDT 24
Peak memory 201792 kb
Host smart-0f5ab1b7-1e69-4e58-bd37-54f062ee29ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3247895359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3247895359
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3729444326
Short name T352
Test name
Test status
Simulation time 64481498325 ps
CPU time 144.32 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:59:42 PM PDT 24
Peak memory 201980 kb
Host smart-1c14d929-086e-4843-aeb5-5ece8839ea44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729444326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3729444326
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2352944839
Short name T445
Test name
Test status
Simulation time 20821295980 ps
CPU time 98.4 seconds
Started Mar 12 12:57:17 PM PDT 24
Finished Mar 12 12:58:56 PM PDT 24
Peak memory 202060 kb
Host smart-16e297fe-822a-499d-b58b-72d5bb531cb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2352944839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2352944839
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.277864197
Short name T203
Test name
Test status
Simulation time 32305536 ps
CPU time 4.56 seconds
Started Mar 12 12:57:09 PM PDT 24
Finished Mar 12 12:57:14 PM PDT 24
Peak memory 201732 kb
Host smart-0c71e420-bb5f-4550-8d75-48e129981a62
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277864197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.277864197
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.415675299
Short name T599
Test name
Test status
Simulation time 324067429 ps
CPU time 5.71 seconds
Started Mar 12 12:57:14 PM PDT 24
Finished Mar 12 12:57:20 PM PDT 24
Peak memory 201784 kb
Host smart-2b2201ce-5617-4052-a4dd-e1a5602ee3d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=415675299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.415675299
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.4201691757
Short name T885
Test name
Test status
Simulation time 60603490 ps
CPU time 1.59 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:24 PM PDT 24
Peak memory 201828 kb
Host smart-d7e9a7a0-e8b8-4e01-9205-bf4a8c77b969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4201691757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4201691757
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1701577998
Short name T568
Test name
Test status
Simulation time 5854438729 ps
CPU time 12.45 seconds
Started Mar 12 12:57:24 PM PDT 24
Finished Mar 12 12:57:37 PM PDT 24
Peak memory 201964 kb
Host smart-afaea0e4-24aa-4873-a670-bf3ddaaeb46f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701577998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1701577998
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4019038192
Short name T378
Test name
Test status
Simulation time 1043880023 ps
CPU time 6.89 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:29 PM PDT 24
Peak memory 201888 kb
Host smart-3a6c629d-948f-4258-ba00-54afe7aabf9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4019038192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4019038192
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3673750194
Short name T344
Test name
Test status
Simulation time 9914327 ps
CPU time 1.13 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201896 kb
Host smart-eef783cd-3972-4dbb-a30c-df05e3cd3755
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673750194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3673750194
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1616222161
Short name T529
Test name
Test status
Simulation time 345986278 ps
CPU time 5.77 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201912 kb
Host smart-c444ec70-d12c-434d-95a5-71311a3d6c97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1616222161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1616222161
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3227458942
Short name T91
Test name
Test status
Simulation time 733236899 ps
CPU time 25.07 seconds
Started Mar 12 12:57:22 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 201920 kb
Host smart-fb3d7c47-eeb5-4646-a4b3-0d6229acd9b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227458942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3227458942
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.868389549
Short name T607
Test name
Test status
Simulation time 69277379 ps
CPU time 9.9 seconds
Started Mar 12 12:57:20 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 202796 kb
Host smart-32f349e6-eb45-4348-a428-1c1f29f02fe5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=868389549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.868389549
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3985776736
Short name T278
Test name
Test status
Simulation time 40945185 ps
CPU time 4.16 seconds
Started Mar 12 12:57:23 PM PDT 24
Finished Mar 12 12:57:28 PM PDT 24
Peak memory 201888 kb
Host smart-f074e483-7d63-48d2-bcd1-d5ae67e2c8bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3985776736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.3985776736
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.959173718
Short name T835
Test name
Test status
Simulation time 22488529 ps
CPU time 2.49 seconds
Started Mar 12 12:57:19 PM PDT 24
Finished Mar 12 12:57:22 PM PDT 24
Peak memory 201812 kb
Host smart-da05accc-512b-473b-9ab4-1d361ce02169
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959173718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.959173718
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.4236977327
Short name T167
Test name
Test status
Simulation time 722361225 ps
CPU time 13.5 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:55:23 PM PDT 24
Peak memory 201880 kb
Host smart-2a49c5c0-b384-43c7-a202-611073dc54c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236977327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4236977327
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3964877300
Short name T267
Test name
Test status
Simulation time 58791107292 ps
CPU time 308.59 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 01:00:04 PM PDT 24
Peak memory 204516 kb
Host smart-3a07e281-941c-4418-8539-51b74f211c60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3964877300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3964877300
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2045707297
Short name T611
Test name
Test status
Simulation time 20946037 ps
CPU time 2.2 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:55:12 PM PDT 24
Peak memory 201916 kb
Host smart-a2b677a3-e60d-4606-ae16-2da63e505639
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045707297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2045707297
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.439963148
Short name T235
Test name
Test status
Simulation time 1416738096 ps
CPU time 14.2 seconds
Started Mar 12 12:55:07 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 201892 kb
Host smart-b08b5940-ab7f-48bb-bdbb-47ad260945bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=439963148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.439963148
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.602983526
Short name T146
Test name
Test status
Simulation time 199972420 ps
CPU time 3.6 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201900 kb
Host smart-4e85f22d-d806-4a43-99f1-3d2bf9861e4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=602983526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.602983526
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4039869055
Short name T610
Test name
Test status
Simulation time 61403246609 ps
CPU time 88.94 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:56:20 PM PDT 24
Peak memory 202072 kb
Host smart-49852be7-02bc-43a5-af10-11fca574b39f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039869055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4039869055
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.183602740
Short name T489
Test name
Test status
Simulation time 9374515231 ps
CPU time 60.84 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:55 PM PDT 24
Peak memory 202060 kb
Host smart-cc8644e7-492f-49c1-8589-d357bfaba756
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=183602740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.183602740
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.980483842
Short name T597
Test name
Test status
Simulation time 32699097 ps
CPU time 4.31 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201940 kb
Host smart-57ba2bce-5f14-4b59-8da8-2ecb8c083243
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980483842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.980483842
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.2908041652
Short name T620
Test name
Test status
Simulation time 186393016 ps
CPU time 2.74 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201944 kb
Host smart-fdb84109-dc52-4365-9c72-a767ac84ea52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2908041652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2908041652
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1988399784
Short name T681
Test name
Test status
Simulation time 44635087 ps
CPU time 1.48 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201908 kb
Host smart-94397a63-01ad-473c-bbbf-de11eac1d025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1988399784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1988399784
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.139421293
Short name T388
Test name
Test status
Simulation time 2095478207 ps
CPU time 10.29 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201912 kb
Host smart-c367d119-fed2-4b42-9480-b61c80a0f8d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=139421293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.139421293
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3898862935
Short name T320
Test name
Test status
Simulation time 2895685305 ps
CPU time 9.17 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 202032 kb
Host smart-1a9b3464-f12f-4093-9124-249c49996487
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3898862935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3898862935
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1337946992
Short name T297
Test name
Test status
Simulation time 15723198 ps
CPU time 1.29 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:54:59 PM PDT 24
Peak memory 201932 kb
Host smart-25cd2d81-e677-4c0d-88e3-7a258210790b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337946992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1337946992
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.53582904
Short name T799
Test name
Test status
Simulation time 2644103248 ps
CPU time 41.84 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:55:53 PM PDT 24
Peak memory 201976 kb
Host smart-8203762f-419c-4e7c-9757-b6603f07a67a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53582904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.53582904
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1470196130
Short name T702
Test name
Test status
Simulation time 4294335758 ps
CPU time 62.06 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:59 PM PDT 24
Peak memory 201588 kb
Host smart-e9f6e4c4-4e7d-44ed-aa55-5c179e9155e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1470196130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1470196130
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3334526121
Short name T121
Test name
Test status
Simulation time 6332101718 ps
CPU time 107.41 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:56:46 PM PDT 24
Peak memory 205608 kb
Host smart-ba91705f-9e58-4269-858a-d159c18da8b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3334526121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3334526121
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.406086526
Short name T503
Test name
Test status
Simulation time 5255367100 ps
CPU time 100 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:56:31 PM PDT 24
Peak memory 207228 kb
Host smart-5a85c6ea-cb21-48a8-90ad-dbc8b3e77ae1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406086526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese
t_error.406086526
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3197050413
Short name T872
Test name
Test status
Simulation time 581446857 ps
CPU time 4.64 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201940 kb
Host smart-1aa59b83-c0ee-4734-a471-320ef44ac32a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3197050413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3197050413
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3264128675
Short name T36
Test name
Test status
Simulation time 82770387 ps
CPU time 2.6 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201940 kb
Host smart-a7a3597d-fe70-4301-a322-ed0ee598aa47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3264128675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3264128675
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1756976684
Short name T106
Test name
Test status
Simulation time 46118227457 ps
CPU time 339.64 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 01:00:36 PM PDT 24
Peak memory 204104 kb
Host smart-94962483-cd07-41c3-a1a5-316f70c7ca1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1756976684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.1756976684
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2525498769
Short name T449
Test name
Test status
Simulation time 61151937 ps
CPU time 5.51 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:55:01 PM PDT 24
Peak memory 201892 kb
Host smart-79f973f4-d451-421a-8aad-f268cfaae1a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2525498769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2525498769
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.384707269
Short name T379
Test name
Test status
Simulation time 52028011 ps
CPU time 5.29 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201928 kb
Host smart-9641491a-0970-44d6-8c29-9d0bcdb30b8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=384707269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.384707269
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.977284893
Short name T79
Test name
Test status
Simulation time 3189925868 ps
CPU time 15 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:55:16 PM PDT 24
Peak memory 202000 kb
Host smart-107fdd3f-edf0-4ade-912b-c9a740266c3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=977284893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.977284893
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2498404924
Short name T738
Test name
Test status
Simulation time 64843150245 ps
CPU time 160.06 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:57:37 PM PDT 24
Peak memory 202064 kb
Host smart-ca07b52e-9d94-4fe9-864c-dd8898ff4af7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498404924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2498404924
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.4205847838
Short name T381
Test name
Test status
Simulation time 5740703184 ps
CPU time 30.02 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:22 PM PDT 24
Peak memory 202064 kb
Host smart-b9121b6e-c82c-4ee8-8b5b-a404bc11863c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4205847838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4205847838
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1128058226
Short name T391
Test name
Test status
Simulation time 21093245 ps
CPU time 2.54 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 201884 kb
Host smart-aebba0a6-094a-4729-8648-c179d8a78955
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128058226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1128058226
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.770804666
Short name T750
Test name
Test status
Simulation time 44173400 ps
CPU time 4.12 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201900 kb
Host smart-99ac3dff-091d-4484-aafa-722c5d535f25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=770804666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.770804666
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.3671868008
Short name T337
Test name
Test status
Simulation time 10682458 ps
CPU time 1.22 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201856 kb
Host smart-f25048e3-4b71-4c22-b0b1-4e603b4e11b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671868008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3671868008
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.356049338
Short name T234
Test name
Test status
Simulation time 13620928343 ps
CPU time 10.92 seconds
Started Mar 12 12:55:08 PM PDT 24
Finished Mar 12 12:55:19 PM PDT 24
Peak memory 202012 kb
Host smart-c8b0c1b1-fe67-45c0-8310-639806cdfeca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=356049338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.356049338
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2741885183
Short name T345
Test name
Test status
Simulation time 4400248274 ps
CPU time 12.78 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 202000 kb
Host smart-3ce88913-3cc2-457e-ac1c-0717936966ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2741885183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2741885183
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4101963821
Short name T140
Test name
Test status
Simulation time 10072019 ps
CPU time 1.22 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:01 PM PDT 24
Peak memory 201912 kb
Host smart-420c142c-abfb-4a81-8329-496019b64962
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101963821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4101963821
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1988707999
Short name T475
Test name
Test status
Simulation time 125180479 ps
CPU time 3.24 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201912 kb
Host smart-41f7fd3b-96a9-4985-9ee2-08a19fcbc0b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1988707999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1988707999
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4197873804
Short name T473
Test name
Test status
Simulation time 101242691 ps
CPU time 9.22 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 201892 kb
Host smart-14ff4a90-551a-4fb7-b400-734a8aed628e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197873804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4197873804
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.518262530
Short name T507
Test name
Test status
Simulation time 2216060216 ps
CPU time 93.82 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:56:32 PM PDT 24
Peak memory 206436 kb
Host smart-ba7f74b4-4e5e-4f13-ab39-0d9df3b0c58d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518262530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.518262530
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1084385336
Short name T8
Test name
Test status
Simulation time 1585619056 ps
CPU time 204.31 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 210084 kb
Host smart-b58d7406-3c24-49f4-8a53-0f087b3de91b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1084385336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1084385336
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2158103900
Short name T736
Test name
Test status
Simulation time 14011148 ps
CPU time 1.63 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201892 kb
Host smart-4bbae448-9599-4472-9e1f-e15c5d4a0f86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158103900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2158103900
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2610442003
Short name T29
Test name
Test status
Simulation time 712986252 ps
CPU time 12.1 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:06 PM PDT 24
Peak memory 201936 kb
Host smart-4893fa18-0215-4fad-8f41-d363b3c8728f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2610442003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2610442003
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2026989774
Short name T260
Test name
Test status
Simulation time 56306549469 ps
CPU time 203.86 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:58:24 PM PDT 24
Peak memory 203068 kb
Host smart-bd32748c-215d-431d-81c7-dd6be9c28dd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2026989774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.2026989774
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3918235800
Short name T283
Test name
Test status
Simulation time 40304709 ps
CPU time 4.24 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201908 kb
Host smart-62b09df8-9e75-48d8-8d99-2c9f4d2bff0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3918235800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3918235800
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3757892207
Short name T406
Test name
Test status
Simulation time 227192621 ps
CPU time 6.45 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201912 kb
Host smart-865fe1fa-40e9-45ed-ae58-3345498a5dc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3757892207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3757892207
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.1304067918
Short name T629
Test name
Test status
Simulation time 2195972990 ps
CPU time 8.19 seconds
Started Mar 12 12:55:04 PM PDT 24
Finished Mar 12 12:55:13 PM PDT 24
Peak memory 201944 kb
Host smart-af85cc68-a0cc-4692-88b2-1a9e4a73972d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1304067918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1304067918
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3387482425
Short name T89
Test name
Test status
Simulation time 6375528376 ps
CPU time 6.42 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 202044 kb
Host smart-9b4a9b4a-7618-4c48-bf2b-d82ecd58ea0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387482425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3387482425
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.752177890
Short name T186
Test name
Test status
Simulation time 2895300564 ps
CPU time 20.39 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:55:14 PM PDT 24
Peak memory 202044 kb
Host smart-1a1e256d-4bf2-4cf4-9b32-c3406d46552e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=752177890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.752177890
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2106824865
Short name T50
Test name
Test status
Simulation time 31640408 ps
CPU time 4.64 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:01 PM PDT 24
Peak memory 201932 kb
Host smart-ab3f9e12-56a5-4c65-abbd-5f36192e1378
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106824865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2106824865
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.1050510117
Short name T28
Test name
Test status
Simulation time 191533422 ps
CPU time 2.82 seconds
Started Mar 12 12:54:59 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 201904 kb
Host smart-76c190ba-a963-4d13-9305-07f76138180f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1050510117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1050510117
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.1844715220
Short name T22
Test name
Test status
Simulation time 9039307 ps
CPU time 1.04 seconds
Started Mar 12 12:54:50 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201896 kb
Host smart-1a8a234a-96d7-4e06-b3b2-a277831d9e5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1844715220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1844715220
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2042287457
Short name T399
Test name
Test status
Simulation time 3653415152 ps
CPU time 9.66 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:06 PM PDT 24
Peak memory 202044 kb
Host smart-4d44c5be-cb0f-4c55-8aeb-e35cc0bb885a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042287457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2042287457
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2989224120
Short name T133
Test name
Test status
Simulation time 1948081438 ps
CPU time 13.47 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:05 PM PDT 24
Peak memory 201936 kb
Host smart-8155bdc7-3b85-446d-9c69-655334b09096
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2989224120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2989224120
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2569129070
Short name T348
Test name
Test status
Simulation time 13199245 ps
CPU time 1.28 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:55:10 PM PDT 24
Peak memory 201884 kb
Host smart-49b59146-8a3c-4638-9887-a43899244518
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569129070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2569129070
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.4047247141
Short name T229
Test name
Test status
Simulation time 842476942 ps
CPU time 9.21 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 201912 kb
Host smart-950c59a9-b132-4e06-ac99-a71d23c871d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4047247141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4047247141
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2769624661
Short name T181
Test name
Test status
Simulation time 2211229671 ps
CPU time 20.92 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:18 PM PDT 24
Peak memory 202088 kb
Host smart-9d807ef1-2baf-43df-90e0-beb3e2d1c306
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769624661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2769624661
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1092870425
Short name T334
Test name
Test status
Simulation time 171827624 ps
CPU time 41.98 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:34 PM PDT 24
Peak memory 203424 kb
Host smart-e85b1be4-f8da-42a2-943a-5a7b9d3babae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1092870425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1092870425
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3820776447
Short name T277
Test name
Test status
Simulation time 1421365608 ps
CPU time 140.77 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:57:19 PM PDT 24
Peak memory 205764 kb
Host smart-f2a1ed9f-808e-4319-b496-601a2cb5c8a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820776447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.3820776447
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1679563436
Short name T450
Test name
Test status
Simulation time 8698320 ps
CPU time 1.07 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201908 kb
Host smart-34fb81c0-b765-4a63-8af3-0ebeeec428da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1679563436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1679563436
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3453607071
Short name T126
Test name
Test status
Simulation time 521290198 ps
CPU time 8.2 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201936 kb
Host smart-79ad1253-04bb-47cb-a232-e6268a1339bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3453607071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3453607071
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.251736248
Short name T895
Test name
Test status
Simulation time 82315469 ps
CPU time 3.44 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:54:59 PM PDT 24
Peak memory 201888 kb
Host smart-1d192a65-a1a2-4895-b7c2-8572825bd039
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=251736248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.251736248
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.1150797842
Short name T739
Test name
Test status
Simulation time 50137038 ps
CPU time 3.1 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:54:56 PM PDT 24
Peak memory 201956 kb
Host smart-cc624482-e141-4b2b-933b-1574950d83a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1150797842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1150797842
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1926957426
Short name T721
Test name
Test status
Simulation time 143982776 ps
CPU time 2.77 seconds
Started Mar 12 12:54:55 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201888 kb
Host smart-ed20b8bc-cbd2-4f3b-8e48-8548c3823386
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1926957426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1926957426
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2401102750
Short name T282
Test name
Test status
Simulation time 36207614009 ps
CPU time 128.78 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:57:06 PM PDT 24
Peak memory 201500 kb
Host smart-afd833cd-60ae-435b-82d4-311454b63e34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401102750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2401102750
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.419499279
Short name T543
Test name
Test status
Simulation time 73059772054 ps
CPU time 107.33 seconds
Started Mar 12 12:54:54 PM PDT 24
Finished Mar 12 12:56:41 PM PDT 24
Peak memory 202060 kb
Host smart-ed4242e4-e702-4829-881c-90e9e166da56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=419499279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.419499279
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3930450772
Short name T188
Test name
Test status
Simulation time 187609600 ps
CPU time 6.21 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:03 PM PDT 24
Peak memory 201872 kb
Host smart-af298686-f780-4c31-9bb1-027c2959eddf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930450772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3930450772
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.731238062
Short name T786
Test name
Test status
Simulation time 340496229 ps
CPU time 5.73 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:06 PM PDT 24
Peak memory 201868 kb
Host smart-f64714ed-4b49-46c3-9ced-649111bbc4eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=731238062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.731238062
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.3624891698
Short name T794
Test name
Test status
Simulation time 47114341 ps
CPU time 1.31 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:01 PM PDT 24
Peak memory 201848 kb
Host smart-59dd3daf-cf04-472a-a5e7-32c1251b90d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3624891698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3624891698
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1205586245
Short name T510
Test name
Test status
Simulation time 4474059888 ps
CPU time 9.17 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 202072 kb
Host smart-9debc182-1a7a-49e3-8bf2-39ff21a89dfb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205586245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1205586245
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.534242105
Short name T491
Test name
Test status
Simulation time 9172720681 ps
CPU time 9.11 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 202032 kb
Host smart-8fb40f2f-4bbc-4867-a30d-9822df519056
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=534242105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.534242105
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2455620510
Short name T14
Test name
Test status
Simulation time 14270429 ps
CPU time 1.13 seconds
Started Mar 12 12:54:57 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201964 kb
Host smart-b18a6e2d-c3c5-4bf7-987e-77863f52cd19
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455620510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2455620510
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2207064279
Short name T360
Test name
Test status
Simulation time 5541118983 ps
CPU time 89.55 seconds
Started Mar 12 12:54:53 PM PDT 24
Finished Mar 12 12:56:23 PM PDT 24
Peak memory 203308 kb
Host smart-0a5c3de0-25bf-4471-9ea5-669e1837d2f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2207064279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2207064279
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4216009689
Short name T663
Test name
Test status
Simulation time 11704823942 ps
CPU time 51.53 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:55:50 PM PDT 24
Peak memory 202068 kb
Host smart-ed7f0163-0e81-484b-aa63-6721bd9a299c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4216009689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4216009689
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.119573765
Short name T870
Test name
Test status
Simulation time 8656773181 ps
CPU time 71.69 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 204072 kb
Host smart-d220e932-2953-489c-8724-3ad0ae210fc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=119573765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.119573765
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.619225756
Short name T788
Test name
Test status
Simulation time 27694755 ps
CPU time 2.1 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201888 kb
Host smart-2334891f-4614-420a-afdc-ca54cc07ae64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619225756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.619225756
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1071446408
Short name T508
Test name
Test status
Simulation time 1237924243 ps
CPU time 17.37 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:55:19 PM PDT 24
Peak memory 201900 kb
Host smart-3fd184dc-b01f-495f-946c-4584ba70a6dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1071446408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1071446408
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1813049493
Short name T665
Test name
Test status
Simulation time 27145641877 ps
CPU time 178.24 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:57:57 PM PDT 24
Peak memory 202984 kb
Host smart-6b38246d-f4d7-4527-b470-3c047bf790f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1813049493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.1813049493
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4200718361
Short name T322
Test name
Test status
Simulation time 63539748 ps
CPU time 6.67 seconds
Started Mar 12 12:55:05 PM PDT 24
Finished Mar 12 12:55:12 PM PDT 24
Peak memory 201900 kb
Host smart-300a57ce-49ba-4ad9-a801-6954e06c5fa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4200718361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4200718361
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2849557463
Short name T160
Test name
Test status
Simulation time 241450170 ps
CPU time 4.96 seconds
Started Mar 12 12:55:09 PM PDT 24
Finished Mar 12 12:55:14 PM PDT 24
Peak memory 201788 kb
Host smart-6c7dad0f-7542-46d6-91e5-66e1a7621125
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2849557463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2849557463
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2301526354
Short name T239
Test name
Test status
Simulation time 331084008 ps
CPU time 6.43 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:07 PM PDT 24
Peak memory 201792 kb
Host smart-28ed1ae9-f421-42dc-873f-61ad2a8d877b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301526354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2301526354
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.685606506
Short name T485
Test name
Test status
Simulation time 1695198485 ps
CPU time 8.91 seconds
Started Mar 12 12:55:00 PM PDT 24
Finished Mar 12 12:55:09 PM PDT 24
Peak memory 201920 kb
Host smart-f3d099f1-03dc-43dc-a084-a571bf1d09e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=685606506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.685606506
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2515255940
Short name T813
Test name
Test status
Simulation time 5650240898 ps
CPU time 39.2 seconds
Started Mar 12 12:55:04 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 202028 kb
Host smart-4f2a4547-4d50-4e1c-8009-3c6e206009a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2515255940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2515255940
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4167441272
Short name T441
Test name
Test status
Simulation time 40368184 ps
CPU time 4.27 seconds
Started Mar 12 12:54:56 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 201836 kb
Host smart-c89c7e4b-3392-4999-ad35-e87439161143
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167441272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4167441272
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.1293937980
Short name T196
Test name
Test status
Simulation time 159921174 ps
CPU time 2.17 seconds
Started Mar 12 12:55:15 PM PDT 24
Finished Mar 12 12:55:17 PM PDT 24
Peak memory 201912 kb
Host smart-311337ac-fc96-4024-bd1f-5e9cd9abbd18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293937980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1293937980
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3779921170
Short name T112
Test name
Test status
Simulation time 63028286 ps
CPU time 1.65 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:54 PM PDT 24
Peak memory 201904 kb
Host smart-717cf10d-4019-476c-8cab-53dc9c5d11e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779921170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3779921170
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.428625065
Short name T855
Test name
Test status
Simulation time 2466255666 ps
CPU time 11.13 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 202076 kb
Host smart-a4226dca-cccd-464d-b4ce-78172657f0e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=428625065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.428625065
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1741582315
Short name T402
Test name
Test status
Simulation time 864836609 ps
CPU time 6.18 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:54:57 PM PDT 24
Peak memory 201924 kb
Host smart-97fd111e-2552-4ae3-ada4-80e10b2b280d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1741582315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1741582315
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2985450364
Short name T440
Test name
Test status
Simulation time 9270309 ps
CPU time 1.18 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 201908 kb
Host smart-241f5c21-058f-45ba-bea6-04543c01830a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985450364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2985450364
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3584044815
Short name T493
Test name
Test status
Simulation time 6409481591 ps
CPU time 93.83 seconds
Started Mar 12 12:55:01 PM PDT 24
Finished Mar 12 12:56:35 PM PDT 24
Peak memory 204124 kb
Host smart-f7da7c65-0be4-465a-be9a-fbfed911d9f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3584044815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3584044815
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3707505883
Short name T19
Test name
Test status
Simulation time 264208144 ps
CPU time 3.58 seconds
Started Mar 12 12:55:11 PM PDT 24
Finished Mar 12 12:55:15 PM PDT 24
Peak memory 201908 kb
Host smart-659b4ff6-a715-40eb-8595-991f885f1074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3707505883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3707505883
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.718978995
Short name T296
Test name
Test status
Simulation time 33692922 ps
CPU time 6.28 seconds
Started Mar 12 12:55:05 PM PDT 24
Finished Mar 12 12:55:11 PM PDT 24
Peak memory 201900 kb
Host smart-198b2175-9537-4ca6-9187-d9570ed509f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=718978995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese
t_error.718978995
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.182408532
Short name T641
Test name
Test status
Simulation time 1398301839 ps
CPU time 6.78 seconds
Started Mar 12 12:54:58 PM PDT 24
Finished Mar 12 12:55:05 PM PDT 24
Peak memory 201892 kb
Host smart-44174750-1ddb-4d08-9741-89d3ecd30abf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=182408532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.182408532
Directory /workspace/9.xbar_unmapped_addr/latest
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