Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 430 1 T40 3 T22 6 T9 3
all_values[1] 471 1 T40 2 T22 9 T9 6
all_values[2] 421 1 T40 3 T23 1 T22 3
all_values[3] 403 1 T22 6 T183 9 T118 2
all_values[4] 439 1 T40 2 T22 3 T9 7
all_values[5] 451 1 T40 1 T22 8 T9 2
all_values[6] 447 1 T40 1 T22 7 T9 3
all_values[7] 443 1 T40 1 T22 9 T9 3
all_values[8] 470 1 T40 2 T22 3 T9 1
all_values[9] 413 1 T21 1 T22 7 T9 4
all_values[10] 397 1 T12 1 T22 5 T9 8
all_values[11] 389 1 T12 1 T22 4 T9 3
all_values[12] 422 1 T12 1 T40 1 T21 2
all_values[13] 397 1 T40 2 T22 2 T9 2
all_values[14] 440 1 T23 1 T22 6 T9 4
all_values[15] 434 1 T40 2 T22 8 T9 5
all_values[16] 452 1 T40 2 T22 7 T9 1
all_values[17] 418 1 T40 2 T22 2 T9 4
all_values[18] 448 1 T40 1 T23 1 T22 7
all_values[19] 410 1 T40 1 T23 1 T22 8
all_values[20] 439 1 T12 1 T40 1 T22 5
all_values[21] 411 1 T40 2 T22 6 T9 4
all_values[22] 456 1 T40 3 T22 9 T9 4
all_values[23] 440 1 T40 1 T22 4 T9 2
all_values[24] 436 1 T40 1 T23 1 T22 6
all_values[25] 439 1 T40 1 T23 1 T22 6
all_values[26] 489 1 T40 1 T23 1 T22 7

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