Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	424	1			T4	3		T16	7		T7	9
all_values[1]	418	1			T4	5		T16	4		T7	7
all_values[2]	413	1			T4	1		T16	8		T7	6
all_values[3]	478	1			T4	4		T14	1		T16	5
all_values[4]	455	1			T4	1		T16	11		T7	10
all_values[5]	409	1			T4	3		T16	8		T7	3
all_values[6]	420	1			T4	5		T16	7		T7	7
all_values[7]	442	1			T4	6		T16	6		T7	7
all_values[8]	439	1			T1	1		T4	5		T16	9
all_values[9]	456	1			T4	4		T16	4		T7	7
all_values[10]	437	1			T1	1		T4	5		T14	1
all_values[11]	484	1			T4	3		T16	6		T7	3
all_values[12]	467	1			T4	9		T16	4		T7	5
all_values[13]	425	1			T4	2		T16	9		T7	5
all_values[14]	436	1			T4	3		T16	3		T7	10
all_values[15]	434	1			T4	7		T16	5		T7	10
all_values[16]	392	1			T4	1		T14	1		T16	3
all_values[17]	444	1			T4	4		T16	9		T7	6
all_values[18]	438	1			T1	1		T4	6		T16	7
all_values[19]	423	1			T4	5		T16	2		T7	7
all_values[20]	426	1			T1	1		T4	5		T16	6
all_values[21]	459	1			T4	5		T16	9		T7	7
all_values[22]	417	1			T1	1		T4	2		T16	5
all_values[23]	442	1			T1	1		T4	6		T16	6
all_values[24]	407	1			T4	5		T14	2		T16	8
all_values[25]	444	1			T4	5		T16	5		T7	4
all_values[26]	428	1			T4	4		T16	3		T7	7