Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	467	1			T1	2		T5	7		T22	1
all_values[1]	489	1			T5	7		T27	1		T40	5
all_values[2]	473	1			T5	7		T30	1		T40	5
all_values[3]	447	1			T5	7		T40	9		T41	4
all_values[4]	482	1			T5	4		T40	5		T41	4
all_values[5]	501	1			T5	5		T40	7		T41	6
all_values[6]	468	1			T1	2		T5	1		T40	5
all_values[7]	513	1			T5	5		T40	8		T41	4
all_values[8]	503	1			T5	4		T40	5		T41	4
all_values[9]	444	1			T1	1		T5	1		T40	5
all_values[10]	509	1			T5	9		T40	7		T41	2
all_values[11]	480	1			T5	5		T40	6		T41	6
all_values[12]	485	1			T5	5		T40	4		T41	6
all_values[13]	491	1			T5	8		T40	5		T41	4
all_values[14]	430	1			T5	3		T40	9		T41	4
all_values[15]	481	1			T5	7		T22	1		T30	1
all_values[16]	474	1			T5	6		T22	1		T40	6
all_values[17]	460	1			T5	5		T40	8		T41	6
all_values[18]	492	1			T1	1		T5	8		T27	2
all_values[19]	476	1			T1	1		T5	6		T30	1
all_values[20]	518	1			T1	1		T5	4		T30	1
all_values[21]	463	1			T1	1		T5	4		T30	2
all_values[22]	463	1			T5	9		T40	4		T41	6
all_values[23]	489	1			T5	7		T22	1		T40	4
all_values[24]	496	1			T5	5		T40	6		T41	3
all_values[25]	486	1			T1	1		T5	4		T22	1
all_values[26]	516	1			T1	1		T5	5		T40	8