Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 453 1 T2 1 T5 3 T16 1
all_values[1] 446 1 T2 2 T5 3 T18 5
all_values[2] 438 1 T2 2 T5 2 T18 5
all_values[3] 438 1 T5 1 T18 7 T23 1
all_values[4] 424 1 T5 3 T16 1 T18 2
all_values[5] 423 1 T5 2 T18 4 T23 2
all_values[6] 427 1 T2 3 T5 1 T16 1
all_values[7] 381 1 T5 2 T18 4 T23 2
all_values[8] 399 1 T2 1 T18 1 T19 1
all_values[9] 449 1 T5 2 T16 1 T18 3
all_values[10] 448 1 T2 3 T5 1 T18 4
all_values[11] 422 1 T2 3 T5 2 T16 1
all_values[12] 409 1 T2 1 T5 1 T18 1
all_values[13] 392 1 T2 1 T5 2 T23 4
all_values[14] 416 1 T2 3 T5 4 T18 4
all_values[15] 398 1 T2 5 T5 1 T18 4
all_values[16] 424 1 T2 3 T5 1 T16 1
all_values[17] 392 1 T2 4 T5 1 T18 3
all_values[18] 398 1 T2 5 T5 1 T16 1
all_values[19] 431 1 T5 1 T18 3 T19 1
all_values[20] 407 1 T2 1 T5 2 T18 3
all_values[21] 432 1 T2 6 T5 6 T16 1
all_values[22] 421 1 T2 2 T5 2 T18 5
all_values[23] 443 1 T2 3 T5 4 T16 2
all_values[24] 394 1 T2 2 T16 1 T18 4
all_values[25] 431 1 T2 4 T5 5 T18 2
all_values[26] 460 1 T5 2 T18 3 T19 1

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