Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	491	1			T5	6		T4	3		T16	3
all_values[1]	447	1			T5	4		T4	2		T16	3
all_values[2]	472	1			T5	4		T24	2		T16	4
all_values[3]	458	1			T5	2		T4	1		T16	5
all_values[4]	441	1			T5	1		T24	1		T16	10
all_values[5]	494	1			T5	3		T4	2		T16	1
all_values[6]	485	1			T5	5		T4	3		T24	1
all_values[7]	500	1			T5	6		T4	4		T16	1
all_values[8]	436	1			T5	5		T4	3		T24	1
all_values[9]	430	1			T5	1		T4	1		T16	7
all_values[10]	462	1			T5	3		T4	2		T24	1
all_values[11]	451	1			T5	1		T24	1		T16	4
all_values[12]	458	1			T5	6		T4	2		T24	1
all_values[13]	436	1			T5	1		T4	2		T24	1
all_values[14]	448	1			T5	1		T4	1		T23	1
all_values[15]	450	1			T4	2		T16	4		T29	2
all_values[16]	467	1			T5	5		T4	1		T16	3
all_values[17]	429	1			T5	3		T4	1		T24	1
all_values[18]	417	1			T5	4		T24	1		T16	2
all_values[19]	483	1			T2	1		T5	1		T16	2
all_values[20]	432	1			T5	3		T23	1		T16	3
all_values[21]	450	1			T5	2		T24	2		T16	5
all_values[22]	462	1			T5	5		T24	1		T16	9
all_values[23]	406	1			T5	3		T16	4		T59	3
all_values[24]	475	1			T5	4		T4	2		T16	3
all_values[25]	453	1			T5	3		T4	1		T16	3
all_values[26]	458	1			T5	4		T23	1		T16	2