Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 447 1 T14 1 T17 4 T76 6
all_values[1] 432 1 T17 2 T76 4 T47 1
all_values[2] 488 1 T17 2 T42 2 T43 3
all_values[3] 472 1 T17 2 T76 2 T181 1
all_values[4] 458 1 T17 2 T22 1 T42 1
all_values[5] 471 1 T17 1 T42 2 T43 2
all_values[6] 450 1 T17 2 T22 1 T43 3
all_values[7] 458 1 T14 1 T17 4 T42 1
all_values[8] 481 1 T17 3 T22 1 T76 5
all_values[9] 474 1 T17 2 T22 1 T42 2
all_values[10] 461 1 T17 1 T22 2 T42 1
all_values[11] 474 1 T14 1 T17 1 T22 1
all_values[12] 428 1 T14 1 T17 1 T42 1
all_values[13] 421 1 T17 2 T42 1 T43 1
all_values[14] 462 1 T17 1 T76 3 T182 1
all_values[15] 489 1 T17 1 T22 2 T76 1
all_values[16] 442 1 T17 1 T42 1 T43 2
all_values[17] 440 1 T14 1 T17 3 T76 1
all_values[18] 461 1 T42 1 T43 2 T76 4
all_values[19] 494 1 T17 2 T22 1 T43 1
all_values[20] 488 1 T17 1 T42 1 T43 1
all_values[21] 456 1 T17 1 T76 3 T181 1
all_values[22] 468 1 T14 1 T17 4 T43 1
all_values[23] 498 1 T17 4 T22 4 T43 1
all_values[24] 432 1 T17 1 T22 1 T42 2
all_values[25] 467 1 T14 1 T17 2 T76 2
all_values[26] 497 1 T14 1 T17 1 T42 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%