Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	100.00	95.52	100.00		100.00	100.00	100.00

Total test records in report: 900

T762	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4258949776	Apr 18 12:39:46 PM PDT 24	Apr 18 12:40:34 PM PDT 24	10659837896 ps
T763	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.4172042379	Apr 18 12:39:41 PM PDT 24	Apr 18 12:40:42 PM PDT 24	9265459434 ps
T764	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3680959228	Apr 18 12:40:06 PM PDT 24	Apr 18 12:40:15 PM PDT 24	3836817652 ps
T765	/workspace/coverage/xbar_build_mode/45.xbar_error_random.2264405009	Apr 18 12:40:12 PM PDT 24	Apr 18 12:40:15 PM PDT 24	12227714 ps
T766	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1527499054	Apr 18 12:39:24 PM PDT 24	Apr 18 12:39:26 PM PDT 24	8265874 ps
T767	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2377122712	Apr 18 12:38:45 PM PDT 24	Apr 18 12:38:54 PM PDT 24	1547011596 ps
T768	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2258640044	Apr 18 12:40:14 PM PDT 24	Apr 18 12:40:17 PM PDT 24	13865712 ps
T769	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3133964480	Apr 18 12:40:29 PM PDT 24	Apr 18 12:40:36 PM PDT 24	114405863 ps
T770	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.4102673818	Apr 18 12:39:59 PM PDT 24	Apr 18 12:40:18 PM PDT 24	3571714434 ps
T771	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3470517494	Apr 18 12:40:35 PM PDT 24	Apr 18 12:40:42 PM PDT 24	603142300 ps
T772	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3748299073	Apr 18 12:38:33 PM PDT 24	Apr 18 12:40:52 PM PDT 24	35523621550 ps
T773	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1868420159	Apr 18 12:39:32 PM PDT 24	Apr 18 12:39:43 PM PDT 24	4886511569 ps
T774	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2880903876	Apr 18 12:39:07 PM PDT 24	Apr 18 12:39:27 PM PDT 24	1011377129 ps
T775	/workspace/coverage/xbar_build_mode/44.xbar_error_random.2796028954	Apr 18 12:40:15 PM PDT 24	Apr 18 12:40:19 PM PDT 24	24599153 ps
T776	/workspace/coverage/xbar_build_mode/25.xbar_same_source.1695303995	Apr 18 12:39:18 PM PDT 24	Apr 18 12:39:22 PM PDT 24	231833840 ps
T777	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1417925227	Apr 18 12:40:15 PM PDT 24	Apr 18 12:42:42 PM PDT 24	79016579333 ps
T778	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1592143961	Apr 18 12:39:08 PM PDT 24	Apr 18 12:39:16 PM PDT 24	186152179 ps
T779	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2893833047	Apr 18 12:39:51 PM PDT 24	Apr 18 12:39:59 PM PDT 24	2166464789 ps
T780	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2780515526	Apr 18 12:39:06 PM PDT 24	Apr 18 12:39:14 PM PDT 24	8541814 ps
T781	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.986501369	Apr 18 12:39:25 PM PDT 24	Apr 18 12:40:04 PM PDT 24	40096162043 ps
T782	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3895704828	Apr 18 12:38:26 PM PDT 24	Apr 18 12:38:38 PM PDT 24	2303485916 ps
T783	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2922938819	Apr 18 12:38:39 PM PDT 24	Apr 18 12:38:48 PM PDT 24	2377328141 ps
T784	/workspace/coverage/xbar_build_mode/34.xbar_same_source.2207322027	Apr 18 12:39:54 PM PDT 24	Apr 18 12:40:07 PM PDT 24	748196445 ps
T785	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2888287818	Apr 18 12:39:58 PM PDT 24	Apr 18 12:40:04 PM PDT 24	53389001 ps
T786	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.806468302	Apr 18 12:38:29 PM PDT 24	Apr 18 12:38:39 PM PDT 24	326660698 ps
T787	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1923108622	Apr 18 12:38:46 PM PDT 24	Apr 18 12:38:51 PM PDT 24	154536482 ps
T788	/workspace/coverage/xbar_build_mode/28.xbar_smoke.1533572041	Apr 18 12:39:37 PM PDT 24	Apr 18 12:39:39 PM PDT 24	18704255 ps
T789	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.130801322	Apr 18 12:38:33 PM PDT 24	Apr 18 12:38:54 PM PDT 24	6034689568 ps
T790	/workspace/coverage/xbar_build_mode/43.xbar_error_random.3417466823	Apr 18 12:40:16 PM PDT 24	Apr 18 12:40:28 PM PDT 24	1725649268 ps
T791	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2835772981	Apr 18 12:38:55 PM PDT 24	Apr 18 12:39:04 PM PDT 24	1323498990 ps
T33	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4113728932	Apr 18 12:39:39 PM PDT 24	Apr 18 12:39:46 PM PDT 24	2531428292 ps
T792	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3128612175	Apr 18 12:40:38 PM PDT 24	Apr 18 12:42:30 PM PDT 24	26799449774 ps
T793	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2496908039	Apr 18 12:39:08 PM PDT 24	Apr 18 12:40:07 PM PDT 24	433349336 ps
T794	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3317873610	Apr 18 12:39:12 PM PDT 24	Apr 18 12:39:33 PM PDT 24	1490975876 ps
T795	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.663623818	Apr 18 12:39:22 PM PDT 24	Apr 18 12:40:05 PM PDT 24	8199801164 ps
T796	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1203467732	Apr 18 12:38:31 PM PDT 24	Apr 18 12:39:27 PM PDT 24	1948598588 ps
T797	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.59809026	Apr 18 12:39:08 PM PDT 24	Apr 18 12:39:27 PM PDT 24	5090116755 ps
T798	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3275265078	Apr 18 12:38:34 PM PDT 24	Apr 18 12:38:37 PM PDT 24	140767968 ps
T799	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1454656141	Apr 18 12:40:42 PM PDT 24	Apr 18 12:43:38 PM PDT 24	27931273761 ps
T800	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.958146596	Apr 18 12:40:01 PM PDT 24	Apr 18 12:40:23 PM PDT 24	2452898541 ps
T801	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3135891675	Apr 18 12:40:10 PM PDT 24	Apr 18 12:40:52 PM PDT 24	419575663 ps
T802	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3045528041	Apr 18 12:39:55 PM PDT 24	Apr 18 12:40:03 PM PDT 24	910156551 ps
T803	/workspace/coverage/xbar_build_mode/48.xbar_random.845317667	Apr 18 12:40:37 PM PDT 24	Apr 18 12:40:43 PM PDT 24	53183508 ps
T804	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3153534374	Apr 18 12:40:14 PM PDT 24	Apr 18 12:41:47 PM PDT 24	100094455332 ps
T805	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.172325741	Apr 18 12:40:47 PM PDT 24	Apr 18 12:40:57 PM PDT 24	1635507414 ps
T806	/workspace/coverage/xbar_build_mode/26.xbar_same_source.1355903388	Apr 18 12:39:21 PM PDT 24	Apr 18 12:39:34 PM PDT 24	3692899447 ps
T807	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3727763839	Apr 18 12:39:04 PM PDT 24	Apr 18 12:39:06 PM PDT 24	13088461 ps
T808	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1492713152	Apr 18 12:39:12 PM PDT 24	Apr 18 12:40:43 PM PDT 24	536520231 ps
T809	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3836556669	Apr 18 12:39:59 PM PDT 24	Apr 18 12:40:06 PM PDT 24	48162143 ps
T810	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2934799321	Apr 18 12:38:57 PM PDT 24	Apr 18 12:39:45 PM PDT 24	10618273503 ps
T34	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2604788386	Apr 18 12:39:39 PM PDT 24	Apr 18 12:39:48 PM PDT 24	1300407607 ps
T811	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3906534846	Apr 18 12:39:27 PM PDT 24	Apr 18 12:39:35 PM PDT 24	206584499 ps
T812	/workspace/coverage/xbar_build_mode/8.xbar_same_source.1118730493	Apr 18 12:39:00 PM PDT 24	Apr 18 12:39:08 PM PDT 24	4316761312 ps
T813	/workspace/coverage/xbar_build_mode/18.xbar_random.4088235757	Apr 18 12:39:11 PM PDT 24	Apr 18 12:39:16 PM PDT 24	113581987 ps
T814	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3790611244	Apr 18 12:40:05 PM PDT 24	Apr 18 12:40:11 PM PDT 24	94723446 ps
T815	/workspace/coverage/xbar_build_mode/39.xbar_same_source.870645098	Apr 18 12:39:57 PM PDT 24	Apr 18 12:40:14 PM PDT 24	647298968 ps
T816	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1526489638	Apr 18 12:39:25 PM PDT 24	Apr 18 12:39:31 PM PDT 24	33984239 ps
T109	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.811762268	Apr 18 12:39:52 PM PDT 24	Apr 18 12:41:08 PM PDT 24	4139353682 ps
T817	/workspace/coverage/xbar_build_mode/30.xbar_smoke.2742420137	Apr 18 12:39:32 PM PDT 24	Apr 18 12:39:35 PM PDT 24	56067128 ps
T818	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1383101105	Apr 18 12:39:57 PM PDT 24	Apr 18 12:42:59 PM PDT 24	943041873 ps
T141	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.420988485	Apr 18 12:39:44 PM PDT 24	Apr 18 12:40:04 PM PDT 24	1206827230 ps
T819	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3544269851	Apr 18 12:39:56 PM PDT 24	Apr 18 12:40:44 PM PDT 24	29419375009 ps
T820	/workspace/coverage/xbar_build_mode/45.xbar_smoke.1115961639	Apr 18 12:40:19 PM PDT 24	Apr 18 12:40:21 PM PDT 24	67255462 ps
T821	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1409405379	Apr 18 12:38:54 PM PDT 24	Apr 18 12:40:06 PM PDT 24	620473782 ps
T822	/workspace/coverage/xbar_build_mode/0.xbar_smoke.4136038501	Apr 18 12:38:25 PM PDT 24	Apr 18 12:38:26 PM PDT 24	10158552 ps
T823	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3957259271	Apr 18 12:39:17 PM PDT 24	Apr 18 12:41:53 PM PDT 24	37146168973 ps
T10	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2097776001	Apr 18 12:39:01 PM PDT 24	Apr 18 12:40:29 PM PDT 24	428461309 ps
T824	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2825973949	Apr 18 12:40:24 PM PDT 24	Apr 18 12:40:26 PM PDT 24	10154507 ps
T825	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.4087038185	Apr 18 12:40:12 PM PDT 24	Apr 18 12:40:17 PM PDT 24	117991732 ps
T826	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2106674912	Apr 18 12:39:56 PM PDT 24	Apr 18 12:40:10 PM PDT 24	876633976 ps
T110	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.380103907	Apr 18 12:38:26 PM PDT 24	Apr 18 12:38:40 PM PDT 24	1181255386 ps
T827	/workspace/coverage/xbar_build_mode/28.xbar_random.3542058188	Apr 18 12:39:30 PM PDT 24	Apr 18 12:39:40 PM PDT 24	59426954 ps
T828	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3480029072	Apr 18 12:38:28 PM PDT 24	Apr 18 12:38:38 PM PDT 24	8898015644 ps
T829	/workspace/coverage/xbar_build_mode/32.xbar_error_random.422213484	Apr 18 12:39:46 PM PDT 24	Apr 18 12:39:51 PM PDT 24	193323064 ps
T830	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1668768754	Apr 18 12:39:26 PM PDT 24	Apr 18 12:39:35 PM PDT 24	817260777 ps
T831	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3634145907	Apr 18 12:39:31 PM PDT 24	Apr 18 12:42:14 PM PDT 24	95179166381 ps
T146	/workspace/coverage/xbar_build_mode/0.xbar_random.3116336886	Apr 18 12:38:20 PM PDT 24	Apr 18 12:38:28 PM PDT 24	423372325 ps
T832	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1773193039	Apr 18 12:39:42 PM PDT 24	Apr 18 12:39:47 PM PDT 24	240751150 ps
T833	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.11289024	Apr 18 12:40:03 PM PDT 24	Apr 18 12:40:31 PM PDT 24	1136888157 ps
T834	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.1849455986	Apr 18 12:38:59 PM PDT 24	Apr 18 12:39:01 PM PDT 24	6699929 ps
T835	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2471821994	Apr 18 12:38:47 PM PDT 24	Apr 18 12:39:24 PM PDT 24	2744416822 ps
T836	/workspace/coverage/xbar_build_mode/36.xbar_same_source.100071178	Apr 18 12:39:59 PM PDT 24	Apr 18 12:40:07 PM PDT 24	49147784 ps
T837	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1388938036	Apr 18 12:38:30 PM PDT 24	Apr 18 12:38:37 PM PDT 24	2079604288 ps
T838	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2258352125	Apr 18 12:39:29 PM PDT 24	Apr 18 12:40:19 PM PDT 24	3431610308 ps
T839	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.751267740	Apr 18 12:40:38 PM PDT 24	Apr 18 12:41:01 PM PDT 24	244797242 ps
T840	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4154909542	Apr 18 12:38:55 PM PDT 24	Apr 18 12:39:29 PM PDT 24	6148564639 ps
T841	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2764444815	Apr 18 12:39:06 PM PDT 24	Apr 18 12:39:17 PM PDT 24	894929294 ps
T842	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2441802283	Apr 18 12:38:50 PM PDT 24	Apr 18 12:39:10 PM PDT 24	146551917 ps
T843	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1714266508	Apr 18 12:39:41 PM PDT 24	Apr 18 12:39:49 PM PDT 24	64155128 ps
T844	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2552658350	Apr 18 12:39:10 PM PDT 24	Apr 18 12:39:24 PM PDT 24	7800661047 ps
T35	/workspace/coverage/xbar_build_mode/26.xbar_smoke.3254851020	Apr 18 12:39:15 PM PDT 24	Apr 18 12:39:18 PM PDT 24	86637701 ps
T845	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2097886858	Apr 18 12:40:04 PM PDT 24	Apr 18 12:41:01 PM PDT 24	11359827089 ps
T846	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2300257852	Apr 18 12:38:33 PM PDT 24	Apr 18 12:38:40 PM PDT 24	4051308062 ps
T847	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.443697885	Apr 18 12:40:01 PM PDT 24	Apr 18 12:40:16 PM PDT 24	3461671628 ps
T848	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1956430504	Apr 18 12:39:12 PM PDT 24	Apr 18 12:39:23 PM PDT 24	65214300 ps
T849	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1256945248	Apr 18 12:39:59 PM PDT 24	Apr 18 12:40:08 PM PDT 24	106748626 ps
T850	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3168209977	Apr 18 12:40:13 PM PDT 24	Apr 18 12:41:04 PM PDT 24	20568217830 ps
T851	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2333223873	Apr 18 12:40:14 PM PDT 24	Apr 18 12:40:17 PM PDT 24	22591956 ps
T852	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1160577843	Apr 18 12:39:37 PM PDT 24	Apr 18 12:40:29 PM PDT 24	758677624 ps
T853	/workspace/coverage/xbar_build_mode/20.xbar_same_source.2756711223	Apr 18 12:39:13 PM PDT 24	Apr 18 12:39:25 PM PDT 24	6195004747 ps
T854	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2496319830	Apr 18 12:40:19 PM PDT 24	Apr 18 12:41:36 PM PDT 24	2568156925 ps
T855	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1141743035	Apr 18 12:39:20 PM PDT 24	Apr 18 12:39:45 PM PDT 24	3677673587 ps
T856	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1598074529	Apr 18 12:39:37 PM PDT 24	Apr 18 12:41:16 PM PDT 24	25344551124 ps
T857	/workspace/coverage/xbar_build_mode/13.xbar_error_random.3477845872	Apr 18 12:39:07 PM PDT 24	Apr 18 12:39:19 PM PDT 24	4332096805 ps
T858	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1875837383	Apr 18 12:39:38 PM PDT 24	Apr 18 12:39:47 PM PDT 24	1733498477 ps
T859	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3461381609	Apr 18 12:38:28 PM PDT 24	Apr 18 12:39:06 PM PDT 24	241624078 ps
T860	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2117239439	Apr 18 12:39:29 PM PDT 24	Apr 18 12:39:49 PM PDT 24	2759279169 ps
T861	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3093254388	Apr 18 12:39:26 PM PDT 24	Apr 18 12:39:29 PM PDT 24	26137946 ps
T862	/workspace/coverage/xbar_build_mode/32.xbar_same_source.3513362297	Apr 18 12:39:39 PM PDT 24	Apr 18 12:39:41 PM PDT 24	19952538 ps
T863	/workspace/coverage/xbar_build_mode/26.xbar_error_random.3449228293	Apr 18 12:39:27 PM PDT 24	Apr 18 12:39:45 PM PDT 24	5352092167 ps
T864	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.719790611	Apr 18 12:39:10 PM PDT 24	Apr 18 12:39:17 PM PDT 24	45130114 ps
T865	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.923177142	Apr 18 12:39:13 PM PDT 24	Apr 18 12:41:24 PM PDT 24	19338355032 ps
T866	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2638206589	Apr 18 12:38:26 PM PDT 24	Apr 18 12:38:40 PM PDT 24	1021562741 ps
T867	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2302467343	Apr 18 12:39:57 PM PDT 24	Apr 18 12:40:18 PM PDT 24	3433245306 ps
T868	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2828488717	Apr 18 12:40:12 PM PDT 24	Apr 18 12:40:18 PM PDT 24	128047158 ps
T869	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.960151006	Apr 18 12:39:27 PM PDT 24	Apr 18 12:39:31 PM PDT 24	101069229 ps
T131	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2336922819	Apr 18 12:39:07 PM PDT 24	Apr 18 12:39:18 PM PDT 24	2936547994 ps
T870	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1946742403	Apr 18 12:39:58 PM PDT 24	Apr 18 12:40:23 PM PDT 24	6026985444 ps
T871	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1499516826	Apr 18 12:39:07 PM PDT 24	Apr 18 12:39:17 PM PDT 24	2552508987 ps
T9	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4157275132	Apr 18 12:40:07 PM PDT 24	Apr 18 12:41:36 PM PDT 24	745381192 ps
T872	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.423587543	Apr 18 12:39:48 PM PDT 24	Apr 18 12:39:56 PM PDT 24	49974048 ps
T873	/workspace/coverage/xbar_build_mode/3.xbar_smoke.2946562951	Apr 18 12:38:28 PM PDT 24	Apr 18 12:38:31 PM PDT 24	38915136 ps
T874	/workspace/coverage/xbar_build_mode/5.xbar_error_random.4058047392	Apr 18 12:38:33 PM PDT 24	Apr 18 12:38:46 PM PDT 24	826231924 ps
T875	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3316625329	Apr 18 12:38:29 PM PDT 24	Apr 18 12:38:41 PM PDT 24	900209358 ps
T876	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1833406795	Apr 18 12:39:20 PM PDT 24	Apr 18 12:39:29 PM PDT 24	766174409 ps
T877	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1966532233	Apr 18 12:40:25 PM PDT 24	Apr 18 12:40:35 PM PDT 24	531034264 ps
T878	/workspace/coverage/xbar_build_mode/13.xbar_smoke.2111004007	Apr 18 12:39:05 PM PDT 24	Apr 18 12:39:08 PM PDT 24	81597882 ps
T879	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1126027953	Apr 18 12:40:04 PM PDT 24	Apr 18 12:40:14 PM PDT 24	1615778457 ps
T880	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1296429778	Apr 18 12:39:20 PM PDT 24	Apr 18 12:39:29 PM PDT 24	4078136082 ps
T881	/workspace/coverage/xbar_build_mode/9.xbar_random.1555944806	Apr 18 12:38:38 PM PDT 24	Apr 18 12:38:43 PM PDT 24	43153049 ps
T882	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.4216072009	Apr 18 12:40:14 PM PDT 24	Apr 18 12:40:27 PM PDT 24	2344674865 ps
T883	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1636997468	Apr 18 12:40:35 PM PDT 24	Apr 18 12:42:09 PM PDT 24	2688809684 ps
T884	/workspace/coverage/xbar_build_mode/30.xbar_random.3685207683	Apr 18 12:39:42 PM PDT 24	Apr 18 12:39:58 PM PDT 24	4033675489 ps
T885	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3978202230	Apr 18 12:39:36 PM PDT 24	Apr 18 12:39:39 PM PDT 24	35930023 ps
T886	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2866872102	Apr 18 12:39:11 PM PDT 24	Apr 18 12:39:46 PM PDT 24	7357898847 ps
T887	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2751269354	Apr 18 12:38:34 PM PDT 24	Apr 18 12:38:39 PM PDT 24	327916317 ps
T888	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.788294793	Apr 18 12:40:20 PM PDT 24	Apr 18 12:40:45 PM PDT 24	3338661856 ps
T889	/workspace/coverage/xbar_build_mode/27.xbar_smoke.414054338	Apr 18 12:39:24 PM PDT 24	Apr 18 12:39:27 PM PDT 24	16761386 ps
T890	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.4167519881	Apr 18 12:40:18 PM PDT 24	Apr 18 12:41:02 PM PDT 24	5125571307 ps
T891	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.2142377842	Apr 18 12:39:32 PM PDT 24	Apr 18 12:39:45 PM PDT 24	5943872853 ps
T892	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1919480223	Apr 18 12:39:50 PM PDT 24	Apr 18 12:39:52 PM PDT 24	8509551 ps
T893	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.743252241	Apr 18 12:38:50 PM PDT 24	Apr 18 12:38:53 PM PDT 24	22204285 ps
T894	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.722877972	Apr 18 12:39:46 PM PDT 24	Apr 18 12:39:51 PM PDT 24	738326612 ps
T895	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3121853816	Apr 18 12:39:46 PM PDT 24	Apr 18 12:39:54 PM PDT 24	641756330 ps
T896	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.2836288623	Apr 18 12:39:12 PM PDT 24	Apr 18 12:39:43 PM PDT 24	3519054601 ps
T897	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.255629133	Apr 18 12:40:04 PM PDT 24	Apr 18 12:40:09 PM PDT 24	187893714 ps
T126	/workspace/coverage/xbar_build_mode/3.xbar_random.3735104616	Apr 18 12:38:27 PM PDT 24	Apr 18 12:38:41 PM PDT 24	697719570 ps
T898	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2759289258	Apr 18 12:39:46 PM PDT 24	Apr 18 12:41:47 PM PDT 24	19353501514 ps
T899	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3715772486	Apr 18 12:39:10 PM PDT 24	Apr 18 12:39:22 PM PDT 24	3267354790 ps
T900	/workspace/coverage/xbar_build_mode/18.xbar_smoke.3488196737	Apr 18 12:39:13 PM PDT 24	Apr 18 12:39:17 PM PDT 24	103115069 ps

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.1861369718
Short name	T14
Test name
Test status
Simulation time	3576649233 ps
CPU time	54.47 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:41:12 PM PDT 24
Peak memory	203068 kb
Host	smart-aec7cb3b-3b6f-4254-b32e-585205fd7912
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1861369718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1861369718
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.309214483
Short name	T149
Test name
Test status
Simulation time	164634388074 ps
CPU time	345.8 seconds
Started	Apr 18 12:38:24 PM PDT 24
Finished	Apr 18 12:44:10 PM PDT 24
Peak memory	202960 kb
Host	smart-e3cef5d1-4d7a-4bb7-80fb-e3f2fcf0f729
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=309214483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.309214483
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2506237954
Short name	T61
Test name
Test status
Simulation time	62467107950 ps
CPU time	301.22 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:44:17 PM PDT 24
Peak memory	203508 kb
Host	smart-5065e6e9-80c7-40b8-943b-3fb98b1043a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2506237954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2506237954
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1694641987
Short name	T145
Test name
Test status
Simulation time	35283898270 ps
CPU time	232.97 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:43:18 PM PDT 24
Peak memory	203100 kb
Host	smart-bf9ae093-f11a-4b29-9e42-a1f5da9e7c7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1694641987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1694641987
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1117992385
Short name	T42
Test name
Test status
Simulation time	7055195601 ps
CPU time	58.48 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	203208 kb
Host	smart-95341fe1-0023-4504-b170-13dfc480e44a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117992385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1117992385
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1253499960
Short name	T68
Test name
Test status
Simulation time	121906653044 ps
CPU time	265.42 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:44:26 PM PDT 24
Peak memory	202964 kb
Host	smart-eb2cc197-3d57-44b8-a4df-7ff4e865925c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1253499960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1253499960
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3423288803
Short name	T12
Test name
Test status
Simulation time	78615602524 ps
CPU time	141.16 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:41:40 PM PDT 24
Peak memory	202072 kb
Host	smart-a5bca41b-7974-49ef-8d30-bfc7dd7993d4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423288803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3423288803
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1006013850
Short name	T25
Test name
Test status
Simulation time	123064312 ps
CPU time	6.26 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	202012 kb
Host	smart-f63d6e5f-98fd-4da6-85d2-aece05415aab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1006013850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1006013850
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2032993729
Short name	T82
Test name
Test status
Simulation time	63468624262 ps
CPU time	368.43 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:45:25 PM PDT 24
Peak memory	205148 kb
Host	smart-8d02f0bf-68fa-4934-b49a-b16023c7aa61
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2032993729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2032993729
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4157275132
Short name	T9
Test name
Test status
Simulation time	745381192 ps
CPU time	87.29 seconds
Started	Apr 18 12:40:07 PM PDT 24
Finished	Apr 18 12:41:36 PM PDT 24
Peak memory	204728 kb
Host	smart-3a1689ed-5fb6-4e86-b19b-de6ad5e56f57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4157275132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.4157275132
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3005926135
Short name	T76
Test name
Test status
Simulation time	3682741011 ps
CPU time	89.79 seconds
Started	Apr 18 12:38:21 PM PDT 24
Finished	Apr 18 12:39:52 PM PDT 24
Peak memory	204168 kb
Host	smart-486f445c-d824-40b3-9a7e-492075a59dda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005926135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3005926135
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.727943015
Short name	T113
Test name
Test status
Simulation time	19065600633 ps
CPU time	141.07 seconds
Started	Apr 18 12:38:50 PM PDT 24
Finished	Apr 18 12:41:12 PM PDT 24
Peak memory	202128 kb
Host	smart-b2745add-1d26-4475-966e-06aac3af5a26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727943015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo w_rsp.727943015
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3110852104
Short name	T475
Test name
Test status
Simulation time	35709404919 ps
CPU time	221.4 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:42:50 PM PDT 24
Peak memory	203344 kb
Host	smart-a90f61a7-8c79-4021-a6cf-ac01200a928c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3110852104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.3110852104
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1384430622
Short name	T6
Test name
Test status
Simulation time	666789000 ps
CPU time	95.21 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:41:09 PM PDT 24
Peak memory	205728 kb
Host	smart-e96c35cc-d46f-4691-aaf6-467923cb659f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1384430622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1384430622
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.2075062029
Short name	T59
Test name
Test status
Simulation time	4301618843 ps
CPU time	75.35 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:40:13 PM PDT 24
Peak memory	205152 kb
Host	smart-3621ccad-81bf-4ac2-84a2-812b0a077ef5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2075062029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2075062029
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.509751520
Short name	T17
Test name
Test status
Simulation time	2574756070 ps
CPU time	76.14 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	206244 kb
Host	smart-e08b5f9c-a275-4600-bc1c-a1698ea9ff21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=509751520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.509751520
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1809737956
Short name	T79
Test name
Test status
Simulation time	2386167837 ps
CPU time	111.37 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:41:01 PM PDT 24
Peak memory	205032 kb
Host	smart-892a7a23-b946-493a-a92b-aa965fd68350
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1809737956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1809737956
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1682340498
Short name	T171
Test name
Test status
Simulation time	668368030 ps
CPU time	61.65 seconds
Started	Apr 18 12:40:21 PM PDT 24
Finished	Apr 18 12:41:24 PM PDT 24
Peak memory	204600 kb
Host	smart-854eb47c-f35a-4f91-a5be-a2d21fcbfb2e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1682340498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1682340498
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2218689727
Short name	T485
Test name
Test status
Simulation time	2117373644 ps
CPU time	90.27 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:41:20 PM PDT 24
Peak memory	205052 kb
Host	smart-8df69a7d-f977-434e-a30f-ba142afafe09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2218689727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2218689727
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.4084084505
Short name	T176
Test name
Test status
Simulation time	1107199095 ps
CPU time	163.09 seconds
Started	Apr 18 12:38:56 PM PDT 24
Finished	Apr 18 12:41:40 PM PDT 24
Peak memory	204612 kb
Host	smart-f31438ad-eac1-4981-ab82-869ceaec44b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4084084505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.4084084505
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.963629358
Short name	T73
Test name
Test status
Simulation time	26828343988 ps
CPU time	77.41 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:41:20 PM PDT 24
Peak memory	204468 kb
Host	smart-047909b7-3ccf-4de8-8120-42d87126052f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963629358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.963629358
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.380103907
Short name	T110
Test name
Test status
Simulation time	1181255386 ps
CPU time	12.83 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:40 PM PDT 24
Peak memory	201880 kb
Host	smart-2ce59d66-1a99-42be-9c3e-10208d7d9864
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=380103907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.380103907
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.124271092
Short name	T355
Test name
Test status
Simulation time	352211505 ps
CPU time	3.23 seconds
Started	Apr 18 12:38:19 PM PDT 24
Finished	Apr 18 12:38:23 PM PDT 24
Peak memory	202008 kb
Host	smart-74327624-226b-452c-92a8-e458ed83c336
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=124271092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.124271092
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.3445930199
Short name	T274
Test name
Test status
Simulation time	1446715660 ps
CPU time	14.26 seconds
Started	Apr 18 12:38:18 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	201908 kb
Host	smart-0eec669f-f709-4c8d-8f3f-e3a3d55db0b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3445930199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3445930199
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3116336886
Short name	T146
Test name
Test status
Simulation time	423372325 ps
CPU time	6.45 seconds
Started	Apr 18 12:38:20 PM PDT 24
Finished	Apr 18 12:38:28 PM PDT 24
Peak memory	201996 kb
Host	smart-0b19f460-2656-4aba-92a2-7ac9ae65eeee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3116336886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3116336886
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2502619869
Short name	T221
Test name
Test status
Simulation time	6637735859 ps
CPU time	25.61 seconds
Started	Apr 18 12:38:23 PM PDT 24
Finished	Apr 18 12:38:49 PM PDT 24
Peak memory	201940 kb
Host	smart-27a36fdb-6447-4e17-a592-3313309edf50
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502619869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2502619869
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.874324129
Short name	T494
Test name
Test status
Simulation time	152324396566 ps
CPU time	129.73 seconds
Started	Apr 18 12:38:24 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	201956 kb
Host	smart-ef2606af-03a7-42cc-b767-c5c943469c2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=874324129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.874324129
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1340047138
Short name	T759
Test name
Test status
Simulation time	121544572 ps
CPU time	6.01 seconds
Started	Apr 18 12:38:25 PM PDT 24
Finished	Apr 18 12:38:31 PM PDT 24
Peak memory	201880 kb
Host	smart-4b5f9d32-d081-4a50-8e28-ca6800a2de48
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340047138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1340047138
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2971235098
Short name	T200
Test name
Test status
Simulation time	165713300 ps
CPU time	2.98 seconds
Started	Apr 18 12:38:20 PM PDT 24
Finished	Apr 18 12:38:24 PM PDT 24
Peak memory	201956 kb
Host	smart-c015bee9-5cff-40bb-a6a5-f38b9387d6ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971235098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2971235098
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.4136038501
Short name	T822
Test name
Test status
Simulation time	10158552 ps
CPU time	1.24 seconds
Started	Apr 18 12:38:25 PM PDT 24
Finished	Apr 18 12:38:26 PM PDT 24
Peak memory	202036 kb
Host	smart-1a804627-6539-4935-b3f8-68fccc91fc87
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4136038501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4136038501
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1326973506
Short name	T761
Test name
Test status
Simulation time	3477528556 ps
CPU time	13.52 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	201996 kb
Host	smart-a01106e7-2eb0-41b8-a0e7-2d40c9eea04f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326973506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1326973506
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.878774620
Short name	T4
Test name
Test status
Simulation time	1351840232 ps
CPU time	6.6 seconds
Started	Apr 18 12:38:25 PM PDT 24
Finished	Apr 18 12:38:32 PM PDT 24
Peak memory	201892 kb
Host	smart-fb2bd636-44b8-4855-b603-9402f5fba56a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=878774620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.878774620
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.349348951
Short name	T366
Test name
Test status
Simulation time	27451865 ps
CPU time	1.19 seconds
Started	Apr 18 12:38:18 PM PDT 24
Finished	Apr 18 12:38:20 PM PDT 24
Peak memory	202008 kb
Host	smart-5d3d53be-0b26-4ab5-9456-c7d710f2645e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349348951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.349348951
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.4026826885
Short name	T739
Test name
Test status
Simulation time	5171098241 ps
CPU time	88.69 seconds
Started	Apr 18 12:38:19 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	202936 kb
Host	smart-d0178d28-cf14-4322-92db-814c0cf54e9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4026826885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4026826885
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.168493226
Short name	T515
Test name
Test status
Simulation time	1321698140 ps
CPU time	11.38 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	201920 kb
Host	smart-fff8b03f-129f-40b7-b929-dbbf5a52f989
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=168493226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.168493226
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.77818876
Short name	T612
Test name
Test status
Simulation time	18107194 ps
CPU time	9.33 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:36 PM PDT 24
Peak memory	201876 kb
Host	smart-ffa17b57-66a0-4bcc-8ee4-4d48c2ffbeca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=77818876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_r eset.77818876
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.540866610
Short name	T456
Test name
Test status
Simulation time	774843490 ps
CPU time	10.29 seconds
Started	Apr 18 12:38:21 PM PDT 24
Finished	Apr 18 12:38:32 PM PDT 24
Peak memory	201920 kb
Host	smart-b5957eb3-ed8b-4971-b5e6-681995b0eaae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=540866610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.540866610
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2638206589
Short name	T866
Test name
Test status
Simulation time	1021562741 ps
CPU time	12.69 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:40 PM PDT 24
Peak memory	201920 kb
Host	smart-6f0edbb2-2ecf-4548-af58-c6f6b64e5d75
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2638206589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2638206589
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3023047340
Short name	T591
Test name
Test status
Simulation time	22009411998 ps
CPU time	148.66 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:40:57 PM PDT 24
Peak memory	203008 kb
Host	smart-4baf840e-321c-4c72-962b-c88ea410b95b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3023047340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3023047340
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.942410213
Short name	T703
Test name
Test status
Simulation time	39775936 ps
CPU time	3.25 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	201936 kb
Host	smart-d9e3608a-f856-4c6f-9774-9358089a1427
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=942410213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.942410213
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.4221014131
Short name	T304
Test name
Test status
Simulation time	119975872 ps
CPU time	2.44 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:31 PM PDT 24
Peak memory	201908 kb
Host	smart-6af5c9ba-51f8-46bb-a3a0-b3af57a14497
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221014131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4221014131
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.2192101618
Short name	T195
Test name
Test status
Simulation time	136069156 ps
CPU time	1.47 seconds
Started	Apr 18 12:38:19 PM PDT 24
Finished	Apr 18 12:38:22 PM PDT 24
Peak memory	201924 kb
Host	smart-9a83ba08-6bcf-429e-b7fd-283f44e7ca66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192101618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2192101618
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1720823915
Short name	T488
Test name
Test status
Simulation time	17139353843 ps
CPU time	47.8 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201996 kb
Host	smart-37f9fef0-40bf-4610-abd2-fad0a5cbc8ea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720823915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1720823915
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.747242071
Short name	T16
Test name
Test status
Simulation time	9886804269 ps
CPU time	72.6 seconds
Started	Apr 18 12:38:19 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	202084 kb
Host	smart-16aeb248-966b-4267-a41a-9f437cc57bb1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=747242071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.747242071
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2577086186
Short name	T45
Test name
Test status
Simulation time	312848876 ps
CPU time	5.43 seconds
Started	Apr 18 12:38:18 PM PDT 24
Finished	Apr 18 12:38:25 PM PDT 24
Peak memory	201912 kb
Host	smart-7dc1fcd4-921d-48b0-ac47-6d83c0f96b0a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577086186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2577086186
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.1503489305
Short name	T603
Test name
Test status
Simulation time	90694521 ps
CPU time	4.01 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:32 PM PDT 24
Peak memory	201884 kb
Host	smart-84880d57-f644-4cf6-be25-67929d3b93af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1503489305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1503489305
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.540325959
Short name	T471
Test name
Test status
Simulation time	131612353 ps
CPU time	1.54 seconds
Started	Apr 18 12:38:25 PM PDT 24
Finished	Apr 18 12:38:27 PM PDT 24
Peak memory	202016 kb
Host	smart-87f60f40-25d2-48b6-a8b3-0bf015295981
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=540325959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.540325959
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1969816232
Short name	T520
Test name
Test status
Simulation time	1274381411 ps
CPU time	6.9 seconds
Started	Apr 18 12:38:19 PM PDT 24
Finished	Apr 18 12:38:27 PM PDT 24
Peak memory	202024 kb
Host	smart-ec082f40-ec4d-4ef8-a75b-4f63eec99ae7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969816232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1969816232
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1890716622
Short name	T264
Test name
Test status
Simulation time	3060608903 ps
CPU time	8.73 seconds
Started	Apr 18 12:38:18 PM PDT 24
Finished	Apr 18 12:38:28 PM PDT 24
Peak memory	202064 kb
Host	smart-a33b5d27-1b77-42a8-8d55-b4a37a0e4291
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1890716622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1890716622
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3058216230
Short name	T568
Test name
Test status
Simulation time	12321875 ps
CPU time	1.26 seconds
Started	Apr 18 12:38:22 PM PDT 24
Finished	Apr 18 12:38:24 PM PDT 24
Peak memory	201956 kb
Host	smart-67ff019e-ad3b-4447-b08c-449a64df0a4e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058216230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3058216230
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.2490171583
Short name	T670
Test name
Test status
Simulation time	3347331674 ps
CPU time	53.44 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	202996 kb
Host	smart-5f71b52a-ea07-48b2-bc2b-2116df6991ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2490171583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2490171583
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.131024301
Short name	T413
Test name
Test status
Simulation time	4018843264 ps
CPU time	57.74 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201976 kb
Host	smart-1a35f811-8f64-436d-a406-b57b328f440b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131024301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.131024301
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1507664746
Short name	T696
Test name
Test status
Simulation time	41969366 ps
CPU time	4.53 seconds
Started	Apr 18 12:38:29 PM PDT 24
Finished	Apr 18 12:38:35 PM PDT 24
Peak memory	201932 kb
Host	smart-eaa06dba-5218-42d0-806d-38988a90e400
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507664746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1507664746
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3461381609
Short name	T859
Test name
Test status
Simulation time	241624078 ps
CPU time	37.21 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	203256 kb
Host	smart-a8242a48-251b-473a-9fb1-cafdad6cf24b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461381609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3461381609
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1388938036
Short name	T837
Test name
Test status
Simulation time	2079604288 ps
CPU time	6.47 seconds
Started	Apr 18 12:38:30 PM PDT 24
Finished	Apr 18 12:38:37 PM PDT 24
Peak memory	202012 kb
Host	smart-c31ebc64-b95f-4170-bf07-c3cd2676dd9f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1388938036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1388938036
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3647608627
Short name	T292
Test name
Test status
Simulation time	112004244 ps
CPU time	8.57 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	201872 kb
Host	smart-f77950c1-34c0-47bb-a244-610ee8ae7b32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3647608627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3647608627
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.387871664
Short name	T482
Test name
Test status
Simulation time	259354827 ps
CPU time	4.4 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:39:02 PM PDT 24
Peak memory	201908 kb
Host	smart-3ce614ca-94de-4aa7-91f1-5de7e850eabc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=387871664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.387871664
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.669249347
Short name	T36
Test name
Test status
Simulation time	257934825 ps
CPU time	3.8 seconds
Started	Apr 18 12:38:58 PM PDT 24
Finished	Apr 18 12:39:03 PM PDT 24
Peak memory	201864 kb
Host	smart-45eb3c93-0fcf-4a7b-9f20-a7ad729e51e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669249347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.669249347
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.4079529760
Short name	T533
Test name
Test status
Simulation time	1566654526 ps
CPU time	12.48 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	201904 kb
Host	smart-28fec1e6-9f21-41d5-8b45-6b6744ce4bc8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4079529760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.4079529760
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2125493724
Short name	T710
Test name
Test status
Simulation time	31466532181 ps
CPU time	79.16 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201928 kb
Host	smart-70217f4a-5370-405f-84d6-ac4440b1b666
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125493724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2125493724
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3425388805
Short name	T40
Test name
Test status
Simulation time	29231876585 ps
CPU time	54.53 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	202060 kb
Host	smart-c9970144-a746-4e39-88fa-971f50848aac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425388805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3425388805
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2528730777
Short name	T297
Test name
Test status
Simulation time	60475760 ps
CPU time	7.15 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	202008 kb
Host	smart-570de330-7f34-4fb8-a089-e8325f643cae
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528730777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2528730777
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.454331210
Short name	T66
Test name
Test status
Simulation time	757889286 ps
CPU time	5.09 seconds
Started	Apr 18 12:38:56 PM PDT 24
Finished	Apr 18 12:39:03 PM PDT 24
Peak memory	201920 kb
Host	smart-4141b192-0d1d-4dbd-87f1-85f17301f387
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454331210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.454331210
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.2535490040
Short name	T729
Test name
Test status
Simulation time	45701489 ps
CPU time	1.37 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:38:57 PM PDT 24
Peak memory	201928 kb
Host	smart-2382be89-5675-4a36-bb09-a45075c35beb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2535490040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2535490040
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3294648344
Short name	T387
Test name
Test status
Simulation time	4419768405 ps
CPU time	11.13 seconds
Started	Apr 18 12:38:49 PM PDT 24
Finished	Apr 18 12:39:01 PM PDT 24
Peak memory	201932 kb
Host	smart-46bc2555-81c7-4979-aa2a-7bb800ccbd57
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294648344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3294648344
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.477901626
Short name	T410
Test name
Test status
Simulation time	1576401520 ps
CPU time	10.59 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	201912 kb
Host	smart-951033b2-6032-4778-a4b0-05c1795e8db8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=477901626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.477901626
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1109339282
Short name	T416
Test name
Test status
Simulation time	10022663 ps
CPU time	1.06 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201924 kb
Host	smart-e098fdba-4b70-49f9-9dd5-1f8239e408da
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109339282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1109339282
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.1230308103
Short name	T108
Test name
Test status
Simulation time	1743940483 ps
CPU time	26.34 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	201920 kb
Host	smart-73619161-e972-4e0c-a51e-407057579af4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1230308103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1230308103
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4199436650
Short name	T377
Test name
Test status
Simulation time	553387007 ps
CPU time	38.48 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:39:42 PM PDT 24
Peak memory	201900 kb
Host	smart-763d9964-cb18-40c1-9e01-492ee7625af1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4199436650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4199436650
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.71227183
Short name	T394
Test name
Test status
Simulation time	304924623 ps
CPU time	17.87 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	201776 kb
Host	smart-231b3f61-0f1b-4ab7-bae9-9156ce20be02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=71227183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rese t_error.71227183
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.743252241
Short name	T893
Test name
Test status
Simulation time	22204285 ps
CPU time	2.37 seconds
Started	Apr 18 12:38:50 PM PDT 24
Finished	Apr 18 12:38:53 PM PDT 24
Peak memory	201944 kb
Host	smart-72c2392d-ffd9-4f3e-8a82-9ca44757210e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=743252241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.743252241
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3953004429
Short name	T434
Test name
Test status
Simulation time	180016299 ps
CPU time	3.03 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	202008 kb
Host	smart-154404db-23da-4f24-b7fd-4a6e2fced06a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3953004429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3953004429
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2188723015
Short name	T99
Test name
Test status
Simulation time	50823099828 ps
CPU time	306.17 seconds
Started	Apr 18 12:39:04 PM PDT 24
Finished	Apr 18 12:44:11 PM PDT 24
Peak memory	203056 kb
Host	smart-67fde51b-fdf2-475d-9e48-a115bd3a27df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2188723015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.2188723015
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4286389969
Short name	T231
Test name
Test status
Simulation time	198798389 ps
CPU time	5.23 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:38:58 PM PDT 24
Peak memory	201992 kb
Host	smart-022e18eb-65c1-47bb-b0c3-2036d47a995c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4286389969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4286389969
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.2934686216
Short name	T19
Test name
Test status
Simulation time	246333401 ps
CPU time	5.06 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	201908 kb
Host	smart-1d521c2b-7a1a-410e-8d2d-2a58a810fd69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2934686216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2934686216
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.760128699
Short name	T409
Test name
Test status
Simulation time	2372832950 ps
CPU time	8.4 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	202072 kb
Host	smart-a71186b1-7003-4dce-b3b1-ea07e98a8a97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760128699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.760128699
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3247460982
Short name	T96
Test name
Test status
Simulation time	6088279254 ps
CPU time	30.07 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	201932 kb
Host	smart-41ffb50a-3b20-4d48-b47a-a3f3f7f276c2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247460982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3247460982
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2056969551
Short name	T535
Test name
Test status
Simulation time	15137023132 ps
CPU time	70.65 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:40:26 PM PDT 24
Peak memory	201972 kb
Host	smart-4ef0eda1-d838-4949-b7f0-afc2611f9fde
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2056969551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2056969551
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1814973072
Short name	T418
Test name
Test status
Simulation time	97267531 ps
CPU time	6.08 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	202024 kb
Host	smart-dba246cd-4840-4e2c-b91b-653918caa9fe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814973072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1814973072
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.1000998964
Short name	T391
Test name
Test status
Simulation time	228739313 ps
CPU time	5.53 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	202012 kb
Host	smart-847bc716-c1e4-4293-b8c8-4d24d7409b80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1000998964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1000998964
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.1364718532
Short name	T26
Test name
Test status
Simulation time	72145232 ps
CPU time	1.36 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:39:05 PM PDT 24
Peak memory	201988 kb
Host	smart-919e312d-bad2-4fa2-aecb-4a78e59833ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1364718532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1364718532
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1499516826
Short name	T871
Test name
Test status
Simulation time	2552508987 ps
CPU time	8.58 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201928 kb
Host	smart-1e966223-3a3b-41e8-a60c-98e5a85ec771
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499516826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1499516826
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3416363022
Short name	T277
Test name
Test status
Simulation time	983611928 ps
CPU time	4.69 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:39:00 PM PDT 24
Peak memory	201936 kb
Host	smart-388099aa-448a-4c5c-92a4-92a87ffc1e99
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3416363022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3416363022
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2385894755
Short name	T726
Test name
Test status
Simulation time	12178878 ps
CPU time	1.15 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201996 kb
Host	smart-6c793142-4210-4a48-8baf-e3c9f9e1617a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385894755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2385894755
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.1825967145
Short name	T143
Test name
Test status
Simulation time	7413097819 ps
CPU time	22.37 seconds
Started	Apr 18 12:38:56 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	203108 kb
Host	smart-ae347b74-c4a4-4493-8fd6-540a1607f8fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825967145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1825967145
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3529182676
Short name	T362
Test name
Test status
Simulation time	382021324 ps
CPU time	17.44 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:25 PM PDT 24
Peak memory	201984 kb
Host	smart-a0cce522-d86c-4267-b25c-e5535e121ac3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3529182676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3529182676
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1409405379
Short name	T821
Test name
Test status
Simulation time	620473782 ps
CPU time	71.49 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:40:06 PM PDT 24
Peak memory	205388 kb
Host	smart-f3960e5f-858e-45e4-b5ca-0c67124760cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1409405379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1409405379
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1776385369
Short name	T344
Test name
Test status
Simulation time	1607642026 ps
CPU time	158.22 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:41:45 PM PDT 24
Peak memory	208100 kb
Host	smart-8a8a11b5-f811-451d-b125-92ed37a6e217
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1776385369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1776385369
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3963434992
Short name	T357
Test name
Test status
Simulation time	1128407953 ps
CPU time	9.5 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:39:02 PM PDT 24
Peak memory	202012 kb
Host	smart-8f419b95-8116-41da-8de4-e0612a57837a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3963434992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3963434992
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3317873610
Short name	T794
Test name
Test status
Simulation time	1490975876 ps
CPU time	17.99 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	202008 kb
Host	smart-41898a85-405b-4368-bea5-bd6a4960c632
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3317873610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3317873610
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4101742138
Short name	T91
Test name
Test status
Simulation time	211681597186 ps
CPU time	250.2 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:43:17 PM PDT 24
Peak memory	203524 kb
Host	smart-d593efc4-f0e2-4cf6-9888-fb04d2ac62ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4101742138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.4101742138
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1215230988
Short name	T339
Test name
Test status
Simulation time	130095377 ps
CPU time	2.68 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:38:56 PM PDT 24
Peak memory	201928 kb
Host	smart-9a65b1a1-428f-450c-bade-11b2f3d39857
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1215230988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1215230988
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.4138039869
Short name	T74
Test name
Test status
Simulation time	520393522 ps
CPU time	7.48 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:39:02 PM PDT 24
Peak memory	201908 kb
Host	smart-853f11cd-942c-44be-9053-c07f66249e48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4138039869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4138039869
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.2168034248
Short name	T619
Test name
Test status
Simulation time	20913238 ps
CPU time	2.58 seconds
Started	Apr 18 12:39:04 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	201936 kb
Host	smart-bfc9d9c4-6c22-477e-a878-f4bb0009212c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168034248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2168034248
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2779277457
Short name	T646
Test name
Test status
Simulation time	62669880533 ps
CPU time	129.6 seconds
Started	Apr 18 12:38:53 PM PDT 24
Finished	Apr 18 12:41:04 PM PDT 24
Peak memory	202084 kb
Host	smart-1a2ee4a4-4771-40cc-b5c1-fcb778e4a09e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779277457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2779277457
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2242187586
Short name	T665
Test name
Test status
Simulation time	31718509781 ps
CPU time	170.07 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:41:51 PM PDT 24
Peak memory	202000 kb
Host	smart-c08b6f73-e05c-4cf1-bc45-f5c4ebd17948
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2242187586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2242187586
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4246071386
Short name	T278
Test name
Test status
Simulation time	54221938 ps
CPU time	4.38 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:05 PM PDT 24
Peak memory	201924 kb
Host	smart-157b7869-f161-4d78-a4a0-9453837341d6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246071386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4246071386
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.21051620
Short name	T552
Test name
Test status
Simulation time	2719455715 ps
CPU time	7.58 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:39:01 PM PDT 24
Peak memory	202064 kb
Host	smart-5f646a0e-e2ee-4724-a7d5-f33908ee7d75
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=21051620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.21051620
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.983239923
Short name	T121
Test name
Test status
Simulation time	90830600 ps
CPU time	1.47 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	202032 kb
Host	smart-2c48cc04-f420-40b2-88b1-6bf8d9cd35e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=983239923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.983239923
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2874923898
Short name	T563
Test name
Test status
Simulation time	1855193150 ps
CPU time	9.74 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:39:05 PM PDT 24
Peak memory	201940 kb
Host	smart-6e21de41-5555-45d1-88e7-9359669c780b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874923898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2874923898
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.820918212
Short name	T398
Test name
Test status
Simulation time	1970061128 ps
CPU time	14.54 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201936 kb
Host	smart-018843da-e9df-4629-be68-94daccf71a06
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=820918212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.820918212
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.162872993
Short name	T593
Test name
Test status
Simulation time	9167241 ps
CPU time	1.07 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	202012 kb
Host	smart-534e4489-b1c1-40da-a78b-6b7eb4fb3513
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162872993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.162872993
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.3479838618
Short name	T687
Test name
Test status
Simulation time	574016472 ps
CPU time	36.17 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	204052 kb
Host	smart-4057f39e-9e4a-4833-9c0f-bfe2f6cf8fd7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3479838618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3479838618
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2097776001
Short name	T10
Test name
Test status
Simulation time	428461309 ps
CPU time	85.81 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:40:29 PM PDT 24
Peak memory	204272 kb
Host	smart-c4f49b8e-7f28-4dd0-a850-91b32511c89b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2097776001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2097776001
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1886533000
Short name	T229
Test name
Test status
Simulation time	99470679 ps
CPU time	5.48 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:05 PM PDT 24
Peak memory	202012 kb
Host	smart-900f4462-3d40-4b87-a4ed-430d50d6d789
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1886533000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1886533000
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2880903876
Short name	T774
Test name
Test status
Simulation time	1011377129 ps
CPU time	18.53 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201996 kb
Host	smart-943ac8c8-2cb3-468d-b719-a5ed9e397331
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2880903876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2880903876
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2656094211
Short name	T356
Test name
Test status
Simulation time	3062795819 ps
CPU time	20.2 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201996 kb
Host	smart-0792ef0e-3ef2-43be-8536-18a1f1ecafdb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2656094211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2656094211
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2723296931
Short name	T649
Test name
Test status
Simulation time	412285210 ps
CPU time	7.65 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	201940 kb
Host	smart-b82724ef-6057-4c09-bdc6-96ca88a51b79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2723296931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2723296931
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.3477845872
Short name	T857
Test name
Test status
Simulation time	4332096805 ps
CPU time	11.06 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	202056 kb
Host	smart-58478308-91df-4fcc-a071-98f3177cc1f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477845872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3477845872
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.739933782
Short name	T438
Test name
Test status
Simulation time	689428717 ps
CPU time	15.22 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	202004 kb
Host	smart-1590e0b8-5a8d-4cc0-9c18-2eba673136ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739933782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.739933782
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2118248818
Short name	T142
Test name
Test status
Simulation time	55844649334 ps
CPU time	140.69 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:41:27 PM PDT 24
Peak memory	202016 kb
Host	smart-00c49a2d-9fca-4301-8a91-180240933838
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118248818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2118248818
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2934799321
Short name	T810
Test name
Test status
Simulation time	10618273503 ps
CPU time	47.04 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	201940 kb
Host	smart-82caa49c-3743-4c2f-bded-2933bc68858f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2934799321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2934799321
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2490051959
Short name	T734
Test name
Test status
Simulation time	35790007 ps
CPU time	4.14 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:38:57 PM PDT 24
Peak memory	201904 kb
Host	smart-81b3f00a-779c-4b59-9206-d2b777d97b7c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490051959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2490051959
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.496151937
Short name	T63
Test name
Test status
Simulation time	1043265109 ps
CPU time	7.11 seconds
Started	Apr 18 12:38:56 PM PDT 24
Finished	Apr 18 12:39:04 PM PDT 24
Peak memory	201932 kb
Host	smart-9164d3fc-c0eb-4ceb-b7e9-a93af12589c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=496151937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.496151937
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.2111004007
Short name	T878
Test name
Test status
Simulation time	81597882 ps
CPU time	1.64 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	201952 kb
Host	smart-7f4f7e7d-7051-4908-a457-cee5d42939c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111004007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2111004007
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3435242910
Short name	T544
Test name
Test status
Simulation time	2559473480 ps
CPU time	9.65 seconds
Started	Apr 18 12:38:53 PM PDT 24
Finished	Apr 18 12:39:04 PM PDT 24
Peak memory	202080 kb
Host	smart-682c47a6-5b7c-4261-8947-026960a743e7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435242910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3435242910
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2270802441
Short name	T577
Test name
Test status
Simulation time	1096364990 ps
CPU time	7.52 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	202024 kb
Host	smart-0d77638a-775c-4380-8cb1-f0c8622b715d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2270802441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2270802441
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.875560161
Short name	T671
Test name
Test status
Simulation time	9744780 ps
CPU time	1.08 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:38:57 PM PDT 24
Peak memory	201984 kb
Host	smart-6369795d-c344-4c53-a2d6-840bb68d54e0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875560161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.875560161
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2472974664
Short name	T43
Test name
Test status
Simulation time	4254398198 ps
CPU time	70.52 seconds
Started	Apr 18 12:38:53 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	203008 kb
Host	smart-45595514-7149-4aa2-aa20-3df64ef19b68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2472974664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2472974664
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.786771538
Short name	T750
Test name
Test status
Simulation time	537122810 ps
CPU time	58.24 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	204080 kb
Host	smart-af4c3901-ea2f-4064-b229-768bb56260b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=786771538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.786771538
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.786890766
Short name	T483
Test name
Test status
Simulation time	9991637340 ps
CPU time	89.06 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:40:39 PM PDT 24
Peak memory	204592 kb
Host	smart-0817a1c4-65ec-4399-8056-aba9e7785e4b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=786890766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.786890766
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3292921529
Short name	T3
Test name
Test status
Simulation time	329994436 ps
CPU time	5.88 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	202016 kb
Host	smart-87c97314-72ab-409d-b089-96b8a69e7f0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3292921529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3292921529
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1627067951
Short name	T454
Test name
Test status
Simulation time	425210465 ps
CPU time	4.63 seconds
Started	Apr 18 12:39:04 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	202008 kb
Host	smart-cbff5d2c-bfec-41c2-95af-d62e0a02a1e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627067951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1627067951
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4154909542
Short name	T840
Test name
Test status
Simulation time	6148564639 ps
CPU time	33.18 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	202072 kb
Host	smart-7cb45089-3790-4bea-b974-a15c968971d6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4154909542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.4154909542
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.637335775
Short name	T196
Test name
Test status
Simulation time	742278789 ps
CPU time	8.41 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	202012 kb
Host	smart-404bfdc1-7200-48b7-9c9e-5038d7c0db87
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=637335775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.637335775
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.1976914481
Short name	T243
Test name
Test status
Simulation time	71347624 ps
CPU time	4.35 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	201908 kb
Host	smart-1bb1ef65-5be4-4815-9825-90408feaa3e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976914481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1976914481
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.1485407516
Short name	T190
Test name
Test status
Simulation time	50151429 ps
CPU time	3.56 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	201948 kb
Host	smart-4a93fa9c-c23c-4cad-9030-e191c56d1edd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485407516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1485407516
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1613083103
Short name	T412
Test name
Test status
Simulation time	72231826196 ps
CPU time	193.59 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:42:20 PM PDT 24
Peak memory	201992 kb
Host	smart-8bc0d313-94e7-4fcf-95be-6e732592b2cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613083103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1613083103
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2866872102
Short name	T886
Test name
Test status
Simulation time	7357898847 ps
CPU time	32.25 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:46 PM PDT 24
Peak memory	202084 kb
Host	smart-bd2b5a00-72d3-4566-ab7c-2c96c2ebcd9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2866872102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2866872102
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3324634147
Short name	T257
Test name
Test status
Simulation time	45583163 ps
CPU time	4.8 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	201968 kb
Host	smart-24c51cf3-ab2f-4c9f-a919-93a905f2f30c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324634147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3324634147
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.86611906
Short name	T284
Test name
Test status
Simulation time	29283294 ps
CPU time	3.29 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:39:09 PM PDT 24
Peak memory	201908 kb
Host	smart-da150b4c-c617-44d1-ab66-f59d13511584
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86611906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.86611906
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.808446603
Short name	T193
Test name
Test status
Simulation time	51500671 ps
CPU time	1.44 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201952 kb
Host	smart-cdff9399-2461-4cc0-83da-c8f9c8b6e498
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808446603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.808446603
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3352252971
Short name	T694
Test name
Test status
Simulation time	1969890526 ps
CPU time	9.29 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	202000 kb
Host	smart-0ea04757-0549-4b6b-989f-5397521e47b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352252971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3352252971
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1328628268
Short name	T508
Test name
Test status
Simulation time	6499125128 ps
CPU time	7.65 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	201992 kb
Host	smart-5a89524c-57b9-4764-8379-d054ee1d8b63
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1328628268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1328628268
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3838230527
Short name	T428
Test name
Test status
Simulation time	8929250 ps
CPU time	1.19 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:01 PM PDT 24
Peak memory	201892 kb
Host	smart-e515d740-41d4-4f84-8cdb-b1083a016373
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838230527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3838230527
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.2118668028
Short name	T600
Test name
Test status
Simulation time	298748952 ps
CPU time	27.06 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201988 kb
Host	smart-e138ac19-a140-4f42-8ffc-e872cdf64b83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2118668028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2118668028
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2764444815
Short name	T841
Test name
Test status
Simulation time	894929294 ps
CPU time	9.67 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201864 kb
Host	smart-9a0814ae-4205-430c-ba68-1e1054f3c2e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764444815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2764444815
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.107110015
Short name	T479
Test name
Test status
Simulation time	165909993 ps
CPU time	23.08 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	203196 kb
Host	smart-a79176e1-5b4b-43ed-b86c-109003fd2258
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=107110015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.107110015
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2473729470
Short name	T178
Test name
Test status
Simulation time	3668306473 ps
CPU time	46.79 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	203032 kb
Host	smart-5a201cbe-2abb-43f1-81d7-c06e4752af3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2473729470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2473729470
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2676450227
Short name	T652
Test name
Test status
Simulation time	55798026 ps
CPU time	2.53 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	201968 kb
Host	smart-b46ec976-d6ce-45ba-b8c4-42fb7c676594
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2676450227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2676450227
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3064441596
Short name	T255
Test name
Test status
Simulation time	24773140 ps
CPU time	2.74 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	201912 kb
Host	smart-00322ccb-8cda-4928-be25-001eec74b347
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3064441596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3064441596
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2172720783
Short name	T123
Test name
Test status
Simulation time	1049422850 ps
CPU time	7.35 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:09 PM PDT 24
Peak memory	201928 kb
Host	smart-60ee3914-d5f0-404c-94ae-2d7f773d30e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172720783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2172720783
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.1741728875
Short name	T233
Test name
Test status
Simulation time	39046211 ps
CPU time	2.4 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201856 kb
Host	smart-890373af-6e2a-4494-b1b0-21ffbb6c9030
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1741728875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1741728875
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.428867239
Short name	T481
Test name
Test status
Simulation time	58411851 ps
CPU time	6.88 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:14 PM PDT 24
Peak memory	202008 kb
Host	smart-df521066-faf3-423d-abac-db869c401b21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428867239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.428867239
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3246092939
Short name	T319
Test name
Test status
Simulation time	9059009095 ps
CPU time	33.74 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201984 kb
Host	smart-19ad4158-d13b-42b8-9f08-f4a2c9249a2f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246092939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3246092939
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.923177142
Short name	T865
Test name
Test status
Simulation time	19338355032 ps
CPU time	127.99 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:41:24 PM PDT 24
Peak memory	202008 kb
Host	smart-325495f0-b526-4576-8259-f52310c80d53
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=923177142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.923177142
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3539214771
Short name	T452
Test name
Test status
Simulation time	25861479 ps
CPU time	2.72 seconds
Started	Apr 18 12:39:02 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	201952 kb
Host	smart-3f0dd620-dd87-4f8f-875d-795078c986a8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539214771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3539214771
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.2384290638
Short name	T638
Test name
Test status
Simulation time	1375868985 ps
CPU time	7.47 seconds
Started	Apr 18 12:39:04 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	201952 kb
Host	smart-25fca90e-7f06-4122-8168-37f094662b32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2384290638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2384290638
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.384283400
Short name	T519
Test name
Test status
Simulation time	13739774 ps
CPU time	1.05 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	202012 kb
Host	smart-f1349d0e-2510-4333-ae6a-4cba0258536e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=384283400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.384283400
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3375250472
Short name	T607
Test name
Test status
Simulation time	8357740800 ps
CPU time	10.58 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	201964 kb
Host	smart-b62b1c8e-8a4d-48de-95a1-8c87b23eae94
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375250472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3375250472
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.988460793
Short name	T518
Test name
Test status
Simulation time	2573516454 ps
CPU time	6.78 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	201980 kb
Host	smart-63c09549-d886-4b5a-9080-13d73eedd1c0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=988460793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.988460793
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2844691839
Short name	T342
Test name
Test status
Simulation time	11739071 ps
CPU time	1.23 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:04 PM PDT 24
Peak memory	201920 kb
Host	smart-2547a1d1-d916-46d3-9de7-c13aec5db6fc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844691839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2844691839
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.3725407048
Short name	T737
Test name
Test status
Simulation time	307892699 ps
CPU time	30.52 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201988 kb
Host	smart-0349fba4-9232-4785-bace-2dc57bd476fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3725407048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3725407048
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.881263220
Short name	T708
Test name
Test status
Simulation time	677814913 ps
CPU time	39.42 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	201956 kb
Host	smart-a1ef4969-2057-473a-9053-489d6abcc895
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=881263220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.881263220
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2634738392
Short name	T571
Test name
Test status
Simulation time	141168180 ps
CPU time	12.73 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	202984 kb
Host	smart-4ab208e8-a6a0-4b23-8711-88d181bb4a39
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2634738392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2634738392
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3517802620
Short name	T511
Test name
Test status
Simulation time	695354330 ps
CPU time	62.43 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:40:11 PM PDT 24
Peak memory	203844 kb
Host	smart-36679d43-6e64-4e53-9420-73595d54503e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3517802620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3517802620
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.494006164
Short name	T101
Test name
Test status
Simulation time	1817853643 ps
CPU time	4.85 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:39:09 PM PDT 24
Peak memory	201912 kb
Host	smart-a12e2607-3bec-4f37-b4f1-b8bd3e4e8e6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=494006164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.494006164
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2336922819
Short name	T131
Test name
Test status
Simulation time	2936547994 ps
CPU time	9.81 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	201968 kb
Host	smart-58fa358d-3017-4c5d-9621-a3bc54b4cbb1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336922819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2336922819
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1619906011
Short name	T245
Test name
Test status
Simulation time	811098380 ps
CPU time	9.89 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201848 kb
Host	smart-9125f876-275a-4812-9348-6ec41ea05338
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1619906011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1619906011
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.230327782
Short name	T188
Test name
Test status
Simulation time	17987251 ps
CPU time	1.66 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	201992 kb
Host	smart-083ff480-b98d-450a-937e-a660263447cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230327782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.230327782
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.1675647284
Short name	T32
Test name
Test status
Simulation time	347516800 ps
CPU time	3.66 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201860 kb
Host	smart-d34085b0-04c0-47c5-8e5e-4506b0e88c6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1675647284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1675647284
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2905765843
Short name	T706
Test name
Test status
Simulation time	195198251175 ps
CPU time	146.38 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:41:30 PM PDT 24
Peak memory	202000 kb
Host	smart-543cf00a-9412-476d-a963-e281b99def95
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905765843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2905765843
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1836478922
Short name	T524
Test name
Test status
Simulation time	33550652982 ps
CPU time	203.36 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:42:28 PM PDT 24
Peak memory	202088 kb
Host	smart-b8d67dc5-69da-4636-a186-4edd203d9c23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1836478922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1836478922
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1912712458
Short name	T700
Test name
Test status
Simulation time	112565275 ps
CPU time	5.84 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	202008 kb
Host	smart-a2cd9ff7-4f82-4271-b027-5aa5a807fa21
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912712458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1912712458
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.2177840039
Short name	T235
Test name
Test status
Simulation time	55015079 ps
CPU time	5.66 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	201988 kb
Host	smart-1f7e2c6c-d014-458c-b2dc-a3415a3d806b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2177840039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2177840039
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.2991816948
Short name	T661
Test name
Test status
Simulation time	16782666 ps
CPU time	1.17 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201884 kb
Host	smart-2084a55b-1a43-4e9f-bc75-2b873dae2f62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991816948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2991816948
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.386653310
Short name	T272
Test name
Test status
Simulation time	9437973490 ps
CPU time	9.51 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	202060 kb
Host	smart-d1dfa353-9b88-4e9d-8204-aabf5effeffd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=386653310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.386653310
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1143012757
Short name	T666
Test name
Test status
Simulation time	1394814812 ps
CPU time	8.47 seconds
Started	Apr 18 12:39:01 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201936 kb
Host	smart-acc73eff-df3c-4a10-a1e7-1c5e46d5a664
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1143012757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1143012757
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1244371329
Short name	T685
Test name
Test status
Simulation time	12328984 ps
CPU time	1.41 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	201876 kb
Host	smart-1f48ff48-5482-4a69-b9f8-43d8633e2cff
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244371329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1244371329
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.1849455986
Short name	T834
Test name
Test status
Simulation time	6699929 ps
CPU time	0.76 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:01 PM PDT 24
Peak memory	193736 kb
Host	smart-36eda866-cd77-44e6-a6a0-aebeda03bc56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849455986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1849455986
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3719401942
Short name	T253
Test name
Test status
Simulation time	3995642429 ps
CPU time	29.59 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	203092 kb
Host	smart-e629daa7-0996-4d41-b25b-24fb4c89d975
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3719401942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3719401942
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1660827922
Short name	T643
Test name
Test status
Simulation time	87592610 ps
CPU time	7.97 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	202004 kb
Host	smart-dccdcfaa-ffa8-4f69-b94b-029626a07ed4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660827922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1660827922
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1123479900
Short name	T276
Test name
Test status
Simulation time	898521463 ps
CPU time	7.18 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	201968 kb
Host	smart-473b6cdb-f79c-4cc8-991f-e1b19a37f324
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1123479900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1123479900
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2291530517
Short name	T628
Test name
Test status
Simulation time	33542487 ps
CPU time	8.02 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201972 kb
Host	smart-447397e0-c794-4d63-bef3-0a6b37c8eddd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291530517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2291530517
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1483845724
Short name	T155
Test name
Test status
Simulation time	156065067049 ps
CPU time	228.16 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:42:55 PM PDT 24
Peak memory	203440 kb
Host	smart-dbc534b6-d30a-4f7f-aa53-021010b2e2fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1483845724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1483845724
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3727763839
Short name	T807
Test name
Test status
Simulation time	13088461 ps
CPU time	1.4 seconds
Started	Apr 18 12:39:04 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	201976 kb
Host	smart-b8521617-1c49-4ae0-bb79-dc023dc98a0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3727763839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3727763839
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.483462337
Short name	T656
Test name
Test status
Simulation time	467764263 ps
CPU time	5.76 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201972 kb
Host	smart-88cda9ce-e209-4e38-ad75-682e33934fed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=483462337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.483462337
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.2404740676
Short name	T341
Test name
Test status
Simulation time	695725450 ps
CPU time	9.16 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	202008 kb
Host	smart-634ed3fb-1d1d-473d-a173-dd353f7879a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404740676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2404740676
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2927242090
Short name	T156
Test name
Test status
Simulation time	13738367079 ps
CPU time	61.67 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201980 kb
Host	smart-17fd095e-132d-4266-a9eb-f5177f2e5dad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2927242090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2927242090
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.259606617
Short name	T722
Test name
Test status
Simulation time	34461588 ps
CPU time	3.34 seconds
Started	Apr 18 12:39:16 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	201976 kb
Host	smart-4113a666-6aa5-4bb5-ac39-f25ac66030e8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259606617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.259606617
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.3889448573
Short name	T325
Test name
Test status
Simulation time	558087332 ps
CPU time	5.47 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	201976 kb
Host	smart-065efab0-6be2-4e36-b806-98a5e067d4ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3889448573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3889448573
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.3137395837
Short name	T273
Test name
Test status
Simulation time	59693891 ps
CPU time	1.66 seconds
Started	Apr 18 12:39:03 PM PDT 24
Finished	Apr 18 12:39:06 PM PDT 24
Peak memory	201916 kb
Host	smart-6b0de936-7e39-43d1-b689-8643a47f1128
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3137395837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3137395837
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.230119344
Short name	T644
Test name
Test status
Simulation time	1913003031 ps
CPU time	9.84 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	201928 kb
Host	smart-30e24b77-eaba-4b82-83fd-1ff4682935cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=230119344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.230119344
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2457659774
Short name	T380
Test name
Test status
Simulation time	12422218373 ps
CPU time	10.23 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:25 PM PDT 24
Peak memory	202072 kb
Host	smart-e5ea9dd8-7025-4a2e-b2dc-53f6002b8cd7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2457659774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2457659774
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2018791839
Short name	T323
Test name
Test status
Simulation time	8336423 ps
CPU time	0.99 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	202008 kb
Host	smart-514a7bfd-3bbf-4c76-b5d4-40ba8378d365
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018791839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2018791839
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.2394660845
Short name	T683
Test name
Test status
Simulation time	4501672121 ps
CPU time	57.46 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	203052 kb
Host	smart-89d9bff1-d2d6-4ebd-bbfe-0b9ebbbca797
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394660845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2394660845
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2495967415
Short name	T371
Test name
Test status
Simulation time	11429847379 ps
CPU time	77.52 seconds
Started	Apr 18 12:39:05 PM PDT 24
Finished	Apr 18 12:40:24 PM PDT 24
Peak memory	203008 kb
Host	smart-35bea668-602d-4597-9455-f0c68d510863
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2495967415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2495967415
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3628471057
Short name	T363
Test name
Test status
Simulation time	658990334 ps
CPU time	121.87 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:41:16 PM PDT 24
Peak memory	204080 kb
Host	smart-f36e457b-f010-41e9-9817-1f7a3fcefdec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628471057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3628471057
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.506965001
Short name	T449
Test name
Test status
Simulation time	2575618299 ps
CPU time	68.95 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	204928 kb
Host	smart-54645300-34da-4c2f-871c-653a1f761a70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=506965001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.506965001
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2780515526
Short name	T780
Test name
Test status
Simulation time	8541814 ps
CPU time	1.02 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:14 PM PDT 24
Peak memory	201876 kb
Host	smart-c8b62e00-54e0-474a-bb8c-747800a510ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2780515526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2780515526
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3993436277
Short name	T711
Test name
Test status
Simulation time	3467749517 ps
CPU time	17.41 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	202052 kb
Host	smart-f9a166d9-b1b5-41f6-9dac-c0981f8d7e60
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3993436277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3993436277
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2850903492
Short name	T589
Test name
Test status
Simulation time	22066227 ps
CPU time	1.21 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:15 PM PDT 24
Peak memory	202012 kb
Host	smart-fc7c544b-6e34-49cf-af96-60207a5c5a23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850903492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2850903492
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.3208613798
Short name	T194
Test name
Test status
Simulation time	52981719 ps
CPU time	6.47 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	202004 kb
Host	smart-31cc9aea-f7ff-4737-873d-677d2f717784
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3208613798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3208613798
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.4088235757
Short name	T813
Test name
Test status
Simulation time	113581987 ps
CPU time	2.23 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:16 PM PDT 24
Peak memory	202012 kb
Host	smart-fe76b46c-3ae3-4cad-a040-31d02de34022
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4088235757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4088235757
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4294421425
Short name	T525
Test name
Test status
Simulation time	27769585405 ps
CPU time	63.76 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201988 kb
Host	smart-8dbd1297-61c1-4604-bcff-5201e1d509dd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294421425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4294421425
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.4222234584
Short name	T256
Test name
Test status
Simulation time	22709987091 ps
CPU time	99.8 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:40:49 PM PDT 24
Peak memory	201928 kb
Host	smart-0e9a2d00-e8d1-4e65-bd62-2509aa104a2b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4222234584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4222234584
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1956430504
Short name	T848
Test name
Test status
Simulation time	65214300 ps
CPU time	8.4 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201980 kb
Host	smart-3935f0de-c92d-4d50-a84b-3de326a72908
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956430504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1956430504
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.2592324687
Short name	T183
Test name
Test status
Simulation time	52507806 ps
CPU time	1.82 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201892 kb
Host	smart-7aeaf4c4-c7e7-4b43-a3b7-a2cfd812887b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2592324687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2592324687
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.3488196737
Short name	T900
Test name
Test status
Simulation time	103115069 ps
CPU time	1.78 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201988 kb
Host	smart-8bd601b4-6645-434b-9d3c-a7339ace82d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3488196737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3488196737
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3715772486
Short name	T899
Test name
Test status
Simulation time	3267354790 ps
CPU time	10.12 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201980 kb
Host	smart-1957d13a-053d-4ce8-af3c-e5fb76a1fbcc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715772486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3715772486
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1296429778
Short name	T880
Test name
Test status
Simulation time	4078136082 ps
CPU time	7.82 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	201984 kb
Host	smart-52b13cc5-31ae-4311-81e0-5576545aec21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1296429778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1296429778
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.454933894
Short name	T280
Test name
Test status
Simulation time	16255023 ps
CPU time	1.37 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201900 kb
Host	smart-b211aaa4-58ec-4643-beb8-0aa31578847b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454933894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.454933894
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.234150428
Short name	T301
Test name
Test status
Simulation time	594065770 ps
CPU time	16.51 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:32 PM PDT 24
Peak memory	201736 kb
Host	smart-9e9e1964-6eb7-4c7a-ac4f-4386e3f80021
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=234150428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.234150428
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.918603313
Short name	T714
Test name
Test status
Simulation time	2428603846 ps
CPU time	22.32 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	202064 kb
Host	smart-ca7d4c44-b359-4ff4-9c49-8d1dfcdef39d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918603313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.918603313
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2496908039
Short name	T793
Test name
Test status
Simulation time	433349336 ps
CPU time	57.74 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	204548 kb
Host	smart-963ec5bf-c58c-4699-94da-5bee6818c60b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496908039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2496908039
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3178887334
Short name	T517
Test name
Test status
Simulation time	703644972 ps
CPU time	122.29 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:41:19 PM PDT 24
Peak memory	207152 kb
Host	smart-3edd0b81-d399-449c-8ce3-1ae0228e0309
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3178887334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3178887334
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4178568884
Short name	T730
Test name
Test status
Simulation time	45918147 ps
CPU time	5.44 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:16 PM PDT 24
Peak memory	201944 kb
Host	smart-42805fd7-19a6-433a-a887-8174fe9b0207
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4178568884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4178568884
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.21710353
Short name	T466
Test name
Test status
Simulation time	233309629 ps
CPU time	9.63 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	201924 kb
Host	smart-55842433-52fb-4654-8fb7-9340e37c3061
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=21710353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.21710353
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.997875532
Short name	T583
Test name
Test status
Simulation time	125548955350 ps
CPU time	254.39 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:43:33 PM PDT 24
Peak memory	203620 kb
Host	smart-d4e792f4-837d-4810-b0de-01631d264294
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=997875532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.997875532
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3992605942
Short name	T539
Test name
Test status
Simulation time	41912716 ps
CPU time	4.03 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201860 kb
Host	smart-fe0f0bb3-b177-4016-8e08-c0d74c229176
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3992605942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3992605942
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.1229125197
Short name	T315
Test name
Test status
Simulation time	3437336172 ps
CPU time	12.15 seconds
Started	Apr 18 12:38:57 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	202052 kb
Host	smart-247b7903-ce65-4a36-978c-490db059a40c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1229125197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1229125197
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.3667608478
Short name	T335
Test name
Test status
Simulation time	428343939 ps
CPU time	5.08 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201984 kb
Host	smart-a80660ef-0755-4b0b-b411-7210011dace7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667608478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3667608478
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.4071977040
Short name	T58
Test name
Test status
Simulation time	26361745141 ps
CPU time	80.95 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	202000 kb
Host	smart-7af27134-1dd8-44b0-876e-542afc06459a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071977040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4071977040
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.59809026
Short name	T797
Test name
Test status
Simulation time	5090116755 ps
CPU time	17.75 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201972 kb
Host	smart-cbe233b3-0976-40b8-abdd-9b22b21e11d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=59809026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.59809026
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1592143961
Short name	T778
Test name
Test status
Simulation time	186152179 ps
CPU time	6.47 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:16 PM PDT 24
Peak memory	202020 kb
Host	smart-f8e3cebb-c755-4012-9bf0-f4d1a3f84180
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592143961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1592143961
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.3437552957
Short name	T530
Test name
Test status
Simulation time	232600198 ps
CPU time	3.45 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201996 kb
Host	smart-4842c4fc-fe31-4279-a55c-cffbb69c46ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437552957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3437552957
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.1167201948
Short name	T403
Test name
Test status
Simulation time	106282129 ps
CPU time	1.66 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201884 kb
Host	smart-85397629-f6ab-4543-aa10-e3f472eb94e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1167201948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1167201948
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.934437264
Short name	T476
Test name
Test status
Simulation time	3658376788 ps
CPU time	9.89 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	202000 kb
Host	smart-1197d782-e11b-46ea-8b47-4767d3029745
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=934437264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.934437264
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1729426591
Short name	T707
Test name
Test status
Simulation time	12300560281 ps
CPU time	10.21 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201996 kb
Host	smart-811b4437-5b5e-4870-ba10-413eddbb94e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1729426591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1729426591
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3266843193
Short name	T654
Test name
Test status
Simulation time	9849021 ps
CPU time	1.12 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:16 PM PDT 24
Peak memory	201936 kb
Host	smart-6e9a9be2-89cf-4221-87ba-1971cbe148d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266843193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3266843193
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.2103019502
Short name	T692
Test name
Test status
Simulation time	1574881280 ps
CPU time	17.3 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	201876 kb
Host	smart-77ef99f2-8554-4caa-ad82-b89301efb99e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103019502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2103019502
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3872949708
Short name	T602
Test name
Test status
Simulation time	4242156863 ps
CPU time	31.46 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	202036 kb
Host	smart-24207385-b11b-4530-80d3-4838cfda62c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872949708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3872949708
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1492713152
Short name	T808
Test name
Test status
Simulation time	536520231 ps
CPU time	89.2 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:40:43 PM PDT 24
Peak memory	204052 kb
Host	smart-ad47a6d1-62c6-49ba-adac-9a7e50f6f29b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492713152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1492713152
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1487601681
Short name	T629
Test name
Test status
Simulation time	8028634 ps
CPU time	6.08 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201920 kb
Host	smart-28338cd8-457c-437a-8fab-0481aeea0687
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487601681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1487601681
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.468404557
Short name	T388
Test name
Test status
Simulation time	1124682492 ps
CPU time	10.75 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201860 kb
Host	smart-0b00a1de-6159-414a-a123-301960514969
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=468404557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.468404557
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3659156868
Short name	T100
Test name
Test status
Simulation time	1391474422 ps
CPU time	20.03 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:55 PM PDT 24
Peak memory	201948 kb
Host	smart-8aab95be-a73d-414f-b917-a520ef8a5140
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3659156868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3659156868
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2335798973
Short name	T532
Test name
Test status
Simulation time	93384098599 ps
CPU time	158.79 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:41:05 PM PDT 24
Peak memory	204012 kb
Host	smart-4d9c75a3-e9a1-48b1-920e-aa39ee6718ce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2335798973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2335798973
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.323515351
Short name	T296
Test name
Test status
Simulation time	1642217299 ps
CPU time	7.5 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:34 PM PDT 24
Peak memory	201908 kb
Host	smart-1a0d1fcf-a4a5-4cf9-804e-11c08df1829f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323515351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.323515351
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.489555992
Short name	T436
Test name
Test status
Simulation time	45655546 ps
CPU time	1.95 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:30 PM PDT 24
Peak memory	201912 kb
Host	smart-e0cc6201-63c1-495e-ac0a-779936d293f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489555992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.489555992
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.645999008
Short name	T537
Test name
Test status
Simulation time	822543099 ps
CPU time	9.8 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	201916 kb
Host	smart-0cac086f-c71f-463b-9deb-051ac3dbb7d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=645999008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.645999008
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4078673890
Short name	T415
Test name
Test status
Simulation time	43143819721 ps
CPU time	102.11 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	201992 kb
Host	smart-2440ebc6-dc77-48ae-aae1-0a63ac9cfe27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078673890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4078673890
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4206693281
Short name	T610
Test name
Test status
Simulation time	8094444126 ps
CPU time	11.26 seconds
Started	Apr 18 12:38:24 PM PDT 24
Finished	Apr 18 12:38:35 PM PDT 24
Peak memory	202048 kb
Host	smart-c6640962-f956-4ed6-ae4c-4fa2c7c372c2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4206693281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4206693281
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1600976807
Short name	T268
Test name
Test status
Simulation time	43381767 ps
CPU time	4.26 seconds
Started	Apr 18 12:38:25 PM PDT 24
Finished	Apr 18 12:38:30 PM PDT 24
Peak memory	202020 kb
Host	smart-ebbc4931-c349-4ecb-901a-04f02c0ae3d5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600976807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1600976807
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.461894834
Short name	T192
Test name
Test status
Simulation time	78089720 ps
CPU time	2.6 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:31 PM PDT 24
Peak memory	201900 kb
Host	smart-77b6496f-873f-48fb-b7d9-1716490c063c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=461894834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.461894834
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.1909482911
Short name	T242
Test name
Test status
Simulation time	54519692 ps
CPU time	1.7 seconds
Started	Apr 18 12:38:29 PM PDT 24
Finished	Apr 18 12:38:32 PM PDT 24
Peak memory	202012 kb
Host	smart-0fa29740-910a-44d9-9359-cd403d300a66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909482911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1909482911
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1498465207
Short name	T395
Test name
Test status
Simulation time	6036819733 ps
CPU time	7.89 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:36 PM PDT 24
Peak memory	202084 kb
Host	smart-3f0003fe-73c1-4999-829d-1ab4d98d51ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498465207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1498465207
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3480029072
Short name	T828
Test name
Test status
Simulation time	8898015644 ps
CPU time	8.56 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	201988 kb
Host	smart-f2767f83-d2d4-40ee-bb77-56b0771a977e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3480029072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3480029072
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1784170056
Short name	T85
Test name
Test status
Simulation time	14152933 ps
CPU time	1.09 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:35 PM PDT 24
Peak memory	201844 kb
Host	smart-0e81cdf3-e617-40a4-9d63-d7ee03f2c061
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784170056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1784170056
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.241097123
Short name	T637
Test name
Test status
Simulation time	3135821270 ps
CPU time	44.16 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	202092 kb
Host	smart-f1908d50-5e41-46be-9ad4-a5705f4acc7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=241097123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.241097123
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1203467732
Short name	T796
Test name
Test status
Simulation time	1948598588 ps
CPU time	54.85 seconds
Started	Apr 18 12:38:31 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201924 kb
Host	smart-fad1a8db-8c09-441d-9a38-d205741c3f6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1203467732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1203467732
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.540570631
Short name	T521
Test name
Test status
Simulation time	4599747865 ps
CPU time	110.05 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	205072 kb
Host	smart-e61a07d7-91af-48d6-8be1-8da2b5ae3df2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=540570631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_ reset.540570631
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3798379521
Short name	T725
Test name
Test status
Simulation time	158413455 ps
CPU time	11.49 seconds
Started	Apr 18 12:38:30 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	202000 kb
Host	smart-436942f3-8dd9-47c2-9f3e-b418814c7190
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3798379521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3798379521
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3316625329
Short name	T875
Test name
Test status
Simulation time	900209358 ps
CPU time	11.21 seconds
Started	Apr 18 12:38:29 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	202004 kb
Host	smart-c50c08b3-1068-40c9-887f-5aa49beb377b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316625329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3316625329
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2486033355
Short name	T336
Test name
Test status
Simulation time	18015275 ps
CPU time	2.05 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:34 PM PDT 24
Peak memory	201940 kb
Host	smart-7b144a32-917b-421c-b360-298c076c6840
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2486033355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2486033355
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.4053632153
Short name	T159
Test name
Test status
Simulation time	37960808611 ps
CPU time	161.04 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:41:56 PM PDT 24
Peak memory	203260 kb
Host	smart-6395daf6-686e-4c73-ad1f-e23333eff9ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4053632153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.4053632153
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1833406795
Short name	T876
Test name
Test status
Simulation time	766174409 ps
CPU time	7.24 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	201924 kb
Host	smart-98af9ef6-0f93-4ccc-a7ac-a64869d87bdb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1833406795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1833406795
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.3054221775
Short name	T609
Test name
Test status
Simulation time	863569746 ps
CPU time	4.34 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201936 kb
Host	smart-0858935b-475b-4f7c-96e3-92cdf1df5ee6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3054221775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3054221775
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.4175471887
Short name	T379
Test name
Test status
Simulation time	231646369 ps
CPU time	7.26 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201880 kb
Host	smart-0ffa5286-a393-42d3-a80c-365792e92ff7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175471887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4175471887
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3725818314
Short name	T383
Test name
Test status
Simulation time	11316807799 ps
CPU time	20.87 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	202084 kb
Host	smart-63458d3b-6b89-4dfd-9b46-f7aa2c2f2a40
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725818314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3725818314
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3063174594
Short name	T210
Test name
Test status
Simulation time	19326149656 ps
CPU time	126.27 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:41:25 PM PDT 24
Peak memory	201980 kb
Host	smart-1ca58871-c9e3-490a-86b9-f9b029603b68
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3063174594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3063174594
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.457028461
Short name	T498
Test name
Test status
Simulation time	43600983 ps
CPU time	6.3 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:15 PM PDT 24
Peak memory	201900 kb
Host	smart-2046a48a-302c-4ecf-8996-e4600824e4bf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457028461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.457028461
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.2756711223
Short name	T853
Test name
Test status
Simulation time	6195004747 ps
CPU time	9.37 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:25 PM PDT 24
Peak memory	202096 kb
Host	smart-b8613e62-9134-4403-8ace-2ad4301d8d5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756711223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2756711223
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.2095861331
Short name	T295
Test name
Test status
Simulation time	106441957 ps
CPU time	1.64 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201924 kb
Host	smart-c80abb68-63a1-443e-b948-cf78ed003575
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2095861331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2095861331
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2781266065
Short name	T305
Test name
Test status
Simulation time	5615855495 ps
CPU time	9.83 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	201928 kb
Host	smart-58bb9754-7a18-4d57-9907-d2918686153e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781266065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2781266065
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.907573264
Short name	T345
Test name
Test status
Simulation time	7281947234 ps
CPU time	10.93 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	202084 kb
Host	smart-82b25a18-8f0d-4e2b-a04a-dac514747666
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=907573264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.907573264
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3157946732
Short name	T350
Test name
Test status
Simulation time	14065121 ps
CPU time	1.34 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:11 PM PDT 24
Peak memory	201972 kb
Host	smart-5f2e14ca-2682-4790-9c37-8d69584235d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157946732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3157946732
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.3403583669
Short name	T298
Test name
Test status
Simulation time	5749122445 ps
CPU time	25.93 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	203236 kb
Host	smart-c189f0cc-31f1-485b-804b-106f99b12cde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403583669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3403583669
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1799740261
Short name	T493
Test name
Test status
Simulation time	571853003 ps
CPU time	31.47 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	201896 kb
Host	smart-e48582e9-bd3b-4630-bee9-716422b44f22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799740261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1799740261
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3971433639
Short name	T180
Test name
Test status
Simulation time	123501488 ps
CPU time	8.62 seconds
Started	Apr 18 12:39:07 PM PDT 24
Finished	Apr 18 12:39:16 PM PDT 24
Peak memory	201892 kb
Host	smart-eb9d87fd-cae1-483b-affd-12a4d7ccf2c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3971433639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.3971433639
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.686429117
Short name	T554
Test name
Test status
Simulation time	1626174634 ps
CPU time	83.09 seconds
Started	Apr 18 12:39:21 PM PDT 24
Finished	Apr 18 12:40:45 PM PDT 24
Peak memory	204844 kb
Host	smart-de8e5ded-6a10-448d-85c4-f5aeadd17a7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686429117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res et_error.686429117
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1402873904
Short name	T686
Test name
Test status
Simulation time	383357063 ps
CPU time	7.09 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201976 kb
Host	smart-3b387d15-c6f2-4799-826d-0b53f4050157
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402873904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1402873904
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1873613616
Short name	T746
Test name
Test status
Simulation time	38418574 ps
CPU time	4.64 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	202044 kb
Host	smart-0b925b21-42a1-40c9-b643-624e45f5d02a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1873613616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1873613616
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3957259271
Short name	T823
Test name
Test status
Simulation time	37146168973 ps
CPU time	154.32 seconds
Started	Apr 18 12:39:17 PM PDT 24
Finished	Apr 18 12:41:53 PM PDT 24
Peak memory	203068 kb
Host	smart-03b5292a-2214-4bcb-aa45-3f1b48f56f20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3957259271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3957259271
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4242150873
Short name	T248
Test name
Test status
Simulation time	811376735 ps
CPU time	10.67 seconds
Started	Apr 18 12:39:09 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	201928 kb
Host	smart-03cb7b82-6cdc-4cd2-bf94-70fca6d75eca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242150873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4242150873
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.1654286988
Short name	T440
Test name
Test status
Simulation time	75417724 ps
CPU time	5.73 seconds
Started	Apr 18 12:39:06 PM PDT 24
Finished	Apr 18 12:39:13 PM PDT 24
Peak memory	201964 kb
Host	smart-3efcd7b8-ab14-491e-9ca4-38e30ed15213
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1654286988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1654286988
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.3253418966
Short name	T240
Test name
Test status
Simulation time	921796243 ps
CPU time	12.14 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	202036 kb
Host	smart-f0061553-9dd9-46fb-aa0c-98b558593c5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253418966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3253418966
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4216221291
Short name	T354
Test name
Test status
Simulation time	19902082440 ps
CPU time	44.1 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	201996 kb
Host	smart-08b9d46b-7da7-4d09-acd5-73ac63a5e3d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216221291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4216221291
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1746388009
Short name	T690
Test name
Test status
Simulation time	9195218581 ps
CPU time	25.86 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:53 PM PDT 24
Peak memory	202000 kb
Host	smart-98417c46-0b79-4a6f-9973-04e0718273ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1746388009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1746388009
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1217222109
Short name	T673
Test name
Test status
Simulation time	41280817 ps
CPU time	5.04 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201864 kb
Host	smart-e3d4b842-d965-4c7b-a509-8114737d3ed7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217222109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1217222109
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.2522839899
Short name	T228
Test name
Test status
Simulation time	484770884 ps
CPU time	5.84 seconds
Started	Apr 18 12:39:16 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201852 kb
Host	smart-fd970502-fc35-44d9-bc3b-363286b204bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522839899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2522839899
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.3436272583
Short name	T5
Test name
Test status
Simulation time	11331040 ps
CPU time	1.28 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	202004 kb
Host	smart-7f5bdba7-ac10-404d-b402-52338b021902
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3436272583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3436272583
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.814780315
Short name	T594
Test name
Test status
Simulation time	2109579464 ps
CPU time	9.48 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	201932 kb
Host	smart-00bccbb4-5194-4365-b9ac-c6e3872e758c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=814780315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.814780315
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.828776521
Short name	T443
Test name
Test status
Simulation time	1604772288 ps
CPU time	12.26 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:37 PM PDT 24
Peak memory	202048 kb
Host	smart-36561a9b-9276-460c-903e-f7b5de10b610
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=828776521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.828776521
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2864584899
Short name	T94
Test name
Test status
Simulation time	11309627 ps
CPU time	0.99 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	201992 kb
Host	smart-aaf02ea8-610a-462a-973e-c9db21c79d01
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864584899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2864584899
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.834435846
Short name	T291
Test name
Test status
Simulation time	1932366232 ps
CPU time	28.27 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:44 PM PDT 24
Peak memory	204092 kb
Host	smart-e46d2368-9d01-461f-9355-c4748353a781
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=834435846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.834435846
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3925360542
Short name	T748
Test name
Test status
Simulation time	562375814 ps
CPU time	16.4 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:39:37 PM PDT 24
Peak memory	202036 kb
Host	smart-2aae5a08-0493-4722-b7d7-a40540f73308
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3925360542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3925360542
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3636515864
Short name	T660
Test name
Test status
Simulation time	2655740998 ps
CPU time	71.78 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	204644 kb
Host	smart-0ebd84d2-272b-47dd-8ff8-88d3b5b8664e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3636515864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3636515864
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3747311685
Short name	T170
Test name
Test status
Simulation time	65386836 ps
CPU time	15.35 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	202644 kb
Host	smart-3f238039-cae0-43f9-9788-290ec87e00de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3747311685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3747311685
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1805367691
Short name	T659
Test name
Test status
Simulation time	68110697 ps
CPU time	1.7 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:32 PM PDT 24
Peak memory	201908 kb
Host	smart-b49e813a-e8fb-46c5-b277-b639782e0987
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805367691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1805367691
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.353973616
Short name	T513
Test name
Test status
Simulation time	116679058 ps
CPU time	12.78 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	202020 kb
Host	smart-a9678f39-ff52-4ab4-81b2-fc428613c8c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353973616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.353973616
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1179456058
Short name	T270
Test name
Test status
Simulation time	812558001 ps
CPU time	9.47 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	202008 kb
Host	smart-2f0677b1-0330-4fc6-8380-0e70b6f62d7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1179456058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1179456058
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.484500905
Short name	T312
Test name
Test status
Simulation time	49443971 ps
CPU time	5.08 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:32 PM PDT 24
Peak memory	201900 kb
Host	smart-e253da0b-ff03-4c09-b4fe-4d797520c421
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=484500905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.484500905
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.2148836174
Short name	T620
Test name
Test status
Simulation time	50408873 ps
CPU time	5.14 seconds
Started	Apr 18 12:39:31 PM PDT 24
Finished	Apr 18 12:39:37 PM PDT 24
Peak memory	201984 kb
Host	smart-416c9bce-1cf3-40af-8b37-326c7914dd70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2148836174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2148836174
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3837228877
Short name	T269
Test name
Test status
Simulation time	24778184502 ps
CPU time	107.64 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:41:08 PM PDT 24
Peak memory	201704 kb
Host	smart-bb94de8f-8a25-436b-904d-3fa85a15141e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837228877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3837228877
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2124700190
Short name	T545
Test name
Test status
Simulation time	16771351677 ps
CPU time	81.32 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:40:45 PM PDT 24
Peak memory	202084 kb
Host	smart-d8d6e58e-0451-460e-9bb7-13daf5142514
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2124700190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2124700190
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.316625750
Short name	T365
Test name
Test status
Simulation time	30873338 ps
CPU time	3.58 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201912 kb
Host	smart-c9a0f22b-7241-425a-b945-05ae4e4ce40a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316625750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.316625750
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.637221025
Short name	T538
Test name
Test status
Simulation time	203443048 ps
CPU time	5.47 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201980 kb
Host	smart-4189c379-2f81-4a6e-b26e-e6b717b32b8f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=637221025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.637221025
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.1714560502
Short name	T749
Test name
Test status
Simulation time	9628970 ps
CPU time	1.38 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201880 kb
Host	smart-98537564-d866-47c9-9bbf-386f1cf319f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714560502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1714560502
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.552004655
Short name	T288
Test name
Test status
Simulation time	5928895830 ps
CPU time	9.63 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	202008 kb
Host	smart-3afeb6d0-b03a-46b8-b53b-0d3186451b59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=552004655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.552004655
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1751059953
Short name	T633
Test name
Test status
Simulation time	1310968474 ps
CPU time	6.6 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	201996 kb
Host	smart-97b3eb8f-d37a-42d2-8195-bc747206556a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1751059953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1751059953
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1979206117
Short name	T128
Test name
Test status
Simulation time	8996148 ps
CPU time	1.19 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201908 kb
Host	smart-6c394a14-5c71-4d7e-86d2-ae5c7a54e68e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979206117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1979206117
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.2836288623
Short name	T896
Test name
Test status
Simulation time	3519054601 ps
CPU time	28.83 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	202052 kb
Host	smart-2cccf13b-9658-4d69-b487-ee56a88f4ea0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2836288623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2836288623
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2258352125
Short name	T838
Test name
Test status
Simulation time	3431610308 ps
CPU time	48.13 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	201996 kb
Host	smart-bd2feb99-769b-4cef-87b5-5afc95545f42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258352125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2258352125
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1058799639
Short name	T84
Test name
Test status
Simulation time	2474333495 ps
CPU time	42.1 seconds
Started	Apr 18 12:39:12 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	205936 kb
Host	smart-1dc5be98-930f-4031-bc20-219bf1d8eaa0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1058799639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1058799639
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3634707153
Short name	T167
Test name
Test status
Simulation time	323506669 ps
CPU time	27.29 seconds
Started	Apr 18 12:39:11 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	203936 kb
Host	smart-c9946e76-f11d-4a8f-8541-0166802c08ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3634707153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3634707153
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.860258859
Short name	T333
Test name
Test status
Simulation time	193879700 ps
CPU time	1.23 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201912 kb
Host	smart-8097c818-48f6-46f5-9c1d-97231feb4b11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860258859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.860258859
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.960151006
Short name	T869
Test name
Test status
Simulation time	101069229 ps
CPU time	1.7 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	202004 kb
Host	smart-aa7db38e-969e-4d39-b3e0-2380ad1792b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960151006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.960151006
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.388905470
Short name	T151
Test name
Test status
Simulation time	46719522950 ps
CPU time	268.08 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:43:49 PM PDT 24
Peak memory	203084 kb
Host	smart-3f46564e-e9b3-4243-a1d8-5aacab86cc91
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=388905470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.388905470
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3978202230
Short name	T885
Test name
Test status
Simulation time	35930023 ps
CPU time	1.74 seconds
Started	Apr 18 12:39:36 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	201908 kb
Host	smart-1fb96fc9-30be-4f8c-8947-d4ee8d5a388c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3978202230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3978202230
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.1889880384
Short name	T368
Test name
Test status
Simulation time	1764300293 ps
CPU time	4.74 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:20 PM PDT 24
Peak memory	201976 kb
Host	smart-25c49b08-3541-4766-926d-15c53ac7df0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1889880384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1889880384
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.2838487217
Short name	T215
Test name
Test status
Simulation time	356088973 ps
CPU time	6.97 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	202020 kb
Host	smart-ea372921-60a1-4f12-9fd2-265881f2a3a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2838487217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2838487217
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.986501369
Short name	T781
Test name
Test status
Simulation time	40096162043 ps
CPU time	37.62 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201984 kb
Host	smart-6ae79baf-772e-4e29-a33e-7ea490e54eb2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=986501369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.986501369
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2526954733
Short name	T375
Test name
Test status
Simulation time	107640906490 ps
CPU time	124.72 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:41:30 PM PDT 24
Peak memory	201984 kb
Host	smart-efa22d16-f83b-41ce-b1c1-0310903b9281
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2526954733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2526954733
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.719790611
Short name	T864
Test name
Test status
Simulation time	45130114 ps
CPU time	5.99 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	202012 kb
Host	smart-f0dccd19-035d-4181-8e23-3cdb2acf969c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719790611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.719790611
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.2313694589
Short name	T185
Test name
Test status
Simulation time	200277485 ps
CPU time	5.27 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	202272 kb
Host	smart-69a0b405-b4df-4cdd-87be-d421fec0f1ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313694589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2313694589
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.3221699564
Short name	T605
Test name
Test status
Simulation time	104679637 ps
CPU time	1.78 seconds
Started	Apr 18 12:39:13 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201632 kb
Host	smart-6d3c9769-5bdf-4250-a9c5-e73ca974caf3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221699564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3221699564
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4023972187
Short name	T429
Test name
Test status
Simulation time	2331236544 ps
CPU time	7.45 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:32 PM PDT 24
Peak memory	202308 kb
Host	smart-fd92164d-ea09-4b22-9355-f73e9a1e522b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023972187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4023972187
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2552658350
Short name	T844
Test name
Test status
Simulation time	7800661047 ps
CPU time	12.84 seconds
Started	Apr 18 12:39:10 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201964 kb
Host	smart-9e66a720-426b-4ac4-944d-9a16a6d4f518
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2552658350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2552658350
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.80126966
Short name	T735
Test name
Test status
Simulation time	18652926 ps
CPU time	1.2 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201868 kb
Host	smart-9e7052bd-a6ff-42d2-a673-8f45a81338da
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80126966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.80126966
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.760817158
Short name	T491
Test name
Test status
Simulation time	3034683588 ps
CPU time	18.78 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	202948 kb
Host	smart-4d71076e-c4a3-4a38-9472-ba6f90cd292d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760817158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.760817158
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.766264048
Short name	T697
Test name
Test status
Simulation time	1743290221 ps
CPU time	27.18 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	201980 kb
Host	smart-636a5121-5836-4553-bb90-a7330fb6ed9f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=766264048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.766264048
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.545479925
Short name	T214
Test name
Test status
Simulation time	41116816 ps
CPU time	5.48 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201996 kb
Host	smart-d278e5e0-8956-4038-891c-0b555d3d213f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=545479925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.545479925
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1526489638
Short name	T816
Test name
Test status
Simulation time	33984239 ps
CPU time	4.12 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201900 kb
Host	smart-2c3392b0-25bf-4a59-bcd6-a187129c0170
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1526489638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1526489638
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1530367114
Short name	T719
Test name
Test status
Simulation time	225474133 ps
CPU time	5.83 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:34 PM PDT 24
Peak memory	201984 kb
Host	smart-d809bffb-58b9-409c-9222-03cf9688dd23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1530367114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1530367114
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3702109431
Short name	T47
Test name
Test status
Simulation time	83291970 ps
CPU time	6.7 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201908 kb
Host	smart-cfc17408-5e4e-464c-a625-6e569d711106
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3702109431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3702109431
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3870135421
Short name	T104
Test name
Test status
Simulation time	36845801537 ps
CPU time	154.55 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:42:05 PM PDT 24
Peak memory	203092 kb
Host	smart-3d9b8f67-07e7-40e1-9580-bc2e5b1fb7e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3870135421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3870135421
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.423814515
Short name	T427
Test name
Test status
Simulation time	597462817 ps
CPU time	3.58 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201936 kb
Host	smart-393e9678-ed3c-473b-8095-28e24aa09226
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=423814515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.423814515
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.1444960691
Short name	T433
Test name
Test status
Simulation time	161790770 ps
CPU time	5.65 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201948 kb
Host	smart-e9e83390-044c-48a5-9c8f-b5f69df81729
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1444960691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1444960691
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.2562867176
Short name	T263
Test name
Test status
Simulation time	14270748 ps
CPU time	1.77 seconds
Started	Apr 18 12:39:43 PM PDT 24
Finished	Apr 18 12:39:46 PM PDT 24
Peak memory	202016 kb
Host	smart-16bb8553-1e97-4519-8cfe-daa4ed3c027b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2562867176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2562867176
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4259444087
Short name	T547
Test name
Test status
Simulation time	12844169706 ps
CPU time	47.39 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:40:25 PM PDT 24
Peak memory	201984 kb
Host	smart-f7ad7143-16c2-4b2f-9de4-a5ef9c6d56a2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259444087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4259444087
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1127632804
Short name	T689
Test name
Test status
Simulation time	25158614731 ps
CPU time	83.84 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:40:47 PM PDT 24
Peak memory	201996 kb
Host	smart-8878b521-a68d-45a4-bbc5-0608d04241e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1127632804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1127632804
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3093254388
Short name	T861
Test name
Test status
Simulation time	26137946 ps
CPU time	1.36 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	201908 kb
Host	smart-8e716ddd-6678-4b36-9e1a-18d76e0fe731
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093254388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3093254388
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.1138788203
Short name	T224
Test name
Test status
Simulation time	186212994 ps
CPU time	6.3 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201916 kb
Host	smart-6673eabb-376c-403e-9901-d6b89d4fe6d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1138788203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1138788203
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.1825832460
Short name	T590
Test name
Test status
Simulation time	128825130 ps
CPU time	1.33 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	201976 kb
Host	smart-04a23ce1-3ea9-4812-9546-0a8421a233ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1825832460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1825832460
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.241238762
Short name	T332
Test name
Test status
Simulation time	3812114409 ps
CPU time	14.09 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:30 PM PDT 24
Peak memory	202056 kb
Host	smart-5515df66-b249-47aa-a871-4c5e9f3cc02b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=241238762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.241238762
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1668768754
Short name	T830
Test name
Test status
Simulation time	817260777 ps
CPU time	6.93 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201996 kb
Host	smart-219371f5-cfd7-47a2-b0f3-c709e4ba8252
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1668768754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1668768754
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2038095436
Short name	T721
Test name
Test status
Simulation time	9324393 ps
CPU time	1.36 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	202020 kb
Host	smart-3c10d6b1-66ec-4815-8ff7-5058c0826124
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038095436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2038095436
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.1329275287
Short name	T462
Test name
Test status
Simulation time	7197881282 ps
CPU time	97.6 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:40:53 PM PDT 24
Peak memory	205884 kb
Host	smart-d89faf7f-ccb6-405c-9dd1-c537ccdcb2f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1329275287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1329275287
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3906534846
Short name	T811
Test name
Test status
Simulation time	206584499 ps
CPU time	5.96 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201924 kb
Host	smart-db54a234-584c-4b49-9a16-bc3414b9d1d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906534846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3906534846
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2847182943
Short name	T130
Test name
Test status
Simulation time	1239612785 ps
CPU time	87.64 seconds
Started	Apr 18 12:39:34 PM PDT 24
Finished	Apr 18 12:41:03 PM PDT 24
Peak memory	204452 kb
Host	smart-329db42f-95cd-4a41-a3c4-98c31a73f1be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847182943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2847182943
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.642588824
Short name	T164
Test name
Test status
Simulation time	11454405918 ps
CPU time	139.95 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:41:48 PM PDT 24
Peak memory	205608 kb
Host	smart-8b0e26af-1cf1-4bd8-8c38-5d1327f8faa8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642588824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.642588824
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.713047591
Short name	T87
Test name
Test status
Simulation time	387216092 ps
CPU time	3.74 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	202008 kb
Host	smart-df780f18-8483-410f-92d6-b9c6e19091a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=713047591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.713047591
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3875526305
Short name	T733
Test name
Test status
Simulation time	34819447 ps
CPU time	6.53 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:40 PM PDT 24
Peak memory	201952 kb
Host	smart-aa1f6326-d6fb-4742-88e8-89bbce8a0f40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3875526305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3875526305
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2514183913
Short name	T423
Test name
Test status
Simulation time	12715970799 ps
CPU time	96.83 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:41:03 PM PDT 24
Peak memory	202076 kb
Host	smart-03be0e47-ec2f-45e0-a4a5-ba6e3e29f427
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2514183913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2514183913
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1171542678
Short name	T351
Test name
Test status
Simulation time	842133078 ps
CPU time	8.42 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201984 kb
Host	smart-0ddbf7b9-d06e-40dc-8b1d-f89d7fea543c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171542678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1171542678
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.1749255567
Short name	T364
Test name
Test status
Simulation time	875126108 ps
CPU time	9.67 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	202020 kb
Host	smart-bd5737fd-61b9-4331-bbc0-b6ce418ac382
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1749255567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1749255567
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.1638574353
Short name	T528
Test name
Test status
Simulation time	88372358 ps
CPU time	5.52 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	201956 kb
Host	smart-0987ffa6-a3ca-441e-813c-4362c35cecb9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1638574353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1638574353
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3449695479
Short name	T38
Test name
Test status
Simulation time	14422267900 ps
CPU time	54.43 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	202048 kb
Host	smart-081e78cd-741a-4a3a-9930-10ba1b6743f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449695479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3449695479
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.663623818
Short name	T795
Test name
Test status
Simulation time	8199801164 ps
CPU time	41.86 seconds
Started	Apr 18 12:39:22 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202000 kb
Host	smart-52f4e0ea-f347-4005-9c83-d86543f8861c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=663623818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.663623818
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3333860856
Short name	T41
Test name
Test status
Simulation time	38290479 ps
CPU time	1.59 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201952 kb
Host	smart-ee826107-9486-4d22-b83d-a3179bfa4f05
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333860856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3333860856
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.1695303995
Short name	T776
Test name
Test status
Simulation time	231833840 ps
CPU time	3.64 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:22 PM PDT 24
Peak memory	201892 kb
Host	smart-f579e407-a47b-4470-9a74-390c58eccb22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1695303995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1695303995
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.4153697960
Short name	T662
Test name
Test status
Simulation time	77389167 ps
CPU time	1.4 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201920 kb
Host	smart-489f2d84-e95d-4840-a6d3-ac824f62d3e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4153697960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4153697960
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1868420159
Short name	T773
Test name
Test status
Simulation time	4886511569 ps
CPU time	8.98 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	202080 kb
Host	smart-7d4b6941-dec7-4273-bd4c-a05c75e705b0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868420159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1868420159
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.13087039
Short name	T397
Test name
Test status
Simulation time	3844301642 ps
CPU time	11.83 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	202012 kb
Host	smart-3c65c19d-b164-47a8-b97c-ad8cbe9d2602
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=13087039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.13087039
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1527499054
Short name	T766
Test name
Test status
Simulation time	8265874 ps
CPU time	1.12 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	201936 kb
Host	smart-6dffbdc5-1f94-49e8-b7c8-c6c79f37e577
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527499054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1527499054
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.2142377842
Short name	T891
Test name
Test status
Simulation time	5943872853 ps
CPU time	11.78 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	202008 kb
Host	smart-1df8277b-f815-41ab-9176-7952f969b67d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2142377842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2142377842
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2336891429
Short name	T680
Test name
Test status
Simulation time	193494976 ps
CPU time	17.05 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:37 PM PDT 24
Peak memory	202008 kb
Host	smart-69ec6551-a31e-4134-a787-c95422a0f242
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336891429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2336891429
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1160577843
Short name	T852
Test name
Test status
Simulation time	758677624 ps
CPU time	50.78 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:40:29 PM PDT 24
Peak memory	204428 kb
Host	smart-e2d7c514-4242-4362-8c02-b4612255cb0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1160577843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1160577843
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1855723131
Short name	T138
Test name
Test status
Simulation time	366388056 ps
CPU time	36.44 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	203012 kb
Host	smart-ec599dac-e6cb-49d0-8c6a-90459e5a8948
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1855723131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1855723131
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3994309473
Short name	T408
Test name
Test status
Simulation time	850888907 ps
CPU time	11.74 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201908 kb
Host	smart-c1791db4-7425-4aa0-9bbb-3b7910a9f4a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994309473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3994309473
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2117239439
Short name	T860
Test name
Test status
Simulation time	2759279169 ps
CPU time	18.59 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	202072 kb
Host	smart-3a5a9eab-1922-4d7b-a67c-fa053d9aa0d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2117239439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2117239439
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.500496522
Short name	T160
Test name
Test status
Simulation time	97797027866 ps
CPU time	307.19 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:44:41 PM PDT 24
Peak memory	203632 kb
Host	smart-7b3975d1-b2ae-44f5-8e26-bfee6ab114a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=500496522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.500496522
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.575805306
Short name	T655
Test name
Test status
Simulation time	607859282 ps
CPU time	9.76 seconds
Started	Apr 18 12:39:16 PM PDT 24
Finished	Apr 18 12:39:28 PM PDT 24
Peak memory	201948 kb
Host	smart-4b689014-7034-4517-b17a-d928f9a89b9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575805306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.575805306
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.3449228293
Short name	T863
Test name
Test status
Simulation time	5352092167 ps
CPU time	16.02 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	202080 kb
Host	smart-3ab9ef20-3945-4407-b619-530e3896ec8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3449228293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3449228293
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.3697183646
Short name	T300
Test name
Test status
Simulation time	589235272 ps
CPU time	9.42 seconds
Started	Apr 18 12:39:34 PM PDT 24
Finished	Apr 18 12:39:44 PM PDT 24
Peak memory	201924 kb
Host	smart-f6c1b50f-3908-454d-8932-a79bab991e89
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697183646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3697183646
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3756709726
Short name	T206
Test name
Test status
Simulation time	42051950399 ps
CPU time	148.92 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:41:49 PM PDT 24
Peak memory	202076 kb
Host	smart-cb28b3df-663f-4d41-aa25-d94c4e8933a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756709726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3756709726
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3382231321
Short name	T127
Test name
Test status
Simulation time	25217763090 ps
CPU time	116.77 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:41:14 PM PDT 24
Peak memory	202080 kb
Host	smart-770e2519-78dc-46e1-a7db-ab71976b5602
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3382231321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3382231321
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.680212316
Short name	T677
Test name
Test status
Simulation time	94095482 ps
CPU time	7.93 seconds
Started	Apr 18 12:39:19 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	201988 kb
Host	smart-2925773b-f438-442a-a038-51e34898a05c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680212316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.680212316
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.1355903388
Short name	T806
Test name
Test status
Simulation time	3692899447 ps
CPU time	12.35 seconds
Started	Apr 18 12:39:21 PM PDT 24
Finished	Apr 18 12:39:34 PM PDT 24
Peak memory	201988 kb
Host	smart-96239fdc-ada9-482d-b58b-4aac68d5e3b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1355903388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1355903388
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.3254851020
Short name	T35
Test name
Test status
Simulation time	86637701 ps
CPU time	1.39 seconds
Started	Apr 18 12:39:15 PM PDT 24
Finished	Apr 18 12:39:18 PM PDT 24
Peak memory	201924 kb
Host	smart-c2c6f2b5-30fd-414e-b25e-a979d01f9ff1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254851020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3254851020
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.4060415494
Short name	T225
Test name
Test status
Simulation time	4089982004 ps
CPU time	10.16 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201952 kb
Host	smart-ec6814ae-c7ef-4c45-9ad3-d5aa3e5ef29a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060415494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.4060415494
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1994093956
Short name	T640
Test name
Test status
Simulation time	1269802307 ps
CPU time	9.15 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201920 kb
Host	smart-21ad3699-71ff-4ff7-8ff0-e07371da7714
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1994093956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1994093956
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1289864776
Short name	T534
Test name
Test status
Simulation time	23564600 ps
CPU time	1.07 seconds
Started	Apr 18 12:39:16 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	201936 kb
Host	smart-15d54966-2c6c-4eb1-abcf-3b398c7a693f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289864776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1289864776
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.1610260803
Short name	T81
Test name
Test status
Simulation time	4882032682 ps
CPU time	61.4 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	203028 kb
Host	smart-3f51e23a-4216-4f21-b15f-bbd662c30b23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1610260803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1610260803
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1508479534
Short name	T469
Test name
Test status
Simulation time	13903293386 ps
CPU time	28.4 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:40:13 PM PDT 24
Peak memory	202072 kb
Host	smart-39136506-33d7-4944-9f26-29a91c20df30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508479534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1508479534
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3443312921
Short name	T587
Test name
Test status
Simulation time	1527608151 ps
CPU time	123.41 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:41:32 PM PDT 24
Peak memory	205560 kb
Host	smart-d2411ace-d8a4-4e12-92a2-27043b180ebf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3443312921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.3443312921
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3254301350
Short name	T11
Test name
Test status
Simulation time	1690076046 ps
CPU time	103.38 seconds
Started	Apr 18 12:39:39 PM PDT 24
Finished	Apr 18 12:41:23 PM PDT 24
Peak memory	205928 kb
Host	smart-a7717702-2751-4dcb-b593-0ea9d3b94673
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254301350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3254301350
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2618965368
Short name	T20
Test name
Test status
Simulation time	35676456 ps
CPU time	2.48 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201956 kb
Host	smart-3672a796-9f88-4f9e-93bd-5297cecadcb2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2618965368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2618965368
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2167992284
Short name	T330
Test name
Test status
Simulation time	818540640 ps
CPU time	16.78 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:50 PM PDT 24
Peak memory	201948 kb
Host	smart-0a909e62-c6be-4c7f-9ea5-64a5619fab28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167992284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2167992284
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2194556669
Short name	T474
Test name
Test status
Simulation time	6156167944 ps
CPU time	34.3 seconds
Started	Apr 18 12:39:38 PM PDT 24
Finished	Apr 18 12:40:13 PM PDT 24
Peak memory	201960 kb
Host	smart-e189e4c3-a734-4890-9033-97b76fe18bf2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2194556669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2194556669
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1976606006
Short name	T742
Test name
Test status
Simulation time	6012667974 ps
CPU time	11.31 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	202000 kb
Host	smart-6e8932fe-33d2-4e5d-afbf-e10df5ed6716
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976606006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1976606006
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.4255250712
Short name	T509
Test name
Test status
Simulation time	296081496 ps
CPU time	4.23 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201540 kb
Host	smart-c7ef149b-f71f-45bd-87bc-31962949a302
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4255250712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4255250712
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.685646041
Short name	T353
Test name
Test status
Simulation time	116540363 ps
CPU time	7.11 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:40 PM PDT 24
Peak memory	201928 kb
Host	smart-95d5dfbf-f9d8-4a63-9788-6e59c3e63ff9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685646041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.685646041
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3634145907
Short name	T831
Test name
Test status
Simulation time	95179166381 ps
CPU time	161.44 seconds
Started	Apr 18 12:39:31 PM PDT 24
Finished	Apr 18 12:42:14 PM PDT 24
Peak memory	202088 kb
Host	smart-75a16531-9b29-47b0-b723-200d88aa0282
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634145907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3634145907
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3661924892
Short name	T222
Test name
Test status
Simulation time	6204205502 ps
CPU time	35.64 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	201992 kb
Host	smart-802139b3-8ac5-4c6f-a355-950b9ccc80d4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3661924892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3661924892
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.792357767
Short name	T217
Test name
Test status
Simulation time	23483671 ps
CPU time	3.17 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201984 kb
Host	smart-b47c758c-5d49-4487-bcbd-001f7e9013fb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792357767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.792357767
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.863062754
Short name	T668
Test name
Test status
Simulation time	732193656 ps
CPU time	10.39 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	202024 kb
Host	smart-f2db36a6-af2f-42f1-a8d5-a84af3c50671
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863062754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.863062754
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.414054338
Short name	T889
Test name
Test status
Simulation time	16761386 ps
CPU time	1.03 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:27 PM PDT 24
Peak memory	201912 kb
Host	smart-2464b569-1c05-49f9-979c-18ec26158e0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414054338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.414054338
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3268223030
Short name	T743
Test name
Test status
Simulation time	1856338779 ps
CPU time	9.84 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:42 PM PDT 24
Peak memory	202028 kb
Host	smart-8940a8d5-0c6f-46af-b036-7afadd8abc3b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268223030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3268223030
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4285017807
Short name	T266
Test name
Test status
Simulation time	4237334363 ps
CPU time	13.59 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	202084 kb
Host	smart-f3dce439-336c-4010-9291-7583db263632
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4285017807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4285017807
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.562251114
Short name	T285
Test name
Test status
Simulation time	8216850 ps
CPU time	0.99 seconds
Started	Apr 18 12:39:23 PM PDT 24
Finished	Apr 18 12:39:26 PM PDT 24
Peak memory	201896 kb
Host	smart-52c97aae-5298-40ba-99a7-96fe7ca5c01c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562251114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.562251114
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.1235350769
Short name	T688
Test name
Test status
Simulation time	359045366 ps
CPU time	20.69 seconds
Started	Apr 18 12:39:31 PM PDT 24
Finished	Apr 18 12:39:53 PM PDT 24
Peak memory	203028 kb
Host	smart-783ef75c-fee0-4ec6-a8f9-26d2e162a74d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235350769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1235350769
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2899733738
Short name	T182
Test name
Test status
Simulation time	1041245988 ps
CPU time	20.51 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:52 PM PDT 24
Peak memory	201980 kb
Host	smart-005514e0-f697-4ac6-b3ce-c1f125079e28
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899733738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2899733738
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2407786758
Short name	T53
Test name
Test status
Simulation time	1126833088 ps
CPU time	119.27 seconds
Started	Apr 18 12:39:38 PM PDT 24
Finished	Apr 18 12:41:38 PM PDT 24
Peak memory	204348 kb
Host	smart-cde521cb-7843-4a18-9423-2245352372e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2407786758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2407786758
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3908254734
Short name	T679
Test name
Test status
Simulation time	4224287798 ps
CPU time	56.03 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:40:26 PM PDT 24
Peak memory	204068 kb
Host	smart-b7c16e66-0a62-4c9a-aba2-e6db303f1b48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3908254734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3908254734
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1003380029
Short name	T348
Test name
Test status
Simulation time	2145430482 ps
CPU time	6.6 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:39:53 PM PDT 24
Peak memory	201928 kb
Host	smart-931ba72a-2985-4b91-b265-28736003760d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1003380029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1003380029
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2789642487
Short name	T551
Test name
Test status
Simulation time	922391059 ps
CPU time	17.96 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201916 kb
Host	smart-3047dba1-992d-4b70-8ba8-8280bb35f4b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789642487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2789642487
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2666745106
Short name	T150
Test name
Test status
Simulation time	53242353716 ps
CPU time	272.14 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:44:18 PM PDT 24
Peak memory	203092 kb
Host	smart-ac0b9415-5fb6-40f6-9343-73b8d73d440f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2666745106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2666745106
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3620889879
Short name	T373
Test name
Test status
Simulation time	396904503 ps
CPU time	7.84 seconds
Started	Apr 18 12:39:34 PM PDT 24
Finished	Apr 18 12:39:42 PM PDT 24
Peak memory	201972 kb
Host	smart-40b32c38-8e1a-4e1f-93b5-32a087174a50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3620889879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3620889879
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.4073265859
Short name	T290
Test name
Test status
Simulation time	1678349804 ps
CPU time	7.94 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	201976 kb
Host	smart-1eed6954-91a2-48da-993a-5d2387a3e7e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073265859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4073265859
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.3542058188
Short name	T827
Test name
Test status
Simulation time	59426954 ps
CPU time	8.55 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:40 PM PDT 24
Peak memory	202020 kb
Host	smart-2830129f-10da-4ca1-99bf-f2ecbc12c919
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542058188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3542058188
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1547568514
Short name	T724
Test name
Test status
Simulation time	48136096399 ps
CPU time	139.8 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:41:50 PM PDT 24
Peak memory	202068 kb
Host	smart-fc71c66c-368c-4a2b-b9ae-da9f36140289
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547568514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1547568514
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1141743035
Short name	T855
Test name
Test status
Simulation time	3677673587 ps
CPU time	23.88 seconds
Started	Apr 18 12:39:20 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	202044 kb
Host	smart-ae3f2df3-e21b-4828-825a-5684890aea0b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1141743035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1141743035
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2679965293
Short name	T318
Test name
Test status
Simulation time	9558824 ps
CPU time	1.21 seconds
Started	Apr 18 12:39:27 PM PDT 24
Finished	Apr 18 12:39:30 PM PDT 24
Peak memory	201880 kb
Host	smart-d7112019-86e3-4e79-b747-81ed8eba84cc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679965293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2679965293
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.196202379
Short name	T316
Test name
Test status
Simulation time	65797729 ps
CPU time	2.24 seconds
Started	Apr 18 12:39:40 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	201908 kb
Host	smart-0d9e6183-e0db-4094-b579-7935a11e79fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196202379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.196202379
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.1533572041
Short name	T788
Test name
Test status
Simulation time	18704255 ps
CPU time	1.36 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	201892 kb
Host	smart-b691257b-9ca1-4778-b3b8-4ee1b88bbc56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1533572041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1533572041
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4113728932
Short name	T33
Test name
Test status
Simulation time	2531428292 ps
CPU time	6.43 seconds
Started	Apr 18 12:39:39 PM PDT 24
Finished	Apr 18 12:39:46 PM PDT 24
Peak memory	202072 kb
Host	smart-3bafd8ea-9b47-430a-9bb5-3cfc3b81056f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113728932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4113728932
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1013935760
Short name	T303
Test name
Test status
Simulation time	5808030289 ps
CPU time	9.89 seconds
Started	Apr 18 12:39:24 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	202080 kb
Host	smart-e347d4e1-36a5-4571-8d9b-486e7d58061e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1013935760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1013935760
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1614902840
Short name	T329
Test name
Test status
Simulation time	9216180 ps
CPU time	1.15 seconds
Started	Apr 18 12:39:34 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	201880 kb
Host	smart-fd593211-e42a-48a8-9244-464dfcef3a78
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614902840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1614902840
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.520608813
Short name	T738
Test name
Test status
Simulation time	138779861 ps
CPU time	16.81 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201984 kb
Host	smart-8ff3bf00-0a07-4b22-9e65-4888fe5958f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=520608813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.520608813
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3627805947
Short name	T507
Test name
Test status
Simulation time	4826876287 ps
CPU time	76.39 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:41:02 PM PDT 24
Peak memory	202080 kb
Host	smart-703d9fe8-54a8-40bf-84f1-bc4fc01c2f56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3627805947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3627805947
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1805994733
Short name	T177
Test name
Test status
Simulation time	1234709186 ps
CPU time	154.02 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:42:08 PM PDT 24
Peak memory	205908 kb
Host	smart-4d708c24-2adf-490a-b4d0-b9a7660b7ed4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805994733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1805994733
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.4286944142
Short name	T343
Test name
Test status
Simulation time	16021174 ps
CPU time	1.91 seconds
Started	Apr 18 12:39:26 PM PDT 24
Finished	Apr 18 12:39:29 PM PDT 24
Peak memory	202012 kb
Host	smart-047d5282-f063-4f38-936e-ca7756e1cb1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4286944142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4286944142
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.420988485
Short name	T141
Test name
Test status
Simulation time	1206827230 ps
CPU time	18.28 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201920 kb
Host	smart-88ea1049-764e-4d6e-adb1-b0bf2afeff01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=420988485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.420988485
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1487768110
Short name	T49
Test name
Test status
Simulation time	15102229293 ps
CPU time	101.73 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:41:12 PM PDT 24
Peak memory	202068 kb
Host	smart-159bb1d2-e5aa-42ee-808e-e7e7aab9193a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1487768110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1487768110
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.775700040
Short name	T744
Test name
Test status
Simulation time	4135934522 ps
CPU time	7.26 seconds
Started	Apr 18 12:39:50 PM PDT 24
Finished	Apr 18 12:39:59 PM PDT 24
Peak memory	201976 kb
Host	smart-71afeea7-6234-4f30-894f-9702dbb00af6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775700040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.775700040
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.3614035301
Short name	T282
Test name
Test status
Simulation time	19398446 ps
CPU time	1.79 seconds
Started	Apr 18 12:39:38 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	201912 kb
Host	smart-2ea43f07-b861-434c-bcf0-4e42a6878af5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3614035301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3614035301
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.1159644402
Short name	T502
Test name
Test status
Simulation time	630212843 ps
CPU time	4.2 seconds
Started	Apr 18 12:39:33 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201924 kb
Host	smart-d05a67f1-a244-43f5-ad05-159f4d7e1b83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1159644402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1159644402
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2200962524
Short name	T691
Test name
Test status
Simulation time	66253303130 ps
CPU time	159.37 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:42:28 PM PDT 24
Peak memory	202084 kb
Host	smart-6b1f1501-0609-425a-ab6a-8f3f3706b025
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200962524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2200962524
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2759289258
Short name	T898
Test name
Test status
Simulation time	19353501514 ps
CPU time	119.37 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:41:47 PM PDT 24
Peak memory	202104 kb
Host	smart-3674b706-0a8c-40b0-8ed8-d9416ae49505
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2759289258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2759289258
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.4288164410
Short name	T464
Test name
Test status
Simulation time	36499324 ps
CPU time	1.3 seconds
Started	Apr 18 12:39:40 PM PDT 24
Finished	Apr 18 12:39:42 PM PDT 24
Peak memory	202008 kb
Host	smart-d7475956-f1c9-4577-a8d7-d33c77bd4d2e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288164410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4288164410
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.2418167360
Short name	T597
Test name
Test status
Simulation time	559302689 ps
CPU time	5.31 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	201996 kb
Host	smart-c6e7eb88-0d46-4bf3-ad52-a80f1fba1e33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418167360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2418167360
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.2809771465
Short name	T406
Test name
Test status
Simulation time	303078383 ps
CPU time	1.25 seconds
Started	Apr 18 12:39:28 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	201940 kb
Host	smart-979a95fd-3518-4389-a5b0-6de46b6af208
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809771465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2809771465
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1228405230
Short name	T588
Test name
Test status
Simulation time	1612400186 ps
CPU time	5.9 seconds
Started	Apr 18 12:39:25 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	202000 kb
Host	smart-d4688fde-acb3-486d-bd6d-85393a6f72c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228405230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1228405230
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.148437386
Short name	T576
Test name
Test status
Simulation time	1229611313 ps
CPU time	9.2 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	201940 kb
Host	smart-7543fadd-7476-465c-ad84-5b2ce7df2754
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=148437386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.148437386
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.4166414545
Short name	T728
Test name
Test status
Simulation time	10141037 ps
CPU time	1.08 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:34 PM PDT 24
Peak memory	201532 kb
Host	smart-7684b345-99b8-419a-b7a6-f27a1f0a1d41
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166414545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.4166414545
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.3699986176
Short name	T46
Test name
Test status
Simulation time	2710097535 ps
CPU time	36.05 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	203120 kb
Host	smart-1c172c64-b75e-4192-9cf7-e57912c00ed0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3699986176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3699986176
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2371385757
Short name	T751
Test name
Test status
Simulation time	3790131583 ps
CPU time	39.27 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201944 kb
Host	smart-d7f8274b-6dbd-4cb1-8eb1-12fb00a11d6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2371385757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2371385757
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.151320116
Short name	T173
Test name
Test status
Simulation time	2718916544 ps
CPU time	40.61 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	204004 kb
Host	smart-13d0dcf0-b413-4ff1-852e-83e6a232d92f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=151320116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.151320116
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.814810790
Short name	T232
Test name
Test status
Simulation time	126922305 ps
CPU time	11.44 seconds
Started	Apr 18 12:39:29 PM PDT 24
Finished	Apr 18 12:39:42 PM PDT 24
Peak memory	202944 kb
Host	smart-eb3c9301-c9ba-4437-b36a-2c1a3533c211
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=814810790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.814810790
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.98619878
Short name	T392
Test name
Test status
Simulation time	125378978 ps
CPU time	6.66 seconds
Started	Apr 18 12:39:33 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	201936 kb
Host	smart-a44c7fc0-41be-4226-9a21-f82dd174d1a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=98619878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.98619878
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2673285271
Short name	T158
Test name
Test status
Simulation time	2479576586 ps
CPU time	17.25 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:46 PM PDT 24
Peak memory	202068 kb
Host	smart-4e16233b-4c48-43fe-9d87-8548af2d7d46
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673285271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2673285271
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2668128838
Short name	T92
Test name
Test status
Simulation time	77195950134 ps
CPU time	246.35 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:42:36 PM PDT 24
Peak memory	203008 kb
Host	smart-94920581-86b0-4ea8-8cd2-8274e343baf0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2668128838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.2668128838
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3185095530
Short name	T431
Test name
Test status
Simulation time	336277236 ps
CPU time	5.75 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:35 PM PDT 24
Peak memory	201924 kb
Host	smart-427f5574-c243-411f-afa8-ac09ab44ffe4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3185095530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3185095530
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.2453367513
Short name	T202
Test name
Test status
Simulation time	1090612763 ps
CPU time	3.52 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	201936 kb
Host	smart-e7bd9115-8080-4591-9cf7-c639a8ff9bcd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2453367513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2453367513
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.3735104616
Short name	T126
Test name
Test status
Simulation time	697719570 ps
CPU time	12.37 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	202012 kb
Host	smart-b5de6bfe-d727-41a6-bc5a-d0039b4854f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3735104616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3735104616
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1873851700
Short name	T731
Test name
Test status
Simulation time	7519926446 ps
CPU time	34.5 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:39:01 PM PDT 24
Peak memory	201996 kb
Host	smart-e58ae798-ddef-402b-a311-d53541364e9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873851700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1873851700
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3934317030
Short name	T444
Test name
Test status
Simulation time	158346643897 ps
CPU time	154.44 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:41:09 PM PDT 24
Peak memory	202072 kb
Host	smart-fbe4f0a0-b132-4cc1-b28b-b19a4d0771f4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3934317030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3934317030
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.806468302
Short name	T786
Test name
Test status
Simulation time	326660698 ps
CPU time	8.84 seconds
Started	Apr 18 12:38:29 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	202016 kb
Host	smart-620f3b26-e01c-4978-a141-b63f00d0667f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806468302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.806468302
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.1776147963
Short name	T324
Test name
Test status
Simulation time	54151608 ps
CPU time	4.42 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	201884 kb
Host	smart-34d31332-ae3f-4df5-a176-d47c9e52e805
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1776147963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1776147963
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.2946562951
Short name	T873
Test name
Test status
Simulation time	38915136 ps
CPU time	1.44 seconds
Started	Apr 18 12:38:28 PM PDT 24
Finished	Apr 18 12:38:31 PM PDT 24
Peak memory	202012 kb
Host	smart-11a933c5-eb1f-47ba-ad3c-21529ad1858c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2946562951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2946562951
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3895704828
Short name	T782
Test name
Test status
Simulation time	2303485916 ps
CPU time	11.43 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	202092 kb
Host	smart-0dfe9b44-15e4-4192-9238-4dd3a8d63e59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895704828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3895704828
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1838813690
Short name	T499
Test name
Test status
Simulation time	997701412 ps
CPU time	7.52 seconds
Started	Apr 18 12:38:26 PM PDT 24
Finished	Apr 18 12:38:34 PM PDT 24
Peak memory	201920 kb
Host	smart-26c2d6ca-4c19-4fa4-a617-998d6fc54440
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1838813690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1838813690
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1868891225
Short name	T701
Test name
Test status
Simulation time	9559741 ps
CPU time	0.99 seconds
Started	Apr 18 12:38:31 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	202012 kb
Host	smart-933890e7-b8d0-4662-a83a-e115792ed607
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868891225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1868891225
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.3653777777
Short name	T402
Test name
Test status
Simulation time	5607108717 ps
CPU time	70.96 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	203500 kb
Host	smart-a402e5a2-d3de-4884-9d62-e01a388881af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653777777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3653777777
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2348554744
Short name	T435
Test name
Test status
Simulation time	1269333401 ps
CPU time	12.58 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:38:50 PM PDT 24
Peak memory	202012 kb
Host	smart-924330a8-e0b6-490d-b588-f716be18a510
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348554744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2348554744
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2455705161
Short name	T64
Test name
Test status
Simulation time	574203086 ps
CPU time	100.65 seconds
Started	Apr 18 12:38:27 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	204700 kb
Host	smart-fc2d6c42-c571-484e-9963-6de4cd28027d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455705161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2455705161
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2229483696
Short name	T599
Test name
Test status
Simulation time	1125988852 ps
CPU time	60.94 seconds
Started	Apr 18 12:38:37 PM PDT 24
Finished	Apr 18 12:39:39 PM PDT 24
Peak memory	204124 kb
Host	smart-715a84b4-082c-43b6-bda0-ce0e6f48d560
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2229483696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.2229483696
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.711679694
Short name	T114
Test name
Test status
Simulation time	4113560894 ps
CPU time	11.43 seconds
Started	Apr 18 12:38:40 PM PDT 24
Finished	Apr 18 12:38:53 PM PDT 24
Peak memory	201960 kb
Host	smart-a652c96d-5275-4e2e-ae0e-a44f032337b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711679694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.711679694
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3502703389
Short name	T48
Test name
Test status
Simulation time	677414610 ps
CPU time	12.02 seconds
Started	Apr 18 12:39:34 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201916 kb
Host	smart-1d2dde61-1405-4602-8e78-4d5a949e707a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3502703389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3502703389
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1235427216
Short name	T161
Test name
Test status
Simulation time	7325600005 ps
CPU time	52.04 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:40:39 PM PDT 24
Peak memory	201940 kb
Host	smart-7eb3a580-ff8b-4ef3-a593-d10ed4027d7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1235427216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.1235427216
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2111107645
Short name	T505
Test name
Test status
Simulation time	78699605 ps
CPU time	6.29 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	201896 kb
Host	smart-82dd2fec-4f6d-46c1-8e93-468f111ce165
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111107645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2111107645
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.1332654184
Short name	T699
Test name
Test status
Simulation time	64779575 ps
CPU time	7.52 seconds
Started	Apr 18 12:39:47 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	201932 kb
Host	smart-c9cd3d20-1953-49fe-b120-b3dae52f1649
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1332654184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1332654184
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.3685207683
Short name	T884
Test name
Test status
Simulation time	4033675489 ps
CPU time	14.29 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:39:58 PM PDT 24
Peak memory	202312 kb
Host	smart-ed43b186-af71-497a-b675-70c38d820c98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3685207683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3685207683
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2419045413
Short name	T617
Test name
Test status
Simulation time	31404348609 ps
CPU time	133.69 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:42:00 PM PDT 24
Peak memory	201960 kb
Host	smart-3869eda5-762c-4379-b258-aa965a01350e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419045413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2419045413
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.440581378
Short name	T234
Test name
Test status
Simulation time	24488941716 ps
CPU time	174.66 seconds
Started	Apr 18 12:39:36 PM PDT 24
Finished	Apr 18 12:42:32 PM PDT 24
Peak memory	201964 kb
Host	smart-b525aadd-559f-4614-8f09-19b501a0b85b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=440581378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.440581378
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3752441097
Short name	T374
Test name
Test status
Simulation time	81031005 ps
CPU time	6.16 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:38 PM PDT 24
Peak memory	201912 kb
Host	smart-70df6ae5-706b-4f3a-aedf-e7f6eb0e0a32
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752441097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3752441097
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2604788386
Short name	T34
Test name
Test status
Simulation time	1300407607 ps
CPU time	7.35 seconds
Started	Apr 18 12:39:39 PM PDT 24
Finished	Apr 18 12:39:48 PM PDT 24
Peak memory	201996 kb
Host	smart-3e30dcb8-4144-44f1-b7d9-8f7584299df2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2604788386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2604788386
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.2742420137
Short name	T817
Test name
Test status
Simulation time	56067128 ps
CPU time	1.4 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:35 PM PDT 24
Peak memory	201924 kb
Host	smart-a0c25d8e-8521-4b34-ab93-396746a658f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742420137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2742420137
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1875837383
Short name	T858
Test name
Test status
Simulation time	1733498477 ps
CPU time	8.42 seconds
Started	Apr 18 12:39:38 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201920 kb
Host	smart-dec8869a-de3f-4f5c-a58e-339d95a7ca08
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875837383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1875837383
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1326889373
Short name	T321
Test name
Test status
Simulation time	1677648137 ps
CPU time	9.75 seconds
Started	Apr 18 12:39:32 PM PDT 24
Finished	Apr 18 12:39:43 PM PDT 24
Peak memory	202032 kb
Host	smart-e9558c81-dfc0-4884-9042-81d32cca29cb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1326889373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1326889373
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3322757643
Short name	T328
Test name
Test status
Simulation time	18633697 ps
CPU time	1.14 seconds
Started	Apr 18 12:39:30 PM PDT 24
Finished	Apr 18 12:39:33 PM PDT 24
Peak memory	201996 kb
Host	smart-c6167455-8d1e-41fd-8ddd-a80761863e8a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322757643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3322757643
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.3867294565
Short name	T83
Test name
Test status
Simulation time	15250847146 ps
CPU time	88.23 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:41:11 PM PDT 24
Peak memory	205360 kb
Host	smart-9b243427-a476-4558-885d-af2cf434c0c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3867294565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3867294565
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.791647991
Short name	T314
Test name
Test status
Simulation time	778160462 ps
CPU time	22.79 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201944 kb
Host	smart-b5d22284-9515-4d55-b1e0-9c818dad7342
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791647991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.791647991
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.645557296
Short name	T69
Test name
Test status
Simulation time	8121284634 ps
CPU time	135.77 seconds
Started	Apr 18 12:39:35 PM PDT 24
Finished	Apr 18 12:41:51 PM PDT 24
Peak memory	206656 kb
Host	smart-dfa9f63a-9f1a-4795-b6f6-c76cfdac0ee4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=645557296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.645557296
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2616495155
Short name	T497
Test name
Test status
Simulation time	105439048 ps
CPU time	14.1 seconds
Started	Apr 18 12:39:45 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	202032 kb
Host	smart-6c5769d9-1341-4b93-bde4-7b1affea6722
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2616495155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2616495155
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1016961887
Short name	T219
Test name
Test status
Simulation time	355331185 ps
CPU time	6.97 seconds
Started	Apr 18 12:39:40 PM PDT 24
Finished	Apr 18 12:39:48 PM PDT 24
Peak memory	201880 kb
Host	smart-7fdf749d-46eb-4eb6-9069-8f6c40d1ef47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1016961887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1016961887
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3124061626
Short name	T144
Test name
Test status
Simulation time	709015750 ps
CPU time	10.07 seconds
Started	Apr 18 12:39:35 PM PDT 24
Finished	Apr 18 12:39:46 PM PDT 24
Peak memory	201856 kb
Host	smart-f12895c9-e2fd-4213-9d65-274b17c8eacb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3124061626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3124061626
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.4172042379
Short name	T763
Test name
Test status
Simulation time	9265459434 ps
CPU time	60.08 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:40:42 PM PDT 24
Peak memory	202076 kb
Host	smart-9812ff16-2318-4f4e-a272-303f413f8e21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4172042379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.4172042379
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1773193039
Short name	T832
Test name
Test status
Simulation time	240751150 ps
CPU time	4.23 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	201852 kb
Host	smart-32fa059b-2220-41ac-a2c2-1a253a6d7b17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773193039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1773193039
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.2573212800
Short name	T204
Test name
Test status
Simulation time	155697888 ps
CPU time	4.83 seconds
Started	Apr 18 12:39:43 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	201956 kb
Host	smart-06a240c0-580d-4b18-bd6c-6fafa173b30c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573212800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2573212800
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.2696935818
Short name	T641
Test name
Test status
Simulation time	151897570 ps
CPU time	2.26 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	201928 kb
Host	smart-0c4152f5-1f1d-4601-8beb-cdf780c98a25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2696935818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2696935818
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1748891824
Short name	T430
Test name
Test status
Simulation time	64265249700 ps
CPU time	90.11 seconds
Started	Apr 18 12:39:36 PM PDT 24
Finished	Apr 18 12:41:07 PM PDT 24
Peak memory	201988 kb
Host	smart-44616751-90f6-48ae-bfe1-25cf75960243
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748891824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1748891824
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3848635194
Short name	T702
Test name
Test status
Simulation time	52882755544 ps
CPU time	168.08 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:42:31 PM PDT 24
Peak memory	202088 kb
Host	smart-0d85a33d-03e1-4109-870a-3c0bea2d6218
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3848635194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3848635194
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.855422206
Short name	T258
Test name
Test status
Simulation time	13118234 ps
CPU time	1.61 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:39:40 PM PDT 24
Peak memory	201880 kb
Host	smart-d095c806-31f2-41e0-89b6-2f2b8a142c86
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855422206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.855422206
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.2684626737
Short name	T308
Test name
Test status
Simulation time	76985709 ps
CPU time	4.59 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:39:47 PM PDT 24
Peak memory	202012 kb
Host	smart-0f226f0b-3682-4e03-adac-1961d159e69f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684626737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2684626737
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.2400564554
Short name	T579
Test name
Test status
Simulation time	8849835 ps
CPU time	1.11 seconds
Started	Apr 18 12:39:35 PM PDT 24
Finished	Apr 18 12:39:37 PM PDT 24
Peak memory	201952 kb
Host	smart-32a05b47-ce74-4c09-a14c-dffc54e8e53f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2400564554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2400564554
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4241841703
Short name	T453
Test name
Test status
Simulation time	2457971761 ps
CPU time	11.21 seconds
Started	Apr 18 12:39:43 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	201984 kb
Host	smart-03827f76-ce62-4055-bfa7-7c97574815c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241841703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4241841703
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1316234981
Short name	T31
Test name
Test status
Simulation time	1734408240 ps
CPU time	6.43 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	202024 kb
Host	smart-13351ee8-d15f-4a28-8d4b-5cf7c548bceb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1316234981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1316234981
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2966226714
Short name	T565
Test name
Test status
Simulation time	10101150 ps
CPU time	1.14 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:39:44 PM PDT 24
Peak memory	202020 kb
Host	smart-b8d02cb9-80bb-4e9b-a332-8aac691fcadb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966226714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2966226714
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.2874642509
Short name	T247
Test name
Test status
Simulation time	117096232 ps
CPU time	8.18 seconds
Started	Apr 18 12:39:42 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	201940 kb
Host	smart-b4fe7f7b-3a08-4541-9e57-c842197a841d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2874642509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2874642509
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4258949776
Short name	T762
Test name
Test status
Simulation time	10659837896 ps
CPU time	46.81 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:40:34 PM PDT 24
Peak memory	201956 kb
Host	smart-c4574a60-cc2a-4d5b-9ea2-7f276862a4d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4258949776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4258949776
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2951095919
Short name	T548
Test name
Test status
Simulation time	149728631 ps
CPU time	37.15 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:40:32 PM PDT 24
Peak memory	203116 kb
Host	smart-6a823552-16cf-4811-8c7a-c78c907980e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951095919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2951095919
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.605270245
Short name	T89
Test name
Test status
Simulation time	8029082672 ps
CPU time	91.75 seconds
Started	Apr 18 12:39:47 PM PDT 24
Finished	Apr 18 12:41:21 PM PDT 24
Peak memory	203760 kb
Host	smart-f051c420-5065-40e9-81d6-d67cca2f2f6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=605270245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.605270245
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1934662980
Short name	T226
Test name
Test status
Simulation time	193121605 ps
CPU time	3.92 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:54 PM PDT 24
Peak memory	201924 kb
Host	smart-024a3ef0-fa0d-4ada-95bd-657baae28cab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934662980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1934662980
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.722877972
Short name	T894
Test name
Test status
Simulation time	738326612 ps
CPU time	3.12 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	202012 kb
Host	smart-35d945fa-4d52-4acb-8b5c-b88460e0a2ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722877972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.722877972
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.727513634
Short name	T437
Test name
Test status
Simulation time	26443747814 ps
CPU time	71.69 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:41:06 PM PDT 24
Peak memory	202032 kb
Host	smart-5a4c8549-0c04-4459-a1fe-4d7a9408325f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727513634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.727513634
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2879323532
Short name	T613
Test name
Test status
Simulation time	1201554032 ps
CPU time	11.27 seconds
Started	Apr 18 12:39:47 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201924 kb
Host	smart-1cf9d989-05c8-483a-9713-c5d67345eba6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879323532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2879323532
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.422213484
Short name	T829
Test name
Test status
Simulation time	193323064 ps
CPU time	3.22 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	201900 kb
Host	smart-14a105dd-05e0-435c-b4df-971b95fdfa6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=422213484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.422213484
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.4242824078
Short name	T755
Test name
Test status
Simulation time	192411313 ps
CPU time	7.97 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201988 kb
Host	smart-9c333021-66e0-4306-b838-a37e0ff0c9c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242824078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4242824078
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2055266387
Short name	T72
Test name
Test status
Simulation time	30186317590 ps
CPU time	38.56 seconds
Started	Apr 18 12:39:47 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	202000 kb
Host	smart-4f8cb679-5e02-430f-880f-1c8c40a2c85b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055266387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2055266387
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1598074529
Short name	T856
Test name
Test status
Simulation time	25344551124 ps
CPU time	98.57 seconds
Started	Apr 18 12:39:37 PM PDT 24
Finished	Apr 18 12:41:16 PM PDT 24
Peak memory	201972 kb
Host	smart-b7930d1a-16f4-40c2-b108-8a3d481013c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1598074529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1598074529
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1824797672
Short name	T352
Test name
Test status
Simulation time	192121189 ps
CPU time	4.35 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	202024 kb
Host	smart-deb58d4f-e611-4853-85e8-de4d60da30f6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824797672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1824797672
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.3513362297
Short name	T862
Test name
Test status
Simulation time	19952538 ps
CPU time	1.36 seconds
Started	Apr 18 12:39:39 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	201856 kb
Host	smart-e7b97df7-67cb-474a-af5e-bdd3bc34b417
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3513362297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3513362297
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.2507496396
Short name	T382
Test name
Test status
Simulation time	248836466 ps
CPU time	1.73 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	201916 kb
Host	smart-3573cb2d-ce89-4f66-b1b3-6dbf6ee5b2f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2507496396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2507496396
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.859204490
Short name	T218
Test name
Test status
Simulation time	2744190425 ps
CPU time	6.7 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	202060 kb
Host	smart-2a9c1c3b-5b3b-4af1-8250-44465ef70048
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=859204490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.859204490
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3045528041
Short name	T802
Test name
Test status
Simulation time	910156551 ps
CPU time	5.22 seconds
Started	Apr 18 12:39:55 PM PDT 24
Finished	Apr 18 12:40:03 PM PDT 24
Peak memory	201940 kb
Host	smart-684795f2-72fd-4213-b60f-2c8aa2f15f36
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3045528041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3045528041
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1168047821
Short name	T558
Test name
Test status
Simulation time	13939651 ps
CPU time	1.38 seconds
Started	Apr 18 12:39:39 PM PDT 24
Finished	Apr 18 12:39:41 PM PDT 24
Peak memory	201880 kb
Host	smart-ff9c414e-dc1d-4fc6-8dad-f473aa3dfacd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168047821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1168047821
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.1875694962
Short name	T331
Test name
Test status
Simulation time	228861114 ps
CPU time	9.27 seconds
Started	Apr 18 12:39:55 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	201984 kb
Host	smart-2eaaa7f5-4a38-4502-97ac-cc73fc7198c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875694962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1875694962
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.710760942
Short name	T389
Test name
Test status
Simulation time	744378726 ps
CPU time	10.25 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	202044 kb
Host	smart-af049339-ea65-4e51-a346-15850ebf1155
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=710760942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.710760942
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1983382361
Short name	T439
Test name
Test status
Simulation time	741040707 ps
CPU time	94.34 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:41:22 PM PDT 24
Peak memory	206204 kb
Host	smart-3c082933-78b1-4e10-8e43-2e57e147988d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1983382361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1983382361
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1714266508
Short name	T843
Test name
Test status
Simulation time	64155128 ps
CPU time	6.53 seconds
Started	Apr 18 12:39:41 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	201916 kb
Host	smart-a3db86cd-1427-418d-8a5a-26ace3a68e44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714266508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1714266508
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.423587543
Short name	T872
Test name
Test status
Simulation time	49974048 ps
CPU time	6.15 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	202008 kb
Host	smart-45b4d53c-135b-4ab2-93c3-6d61563d9b43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=423587543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.423587543
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2889099268
Short name	T148
Test name
Test status
Simulation time	57939811828 ps
CPU time	263.83 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:44:18 PM PDT 24
Peak memory	203080 kb
Host	smart-3e1f2066-a9d7-46d8-89c8-29b114064d9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2889099268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2889099268
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1241676991
Short name	T134
Test name
Test status
Simulation time	30870196 ps
CPU time	1.51 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	201920 kb
Host	smart-1aaaf520-ece6-476f-9128-fb6e747213c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241676991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1241676991
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.553244198
Short name	T307
Test name
Test status
Simulation time	65482875 ps
CPU time	7.03 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201908 kb
Host	smart-179176e1-9ed9-4738-ace3-45ce3fba0fe3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=553244198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.553244198
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.4064841188
Short name	T187
Test name
Test status
Simulation time	744783255 ps
CPU time	10.21 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201924 kb
Host	smart-025a6112-57f9-4684-9651-181e5812b56b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064841188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4064841188
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1301871556
Short name	T105
Test name
Test status
Simulation time	83685010794 ps
CPU time	188.38 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:43:08 PM PDT 24
Peak memory	201964 kb
Host	smart-d3de527a-cbee-4494-a0ae-da4d0a008b2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301871556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1301871556
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1701169913
Short name	T399
Test name
Test status
Simulation time	2176772703 ps
CPU time	12.32 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	202020 kb
Host	smart-0abea678-158b-4450-ab90-ee65105a7763
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1701169913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1701169913
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3770558559
Short name	T717
Test name
Test status
Simulation time	30008962 ps
CPU time	3.12 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:39:54 PM PDT 24
Peak memory	201952 kb
Host	smart-2068a19e-ac50-42d4-aeb0-270e5698bec7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770558559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3770558559
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2273510323
Short name	T556
Test name
Test status
Simulation time	880232846 ps
CPU time	7.08 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201916 kb
Host	smart-f87fb948-3d10-4b37-8e80-51c916b28fe2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273510323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2273510323
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.585821469
Short name	T705
Test name
Test status
Simulation time	8376641 ps
CPU time	1.1 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:39:58 PM PDT 24
Peak memory	201824 kb
Host	smart-56bed354-93a1-43c1-b16c-b7737651cae3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=585821469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.585821469
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2237315651
Short name	T723
Test name
Test status
Simulation time	1788716933 ps
CPU time	8.82 seconds
Started	Apr 18 12:39:44 PM PDT 24
Finished	Apr 18 12:39:54 PM PDT 24
Peak memory	202024 kb
Host	smart-21a9b197-d445-4fbb-8f63-b8ba4efae275
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237315651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2237315651
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3658124534
Short name	T30
Test name
Test status
Simulation time	1128463925 ps
CPU time	5.81 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:06 PM PDT 24
Peak memory	202016 kb
Host	smart-7016619f-6b10-4beb-bcc6-813e51da17a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3658124534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3658124534
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3713737071
Short name	T44
Test name
Test status
Simulation time	8760220 ps
CPU time	1.09 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:53 PM PDT 24
Peak memory	201944 kb
Host	smart-537b2e33-9712-4eb9-9a9c-8474f89a6325
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713737071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3713737071
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.811762268
Short name	T109
Test name
Test status
Simulation time	4139353682 ps
CPU time	74.24 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:41:08 PM PDT 24
Peak memory	203072 kb
Host	smart-236c63b7-a1b8-4229-a0c0-f087f0996750
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811762268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.811762268
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3121853816
Short name	T895
Test name
Test status
Simulation time	641756330 ps
CPU time	7.6 seconds
Started	Apr 18 12:39:46 PM PDT 24
Finished	Apr 18 12:39:54 PM PDT 24
Peak memory	202256 kb
Host	smart-565904d8-3642-4bb3-99ac-49ec469f7002
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3121853816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3121853816
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.22821464
Short name	T426
Test name
Test status
Simulation time	1305512525 ps
CPU time	68.03 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:41:03 PM PDT 24
Peak memory	204132 kb
Host	smart-16f6152f-7350-4443-9324-e18dd23374ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=22821464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_ reset.22821464
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2832762833
Short name	T346
Test name
Test status
Simulation time	2004028946 ps
CPU time	163.16 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:42:37 PM PDT 24
Peak memory	204956 kb
Host	smart-00bfdcc0-942d-4b7c-be47-612df433ff77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2832762833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2832762833
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1198711849
Short name	T265
Test name
Test status
Simulation time	10542796 ps
CPU time	1.12 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	201860 kb
Host	smart-f89b7f7c-9aad-4231-ad6b-be794f0b39f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198711849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1198711849
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.873454776
Short name	T441
Test name
Test status
Simulation time	167938582 ps
CPU time	4.05 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:39:59 PM PDT 24
Peak memory	201912 kb
Host	smart-91c8f072-576d-4bce-8a32-b37b70fc8f0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=873454776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.873454776
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1999057851
Short name	T162
Test name
Test status
Simulation time	90183546219 ps
CPU time	177.73 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:42:51 PM PDT 24
Peak memory	203096 kb
Host	smart-26316649-1f3a-46a0-b1a7-776d5dd5d201
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1999057851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1999057851
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.613401256
Short name	T480
Test name
Test status
Simulation time	451197746 ps
CPU time	4.55 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:03 PM PDT 24
Peak memory	201916 kb
Host	smart-90ddeb6f-28f6-4fb5-8b80-628be3ec7c83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=613401256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.613401256
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.527896597
Short name	T604
Test name
Test status
Simulation time	49066218 ps
CPU time	1.99 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:39:59 PM PDT 24
Peak memory	201976 kb
Host	smart-0287fca8-fc34-4ef7-baea-80a6badc4edb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=527896597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.527896597
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.638788832
Short name	T367
Test name
Test status
Simulation time	993385266 ps
CPU time	14.48 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202020 kb
Host	smart-23d0bf89-573f-4251-ae12-4f0c8ae54c57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=638788832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.638788832
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2133734705
Short name	T56
Test name
Test status
Simulation time	11084808684 ps
CPU time	42.54 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:40 PM PDT 24
Peak memory	202012 kb
Host	smart-7c099441-4691-419e-86fb-97913028ebb5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133734705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2133734705
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1687462592
Short name	T647
Test name
Test status
Simulation time	35940520290 ps
CPU time	116.43 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:41:56 PM PDT 24
Peak memory	201972 kb
Host	smart-6a0d649e-ae30-4bbf-ab42-51fc086dd92f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1687462592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1687462592
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2013927990
Short name	T262
Test name
Test status
Simulation time	340605101 ps
CPU time	7.89 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	202008 kb
Host	smart-1ee575d7-6a45-4830-aaf7-79bb74dbcc89
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013927990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2013927990
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.2207322027
Short name	T784
Test name
Test status
Simulation time	748196445 ps
CPU time	9.93 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	202012 kb
Host	smart-5792d995-d9c7-495a-bf8e-afe103442b9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2207322027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2207322027
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.1404882271
Short name	T757
Test name
Test status
Simulation time	73496939 ps
CPU time	1.66 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201928 kb
Host	smart-3603ff85-ce90-4100-94fd-190a792aa058
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1404882271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1404882271
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3931577988
Short name	T54
Test name
Test status
Simulation time	2798480884 ps
CPU time	9.89 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201996 kb
Host	smart-8e05c497-a4ee-43f5-a868-399b9dcf581b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931577988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3931577988
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3918578913
Short name	T23
Test name
Test status
Simulation time	1585454164 ps
CPU time	5.93 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	202012 kb
Host	smart-89315eb5-0523-4a21-95ba-b254a7bd0013
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3918578913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3918578913
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.424923143
Short name	T384
Test name
Test status
Simulation time	8953203 ps
CPU time	1.09 seconds
Started	Apr 18 12:39:49 PM PDT 24
Finished	Apr 18 12:39:51 PM PDT 24
Peak memory	201920 kb
Host	smart-1b0e2f34-632b-45dc-8a37-e31f56d0944b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424923143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.424923143
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.3270883037
Short name	T614
Test name
Test status
Simulation time	140287743 ps
CPU time	12.14 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	201984 kb
Host	smart-2854a7e5-d3f4-4252-8ce8-5ac33a46e884
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3270883037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3270883037
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.853720637
Short name	T275
Test name
Test status
Simulation time	803099619 ps
CPU time	11.65 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	201924 kb
Host	smart-09fb866a-129f-4fd6-b945-6b4b62e9d508
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=853720637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.853720637
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.303306569
Short name	T639
Test name
Test status
Simulation time	608131040 ps
CPU time	44.36 seconds
Started	Apr 18 12:39:50 PM PDT 24
Finished	Apr 18 12:40:36 PM PDT 24
Peak memory	204020 kb
Host	smart-1e93337e-6d0f-4891-b04e-9c6559fdc963
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303306569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.303306569
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3487298456
Short name	T179
Test name
Test status
Simulation time	10181818833 ps
CPU time	181.96 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:42:59 PM PDT 24
Peak memory	207024 kb
Host	smart-b49192f0-b08c-4be4-b968-8f024b39461e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3487298456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3487298456
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2766946081
Short name	T541
Test name
Test status
Simulation time	75082878 ps
CPU time	5.13 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	201912 kb
Host	smart-c741b360-8cac-4d32-acd2-a63f7b796612
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2766946081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2766946081
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3363304737
Short name	T107
Test name
Test status
Simulation time	26475851035 ps
CPU time	51.82 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:47 PM PDT 24
Peak memory	202076 kb
Host	smart-07081072-263d-461b-bc9c-4a5f21939efc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3363304737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.3363304737
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.404489627
Short name	T186
Test name
Test status
Simulation time	795866234 ps
CPU time	8.1 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201916 kb
Host	smart-cf67f743-3c87-403e-8938-ef20662f8e48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404489627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.404489627
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.1840002506
Short name	T287
Test name
Test status
Simulation time	97579075 ps
CPU time	7.09 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201900 kb
Host	smart-e9bc3cd9-5632-4a6e-936c-e5073754b019
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840002506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1840002506
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.1578908853
Short name	T632
Test name
Test status
Simulation time	501991849 ps
CPU time	7.91 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	201872 kb
Host	smart-2d815977-4ad9-4bd3-8e4a-f3b1fc696742
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1578908853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1578908853
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2865067194
Short name	T208
Test name
Test status
Simulation time	62831965688 ps
CPU time	110.1 seconds
Started	Apr 18 12:39:47 PM PDT 24
Finished	Apr 18 12:41:40 PM PDT 24
Peak memory	202072 kb
Host	smart-8b95a8a9-41fa-465c-90e2-6ca180140edf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865067194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2865067194
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2587006577
Short name	T681
Test name
Test status
Simulation time	15343386534 ps
CPU time	88.74 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:41:24 PM PDT 24
Peak memory	201976 kb
Host	smart-c7896edc-71b6-402c-a0a7-238b58d15e56
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2587006577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2587006577
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1101620295
Short name	T281
Test name
Test status
Simulation time	59818247 ps
CPU time	5.61 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201888 kb
Host	smart-d7dc6549-e768-42dd-8c4f-a4dfdfadd8f9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101620295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1101620295
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.3805900673
Short name	T581
Test name
Test status
Simulation time	1275130682 ps
CPU time	4.97 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	201916 kb
Host	smart-32b38e49-8f83-45e4-8c88-2e9f14371c49
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805900673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3805900673
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.1371705112
Short name	T120
Test name
Test status
Simulation time	24149997 ps
CPU time	1.24 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	202272 kb
Host	smart-d86839d3-d91c-4e3a-9409-0250de92b43b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1371705112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1371705112
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3874491491
Short name	T250
Test name
Test status
Simulation time	3427561910 ps
CPU time	5.87 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202064 kb
Host	smart-6852ed5e-57da-4907-84a8-8341c7b481e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874491491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3874491491
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1059391532
Short name	T334
Test name
Test status
Simulation time	1241961091 ps
CPU time	8.54 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201980 kb
Host	smart-617888ba-dfe2-4092-b88c-e42b69964e95
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1059391532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1059391532
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2936989732
Short name	T15
Test name
Test status
Simulation time	13323472 ps
CPU time	1.07 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:39:56 PM PDT 24
Peak memory	201928 kb
Host	smart-45c4448c-c652-4f3c-b812-b244cb4860d2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936989732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2936989732
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2302467343
Short name	T867
Test name
Test status
Simulation time	3433245306 ps
CPU time	17.9 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	202064 kb
Host	smart-ffe96394-6bfa-484b-bb32-3c69ea0b6920
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2302467343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2302467343
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4245946592
Short name	T166
Test name
Test status
Simulation time	1723486161 ps
CPU time	245.81 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:44:08 PM PDT 24
Peak memory	205336 kb
Host	smart-7be5b9fc-da91-47f1-8e72-2f1c4612746f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4245946592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.4245946592
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.43868381
Short name	T752
Test name
Test status
Simulation time	988296768 ps
CPU time	122.24 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:42:03 PM PDT 24
Peak memory	207516 kb
Host	smart-bd1274bb-3855-461b-8cb0-579af020c175
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=43868381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rese t_error.43868381
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1129590778
Short name	T451
Test name
Test status
Simulation time	557148383 ps
CPU time	7.95 seconds
Started	Apr 18 12:39:48 PM PDT 24
Finished	Apr 18 12:39:58 PM PDT 24
Peak memory	201872 kb
Host	smart-360d41cf-ea15-4f42-92a6-b7c529198460
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129590778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1129590778
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2106674912
Short name	T826
Test name
Test status
Simulation time	876633976 ps
CPU time	10.47 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	202036 kb
Host	smart-1c557e77-1f6f-41af-89de-1aa5783b5628
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2106674912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2106674912
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.4102673818
Short name	T770
Test name
Test status
Simulation time	3571714434 ps
CPU time	16.33 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201980 kb
Host	smart-253d8cfe-99e3-4c2f-954d-25184482b92c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4102673818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.4102673818
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.689207518
Short name	T326
Test name
Test status
Simulation time	26363986 ps
CPU time	2.56 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	201844 kb
Host	smart-550b4729-b302-45f8-8d34-9a1bb04e4a56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=689207518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.689207518
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.3484080506
Short name	T212
Test name
Test status
Simulation time	61084356 ps
CPU time	3.33 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201916 kb
Host	smart-7c5f5c0f-955c-49da-9e32-e4191fbdc955
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484080506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3484080506
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.595204051
Short name	T531
Test name
Test status
Simulation time	451409213 ps
CPU time	5.74 seconds
Started	Apr 18 12:39:55 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201984 kb
Host	smart-e1c9b135-bc97-48a1-8aca-29b3f08c1ecf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=595204051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.595204051
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3544269851
Short name	T819
Test name
Test status
Simulation time	29419375009 ps
CPU time	44.8 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:44 PM PDT 24
Peak memory	201936 kb
Host	smart-548d67f0-7762-4721-8612-c0b5ea0f83b7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544269851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3544269851
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2109365786
Short name	T569
Test name
Test status
Simulation time	27038876296 ps
CPU time	95.04 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:41:30 PM PDT 24
Peak memory	201924 kb
Host	smart-40211ea6-d0fe-455a-afb3-3af6c9226cbf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2109365786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2109365786
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3078974300
Short name	T310
Test name
Test status
Simulation time	43605425 ps
CPU time	4.65 seconds
Started	Apr 18 12:39:55 PM PDT 24
Finished	Apr 18 12:40:03 PM PDT 24
Peak memory	202012 kb
Host	smart-8171879c-d881-456e-b2b7-d6aaac8f38ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078974300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3078974300
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.100071178
Short name	T836
Test name
Test status
Simulation time	49147784 ps
CPU time	4.23 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	202028 kb
Host	smart-c5c7961e-b516-4218-9e58-6a9f20c522a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100071178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.100071178
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.1960656293
Short name	T237
Test name
Test status
Simulation time	11709579 ps
CPU time	1.08 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:00 PM PDT 24
Peak memory	201868 kb
Host	smart-0150a364-603d-4868-b5f0-fd339a31dffd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1960656293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1960656293
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2893833047
Short name	T779
Test name
Test status
Simulation time	2166464789 ps
CPU time	6.44 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:59 PM PDT 24
Peak memory	201992 kb
Host	smart-da13ffdb-756a-40a6-8602-6be8b884d4d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893833047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2893833047
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.195426449
Short name	T90
Test name
Test status
Simulation time	4161795837 ps
CPU time	5.34 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202084 kb
Host	smart-59ea6efa-8a6f-4a40-90e0-c03e25b9070b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=195426449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.195426449
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2367813027
Short name	T360
Test name
Test status
Simulation time	15621517 ps
CPU time	1.1 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	202032 kb
Host	smart-404b9183-bd8a-42d9-ba51-ea43acc252ce
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367813027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2367813027
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.4088787530
Short name	T667
Test name
Test status
Simulation time	814724797 ps
CPU time	49.4 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:51 PM PDT 24
Peak memory	203756 kb
Host	smart-257235f7-5c09-4c9b-944a-5d0152e07f2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4088787530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4088787530
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.958146596
Short name	T800
Test name
Test status
Simulation time	2452898541 ps
CPU time	20.18 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201984 kb
Host	smart-0e58ca39-3308-4885-8d5a-acdebd2cb72e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958146596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.958146596
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2620636295
Short name	T424
Test name
Test status
Simulation time	657930022 ps
CPU time	71.24 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:41:06 PM PDT 24
Peak memory	204716 kb
Host	smart-22b18979-3f93-422c-b4eb-075f9e1517c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2620636295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2620636295
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3557900805
Short name	T468
Test name
Test status
Simulation time	1729159034 ps
CPU time	71.44 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:41:11 PM PDT 24
Peak memory	204504 kb
Host	smart-9b196b7b-b76f-4596-805a-3ad2b54e57a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3557900805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3557900805
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2331239303
Short name	T95
Test name
Test status
Simulation time	361771423 ps
CPU time	4.61 seconds
Started	Apr 18 12:39:52 PM PDT 24
Finished	Apr 18 12:39:59 PM PDT 24
Peak memory	201932 kb
Host	smart-901701ad-a5a6-4fe7-a54c-d9222d85870f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2331239303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2331239303
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.302846534
Short name	T51
Test name
Test status
Simulation time	676333178 ps
CPU time	13.98 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:15 PM PDT 24
Peak memory	201924 kb
Host	smart-d66a25fd-f9cf-4bb5-abfa-b690b8cb82b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302846534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.302846534
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1256945248
Short name	T849
Test name
Test status
Simulation time	106748626 ps
CPU time	6.36 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	202016 kb
Host	smart-159a0482-c872-4950-a237-fdbaf586070e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1256945248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1256945248
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.8826562
Short name	T309
Test name
Test status
Simulation time	752879992 ps
CPU time	7.62 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	201944 kb
Host	smart-b9ac0395-c58a-4f9a-acd9-3b4c95a3be81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8826562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.8826562
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.1522107997
Short name	T645
Test name
Test status
Simulation time	150246134 ps
CPU time	3.13 seconds
Started	Apr 18 12:39:51 PM PDT 24
Finished	Apr 18 12:39:57 PM PDT 24
Peak memory	201924 kb
Host	smart-af1de707-f9a3-44fc-91be-da05439ed8e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1522107997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1522107997
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1004904353
Short name	T573
Test name
Test status
Simulation time	31793825039 ps
CPU time	111.85 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:41:49 PM PDT 24
Peak memory	202088 kb
Host	smart-bc36f931-037d-43ce-8a4c-96344772b4ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004904353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1004904353
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1473391241
Short name	T446
Test name
Test status
Simulation time	105857513770 ps
CPU time	98.98 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:41:40 PM PDT 24
Peak memory	202076 kb
Host	smart-bf809e45-131c-4cfc-81a3-1c417b0761ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1473391241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1473391241
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3855511753
Short name	T340
Test name
Test status
Simulation time	40914644 ps
CPU time	3.19 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202024 kb
Host	smart-6af5cac7-2783-4a5d-b029-d7dbd9f008ce
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855511753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3855511753
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.3619442178
Short name	T400
Test name
Test status
Simulation time	89977084 ps
CPU time	3.16 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	202012 kb
Host	smart-dc60e74c-29ea-4379-9155-5c8e27710c30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3619442178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3619442178
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.2405775495
Short name	T337
Test name
Test status
Simulation time	116812924 ps
CPU time	1.62 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201920 kb
Host	smart-9cdf4a93-6e05-422f-bc15-1cddb1022c11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2405775495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2405775495
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3271981164
Short name	T650
Test name
Test status
Simulation time	15405998651 ps
CPU time	12.88 seconds
Started	Apr 18 12:39:53 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	202032 kb
Host	smart-0c973200-2a53-4f39-9fa2-bfbf5860a10e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271981164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3271981164
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3567028409
Short name	T136
Test name
Test status
Simulation time	877686573 ps
CPU time	7.23 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	202024 kb
Host	smart-99f4c512-d558-4a83-af11-5b32ff817eeb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3567028409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3567028409
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1919480223
Short name	T892
Test name
Test status
Simulation time	8509551 ps
CPU time	1.12 seconds
Started	Apr 18 12:39:50 PM PDT 24
Finished	Apr 18 12:39:52 PM PDT 24
Peak memory	201860 kb
Host	smart-355aa317-9536-4b0d-a519-dcf143f36444
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919480223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1919480223
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.2972881977
Short name	T693
Test name
Test status
Simulation time	3776420466 ps
CPU time	36.28 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	203004 kb
Host	smart-642f0f60-9e90-4a12-98cb-7f186537578e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2972881977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2972881977
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.113110557
Short name	T75
Test name
Test status
Simulation time	85666411 ps
CPU time	6.49 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	201924 kb
Host	smart-e1c4d6b4-97e7-4be3-bcc9-ce3febf2a4ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=113110557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.113110557
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2494607612
Short name	T168
Test name
Test status
Simulation time	100324162 ps
CPU time	4.27 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	202004 kb
Host	smart-c932527b-9999-4897-8987-b10f913fd512
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2494607612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2494607612
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1966078240
Short name	T172
Test name
Test status
Simulation time	8315577445 ps
CPU time	174.26 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:42:56 PM PDT 24
Peak memory	205556 kb
Host	smart-16b4b232-4c3b-4f11-a364-f4476de82686
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966078240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1966078240
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2327937779
Short name	T642
Test name
Test status
Simulation time	13385629 ps
CPU time	1.29 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201992 kb
Host	smart-9d208b3e-b232-4fd9-be65-8265049bef50
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327937779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2327937779
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1516918798
Short name	T22
Test name
Test status
Simulation time	830220648 ps
CPU time	18.92 seconds
Started	Apr 18 12:40:11 PM PDT 24
Finished	Apr 18 12:40:31 PM PDT 24
Peak memory	201980 kb
Host	smart-439c4620-e811-4532-b5d2-e4695f7b065d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1516918798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1516918798
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2750761615
Short name	T510
Test name
Test status
Simulation time	56291749357 ps
CPU time	329.71 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:45:33 PM PDT 24
Peak memory	204116 kb
Host	smart-44b871dc-e23f-4cd3-8909-02392f3b8b4f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2750761615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2750761615
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1401349646
Short name	T286
Test name
Test status
Simulation time	198994534 ps
CPU time	4.99 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	201956 kb
Host	smart-12aeb3d9-38b0-48a3-ba55-a83baaec37fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1401349646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1401349646
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.1313194513
Short name	T527
Test name
Test status
Simulation time	2824172063 ps
CPU time	4.8 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	202048 kb
Host	smart-ae1ea884-ba49-4320-8710-ba36d1144b24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1313194513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1313194513
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.2191610310
Short name	T358
Test name
Test status
Simulation time	277649939 ps
CPU time	7.3 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	201968 kb
Host	smart-161c12a0-d19a-48df-98e5-d7dde4fedcf2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2191610310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2191610310
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2884280789
Short name	T648
Test name
Test status
Simulation time	30267801761 ps
CPU time	131.9 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:42:11 PM PDT 24
Peak memory	202040 kb
Host	smart-41457558-c0e9-4c52-b1fe-4b5dd6fde47b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884280789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2884280789
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.603243164
Short name	T129
Test name
Test status
Simulation time	7375193627 ps
CPU time	58.98 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:41:01 PM PDT 24
Peak memory	202084 kb
Host	smart-0bf86ff0-4862-4871-8654-15c115f63044
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=603243164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.603243164
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3836556669
Short name	T809
Test name
Test status
Simulation time	48162143 ps
CPU time	4 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:06 PM PDT 24
Peak memory	201972 kb
Host	smart-bd716e81-4364-4165-a8fc-34cc642668b9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836556669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3836556669
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.2804996176
Short name	T139
Test name
Test status
Simulation time	44410268 ps
CPU time	2.78 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202000 kb
Host	smart-779a4236-70f8-4fb3-bee7-806d7cfde2ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2804996176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2804996176
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.27247323
Short name	T86
Test name
Test status
Simulation time	90397497 ps
CPU time	1.34 seconds
Started	Apr 18 12:40:02 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201940 kb
Host	smart-d91d5f19-9b1f-4fb2-992a-e710022f0d89
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27247323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.27247323
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3874891855
Short name	T203
Test name
Test status
Simulation time	1754503901 ps
CPU time	8.38 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:40:11 PM PDT 24
Peak memory	201928 kb
Host	smart-ecdbedd3-8b03-42b3-ac87-0cb13f84ede3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874891855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3874891855
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.636614713
Short name	T695
Test name
Test status
Simulation time	3031455031 ps
CPU time	11.73 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:12 PM PDT 24
Peak memory	202072 kb
Host	smart-4533864d-36f2-4565-84ca-20805dfcc27a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=636614713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.636614713
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3121978130
Short name	T241
Test name
Test status
Simulation time	33767213 ps
CPU time	1.12 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:39:58 PM PDT 24
Peak memory	201924 kb
Host	smart-508894ea-af0e-44f2-8622-da9786726738
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121978130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3121978130
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.4167519881
Short name	T890
Test name
Test status
Simulation time	5125571307 ps
CPU time	42.52 seconds
Started	Apr 18 12:40:18 PM PDT 24
Finished	Apr 18 12:41:02 PM PDT 24
Peak memory	202976 kb
Host	smart-a887c7b4-d086-4354-af20-cd9ce00a0258
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4167519881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.4167519881
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3132464364
Short name	T432
Test name
Test status
Simulation time	4055863926 ps
CPU time	58.16 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:41:13 PM PDT 24
Peak memory	202032 kb
Host	smart-6e777179-d4a2-459b-a4d8-9c0cb27310ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3132464364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3132464364
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2738400224
Short name	T477
Test name
Test status
Simulation time	7501061306 ps
CPU time	115.59 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:41:58 PM PDT 24
Peak memory	205244 kb
Host	smart-455df45f-8cec-4dd0-937c-5b9dd0156895
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738400224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2738400224
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2286398671
Short name	T463
Test name
Test status
Simulation time	997788506 ps
CPU time	127.17 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:42:04 PM PDT 24
Peak memory	206364 kb
Host	smart-a38b2f3d-9d5e-4fd9-919a-0a873c6dd3a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286398671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2286398671
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1732757686
Short name	T484
Test name
Test status
Simulation time	20110231 ps
CPU time	1.3 seconds
Started	Apr 18 12:40:08 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	201996 kb
Host	smart-9d723f3c-d261-40dc-a5ec-90438a0b260d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732757686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1732757686
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3431078249
Short name	T311
Test name
Test status
Simulation time	534916331 ps
CPU time	5.1 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201908 kb
Host	smart-cae77bd1-e9fe-4e7a-a169-7c36ca267cda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3431078249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3431078249
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3942739044
Short name	T106
Test name
Test status
Simulation time	19099634623 ps
CPU time	137.4 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:42:20 PM PDT 24
Peak memory	202744 kb
Host	smart-b20cc1c8-b87e-4bf9-a40f-0d9a91619e79
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3942739044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3942739044
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1472850451
Short name	T561
Test name
Test status
Simulation time	291214598 ps
CPU time	2.99 seconds
Started	Apr 18 12:39:59 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201964 kb
Host	smart-b614ddac-29a4-4864-abcb-ecc298e5e3bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1472850451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1472850451
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.2781407417
Short name	T624
Test name
Test status
Simulation time	57755580 ps
CPU time	4.66 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	201984 kb
Host	smart-1d51577d-ca67-4f93-9243-b0628a7feaed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781407417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2781407417
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.4067841864
Short name	T317
Test name
Test status
Simulation time	975135295 ps
CPU time	15.39 seconds
Started	Apr 18 12:39:54 PM PDT 24
Finished	Apr 18 12:40:13 PM PDT 24
Peak memory	202012 kb
Host	smart-b279a6ae-173d-4f59-8956-cb7bd7808c2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4067841864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.4067841864
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1946742403
Short name	T870
Test name
Test status
Simulation time	6026985444 ps
CPU time	22.38 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	202000 kb
Host	smart-69ab13e0-3473-48a5-9f5f-e2b1ad52fdd6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946742403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1946742403
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2097886858
Short name	T845
Test name
Test status
Simulation time	11359827089 ps
CPU time	55.93 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:41:01 PM PDT 24
Peak memory	201972 kb
Host	smart-6646cd4e-64ac-44bc-b910-ee4e3b6c8b1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2097886858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2097886858
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2750279625
Short name	T720
Test name
Test status
Simulation time	41075171 ps
CPU time	3.7 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	202012 kb
Host	smart-dca58308-6b9f-4b5e-b580-8fae2d098fb0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750279625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2750279625
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.870645098
Short name	T815
Test name
Test status
Simulation time	647298968 ps
CPU time	9.46 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:14 PM PDT 24
Peak memory	201932 kb
Host	smart-6aca1e65-2749-48fa-adbd-a177a3a3dec3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=870645098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.870645098
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.309949279
Short name	T457
Test name
Test status
Simulation time	9586743 ps
CPU time	1.14 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201980 kb
Host	smart-fd283b4e-706a-448b-a930-5ed7907942c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=309949279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.309949279
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.870454877
Short name	T760
Test name
Test status
Simulation time	4643784456 ps
CPU time	8.59 seconds
Started	Apr 18 12:40:02 PM PDT 24
Finished	Apr 18 12:40:12 PM PDT 24
Peak memory	202000 kb
Host	smart-a3c55023-53ff-4ca2-b23e-86257aacdfa2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=870454877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.870454877
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2350157886
Short name	T470
Test name
Test status
Simulation time	1583918330 ps
CPU time	8.1 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	201912 kb
Host	smart-7ec3e86a-84b8-4647-9290-cf0dbf1d013d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2350157886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2350157886
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2759106422
Short name	T606
Test name
Test status
Simulation time	8340482 ps
CPU time	1.04 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:01 PM PDT 24
Peak memory	201876 kb
Host	smart-e80b9a1d-3e34-4faf-9ea0-cb04712ff6ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759106422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2759106422
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.2573000988
Short name	T526
Test name
Test status
Simulation time	7689065305 ps
CPU time	56.21 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:59 PM PDT 24
Peak memory	204320 kb
Host	smart-af3f707a-efd6-42d6-ac1e-e37606f48d82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573000988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2573000988
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1955412495
Short name	T658
Test name
Test status
Simulation time	2890921878 ps
CPU time	43.58 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:40:46 PM PDT 24
Peak memory	202072 kb
Host	smart-5c9daeef-0af7-4dec-acd7-c3b26a2072d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1955412495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1955412495
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1383101105
Short name	T818
Test name
Test status
Simulation time	943041873 ps
CPU time	178.51 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:42:59 PM PDT 24
Peak memory	207576 kb
Host	smart-119fd0a2-e82c-435a-a0ae-a341d5bf5a62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1383101105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1383101105
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1133527672
Short name	T758
Test name
Test status
Simulation time	1778137492 ps
CPU time	39.51 seconds
Started	Apr 18 12:40:03 PM PDT 24
Finished	Apr 18 12:40:49 PM PDT 24
Peak memory	203296 kb
Host	smart-e90b1ac6-e155-48fa-b50a-4cfbf0619ee5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1133527672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1133527672
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.741587194
Short name	T88
Test name
Test status
Simulation time	46707597 ps
CPU time	2.62 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:06 PM PDT 24
Peak memory	201900 kb
Host	smart-4ad7c001-afd3-402c-a557-5dc83ab78f05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=741587194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.741587194
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.130801322
Short name	T789
Test name
Test status
Simulation time	6034689568 ps
CPU time	20.22 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:54 PM PDT 24
Peak memory	201972 kb
Host	smart-b6069140-8b14-43a1-9d49-c2b2e0c74ca9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=130801322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.130801322
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3748299073
Short name	T772
Test name
Test status
Simulation time	35523621550 ps
CPU time	138.73 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:40:52 PM PDT 24
Peak memory	203028 kb
Host	smart-c7d72144-a970-4ded-8765-e8a5fda059d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3748299073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.3748299073
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.524105486
Short name	T572
Test name
Test status
Simulation time	179131993 ps
CPU time	3.67 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	202020 kb
Host	smart-b80a3fe4-940a-4a75-8616-549df36c57f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=524105486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.524105486
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.1861917641
Short name	T560
Test name
Test status
Simulation time	571292674 ps
CPU time	9.97 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	201872 kb
Host	smart-e9a54dde-335f-439f-b00a-662e30f87b61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1861917641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1861917641
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.759525093
Short name	T574
Test name
Test status
Simulation time	50255266 ps
CPU time	1.99 seconds
Started	Apr 18 12:38:31 PM PDT 24
Finished	Apr 18 12:38:33 PM PDT 24
Peak memory	202064 kb
Host	smart-fe127315-7935-479f-8042-30afab639fd9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=759525093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.759525093
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1439750992
Short name	T756
Test name
Test status
Simulation time	16057644113 ps
CPU time	72.08 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:39:48 PM PDT 24
Peak memory	202000 kb
Host	smart-bb87faef-9e6f-4de2-a381-7bb036363a92
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439750992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1439750992
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.151493055
Short name	T601
Test name
Test status
Simulation time	11902216715 ps
CPU time	71.31 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:39:45 PM PDT 24
Peak memory	201992 kb
Host	smart-2c1210d5-042a-48a3-b10c-2c46fe7c2a05
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=151493055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.151493055
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1702434962
Short name	T414
Test name
Test status
Simulation time	58889763 ps
CPU time	7.15 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	201980 kb
Host	smart-c8c3cd2d-d0a2-4e20-8a48-1b58767a5b64
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702434962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1702434962
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.4091846633
Short name	T199
Test name
Test status
Simulation time	539723765 ps
CPU time	3.75 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	201892 kb
Host	smart-7dcd06d1-2b9f-4415-924c-2777c4ece110
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091846633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4091846633
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.3070546258
Short name	T718
Test name
Test status
Simulation time	13221594 ps
CPU time	1.25 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	201880 kb
Host	smart-4a551e17-b6ba-48a8-bfad-7b7a9b7f5d5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070546258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3070546258
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2525080387
Short name	T747
Test name
Test status
Simulation time	3338951524 ps
CPU time	5.99 seconds
Started	Apr 18 12:38:32 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	202064 kb
Host	smart-8c42dfe6-0833-477c-b05e-78eb7e1fa86a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525080387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2525080387
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1961893570
Short name	T575
Test name
Test status
Simulation time	11620878202 ps
CPU time	10.61 seconds
Started	Apr 18 12:38:32 PM PDT 24
Finished	Apr 18 12:38:49 PM PDT 24
Peak memory	202084 kb
Host	smart-5a8bbc89-16fa-4392-b2f3-a32a56afb665
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1961893570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1961893570
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.4063810789
Short name	T320
Test name
Test status
Simulation time	9120067 ps
CPU time	1.09 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:37 PM PDT 24
Peak memory	202004 kb
Host	smart-bf00bf2b-b1d2-4367-95e6-e4d7ba8619c4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063810789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.4063810789
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.3929430590
Short name	T570
Test name
Test status
Simulation time	828079873 ps
CPU time	30.26 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:39:05 PM PDT 24
Peak memory	202104 kb
Host	smart-3af493f5-9f0b-4e90-93d7-fd57c94ac490
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3929430590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3929430590
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2505878833
Short name	T249
Test name
Test status
Simulation time	1122990040 ps
CPU time	23.44 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:58 PM PDT 24
Peak memory	202968 kb
Host	smart-97fa894a-1777-4d7a-a825-a846e58f6289
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2505878833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2505878833
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.548130461
Short name	T52
Test name
Test status
Simulation time	488677643 ps
CPU time	49.18 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:39:23 PM PDT 24
Peak memory	203956 kb
Host	smart-f04a0fea-a233-46bc-bc8e-b66997a33b99
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=548130461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.548130461
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1138321157
Short name	T165
Test name
Test status
Simulation time	177523819 ps
CPU time	5.41 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	201996 kb
Host	smart-58019cca-1276-4541-8be0-93ad3f5a2d6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1138321157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1138321157
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1284265935
Short name	T223
Test name
Test status
Simulation time	11338966 ps
CPU time	1.37 seconds
Started	Apr 18 12:38:37 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	201848 kb
Host	smart-c04d10e8-5889-4736-8d82-7a0bc8208afb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1284265935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1284265935
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2888287818
Short name	T785
Test name
Test status
Simulation time	53389001 ps
CPU time	3.58 seconds
Started	Apr 18 12:39:58 PM PDT 24
Finished	Apr 18 12:40:04 PM PDT 24
Peak memory	201924 kb
Host	smart-d8f0ea71-20a5-47ef-b876-29b46863efc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2888287818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.2888287818
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.681922825
Short name	T555
Test name
Test status
Simulation time	39182197065 ps
CPU time	92.66 seconds
Started	Apr 18 12:39:56 PM PDT 24
Finished	Apr 18 12:41:31 PM PDT 24
Peak memory	201996 kb
Host	smart-cf94a297-7ebe-4c31-b59f-15ef23670046
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=681922825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.681922825
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2369352998
Short name	T582
Test name
Test status
Simulation time	813244085 ps
CPU time	8.79 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:14 PM PDT 24
Peak memory	202012 kb
Host	smart-c3238b3a-140e-4b84-a371-d5c21833bfcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369352998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2369352998
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.1517828632
Short name	T503
Test name
Test status
Simulation time	62944973 ps
CPU time	3.06 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	201932 kb
Host	smart-8add4cc1-9cc4-4b95-8ea2-1f709a01c2a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1517828632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1517828632
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.1384741020
Short name	T327
Test name
Test status
Simulation time	82360435 ps
CPU time	4.38 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	201876 kb
Host	smart-da863036-31f5-4c14-8f58-91ff8a389cf7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1384741020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1384741020
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1345785775
Short name	T97
Test name
Test status
Simulation time	40116028732 ps
CPU time	118.78 seconds
Started	Apr 18 12:40:00 PM PDT 24
Finished	Apr 18 12:42:01 PM PDT 24
Peak memory	202060 kb
Host	smart-c5b65c35-37fe-40e5-ac43-1ed4c7cb90d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345785775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1345785775
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.4199191437
Short name	T542
Test name
Test status
Simulation time	5211712964 ps
CPU time	18.45 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	202084 kb
Host	smart-59ff93ea-cae1-4d88-9cfd-562e2b04f778
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4199191437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4199191437
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.806805357
Short name	T370
Test name
Test status
Simulation time	80731585 ps
CPU time	4.69 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	202012 kb
Host	smart-db36b8cb-ad19-4bec-9242-8a324abc89a4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806805357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.806805357
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.4178846310
Short name	T259
Test name
Test status
Simulation time	654721579 ps
CPU time	7.31 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	201976 kb
Host	smart-bf054f67-f0ba-479c-ab57-bed913190a3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4178846310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4178846310
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.2784020511
Short name	T299
Test name
Test status
Simulation time	120619534 ps
CPU time	1.37 seconds
Started	Apr 18 12:39:57 PM PDT 24
Finished	Apr 18 12:40:02 PM PDT 24
Peak memory	201924 kb
Host	smart-ee68bf4e-e54f-48ff-a9aa-2e38f2915cb1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784020511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2784020511
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.443697885
Short name	T847
Test name
Test status
Simulation time	3461671628 ps
CPU time	12.98 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:16 PM PDT 24
Peak memory	202060 kb
Host	smart-d12d4b08-e5e9-427d-9c16-41b3f4319a6d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=443697885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.443697885
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2572610529
Short name	T675
Test name
Test status
Simulation time	1278113053 ps
CPU time	6.42 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201984 kb
Host	smart-d78122d0-43b6-4262-83f0-10d476e6e3ad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2572610529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2572610529
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1690766034
Short name	T251
Test name
Test status
Simulation time	15991848 ps
CPU time	1.25 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201924 kb
Host	smart-851bac48-d6c6-4dd0-9265-6354ed93084a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690766034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1690766034
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.4219509981
Short name	T157
Test name
Test status
Simulation time	9693678075 ps
CPU time	78.53 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:41:37 PM PDT 24
Peak memory	204348 kb
Host	smart-003e8a2a-39a2-4066-b6ac-0b4bb5af40de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4219509981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4219509981
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.11289024
Short name	T833
Test name
Test status
Simulation time	1136888157 ps
CPU time	21.62 seconds
Started	Apr 18 12:40:03 PM PDT 24
Finished	Apr 18 12:40:31 PM PDT 24
Peak memory	201992 kb
Host	smart-c4bf15f9-0ae0-42a5-866b-b5efc5458435
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=11289024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.11289024
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2700232239
Short name	T501
Test name
Test status
Simulation time	930486220 ps
CPU time	83.02 seconds
Started	Apr 18 12:40:07 PM PDT 24
Finished	Apr 18 12:41:32 PM PDT 24
Peak memory	204748 kb
Host	smart-69cce794-063c-4cff-8155-2da02cc59bdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2700232239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2700232239
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1186491686
Short name	T28
Test name
Test status
Simulation time	409078967 ps
CPU time	4.98 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	202020 kb
Host	smart-4ced27cb-befe-4073-ab42-21ce0ead0453
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1186491686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1186491686
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2782941500
Short name	T239
Test name
Test status
Simulation time	5358498798 ps
CPU time	21.16 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	202072 kb
Host	smart-0f7d24f7-7287-4a65-a91f-3bf4b784b1c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782941500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2782941500
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1839750079
Short name	T153
Test name
Test status
Simulation time	62657370778 ps
CPU time	187.86 seconds
Started	Apr 18 12:40:11 PM PDT 24
Finished	Apr 18 12:43:20 PM PDT 24
Peak memory	203980 kb
Host	smart-8d0f539e-627a-4a66-abb6-b68128c89137
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1839750079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1839750079
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.255629133
Short name	T897
Test name
Test status
Simulation time	187893714 ps
CPU time	3.98 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	201956 kb
Host	smart-d5f353fe-01d0-4402-ac25-835078de391b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=255629133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.255629133
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.3175078054
Short name	T616
Test name
Test status
Simulation time	1495026939 ps
CPU time	12.55 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	201900 kb
Host	smart-87958bf0-bd14-46bd-a56f-a2353e2a8b69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175078054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3175078054
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.701722186
Short name	T254
Test name
Test status
Simulation time	184164502 ps
CPU time	3.08 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201880 kb
Host	smart-774f6edd-7c03-4f5c-b1e5-c4ce64062dd4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=701722186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.701722186
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.432596069
Short name	T536
Test name
Test status
Simulation time	68655830932 ps
CPU time	86.23 seconds
Started	Apr 18 12:40:21 PM PDT 24
Finished	Apr 18 12:41:48 PM PDT 24
Peak memory	202088 kb
Host	smart-ce1db3d1-5b48-4148-b5b6-e6d948ec6b90
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=432596069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.432596069
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2333393703
Short name	T664
Test name
Test status
Simulation time	71427257396 ps
CPU time	72.27 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:41:28 PM PDT 24
Peak memory	202048 kb
Host	smart-fcc40440-9afc-4634-847d-98b5a82530b4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2333393703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2333393703
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.153751066
Short name	T390
Test name
Test status
Simulation time	93808758 ps
CPU time	8.14 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:24 PM PDT 24
Peak memory	202008 kb
Host	smart-70013baa-ea1c-434e-9907-8bc7f8bf5d77
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153751066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.153751066
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.209650703
Short name	T608
Test name
Test status
Simulation time	1347167880 ps
CPU time	12.87 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:29 PM PDT 24
Peak memory	201980 kb
Host	smart-a0c419e4-4a05-4145-9878-fd6c6aad01b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209650703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.209650703
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.3605002873
Short name	T378
Test name
Test status
Simulation time	9175653 ps
CPU time	1.14 seconds
Started	Apr 18 12:40:06 PM PDT 24
Finished	Apr 18 12:40:09 PM PDT 24
Peak memory	201892 kb
Host	smart-f01e83d4-8d7c-49a7-970b-ff4071bc92ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605002873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3605002873
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1404125905
Short name	T236
Test name
Test status
Simulation time	1764002112 ps
CPU time	6.78 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	201900 kb
Host	smart-33cc4766-0ddf-4856-8ef2-56fd439c1c3b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404125905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1404125905
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.892090297
Short name	T732
Test name
Test status
Simulation time	1656187692 ps
CPU time	11.61 seconds
Started	Apr 18 12:40:03 PM PDT 24
Finished	Apr 18 12:40:16 PM PDT 24
Peak memory	202024 kb
Host	smart-2d86ae5a-a478-42a7-8577-536ad717a3d5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=892090297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.892090297
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1812106322
Short name	T745
Test name
Test status
Simulation time	10789607 ps
CPU time	1 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201900 kb
Host	smart-72bff915-906d-4d3e-96e0-9f8d03497b87
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812106322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1812106322
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.788294793
Short name	T888
Test name
Test status
Simulation time	3338661856 ps
CPU time	24.01 seconds
Started	Apr 18 12:40:20 PM PDT 24
Finished	Apr 18 12:40:45 PM PDT 24
Peak memory	202044 kb
Host	smart-5dadeb20-a805-4b44-aaa0-f31270f65207
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788294793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.788294793
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.72062635
Short name	T220
Test name
Test status
Simulation time	1511207529 ps
CPU time	47.73 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:53 PM PDT 24
Peak memory	203024 kb
Host	smart-c00f2fc5-6fc9-4801-8de2-f85bf82b5166
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=72062635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.72062635
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2018722745
Short name	T279
Test name
Test status
Simulation time	3315941575 ps
CPU time	67.41 seconds
Started	Apr 18 12:40:06 PM PDT 24
Finished	Apr 18 12:41:15 PM PDT 24
Peak memory	204020 kb
Host	smart-85a7dff4-2b41-4f90-b80b-1d8ceccf9cf8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2018722745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2018722745
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3135891675
Short name	T801
Test name
Test status
Simulation time	419575663 ps
CPU time	40.28 seconds
Started	Apr 18 12:40:10 PM PDT 24
Finished	Apr 18 12:40:52 PM PDT 24
Peak memory	203996 kb
Host	smart-79c84bf7-8b31-44c7-bfe1-74830d213bb5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3135891675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.3135891675
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2588562630
Short name	T198
Test name
Test status
Simulation time	150014602 ps
CPU time	3.08 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	201876 kb
Host	smart-92c7b077-a424-4b29-aa11-9880cfab4500
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588562630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2588562630
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2828488717
Short name	T868
Test name
Test status
Simulation time	128047158 ps
CPU time	4.44 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201980 kb
Host	smart-dfbb1187-1ab4-49ed-9626-2fefed0c8292
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828488717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2828488717
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2751318077
Short name	T154
Test name
Test status
Simulation time	4321954392 ps
CPU time	31.1 seconds
Started	Apr 18 12:40:08 PM PDT 24
Finished	Apr 18 12:40:46 PM PDT 24
Peak memory	202044 kb
Host	smart-349dd195-cab8-4a8d-9473-c0790cd434d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2751318077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2751318077
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2186192338
Short name	T18
Test name
Test status
Simulation time	66678505 ps
CPU time	1.13 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201896 kb
Host	smart-bb6ce461-7e4b-4917-a657-aae155603f77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186192338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2186192338
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.3724563103
Short name	T492
Test name
Test status
Simulation time	58547896 ps
CPU time	4.61 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201880 kb
Host	smart-6f4b9d04-1034-43f2-9a1b-ecfe7d333ccd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3724563103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3724563103
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.3556985166
Short name	T618
Test name
Test status
Simulation time	40957856 ps
CPU time	4.81 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	202036 kb
Host	smart-afbec91c-d10a-4387-9823-2067538e2ee7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3556985166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3556985166
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3920336191
Short name	T349
Test name
Test status
Simulation time	39579201586 ps
CPU time	132.18 seconds
Started	Apr 18 12:40:09 PM PDT 24
Finished	Apr 18 12:42:22 PM PDT 24
Peak memory	202012 kb
Host	smart-766206c6-a037-4256-832d-2b2168c42951
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920336191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3920336191
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2467087724
Short name	T117
Test name
Test status
Simulation time	33934099495 ps
CPU time	214.76 seconds
Started	Apr 18 12:40:01 PM PDT 24
Finished	Apr 18 12:43:37 PM PDT 24
Peak memory	201984 kb
Host	smart-92ae0c0a-2a16-4d0e-9fec-92ab8f57b45c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2467087724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2467087724
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3790611244
Short name	T814
Test name
Test status
Simulation time	94723446 ps
CPU time	5.32 seconds
Started	Apr 18 12:40:05 PM PDT 24
Finished	Apr 18 12:40:11 PM PDT 24
Peak memory	201904 kb
Host	smart-c6148a39-b223-409c-96d0-f4b82d6fd815
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790611244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3790611244
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.865417868
Short name	T592
Test name
Test status
Simulation time	260316903 ps
CPU time	4.39 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:10 PM PDT 24
Peak memory	201908 kb
Host	smart-567684e6-e4b7-4571-b3a0-3a116edd2244
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=865417868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.865417868
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.4172990676
Short name	T460
Test name
Test status
Simulation time	98196465 ps
CPU time	1.74 seconds
Started	Apr 18 12:40:05 PM PDT 24
Finished	Apr 18 12:40:08 PM PDT 24
Peak memory	202036 kb
Host	smart-5e76914f-6c54-4036-ab99-785861efd589
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172990676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4172990676
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.824836064
Short name	T512
Test name
Test status
Simulation time	2815852478 ps
CPU time	6.93 seconds
Started	Apr 18 12:40:07 PM PDT 24
Finished	Apr 18 12:40:15 PM PDT 24
Peak memory	202056 kb
Host	smart-f06c0a67-b501-4ec7-9b1f-82150f828d86
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=824836064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.824836064
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3680959228
Short name	T764
Test name
Test status
Simulation time	3836817652 ps
CPU time	8.8 seconds
Started	Apr 18 12:40:06 PM PDT 24
Finished	Apr 18 12:40:15 PM PDT 24
Peak memory	202088 kb
Host	smart-f2cbf747-958d-4376-899f-fd3bf9af1147
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3680959228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3680959228
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2258640044
Short name	T768
Test name
Test status
Simulation time	13865712 ps
CPU time	1.1 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201880 kb
Host	smart-d3a165f4-3687-4e99-b9f9-ba8edc9c0a84
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258640044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2258640044
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.3330963715
Short name	T246
Test name
Test status
Simulation time	2676585659 ps
CPU time	50.73 seconds
Started	Apr 18 12:40:03 PM PDT 24
Finished	Apr 18 12:40:55 PM PDT 24
Peak memory	203004 kb
Host	smart-c3c26495-7971-4245-b389-0266a27858d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3330963715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3330963715
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1066215921
Short name	T716
Test name
Test status
Simulation time	574313251 ps
CPU time	8.34 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:25 PM PDT 24
Peak memory	201888 kb
Host	smart-4e76c190-0c75-46e1-972c-60b99fdd2f35
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1066215921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1066215921
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3504470929
Short name	T636
Test name
Test status
Simulation time	622447541 ps
CPU time	109.73 seconds
Started	Apr 18 12:40:03 PM PDT 24
Finished	Apr 18 12:41:54 PM PDT 24
Peak memory	204432 kb
Host	smart-8a26f9d1-e976-451a-8846-60b13d385a4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3504470929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3504470929
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.4281632079
Short name	T7
Test name
Test status
Simulation time	6770141359 ps
CPU time	85.63 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:41:43 PM PDT 24
Peak memory	204856 kb
Host	smart-98b49ce8-3e64-417f-9503-7af71416a4ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4281632079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.4281632079
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2636799261
Short name	T753
Test name
Test status
Simulation time	21504494 ps
CPU time	1.7 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:07 PM PDT 24
Peak memory	201908 kb
Host	smart-c3d29440-cb2f-41a2-97cf-b981a0079264
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2636799261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2636799261
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1921694691
Short name	T669
Test name
Test status
Simulation time	1168257463 ps
CPU time	13.22 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:30 PM PDT 24
Peak memory	202008 kb
Host	smart-0f6beb44-fb51-4a4a-93d2-f953d15b729e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1921694691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1921694691
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3867944514
Short name	T147
Test name
Test status
Simulation time	25583895490 ps
CPU time	70.47 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:41:26 PM PDT 24
Peak memory	201924 kb
Host	smart-455ffbac-1aaa-4ed4-bde8-11f083449dad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3867944514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3867944514
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3208224885
Short name	T111
Test name
Test status
Simulation time	470868089 ps
CPU time	5.47 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	201932 kb
Host	smart-ead6d99d-cc19-45a1-8ccb-3077633abb97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3208224885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3208224885
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.3417466823
Short name	T790
Test name
Test status
Simulation time	1725649268 ps
CPU time	10.27 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	201900 kb
Host	smart-ef1e1f48-2f83-4b95-bb7d-1610413e6501
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417466823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3417466823
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.3619049079
Short name	T529
Test name
Test status
Simulation time	168099452 ps
CPU time	4.11 seconds
Started	Apr 18 12:40:06 PM PDT 24
Finished	Apr 18 12:40:12 PM PDT 24
Peak memory	201976 kb
Host	smart-9106b95f-fc3a-41c9-854e-d3c6d10f4ca5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3619049079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3619049079
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1417925227
Short name	T777
Test name
Test status
Simulation time	79016579333 ps
CPU time	145.52 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:42:42 PM PDT 24
Peak memory	201964 kb
Host	smart-f7074d0c-9cd9-42af-84bc-b3c5172b7289
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417925227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1417925227
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3259434449
Short name	T163
Test name
Test status
Simulation time	9048393496 ps
CPU time	14.22 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:29 PM PDT 24
Peak memory	202000 kb
Host	smart-0c20a2b7-c984-4b13-949d-5bfc22a822f5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3259434449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3259434449
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.108821620
Short name	T578
Test name
Test status
Simulation time	29615299 ps
CPU time	1.78 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201912 kb
Host	smart-e2465923-dfdc-4bf3-99d3-58f128ffd499
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108821620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.108821620
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.1008298058
Short name	T473
Test name
Test status
Simulation time	29616902 ps
CPU time	2.85 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201928 kb
Host	smart-4576e760-2e16-44db-bcd4-de7e698b5b66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1008298058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1008298058
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.86855173
Short name	T489
Test name
Test status
Simulation time	56071312 ps
CPU time	1.43 seconds
Started	Apr 18 12:40:02 PM PDT 24
Finished	Apr 18 12:40:05 PM PDT 24
Peak memory	201940 kb
Host	smart-7b6bfc33-dbd8-4c77-91a8-32cc222b0620
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86855173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.86855173
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1126027953
Short name	T879
Test name
Test status
Simulation time	1615778457 ps
CPU time	8.72 seconds
Started	Apr 18 12:40:04 PM PDT 24
Finished	Apr 18 12:40:14 PM PDT 24
Peak memory	202060 kb
Host	smart-06e1405a-e37a-496b-be4e-dfbec36eef94
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126027953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1126027953
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.445705995
Short name	T486
Test name
Test status
Simulation time	2433618545 ps
CPU time	14.88 seconds
Started	Apr 18 12:40:07 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	202000 kb
Host	smart-515ec3b3-81c4-42e1-8f7a-a0534353c709
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=445705995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.445705995
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1787982947
Short name	T213
Test name
Test status
Simulation time	10213872 ps
CPU time	1.18 seconds
Started	Apr 18 12:40:10 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	202004 kb
Host	smart-af574311-7e6a-47c2-bd44-927b34b1d01c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787982947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1787982947
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.2944895681
Short name	T293
Test name
Test status
Simulation time	6265567015 ps
CPU time	37.06 seconds
Started	Apr 18 12:40:09 PM PDT 24
Finished	Apr 18 12:40:47 PM PDT 24
Peak memory	202008 kb
Host	smart-48a63c06-0f82-4040-a338-ed9063a669b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944895681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2944895681
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1503646316
Short name	T405
Test name
Test status
Simulation time	160223612 ps
CPU time	12.46 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	201964 kb
Host	smart-63910f35-8551-468e-9aeb-845f55997b25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1503646316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1503646316
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2496319830
Short name	T854
Test name
Test status
Simulation time	2568156925 ps
CPU time	76.07 seconds
Started	Apr 18 12:40:19 PM PDT 24
Finished	Apr 18 12:41:36 PM PDT 24
Peak memory	206396 kb
Host	smart-c2121e38-a5b3-43a2-a806-21cd63fd05b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496319830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2496319830
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1875619888
Short name	T39
Test name
Test status
Simulation time	166173599 ps
CPU time	6.79 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201880 kb
Host	smart-612c2d22-6e12-4841-a73d-4861d217426e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875619888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1875619888
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1015119594
Short name	T678
Test name
Test status
Simulation time	142757225 ps
CPU time	12 seconds
Started	Apr 18 12:40:21 PM PDT 24
Finished	Apr 18 12:40:34 PM PDT 24
Peak memory	202008 kb
Host	smart-b67ad9c5-ab5f-4a50-8d6f-692e732ffab5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1015119594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1015119594
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3185716929
Short name	T359
Test name
Test status
Simulation time	105424103657 ps
CPU time	183.6 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:43:19 PM PDT 24
Peak memory	204128 kb
Host	smart-889e7ef4-bc40-4dd4-a09b-b561d3b8c11a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3185716929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3185716929
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2272980138
Short name	T420
Test name
Test status
Simulation time	49637012 ps
CPU time	4.1 seconds
Started	Apr 18 12:40:08 PM PDT 24
Finished	Apr 18 12:40:13 PM PDT 24
Peak memory	201880 kb
Host	smart-db0ee0e0-d964-4c25-88aa-24eb471e882d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2272980138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2272980138
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.2796028954
Short name	T775
Test name
Test status
Simulation time	24599153 ps
CPU time	2.34 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	202008 kb
Host	smart-41c86ed3-3186-4925-9faf-aa94b740d1f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2796028954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2796028954
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.3851456446
Short name	T27
Test name
Test status
Simulation time	576065624 ps
CPU time	6.65 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:40:31 PM PDT 24
Peak memory	202008 kb
Host	smart-4bf7a84d-58ee-43fc-a419-2fa24ddaab15
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3851456446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3851456446
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3168209977
Short name	T850
Test name
Test status
Simulation time	20568217830 ps
CPU time	48.9 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:41:04 PM PDT 24
Peak memory	202048 kb
Host	smart-3e76db66-d6a4-429f-b144-6005109b366e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168209977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3168209977
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3153534374
Short name	T804
Test name
Test status
Simulation time	100094455332 ps
CPU time	91.33 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:41:47 PM PDT 24
Peak memory	202000 kb
Host	smart-da779113-6e42-42be-9219-4bb35a473b49
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3153534374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3153534374
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.404596871
Short name	T381
Test name
Test status
Simulation time	24186112 ps
CPU time	3.37 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	201916 kb
Host	smart-3d5e0237-4915-4c88-9a57-5b0146595335
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404596871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.404596871
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.410937865
Short name	T191
Test name
Test status
Simulation time	24170042 ps
CPU time	2.54 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:15 PM PDT 24
Peak memory	202024 kb
Host	smart-b9c40cac-b63b-4395-ab11-d01d61e1a996
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410937865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.410937865
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.459463581
Short name	T611
Test name
Test status
Simulation time	227444175 ps
CPU time	1.34 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201880 kb
Host	smart-9510efcb-d674-4e48-a970-11aa3aa7b6af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=459463581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.459463581
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.4216072009
Short name	T882
Test name
Test status
Simulation time	2344674865 ps
CPU time	11.29 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	202084 kb
Host	smart-005ee157-bd4f-40ed-948b-2a592d397049
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216072009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.4216072009
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4053290542
Short name	T271
Test name
Test status
Simulation time	3448633176 ps
CPU time	10.52 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	201976 kb
Host	smart-46ad7d29-4285-4803-9823-da9ada94034c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4053290542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4053290542
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.159950069
Short name	T740
Test name
Test status
Simulation time	7698907 ps
CPU time	1.01 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201956 kb
Host	smart-d757b378-b89d-4290-a3b8-0849ecc85780
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159950069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.159950069
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.2749715864
Short name	T115
Test name
Test status
Simulation time	8168238147 ps
CPU time	79.52 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:41:37 PM PDT 24
Peak memory	202964 kb
Host	smart-3fc1fd5d-e24f-4642-8fc2-aa9fbaa8d98a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749715864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2749715864
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.303265377
Short name	T227
Test name
Test status
Simulation time	290286438 ps
CPU time	6.19 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201936 kb
Host	smart-9fb2f887-1cbf-4063-a0e6-2fd930a431da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303265377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.303265377
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2010678524
Short name	T369
Test name
Test status
Simulation time	6306003422 ps
CPU time	50.99 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:41:09 PM PDT 24
Peak memory	204628 kb
Host	smart-79853414-76e7-4e9f-b3d4-1bb0b5a75557
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2010678524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.2010678524
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.18191720
Short name	T448
Test name
Test status
Simulation time	910687623 ps
CPU time	119.69 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:42:18 PM PDT 24
Peak memory	206148 kb
Host	smart-ec335bc3-bbc3-402c-b708-0cdaffb60562
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18191720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rese t_error.18191720
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1044025585
Short name	T338
Test name
Test status
Simulation time	82809682 ps
CPU time	1.33 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	201892 kb
Host	smart-c35fb432-2b4b-4ba3-b531-d57f16337e90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1044025585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1044025585
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3872923388
Short name	T516
Test name
Test status
Simulation time	1081649188 ps
CPU time	11.04 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	202008 kb
Host	smart-2e7b6652-56fd-463b-addc-f7ba2210ecdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872923388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3872923388
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3209889585
Short name	T78
Test name
Test status
Simulation time	43135813621 ps
CPU time	219.13 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:43:57 PM PDT 24
Peak memory	203092 kb
Host	smart-2778870c-147b-4268-ba35-903987b24f9a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3209889585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3209889585
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2631168309
Short name	T504
Test name
Test status
Simulation time	523708907 ps
CPU time	8.82 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:40:33 PM PDT 24
Peak memory	201992 kb
Host	smart-26139bf2-9897-4bc1-8321-96cdd1ad7b44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631168309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2631168309
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.2264405009
Short name	T765
Test name
Test status
Simulation time	12227714 ps
CPU time	1.51 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:15 PM PDT 24
Peak memory	201916 kb
Host	smart-6dff4b0b-d0c7-472b-b80a-cb8f38b328cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2264405009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2264405009
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.1550945633
Short name	T205
Test name
Test status
Simulation time	237893356 ps
CPU time	4.43 seconds
Started	Apr 18 12:40:15 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	202004 kb
Host	smart-a352d3a4-9458-4fe4-86c1-d7ed39272ca6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1550945633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1550945633
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2112574388
Short name	T21
Test name
Test status
Simulation time	28734253662 ps
CPU time	60.12 seconds
Started	Apr 18 12:40:10 PM PDT 24
Finished	Apr 18 12:41:11 PM PDT 24
Peak memory	202000 kb
Host	smart-b1359555-daba-45da-839b-60fe5dae7933
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112574388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2112574388
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3531505039
Short name	T93
Test name
Test status
Simulation time	15351617516 ps
CPU time	90.72 seconds
Started	Apr 18 12:40:19 PM PDT 24
Finished	Apr 18 12:41:51 PM PDT 24
Peak memory	202084 kb
Host	smart-33601db6-82f2-4a35-80ba-87e9aebc85b1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3531505039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3531505039
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2333223873
Short name	T851
Test name
Test status
Simulation time	22591956 ps
CPU time	1.03 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201864 kb
Host	smart-fbcb0d1b-4a3a-4bdb-af58-54401cbfc551
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333223873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2333223873
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.2232342646
Short name	T672
Test name
Test status
Simulation time	59099478 ps
CPU time	5.75 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	202016 kb
Host	smart-daeda78e-624c-4346-80ef-724dd4b8502e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232342646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2232342646
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.1115961639
Short name	T820
Test name
Test status
Simulation time	67255462 ps
CPU time	1.6 seconds
Started	Apr 18 12:40:19 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	201920 kb
Host	smart-0ea5c147-d157-459c-9fbb-e51129a8aab2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115961639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1115961639
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2986142993
Short name	T549
Test name
Test status
Simulation time	2865889503 ps
CPU time	10.88 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	202080 kb
Host	smart-0d4805ec-6674-4602-a3c3-3ecf9a914f3e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986142993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2986142993
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.727522924
Short name	T306
Test name
Test status
Simulation time	1634186423 ps
CPU time	10.63 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	202024 kb
Host	smart-dca2922c-6c64-4e03-8c53-29aaca057844
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727522924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.727522924
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2825973949
Short name	T824
Test name
Test status
Simulation time	10154507 ps
CPU time	1.12 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:40:26 PM PDT 24
Peak memory	201900 kb
Host	smart-1f12d516-a432-4221-b920-d0494f0cc4b2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825973949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2825973949
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.1076336841
Short name	T478
Test name
Test status
Simulation time	15365697228 ps
CPU time	80.81 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:41:35 PM PDT 24
Peak memory	204376 kb
Host	smart-70a2ce93-838b-4eec-a08c-e64e83ead405
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1076336841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1076336841
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.4266580005
Short name	T421
Test name
Test status
Simulation time	1484906679 ps
CPU time	39.7 seconds
Started	Apr 18 12:40:20 PM PDT 24
Finished	Apr 18 12:41:00 PM PDT 24
Peak memory	202024 kb
Host	smart-c345e641-1e64-4adb-bd09-dfc881f00784
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266580005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4266580005
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3759333052
Short name	T634
Test name
Test status
Simulation time	13981667511 ps
CPU time	112.55 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:42:16 PM PDT 24
Peak memory	204436 kb
Host	smart-20acfa2a-f0f4-4fe0-bcc3-29d7e4e013a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3759333052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.3759333052
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2512657895
Short name	T174
Test name
Test status
Simulation time	5476013937 ps
CPU time	139.73 seconds
Started	Apr 18 12:40:09 PM PDT 24
Finished	Apr 18 12:42:30 PM PDT 24
Peak memory	206680 kb
Host	smart-625bd7db-fa1e-4880-8938-a0c588e79c36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2512657895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2512657895
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3899383471
Short name	T657
Test name
Test status
Simulation time	395188736 ps
CPU time	7.77 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:40:25 PM PDT 24
Peak memory	201976 kb
Host	smart-d5461f57-b2ab-4653-ae28-72a05a77a5c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3899383471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3899383471
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2551743841
Short name	T252
Test name
Test status
Simulation time	560524972 ps
CPU time	12.97 seconds
Started	Apr 18 12:40:48 PM PDT 24
Finished	Apr 18 12:41:02 PM PDT 24
Peak memory	201988 kb
Host	smart-1c3e7071-0146-47e0-be9d-2ec1826cceef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2551743841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2551743841
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.460567641
Short name	T125
Test name
Test status
Simulation time	51509395459 ps
CPU time	118.83 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:42:17 PM PDT 24
Peak memory	203012 kb
Host	smart-08ae835a-801e-4adb-ace8-9ef90c3f7736
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=460567641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.460567641
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1966532233
Short name	T877
Test name
Test status
Simulation time	531034264 ps
CPU time	8.86 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	201956 kb
Host	smart-8df31b50-2c8d-468b-ab62-8e18755347cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966532233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1966532233
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.2956829620
Short name	T543
Test name
Test status
Simulation time	882367377 ps
CPU time	9.47 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	201948 kb
Host	smart-eb4b33b4-bf3a-4fd9-bc79-9cccfdd351dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2956829620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2956829620
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.20117637
Short name	T322
Test name
Test status
Simulation time	92959866 ps
CPU time	5.9 seconds
Started	Apr 18 12:40:16 PM PDT 24
Finished	Apr 18 12:40:24 PM PDT 24
Peak memory	201876 kb
Host	smart-752a1487-01fc-45d1-bd2b-25a02537c3bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20117637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.20117637
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3460954100
Short name	T461
Test name
Test status
Simulation time	21119865804 ps
CPU time	85.52 seconds
Started	Apr 18 12:40:13 PM PDT 24
Finished	Apr 18 12:41:40 PM PDT 24
Peak memory	202080 kb
Host	smart-955fbe6b-8de5-453b-9966-fdd0cce64380
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460954100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3460954100
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3372637209
Short name	T313
Test name
Test status
Simulation time	3839343194 ps
CPU time	8.88 seconds
Started	Apr 18 12:40:36 PM PDT 24
Finished	Apr 18 12:40:45 PM PDT 24
Peak memory	202056 kb
Host	smart-c925996d-6d12-4c05-824a-47b79599640e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3372637209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3372637209
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.4087038185
Short name	T825
Test name
Test status
Simulation time	117991732 ps
CPU time	3.69 seconds
Started	Apr 18 12:40:12 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	201920 kb
Host	smart-41adbcfb-8436-4c2d-b111-c87a172e9f2f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087038185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4087038185
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.2380220309
Short name	T197
Test name
Test status
Simulation time	26947839 ps
CPU time	2.88 seconds
Started	Apr 18 12:40:38 PM PDT 24
Finished	Apr 18 12:40:42 PM PDT 24
Peak memory	202036 kb
Host	smart-cd936566-5267-4de7-98e5-7e7fab5e9728
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2380220309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2380220309
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.3154739179
Short name	T67
Test name
Test status
Simulation time	146631427 ps
CPU time	1.76 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:40:20 PM PDT 24
Peak memory	202012 kb
Host	smart-f2c49101-402b-4181-99d5-e5811f256546
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154739179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3154739179
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.595997808
Short name	T386
Test name
Test status
Simulation time	2162672043 ps
CPU time	8.83 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:25 PM PDT 24
Peak memory	202000 kb
Host	smart-f30737ab-f99c-4705-9d42-af5aaf06973f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=595997808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.595997808
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2618309395
Short name	T653
Test name
Test status
Simulation time	1910340078 ps
CPU time	9.75 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:40:34 PM PDT 24
Peak memory	201928 kb
Host	smart-6e588175-d51d-4cb1-bd11-75b6fc6dbe78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2618309395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2618309395
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3165754641
Short name	T1
Test name
Test status
Simulation time	9546652 ps
CPU time	1.24 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:17 PM PDT 24
Peak memory	202012 kb
Host	smart-a27584a3-71a2-4152-8109-2aebe7996cac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165754641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3165754641
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.139232563
Short name	T50
Test name
Test status
Simulation time	12758704125 ps
CPU time	99.85 seconds
Started	Apr 18 12:40:30 PM PDT 24
Finished	Apr 18 12:42:10 PM PDT 24
Peak memory	204376 kb
Host	smart-0563bd1d-31bf-4425-9d9b-9bec1eeecfa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=139232563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.139232563
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.904342679
Short name	T2
Test name
Test status
Simulation time	344909329 ps
CPU time	11.4 seconds
Started	Apr 18 12:40:26 PM PDT 24
Finished	Apr 18 12:40:38 PM PDT 24
Peak memory	201856 kb
Host	smart-bc5f9310-b574-4416-a4f4-0fb1c1f229ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=904342679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.904342679
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.56907056
Short name	T712
Test name
Test status
Simulation time	296799976 ps
CPU time	48.62 seconds
Started	Apr 18 12:40:34 PM PDT 24
Finished	Apr 18 12:41:24 PM PDT 24
Peak memory	204228 kb
Host	smart-571cfb51-1099-4100-9bab-7b6bf5f45c0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56907056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_ reset.56907056
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2000991346
Short name	T523
Test name
Test status
Simulation time	916996754 ps
CPU time	107.74 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:42:13 PM PDT 24
Peak memory	206320 kb
Host	smart-ffab341f-cb00-4cf6-89e8-8a7febd8c0bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000991346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2000991346
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.768455788
Short name	T302
Test name
Test status
Simulation time	81572147 ps
CPU time	1.91 seconds
Started	Apr 18 12:40:14 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	202004 kb
Host	smart-30c7d6cb-d6d1-4008-9311-73059c83e396
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=768455788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.768455788
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3081141480
Short name	T564
Test name
Test status
Simulation time	258471196 ps
CPU time	3.85 seconds
Started	Apr 18 12:40:33 PM PDT 24
Finished	Apr 18 12:40:38 PM PDT 24
Peak memory	201952 kb
Host	smart-f1fde039-5414-4455-8dd6-7eafe6c8f95a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3081141480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3081141480
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3339182600
Short name	T132
Test name
Test status
Simulation time	30834140935 ps
CPU time	175.01 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:43:20 PM PDT 24
Peak memory	203080 kb
Host	smart-5c4fbe95-3561-4f55-b823-b87f97652a1b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3339182600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3339182600
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2813538876
Short name	T184
Test name
Test status
Simulation time	266182174 ps
CPU time	2.92 seconds
Started	Apr 18 12:40:33 PM PDT 24
Finished	Apr 18 12:40:37 PM PDT 24
Peak memory	201920 kb
Host	smart-e4437417-5c27-45a5-9563-69b1735a308a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2813538876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2813538876
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.1223519819
Short name	T450
Test name
Test status
Simulation time	88578610 ps
CPU time	5.14 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	201900 kb
Host	smart-efbd1311-7385-4edf-bee6-7d85c98590c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223519819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1223519819
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.3148656383
Short name	T417
Test name
Test status
Simulation time	1417018402 ps
CPU time	14.85 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:40:40 PM PDT 24
Peak memory	201860 kb
Host	smart-77f27f56-1fc8-45f0-aee4-911f2bb25677
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3148656383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3148656383
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1172140741
Short name	T207
Test name
Test status
Simulation time	6781133077 ps
CPU time	7.31 seconds
Started	Apr 18 12:40:38 PM PDT 24
Finished	Apr 18 12:40:46 PM PDT 24
Peak memory	201976 kb
Host	smart-3b752b28-15e2-405a-8376-19ffbcd17b32
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172140741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1172140741
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1525621238
Short name	T682
Test name
Test status
Simulation time	35003164569 ps
CPU time	116.28 seconds
Started	Apr 18 12:40:36 PM PDT 24
Finished	Apr 18 12:42:33 PM PDT 24
Peak memory	202080 kb
Host	smart-8881a996-fe76-44bf-98a6-a2859317546e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1525621238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1525621238
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2200387893
Short name	T754
Test name
Test status
Simulation time	47506702 ps
CPU time	5.01 seconds
Started	Apr 18 12:40:33 PM PDT 24
Finished	Apr 18 12:40:39 PM PDT 24
Peak memory	201920 kb
Host	smart-8776bf20-a3c0-419f-9d21-9c6352248594
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200387893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2200387893
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.4049323288
Short name	T522
Test name
Test status
Simulation time	1079936875 ps
CPU time	9.21 seconds
Started	Apr 18 12:40:21 PM PDT 24
Finished	Apr 18 12:40:31 PM PDT 24
Peak memory	201848 kb
Host	smart-eba964c1-43a7-41c7-964d-64cbf30513d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049323288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.4049323288
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.4053040704
Short name	T550
Test name
Test status
Simulation time	49239319 ps
CPU time	1.45 seconds
Started	Apr 18 12:40:20 PM PDT 24
Finished	Apr 18 12:40:23 PM PDT 24
Peak memory	201876 kb
Host	smart-8e1a3e73-448f-4a4d-9833-7d647f9a99ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4053040704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4053040704
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2822130654
Short name	T112
Test name
Test status
Simulation time	1683406417 ps
CPU time	7.92 seconds
Started	Apr 18 12:40:27 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	202000 kb
Host	smart-a945c403-d849-4d8f-ba83-ba2e4a9bf1a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822130654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2822130654
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2966472428
Short name	T626
Test name
Test status
Simulation time	1848322290 ps
CPU time	8.03 seconds
Started	Apr 18 12:40:31 PM PDT 24
Finished	Apr 18 12:40:39 PM PDT 24
Peak memory	201908 kb
Host	smart-6cf8ee66-3623-4cf2-b612-c4ba3adf7931
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2966472428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2966472428
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3987853726
Short name	T13
Test name
Test status
Simulation time	9136758 ps
CPU time	1.18 seconds
Started	Apr 18 12:40:28 PM PDT 24
Finished	Apr 18 12:40:30 PM PDT 24
Peak memory	201956 kb
Host	smart-f150fde5-8a16-4bbb-b2d7-beb337c388ff
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987853726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3987853726
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1256124973
Short name	T407
Test name
Test status
Simulation time	4543845303 ps
CPU time	33.47 seconds
Started	Apr 18 12:40:38 PM PDT 24
Finished	Apr 18 12:41:13 PM PDT 24
Peak memory	202044 kb
Host	smart-1117c5d7-1754-41dc-ac37-6f151f09d7ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1256124973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1256124973
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.796684505
Short name	T586
Test name
Test status
Simulation time	465887653 ps
CPU time	89.17 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:42:07 PM PDT 24
Peak memory	206904 kb
Host	smart-08cd4c3e-53c9-4c99-8f82-692a46f148a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796684505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand _reset.796684505
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2723018723
Short name	T98
Test name
Test status
Simulation time	729979855 ps
CPU time	87.41 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:41:51 PM PDT 24
Peak memory	204736 kb
Host	smart-43f98e5d-bbef-47ac-be85-c34e62c52fe7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2723018723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2723018723
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1507289512
Short name	T500
Test name
Test status
Simulation time	32162416 ps
CPU time	3.74 seconds
Started	Apr 18 12:40:24 PM PDT 24
Finished	Apr 18 12:40:28 PM PDT 24
Peak memory	201988 kb
Host	smart-7b5a0cf1-af28-4949-ba7c-3539a3b01095
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507289512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1507289512
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3345201115
Short name	T458
Test name
Test status
Simulation time	957227441 ps
CPU time	15.93 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	201948 kb
Host	smart-71c0480d-e9cb-4302-9669-3093e295a833
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345201115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3345201115
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2757480432
Short name	T62
Test name
Test status
Simulation time	73310458668 ps
CPU time	280.6 seconds
Started	Apr 18 12:40:27 PM PDT 24
Finished	Apr 18 12:45:08 PM PDT 24
Peak memory	204492 kb
Host	smart-805d74bd-e01c-4922-b5d2-0d941d147db8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2757480432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2757480432
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3432989986
Short name	T230
Test name
Test status
Simulation time	526700085 ps
CPU time	6.61 seconds
Started	Apr 18 12:40:36 PM PDT 24
Finished	Apr 18 12:40:43 PM PDT 24
Peak memory	201872 kb
Host	smart-5a0034a7-7bd6-4668-b4e1-cff2989c6dc6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432989986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3432989986
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.3548607252
Short name	T347
Test name
Test status
Simulation time	128497985 ps
CPU time	2.58 seconds
Started	Apr 18 12:40:18 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	201852 kb
Host	smart-44f55838-0e71-4e07-9c0c-29fa1cf39ce0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3548607252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3548607252
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.845317667
Short name	T803
Test name
Test status
Simulation time	53183508 ps
CPU time	5.34 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:40:43 PM PDT 24
Peak memory	202016 kb
Host	smart-f99778e7-104e-44e7-9f6e-b8e09cc3cddf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=845317667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.845317667
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3973685935
Short name	T596
Test name
Test status
Simulation time	22741708030 ps
CPU time	28.87 seconds
Started	Apr 18 12:40:35 PM PDT 24
Finished	Apr 18 12:41:05 PM PDT 24
Peak memory	202084 kb
Host	smart-55bd0ae3-592c-4003-942c-b08c8ba08bd6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973685935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3973685935
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3363826918
Short name	T495
Test name
Test status
Simulation time	7346996587 ps
CPU time	29.14 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:40:52 PM PDT 24
Peak memory	202084 kb
Host	smart-8d30568e-27bf-42af-9028-92499131fe6b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3363826918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3363826918
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.482588868
Short name	T24
Test name
Test status
Simulation time	19649188 ps
CPU time	2.42 seconds
Started	Apr 18 12:40:17 PM PDT 24
Finished	Apr 18 12:40:21 PM PDT 24
Peak memory	202020 kb
Host	smart-86d37f75-ec0c-4371-a5e1-0131fe0e15af
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482588868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.482588868
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.1177220155
Short name	T404
Test name
Test status
Simulation time	470552550 ps
CPU time	4.61 seconds
Started	Apr 18 12:40:34 PM PDT 24
Finished	Apr 18 12:40:40 PM PDT 24
Peak memory	201952 kb
Host	smart-c212bb1c-d07f-40bd-9ebd-38f10da6671d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1177220155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1177220155
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.941179957
Short name	T584
Test name
Test status
Simulation time	80380780 ps
CPU time	1.44 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	201892 kb
Host	smart-1a174124-1f87-431f-b5ae-2d2efdb0a117
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=941179957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.941179957
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3253956138
Short name	T70
Test name
Test status
Simulation time	1881580940 ps
CPU time	8.48 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:40:46 PM PDT 24
Peak memory	201888 kb
Host	smart-9dfccbe5-259c-4da7-98b7-ec6cc975bfb8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253956138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3253956138
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.877678796
Short name	T557
Test name
Test status
Simulation time	3232733644 ps
CPU time	8.78 seconds
Started	Apr 18 12:40:22 PM PDT 24
Finished	Apr 18 12:40:32 PM PDT 24
Peak memory	201992 kb
Host	smart-2864814f-7834-490d-952c-f066d5184c50
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=877678796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.877678796
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2332372790
Short name	T283
Test name
Test status
Simulation time	10577516 ps
CPU time	1.22 seconds
Started	Apr 18 12:40:25 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	202020 kb
Host	smart-0573d166-3d77-4330-9363-ef1656ce268d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332372790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2332372790
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.1256757294
Short name	T116
Test name
Test status
Simulation time	1232057966 ps
CPU time	15.66 seconds
Started	Apr 18 12:40:34 PM PDT 24
Finished	Apr 18 12:40:51 PM PDT 24
Peak memory	202016 kb
Host	smart-522d0690-0fa4-4adc-94c2-3139b66ad658
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1256757294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1256757294
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3440889053
Short name	T181
Test name
Test status
Simulation time	279875376 ps
CPU time	34.99 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:41:13 PM PDT 24
Peak memory	201876 kb
Host	smart-8db529b0-6b86-46b0-af9b-64bae82275f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440889053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3440889053
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1636997468
Short name	T883
Test name
Test status
Simulation time	2688809684 ps
CPU time	92.55 seconds
Started	Apr 18 12:40:35 PM PDT 24
Finished	Apr 18 12:42:09 PM PDT 24
Peak memory	204824 kb
Host	smart-329781ab-5524-434d-bb19-87b183e88e61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636997468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1636997468
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3283624135
Short name	T385
Test name
Test status
Simulation time	871644431 ps
CPU time	121.34 seconds
Started	Apr 18 12:40:33 PM PDT 24
Finished	Apr 18 12:42:35 PM PDT 24
Peak memory	205932 kb
Host	smart-c1824083-83c9-4a2b-bef5-4a2741a02504
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3283624135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3283624135
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3036087069
Short name	T635
Test name
Test status
Simulation time	64687030 ps
CPU time	6.16 seconds
Started	Apr 18 12:40:42 PM PDT 24
Finished	Apr 18 12:40:48 PM PDT 24
Peak memory	201948 kb
Host	smart-2f6e8a1f-11d8-4c2f-9298-5b7d14ab2c8c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036087069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3036087069
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3508461582
Short name	T80
Test name
Test status
Simulation time	268010915 ps
CPU time	3.85 seconds
Started	Apr 18 12:40:46 PM PDT 24
Finished	Apr 18 12:40:51 PM PDT 24
Peak memory	201880 kb
Host	smart-d5d07061-3fa4-4072-b7f9-40929f972234
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3508461582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3508461582
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1454656141
Short name	T799
Test name
Test status
Simulation time	27931273761 ps
CPU time	174.69 seconds
Started	Apr 18 12:40:42 PM PDT 24
Finished	Apr 18 12:43:38 PM PDT 24
Peak memory	204124 kb
Host	smart-520dc49f-86ed-40c8-88b7-008e4a50f6d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1454656141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1454656141
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1198809277
Short name	T419
Test name
Test status
Simulation time	70356926 ps
CPU time	3.19 seconds
Started	Apr 18 12:40:33 PM PDT 24
Finished	Apr 18 12:40:38 PM PDT 24
Peak memory	201940 kb
Host	smart-eff4e2ec-d3d6-499e-a0c8-3ad9ab15ac31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198809277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1198809277
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3470517494
Short name	T771
Test name
Test status
Simulation time	603142300 ps
CPU time	6.02 seconds
Started	Apr 18 12:40:35 PM PDT 24
Finished	Apr 18 12:40:42 PM PDT 24
Peak memory	201948 kb
Host	smart-c0591271-07fc-4060-b019-5a7b624438e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3470517494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3470517494
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.3671695225
Short name	T37
Test name
Test status
Simulation time	1164100076 ps
CPU time	6.95 seconds
Started	Apr 18 12:40:28 PM PDT 24
Finished	Apr 18 12:40:36 PM PDT 24
Peak memory	201908 kb
Host	smart-dccfbb82-69e6-441e-93b2-a3bb70a08dbc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3671695225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3671695225
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.216433665
Short name	T627
Test name
Test status
Simulation time	305039200626 ps
CPU time	171.4 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:43:29 PM PDT 24
Peak memory	202120 kb
Host	smart-d540f3bb-0208-4665-a235-24dd2413fd00
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=216433665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.216433665
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3128612175
Short name	T792
Test name
Test status
Simulation time	26799449774 ps
CPU time	110.86 seconds
Started	Apr 18 12:40:38 PM PDT 24
Finished	Apr 18 12:42:30 PM PDT 24
Peak memory	202056 kb
Host	smart-db75e23b-882c-4c24-9c63-bdf9cde0b848
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3128612175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3128612175
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3133964480
Short name	T769
Test name
Test status
Simulation time	114405863 ps
CPU time	6.21 seconds
Started	Apr 18 12:40:29 PM PDT 24
Finished	Apr 18 12:40:36 PM PDT 24
Peak memory	202036 kb
Host	smart-061092c5-290f-4ccb-8509-cb2bf10993c1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133964480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3133964480
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.4281991915
Short name	T651
Test name
Test status
Simulation time	375297822 ps
CPU time	4.62 seconds
Started	Apr 18 12:40:40 PM PDT 24
Finished	Apr 18 12:40:45 PM PDT 24
Peak memory	201900 kb
Host	smart-64a8fb85-2e63-48b8-8407-df5c3551ba40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4281991915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4281991915
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.11049282
Short name	T401
Test name
Test status
Simulation time	83657910 ps
CPU time	1.48 seconds
Started	Apr 18 12:40:32 PM PDT 24
Finished	Apr 18 12:40:34 PM PDT 24
Peak memory	202016 kb
Host	smart-356034b0-ff89-4be0-b5d4-128f445abc77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=11049282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.11049282
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2422598539
Short name	T411
Test name
Test status
Simulation time	3073591657 ps
CPU time	9.55 seconds
Started	Apr 18 12:40:37 PM PDT 24
Finished	Apr 18 12:40:47 PM PDT 24
Peak memory	202116 kb
Host	smart-7610a513-81f5-48c2-8422-2770afcd3959
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422598539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2422598539
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.172325741
Short name	T805
Test name
Test status
Simulation time	1635507414 ps
CPU time	9.17 seconds
Started	Apr 18 12:40:47 PM PDT 24
Finished	Apr 18 12:40:57 PM PDT 24
Peak memory	201984 kb
Host	smart-5f540c9c-9d03-4d7b-9b57-08c014c3552a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=172325741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.172325741
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4036781727
Short name	T623
Test name
Test status
Simulation time	8121257 ps
CPU time	1.05 seconds
Started	Apr 18 12:40:35 PM PDT 24
Finished	Apr 18 12:40:37 PM PDT 24
Peak memory	202020 kb
Host	smart-21a499e8-10e2-4000-9e16-7b6b2cd8b4bc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036781727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4036781727
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.114356799
Short name	T103
Test name
Test status
Simulation time	3290457387 ps
CPU time	55.01 seconds
Started	Apr 18 12:40:42 PM PDT 24
Finished	Apr 18 12:41:37 PM PDT 24
Peak memory	204040 kb
Host	smart-3e8593fe-c3fc-4203-9667-b48909c68008
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=114356799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.114356799
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4203956466
Short name	T704
Test name
Test status
Simulation time	901706381 ps
CPU time	42.74 seconds
Started	Apr 18 12:40:41 PM PDT 24
Finished	Apr 18 12:41:24 PM PDT 24
Peak memory	201888 kb
Host	smart-201d5aa4-1a62-4702-9ae1-9241d6de6f9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203956466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4203956466
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3109489157
Short name	T8
Test name
Test status
Simulation time	652359691 ps
CPU time	76.03 seconds
Started	Apr 18 12:40:31 PM PDT 24
Finished	Apr 18 12:41:48 PM PDT 24
Peak memory	204588 kb
Host	smart-91b8aa7d-7b5b-4313-b925-537937bff060
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109489157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3109489157
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.751267740
Short name	T839
Test name
Test status
Simulation time	244797242 ps
CPU time	22.03 seconds
Started	Apr 18 12:40:38 PM PDT 24
Finished	Apr 18 12:41:01 PM PDT 24
Peak memory	203956 kb
Host	smart-688b2901-890c-4f6c-be38-2d0d2b8e9d31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=751267740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.751267740
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.830160675
Short name	T598
Test name
Test status
Simulation time	14644668 ps
CPU time	1.47 seconds
Started	Apr 18 12:40:34 PM PDT 24
Finished	Apr 18 12:40:37 PM PDT 24
Peak memory	202012 kb
Host	smart-274962b2-0588-4cef-ba63-289de9f012fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830160675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.830160675
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1344127680
Short name	T244
Test name
Test status
Simulation time	322281826 ps
CPU time	9.89 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	202012 kb
Host	smart-83a3992a-942a-43a1-9a27-ba74d225e005
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1344127680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1344127680
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3980113083
Short name	T487
Test name
Test status
Simulation time	22854866555 ps
CPU time	175.6 seconds
Started	Apr 18 12:38:32 PM PDT 24
Finished	Apr 18 12:41:28 PM PDT 24
Peak memory	203060 kb
Host	smart-990b8d53-12b3-4a4d-af0b-4a45bf22a118
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3980113083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3980113083
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3275265078
Short name	T798
Test name
Test status
Simulation time	140767968 ps
CPU time	2.21 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:37 PM PDT 24
Peak memory	202012 kb
Host	smart-dea58c3d-e22f-411f-982d-978d7b227197
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3275265078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3275265078
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.4058047392
Short name	T874
Test name
Test status
Simulation time	826231924 ps
CPU time	11.87 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:46 PM PDT 24
Peak memory	201924 kb
Host	smart-9edab491-5b4e-4da2-be47-b401777856df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4058047392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4058047392
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.2054063406
Short name	T119
Test name
Test status
Simulation time	331536606 ps
CPU time	2.73 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	201936 kb
Host	smart-50fd194e-9005-4ec3-a432-d6a61afc0547
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2054063406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2054063406
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3033335446
Short name	T506
Test name
Test status
Simulation time	58165822775 ps
CPU time	102.39 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:40:19 PM PDT 24
Peak memory	202012 kb
Host	smart-7b677b23-a72a-4446-9af8-e959f8cf5535
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033335446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3033335446
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3491458242
Short name	T736
Test name
Test status
Simulation time	32543293205 ps
CPU time	70.54 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	201924 kb
Host	smart-11464ef7-94ea-4ab7-830e-e858de11a290
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3491458242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3491458242
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.766727174
Short name	T540
Test name
Test status
Simulation time	51160406 ps
CPU time	6.66 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	201960 kb
Host	smart-43c00501-3825-4098-812f-67eb9865d3e4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766727174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.766727174
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2751269354
Short name	T887
Test name
Test status
Simulation time	327916317 ps
CPU time	3.32 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	202004 kb
Host	smart-0430d752-78b9-456c-ad1f-3aa42ab44213
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751269354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2751269354
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.557829682
Short name	T595
Test name
Test status
Simulation time	21469346 ps
CPU time	1.26 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:36 PM PDT 24
Peak memory	201892 kb
Host	smart-524f3110-cb72-4c82-a381-b34da86e7cb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=557829682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.557829682
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2300257852
Short name	T846
Test name
Test status
Simulation time	4051308062 ps
CPU time	6.4 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:40 PM PDT 24
Peak memory	201992 kb
Host	smart-17b0acf4-d74e-4af8-9589-f908d3d52a6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300257852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2300257852
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2473244071
Short name	T201
Test name
Test status
Simulation time	717447652 ps
CPU time	6.11 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	201944 kb
Host	smart-8cf91de4-b7eb-40db-b27b-cbd079c10c32
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2473244071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2473244071
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3052704568
Short name	T77
Test name
Test status
Simulation time	8123177 ps
CPU time	1.05 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:35 PM PDT 24
Peak memory	202004 kb
Host	smart-06f54b51-c1a5-43e8-a873-17fdb23f4f26
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052704568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3052704568
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.874102204
Short name	T133
Test name
Test status
Simulation time	241097183 ps
CPU time	24.99 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:59 PM PDT 24
Peak memory	201992 kb
Host	smart-ec29adad-a9c4-4883-815e-d7653df56dd2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874102204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.874102204
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2665684649
Short name	T727
Test name
Test status
Simulation time	3696897356 ps
CPU time	39.83 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	201928 kb
Host	smart-3f602194-f81b-4baa-a216-d36cc6afc4dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665684649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2665684649
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.306053110
Short name	T361
Test name
Test status
Simulation time	7760202344 ps
CPU time	54.1 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:39:31 PM PDT 24
Peak memory	203140 kb
Host	smart-438626ce-a1c2-46dd-acab-98f1d2f90698
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=306053110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_ reset.306053110
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1844878324
Short name	T169
Test name
Test status
Simulation time	331865458 ps
CPU time	71.29 seconds
Started	Apr 18 12:38:32 PM PDT 24
Finished	Apr 18 12:39:44 PM PDT 24
Peak memory	204780 kb
Host	smart-fb1fc259-2f06-471a-b751-2c7db054a285
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844878324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1844878324
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3642790896
Short name	T713
Test name
Test status
Simulation time	32438648 ps
CPU time	3.2 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:38:39 PM PDT 24
Peak memory	201896 kb
Host	smart-8bbb5a07-f7f2-4785-a9d1-d1fbf75338e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3642790896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3642790896
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.938061613
Short name	T490
Test name
Test status
Simulation time	86894648 ps
CPU time	10.34 seconds
Started	Apr 18 12:38:33 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	201980 kb
Host	smart-7b58a8b4-c873-4f92-a48d-baedfa883a67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=938061613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.938061613
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2555527554
Short name	T465
Test name
Test status
Simulation time	30026863411 ps
CPU time	176.62 seconds
Started	Apr 18 12:38:32 PM PDT 24
Finished	Apr 18 12:41:30 PM PDT 24
Peak memory	203220 kb
Host	smart-e3474a3d-9114-4a1d-bb56-5575f9ea518d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2555527554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.2555527554
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.924269514
Short name	T514
Test name
Test status
Simulation time	68160665 ps
CPU time	5.64 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:38:58 PM PDT 24
Peak memory	202008 kb
Host	smart-846c3ede-414f-4350-98a2-483a88440e33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=924269514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.924269514
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.165495180
Short name	T118
Test name
Test status
Simulation time	100622044 ps
CPU time	9.17 seconds
Started	Apr 18 12:38:35 PM PDT 24
Finished	Apr 18 12:38:46 PM PDT 24
Peak memory	201908 kb
Host	smart-1c471290-722e-4786-99e3-8b40d723ed74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=165495180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.165495180
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.3572028464
Short name	T467
Test name
Test status
Simulation time	747891151 ps
CPU time	12.61 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:38:49 PM PDT 24
Peak memory	201952 kb
Host	smart-73df2215-75f6-4b27-b109-4357f9b731a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3572028464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3572028464
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1235767225
Short name	T625
Test name
Test status
Simulation time	46256065696 ps
CPU time	132.42 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:40:49 PM PDT 24
Peak memory	201948 kb
Host	smart-91cc926e-9955-4d62-83b0-ef8f0db7fa8c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235767225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1235767225
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1790603106
Short name	T622
Test name
Test status
Simulation time	6630788855 ps
CPU time	9.17 seconds
Started	Apr 18 12:38:37 PM PDT 24
Finished	Apr 18 12:38:48 PM PDT 24
Peak memory	202012 kb
Host	smart-d500ef5d-624f-45e0-a7e2-d2b8c99c0e55
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1790603106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1790603106
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1765676572
Short name	T562
Test name
Test status
Simulation time	40469808 ps
CPU time	6.39 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	202020 kb
Host	smart-52f6618c-7675-479a-874e-4617a68a4a77
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765676572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1765676572
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.3961084572
Short name	T425
Test name
Test status
Simulation time	308645078 ps
CPU time	5.51 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:41 PM PDT 24
Peak memory	201920 kb
Host	smart-11a95b0e-3702-47b9-8ef1-870c8b6974ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961084572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3961084572
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.3041034609
Short name	T60
Test name
Test status
Simulation time	62392075 ps
CPU time	1.59 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:37 PM PDT 24
Peak memory	202020 kb
Host	smart-ba82819f-a0b5-4877-b331-338eefa5c973
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3041034609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3041034609
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3841520069
Short name	T135
Test name
Test status
Simulation time	2151180810 ps
CPU time	6.74 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	201936 kb
Host	smart-16cc98b8-ab11-47ab-8283-8d0748524ecb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841520069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3841520069
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1870503904
Short name	T676
Test name
Test status
Simulation time	2908994628 ps
CPU time	14.56 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:50 PM PDT 24
Peak memory	202000 kb
Host	smart-a3020481-e20d-4063-aa27-7307ecf0bb6a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1870503904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1870503904
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1422199164
Short name	T122
Test name
Test status
Simulation time	10382131 ps
CPU time	1.2 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:37 PM PDT 24
Peak memory	201920 kb
Host	smart-152837fd-debc-4e2d-8972-bb0fbb2bda0a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422199164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1422199164
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.3237985471
Short name	T567
Test name
Test status
Simulation time	5070652136 ps
CPU time	73.2 seconds
Started	Apr 18 12:38:41 PM PDT 24
Finished	Apr 18 12:39:55 PM PDT 24
Peak memory	203352 kb
Host	smart-ca446249-64d8-4997-a373-bdf12ba0000a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3237985471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3237985471
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2471821994
Short name	T835
Test name
Test status
Simulation time	2744416822 ps
CPU time	35.33 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:39:24 PM PDT 24
Peak memory	201912 kb
Host	smart-c655bca9-19fd-44df-ba4d-d1d59633b501
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2471821994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2471821994
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2581311101
Short name	T715
Test name
Test status
Simulation time	3396048443 ps
CPU time	158.26 seconds
Started	Apr 18 12:38:49 PM PDT 24
Finished	Apr 18 12:41:28 PM PDT 24
Peak memory	205844 kb
Host	smart-daee492c-4f25-4643-9e76-bafa335a263f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581311101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.2581311101
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3410021877
Short name	T422
Test name
Test status
Simulation time	138994640 ps
CPU time	6.71 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:38:46 PM PDT 24
Peak memory	202000 kb
Host	smart-d408ab6c-b27d-422b-bde4-0f6b9b9df730
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3410021877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.3410021877
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.4193429163
Short name	T580
Test name
Test status
Simulation time	465880380 ps
CPU time	10.1 seconds
Started	Apr 18 12:38:34 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	201976 kb
Host	smart-65eb56da-7f90-4ba0-874e-8880c907bdb6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4193429163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.4193429163
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2475151308
Short name	T376
Test name
Test status
Simulation time	34670424 ps
CPU time	3.47 seconds
Started	Apr 18 12:38:44 PM PDT 24
Finished	Apr 18 12:38:48 PM PDT 24
Peak memory	201888 kb
Host	smart-94797a8d-1049-4027-8684-366d0eaf0938
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475151308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2475151308
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2258412952
Short name	T445
Test name
Test status
Simulation time	270445645140 ps
CPU time	378.03 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:44:57 PM PDT 24
Peak memory	203732 kb
Host	smart-1f28431c-f081-4f8a-8b77-09d4827835de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2258412952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2258412952
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.371923982
Short name	T211
Test name
Test status
Simulation time	486729164 ps
CPU time	8.68 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:38:48 PM PDT 24
Peak memory	201972 kb
Host	smart-f55f7a21-5243-4eae-8ae3-7932174cf1ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371923982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.371923982
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.1884522725
Short name	T447
Test name
Test status
Simulation time	75991109 ps
CPU time	1.67 seconds
Started	Apr 18 12:38:36 PM PDT 24
Finished	Apr 18 12:38:38 PM PDT 24
Peak memory	201948 kb
Host	smart-3387335e-32a9-4131-8928-21ff6e8dfc2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884522725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1884522725
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.3362461314
Short name	T709
Test name
Test status
Simulation time	62218986 ps
CPU time	5.85 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:38:59 PM PDT 24
Peak memory	201992 kb
Host	smart-bfa2d16c-59c3-4e27-af3f-c7c3916e2fc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3362461314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3362461314
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.689259442
Short name	T442
Test name
Test status
Simulation time	34282968462 ps
CPU time	152.96 seconds
Started	Apr 18 12:38:40 PM PDT 24
Finished	Apr 18 12:41:14 PM PDT 24
Peak memory	202328 kb
Host	smart-40dafa36-a876-4b4a-a6fc-49d2fbf2875f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=689259442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.689259442
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.341941065
Short name	T55
Test name
Test status
Simulation time	15503202660 ps
CPU time	121.59 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:40:58 PM PDT 24
Peak memory	201984 kb
Host	smart-dcbc69c8-1264-4ad8-be61-c3973f9df6d6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=341941065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.341941065
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1923108622
Short name	T787
Test name
Test status
Simulation time	154536482 ps
CPU time	3.9 seconds
Started	Apr 18 12:38:46 PM PDT 24
Finished	Apr 18 12:38:51 PM PDT 24
Peak memory	202032 kb
Host	smart-4c407935-d1e8-4d23-9fc8-6236d7c88264
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923108622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1923108622
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.665077933
Short name	T546
Test name
Test status
Simulation time	40031636 ps
CPU time	3.78 seconds
Started	Apr 18 12:38:52 PM PDT 24
Finished	Apr 18 12:38:57 PM PDT 24
Peak memory	202000 kb
Host	smart-3ea9339e-450c-4dfa-92fc-2d919c48d5cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=665077933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.665077933
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.4043618681
Short name	T684
Test name
Test status
Simulation time	188911436 ps
CPU time	1.41 seconds
Started	Apr 18 12:38:43 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	201912 kb
Host	smart-048f8b60-4b92-4167-a1af-da37b76b39c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4043618681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4043618681
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2922938819
Short name	T783
Test name
Test status
Simulation time	2377328141 ps
CPU time	7.87 seconds
Started	Apr 18 12:38:39 PM PDT 24
Finished	Apr 18 12:38:48 PM PDT 24
Peak memory	202044 kb
Host	smart-00248a24-a22d-41ed-aec4-9b387e100718
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922938819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2922938819
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3673909739
Short name	T553
Test name
Test status
Simulation time	1405596168 ps
CPU time	10 seconds
Started	Apr 18 12:38:43 PM PDT 24
Finished	Apr 18 12:38:53 PM PDT 24
Peak memory	201860 kb
Host	smart-8ea3af56-fafc-45cb-9267-204f5979198f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3673909739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3673909739
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.4262846181
Short name	T124
Test name
Test status
Simulation time	8505731 ps
CPU time	1.08 seconds
Started	Apr 18 12:38:40 PM PDT 24
Finished	Apr 18 12:38:42 PM PDT 24
Peak memory	201856 kb
Host	smart-0f03dcb9-852d-4ca1-a492-074513648606
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262846181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4262846181
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.2712558932
Short name	T621
Test name
Test status
Simulation time	2527690677 ps
CPU time	26.73 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:39:19 PM PDT 24
Peak memory	202996 kb
Host	smart-ecab07a8-27de-4d48-a606-a01c06850308
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2712558932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2712558932
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2441802283
Short name	T842
Test name
Test status
Simulation time	146551917 ps
CPU time	19 seconds
Started	Apr 18 12:38:50 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	202016 kb
Host	smart-18142742-a1e8-4f87-ba3c-4198786c17d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2441802283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2441802283
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.4168116155
Short name	T674
Test name
Test status
Simulation time	8798243101 ps
CPU time	92.54 seconds
Started	Apr 18 12:38:37 PM PDT 24
Finished	Apr 18 12:40:11 PM PDT 24
Peak memory	204624 kb
Host	smart-013ef9d8-3934-4917-bce5-2fbc7bb5afc3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168116155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.4168116155
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4145619057
Short name	T496
Test name
Test status
Simulation time	828684185 ps
CPU time	91.89 seconds
Started	Apr 18 12:38:49 PM PDT 24
Finished	Apr 18 12:40:22 PM PDT 24
Peak memory	205968 kb
Host	smart-fad270c3-5cc9-4876-83f2-e851912e8135
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145619057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.4145619057
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2377122712
Short name	T767
Test name
Test status
Simulation time	1547011596 ps
CPU time	7.82 seconds
Started	Apr 18 12:38:45 PM PDT 24
Finished	Apr 18 12:38:54 PM PDT 24
Peak memory	201920 kb
Host	smart-a55fd2c1-b10d-48b0-8861-37493eea6815
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377122712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2377122712
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1160438942
Short name	T559
Test name
Test status
Simulation time	169309697 ps
CPU time	4.2 seconds
Started	Apr 18 12:38:58 PM PDT 24
Finished	Apr 18 12:39:03 PM PDT 24
Peak memory	201984 kb
Host	smart-3aa479a3-4f1e-4965-b0ab-661958df877d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1160438942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1160438942
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1506694960
Short name	T152
Test name
Test status
Simulation time	44498880387 ps
CPU time	276.43 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:43:28 PM PDT 24
Peak memory	203012 kb
Host	smart-10016858-3983-410c-8bae-33f5902d692b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1506694960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.1506694960
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1152785807
Short name	T663
Test name
Test status
Simulation time	98624550 ps
CPU time	5.45 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:38:52 PM PDT 24
Peak memory	201900 kb
Host	smart-2b0b7043-c417-42b7-a3cc-62e2f87df2c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152785807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1152785807
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.2834799972
Short name	T209
Test name
Test status
Simulation time	595435371 ps
CPU time	8.64 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:09 PM PDT 24
Peak memory	201924 kb
Host	smart-2df58190-c60d-4758-9047-3165ef9ed292
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834799972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2834799972
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.2401935599
Short name	T57
Test name
Test status
Simulation time	1325745277 ps
CPU time	11.53 seconds
Started	Apr 18 12:38:58 PM PDT 24
Finished	Apr 18 12:39:10 PM PDT 24
Peak memory	201992 kb
Host	smart-b7317c93-43bb-4c8f-94d3-5bf4a0b81a5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401935599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2401935599
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1924824032
Short name	T261
Test name
Test status
Simulation time	23756427595 ps
CPU time	80.43 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:40:12 PM PDT 24
Peak memory	202000 kb
Host	smart-536d832c-4616-4ee8-8a80-669340766ca7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924824032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1924824032
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1116957240
Short name	T455
Test name
Test status
Simulation time	143122860288 ps
CPU time	112.48 seconds
Started	Apr 18 12:38:42 PM PDT 24
Finished	Apr 18 12:40:35 PM PDT 24
Peak memory	201972 kb
Host	smart-b3357ca3-83cb-4b31-895f-b47d9cdbb45d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1116957240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1116957240
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1686659773
Short name	T459
Test name
Test status
Simulation time	78996560 ps
CPU time	5.61 seconds
Started	Apr 18 12:38:37 PM PDT 24
Finished	Apr 18 12:38:44 PM PDT 24
Peak memory	201912 kb
Host	smart-c3775bfd-b263-48de-9b85-5dc14fdf353e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686659773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1686659773
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.1118730493
Short name	T812
Test name
Test status
Simulation time	4316761312 ps
CPU time	6.92 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	202064 kb
Host	smart-a49b94b5-193c-4ac4-b7be-66f14bce32bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1118730493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1118730493
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.1089114107
Short name	T472
Test name
Test status
Simulation time	84905626 ps
CPU time	1.58 seconds
Started	Apr 18 12:38:43 PM PDT 24
Finished	Apr 18 12:38:45 PM PDT 24
Peak memory	201828 kb
Host	smart-d993c725-8794-4dd3-884a-8c6b1078131e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089114107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1089114107
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.599645781
Short name	T29
Test name
Test status
Simulation time	4472218657 ps
CPU time	6.72 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:38:55 PM PDT 24
Peak memory	202324 kb
Host	smart-ef72cb19-a98d-46d7-ae1a-a6abcccc1b28
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=599645781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.599645781
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3855562512
Short name	T566
Test name
Test status
Simulation time	1406368482 ps
CPU time	4.9 seconds
Started	Apr 18 12:38:41 PM PDT 24
Finished	Apr 18 12:38:46 PM PDT 24
Peak memory	202028 kb
Host	smart-f71b5c23-18ca-4175-b5b9-1a42cd058338
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3855562512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3855562512
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1524571573
Short name	T393
Test name
Test status
Simulation time	9196043 ps
CPU time	1.26 seconds
Started	Apr 18 12:38:48 PM PDT 24
Finished	Apr 18 12:38:50 PM PDT 24
Peak memory	202012 kb
Host	smart-5ad578c8-d0ed-428a-a205-5118cbd8fdb3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524571573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1524571573
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.4150805744
Short name	T102
Test name
Test status
Simulation time	3517423943 ps
CPU time	39.17 seconds
Started	Apr 18 12:39:00 PM PDT 24
Finished	Apr 18 12:39:40 PM PDT 24
Peak memory	203000 kb
Host	smart-5c187613-f6fe-478b-9b4e-025bd41ff79f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4150805744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4150805744
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2854957905
Short name	T267
Test name
Test status
Simulation time	203716637 ps
CPU time	14.2 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:14 PM PDT 24
Peak memory	202008 kb
Host	smart-38d38f0f-4851-4825-bc8c-406c94aac5d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854957905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2854957905
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2602395541
Short name	T698
Test name
Test status
Simulation time	1971399450 ps
CPU time	101.2 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:40:33 PM PDT 24
Peak memory	204620 kb
Host	smart-7c40b433-fbcd-4e95-a1d2-afcac24a5315
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2602395541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2602395541
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2806740012
Short name	T175
Test name
Test status
Simulation time	523964632 ps
CPU time	26.76 seconds
Started	Apr 18 12:38:45 PM PDT 24
Finished	Apr 18 12:39:12 PM PDT 24
Peak memory	203584 kb
Host	smart-eb168267-b354-4c32-bf03-c34ef311ed06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2806740012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2806740012
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2214253761
Short name	T137
Test name
Test status
Simulation time	89623129 ps
CPU time	7.54 seconds
Started	Apr 18 12:39:08 PM PDT 24
Finished	Apr 18 12:39:17 PM PDT 24
Peak memory	201924 kb
Host	smart-04c9777f-be98-4f0c-a0df-5447422a1257
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2214253761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2214253761
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2835772981
Short name	T791
Test name
Test status
Simulation time	1323498990 ps
CPU time	7.62 seconds
Started	Apr 18 12:38:55 PM PDT 24
Finished	Apr 18 12:39:04 PM PDT 24
Peak memory	202272 kb
Host	smart-18aba586-41cd-47d3-bca8-3136706d9023
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2835772981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2835772981
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3450706404
Short name	T65
Test name
Test status
Simulation time	43602200126 ps
CPU time	218.74 seconds
Started	Apr 18 12:39:14 PM PDT 24
Finished	Apr 18 12:42:55 PM PDT 24
Peak memory	203096 kb
Host	smart-31fd9a49-611b-48f9-98d3-2517ebe1b347
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3450706404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.3450706404
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1789200557
Short name	T372
Test name
Test status
Simulation time	35844058 ps
CPU time	3.83 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:38:55 PM PDT 24
Peak memory	202016 kb
Host	smart-27160055-78b9-4389-8197-f606114896c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789200557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1789200557
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.2127297208
Short name	T396
Test name
Test status
Simulation time	27825447 ps
CPU time	2.16 seconds
Started	Apr 18 12:39:18 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	201904 kb
Host	smart-4d4dc07c-82a4-4272-ad8d-6420e52e3497
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2127297208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2127297208
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.1555944806
Short name	T881
Test name
Test status
Simulation time	43153049 ps
CPU time	3.5 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:38:43 PM PDT 24
Peak memory	201940 kb
Host	smart-db813d03-1e4a-4c3a-9ed4-79375a87e803
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555944806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1555944806
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1689469247
Short name	T238
Test name
Test status
Simulation time	13630249929 ps
CPU time	54.56 seconds
Started	Apr 18 12:38:54 PM PDT 24
Finished	Apr 18 12:39:49 PM PDT 24
Peak memory	202084 kb
Host	smart-a5989e86-995b-4255-9639-2f23572171da
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689469247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1689469247
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2405841545
Short name	T289
Test name
Test status
Simulation time	14088087684 ps
CPU time	88.13 seconds
Started	Apr 18 12:38:49 PM PDT 24
Finished	Apr 18 12:40:18 PM PDT 24
Peak memory	201936 kb
Host	smart-fa9dc721-9b07-4bb6-bd98-b71420537f18
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2405841545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2405841545
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3373706902
Short name	T260
Test name
Test status
Simulation time	13142273 ps
CPU time	1.38 seconds
Started	Apr 18 12:38:50 PM PDT 24
Finished	Apr 18 12:38:53 PM PDT 24
Peak memory	201920 kb
Host	smart-8c7cafcf-6d59-49b2-8ae5-2f741064b516
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373706902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3373706902
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.2701479185
Short name	T216
Test name
Test status
Simulation time	998928264 ps
CPU time	12.64 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:39:00 PM PDT 24
Peak memory	202004 kb
Host	smart-777bdd7c-3388-4201-bbe2-bd4adb4f68d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2701479185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2701479185
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.3145233477
Short name	T189
Test name
Test status
Simulation time	36747011 ps
CPU time	1.44 seconds
Started	Apr 18 12:38:53 PM PDT 24
Finished	Apr 18 12:38:55 PM PDT 24
Peak memory	201908 kb
Host	smart-f21d0483-76a8-4bb8-ae63-15547a258588
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3145233477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3145233477
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1465411959
Short name	T631
Test name
Test status
Simulation time	1899120148 ps
CPU time	10.21 seconds
Started	Apr 18 12:38:51 PM PDT 24
Finished	Apr 18 12:39:02 PM PDT 24
Peak memory	201940 kb
Host	smart-91a532f6-9342-4c41-8c2b-2d012e03d90c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465411959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1465411959
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.938296579
Short name	T71
Test name
Test status
Simulation time	916509718 ps
CPU time	7.08 seconds
Started	Apr 18 12:38:46 PM PDT 24
Finished	Apr 18 12:38:53 PM PDT 24
Peak memory	201936 kb
Host	smart-3db05a9a-114b-40e7-a5dd-fce609b0d96e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=938296579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.938296579
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.122310416
Short name	T615
Test name
Test status
Simulation time	27228909 ps
CPU time	1.12 seconds
Started	Apr 18 12:38:38 PM PDT 24
Finished	Apr 18 12:38:40 PM PDT 24
Peak memory	202008 kb
Host	smart-42b528ee-223b-4730-9f98-c85cf50bec68
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122310416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.122310416
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.2171416676
Short name	T140
Test name
Test status
Simulation time	1057981995 ps
CPU time	13.32 seconds
Started	Apr 18 12:38:53 PM PDT 24
Finished	Apr 18 12:39:08 PM PDT 24
Peak memory	201920 kb
Host	smart-2b68c93f-e02d-4fe7-a3ad-afd0734b6b25
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2171416676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2171416676
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.221545044
Short name	T741
Test name
Test status
Simulation time	40565413492 ps
CPU time	95.9 seconds
Started	Apr 18 12:38:50 PM PDT 24
Finished	Apr 18 12:40:27 PM PDT 24
Peak memory	204336 kb
Host	smart-7a1b6030-b5c8-4000-8530-63e3c03a927b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=221545044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.221545044
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.4088147371
Short name	T294
Test name
Test status
Simulation time	184307956 ps
CPU time	23.58 seconds
Started	Apr 18 12:38:56 PM PDT 24
Finished	Apr 18 12:39:21 PM PDT 24
Peak memory	202936 kb
Host	smart-43f3a44f-7740-4c50-ad24-0632599a8c30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4088147371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.4088147371
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1013134623
Short name	T630
Test name
Test status
Simulation time	553136869 ps
CPU time	36.19 seconds
Started	Apr 18 12:38:59 PM PDT 24
Finished	Apr 18 12:39:36 PM PDT 24
Peak memory	203560 kb
Host	smart-8d18d4bf-528e-4572-ba6d-a395c3387644
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013134623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1013134623
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3007196002
Short name	T585
Test name
Test status
Simulation time	368224817 ps
CPU time	6.72 seconds
Started	Apr 18 12:38:47 PM PDT 24
Finished	Apr 18 12:38:54 PM PDT 24
Peak memory	202012 kb
Host	smart-779821a1-ae20-4b4a-97fb-187ac345f5e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3007196002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3007196002
Directory	/workspace/9.xbar_unmapped_addr/latest