Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 394 1 T1 7 T4 1 T5 5
all_values[1] 422 1 T1 6 T3 1 T5 1
all_values[2] 419 1 T1 9 T5 7 T20 1
all_values[3] 404 1 T1 8 T5 3 T19 1
all_values[4] 450 1 T1 6 T5 1 T19 1
all_values[5] 421 1 T1 3 T3 1 T15 1
all_values[6] 409 1 T1 7 T3 1 T4 1
all_values[7] 438 1 T1 9 T5 3 T20 7
all_values[8] 411 1 T1 4 T5 5 T20 1
all_values[9] 409 1 T1 7 T3 1 T4 1
all_values[10] 453 1 T1 2 T3 1 T4 1
all_values[11] 445 1 T1 9 T3 1 T5 8
all_values[12] 428 1 T1 4 T3 1 T5 5
all_values[13] 435 1 T1 11 T3 1 T5 4
all_values[14] 445 1 T1 8 T3 1 T5 3
all_values[15] 434 1 T1 8 T4 1 T5 3
all_values[16] 409 1 T1 5 T5 3 T19 1
all_values[17] 424 1 T1 3 T5 4 T15 2
all_values[18] 421 1 T1 3 T3 3 T5 3
all_values[19] 424 1 T1 6 T5 3 T15 1
all_values[20] 473 1 T1 12 T4 1 T5 2
all_values[21] 424 1 T1 2 T5 4 T15 2
all_values[22] 465 1 T1 6 T3 1 T5 6
all_values[23] 409 1 T1 8 T5 1 T20 2
all_values[24] 415 1 T1 4 T4 2 T5 1
all_values[25] 429 1 T1 2 T3 3 T5 6
all_values[26] 420 1 T1 4 T5 2 T15 3

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