Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.20 100.00 95.23 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T760 /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2307905315 Apr 21 12:29:17 PM PDT 24 Apr 21 12:29:18 PM PDT 24 9336855 ps
T761 /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1313146667 Apr 21 12:30:53 PM PDT 24 Apr 21 12:31:02 PM PDT 24 1972959089 ps
T762 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3285325204 Apr 21 12:29:19 PM PDT 24 Apr 21 12:34:25 PM PDT 24 39074279789 ps
T763 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4237555938 Apr 21 12:30:24 PM PDT 24 Apr 21 12:30:27 PM PDT 24 24355802 ps
T764 /workspace/coverage/xbar_build_mode/38.xbar_error_random.2013879855 Apr 21 12:30:23 PM PDT 24 Apr 21 12:30:32 PM PDT 24 1043565395 ps
T765 /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1920848439 Apr 21 12:28:42 PM PDT 24 Apr 21 12:28:44 PM PDT 24 15225266 ps
T766 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3569118223 Apr 21 12:31:01 PM PDT 24 Apr 21 12:31:37 PM PDT 24 1044494798 ps
T767 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.502291843 Apr 21 12:29:06 PM PDT 24 Apr 21 12:29:42 PM PDT 24 261730728 ps
T768 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2989635624 Apr 21 12:30:42 PM PDT 24 Apr 21 12:33:10 PM PDT 24 29747480122 ps
T769 /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2869512651 Apr 21 12:30:28 PM PDT 24 Apr 21 12:30:31 PM PDT 24 42006573 ps
T770 /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2130578586 Apr 21 12:30:29 PM PDT 24 Apr 21 12:30:34 PM PDT 24 59722454 ps
T771 /workspace/coverage/xbar_build_mode/29.xbar_same_source.3463650020 Apr 21 12:29:54 PM PDT 24 Apr 21 12:30:04 PM PDT 24 2715443957 ps
T772 /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4023845976 Apr 21 12:29:03 PM PDT 24 Apr 21 12:29:07 PM PDT 24 165742277 ps
T773 /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2660481839 Apr 21 12:28:48 PM PDT 24 Apr 21 12:29:31 PM PDT 24 5347341409 ps
T774 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3187768596 Apr 21 12:30:30 PM PDT 24 Apr 21 12:33:46 PM PDT 24 40186732153 ps
T775 /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1414968544 Apr 21 12:28:40 PM PDT 24 Apr 21 12:28:44 PM PDT 24 59053475 ps
T776 /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.887464627 Apr 21 12:29:12 PM PDT 24 Apr 21 12:29:17 PM PDT 24 56442371 ps
T92 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3056582770 Apr 21 12:28:54 PM PDT 24 Apr 21 12:30:10 PM PDT 24 11844387989 ps
T777 /workspace/coverage/xbar_build_mode/23.xbar_same_source.4077709961 Apr 21 12:29:46 PM PDT 24 Apr 21 12:29:52 PM PDT 24 129043475 ps
T778 /workspace/coverage/xbar_build_mode/39.xbar_error_random.2961119972 Apr 21 12:30:40 PM PDT 24 Apr 21 12:30:45 PM PDT 24 689506870 ps
T779 /workspace/coverage/xbar_build_mode/33.xbar_smoke.3898243414 Apr 21 12:30:01 PM PDT 24 Apr 21 12:30:03 PM PDT 24 134711071 ps
T780 /workspace/coverage/xbar_build_mode/38.xbar_same_source.3335498408 Apr 21 12:30:20 PM PDT 24 Apr 21 12:30:29 PM PDT 24 716370754 ps
T781 /workspace/coverage/xbar_build_mode/21.xbar_random.3867654526 Apr 21 12:29:34 PM PDT 24 Apr 21 12:29:44 PM PDT 24 3667056046 ps
T782 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1639949734 Apr 21 12:28:56 PM PDT 24 Apr 21 12:29:07 PM PDT 24 474109801 ps
T783 /workspace/coverage/xbar_build_mode/19.xbar_error_random.2850874619 Apr 21 12:29:34 PM PDT 24 Apr 21 12:29:41 PM PDT 24 63608224 ps
T784 /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1418809895 Apr 21 12:31:15 PM PDT 24 Apr 21 12:31:17 PM PDT 24 9581746 ps
T785 /workspace/coverage/xbar_build_mode/30.xbar_random.2103642585 Apr 21 12:30:08 PM PDT 24 Apr 21 12:30:13 PM PDT 24 53093496 ps
T786 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.979831725 Apr 21 12:30:48 PM PDT 24 Apr 21 12:32:48 PM PDT 24 30613211338 ps
T787 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3528547758 Apr 21 12:29:07 PM PDT 24 Apr 21 12:29:14 PM PDT 24 1798313822 ps
T788 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1842568835 Apr 21 12:29:05 PM PDT 24 Apr 21 12:29:16 PM PDT 24 43789511 ps
T789 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.900559522 Apr 21 12:29:43 PM PDT 24 Apr 21 12:29:48 PM PDT 24 102966927 ps
T790 /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2329590475 Apr 21 12:28:58 PM PDT 24 Apr 21 12:29:06 PM PDT 24 248561094 ps
T791 /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2867580774 Apr 21 12:29:49 PM PDT 24 Apr 21 12:29:54 PM PDT 24 475618150 ps
T792 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2932724077 Apr 21 12:30:32 PM PDT 24 Apr 21 12:31:05 PM PDT 24 2683245362 ps
T793 /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3479809274 Apr 21 12:28:37 PM PDT 24 Apr 21 12:31:05 PM PDT 24 33133086848 ps
T794 /workspace/coverage/xbar_build_mode/8.xbar_random.1297797470 Apr 21 12:29:00 PM PDT 24 Apr 21 12:29:06 PM PDT 24 621275637 ps
T795 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.313999868 Apr 21 12:29:06 PM PDT 24 Apr 21 12:30:30 PM PDT 24 987684230 ps
T796 /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4271084107 Apr 21 12:29:49 PM PDT 24 Apr 21 12:29:50 PM PDT 24 9809461 ps
T797 /workspace/coverage/xbar_build_mode/0.xbar_error_random.1553903923 Apr 21 12:28:38 PM PDT 24 Apr 21 12:28:41 PM PDT 24 401303522 ps
T798 /workspace/coverage/xbar_build_mode/44.xbar_random.1893236651 Apr 21 12:30:32 PM PDT 24 Apr 21 12:30:37 PM PDT 24 173405487 ps
T799 /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3968785425 Apr 21 12:30:17 PM PDT 24 Apr 21 12:31:08 PM PDT 24 66021563589 ps
T800 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1576735340 Apr 21 12:30:07 PM PDT 24 Apr 21 12:31:01 PM PDT 24 2336164658 ps
T161 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1080643040 Apr 21 12:30:20 PM PDT 24 Apr 21 12:30:58 PM PDT 24 424748893 ps
T801 /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.958526847 Apr 21 12:29:22 PM PDT 24 Apr 21 12:29:24 PM PDT 24 27123631 ps
T802 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3176880588 Apr 21 12:30:55 PM PDT 24 Apr 21 12:30:56 PM PDT 24 10750607 ps
T803 /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2063767675 Apr 21 12:28:39 PM PDT 24 Apr 21 12:28:41 PM PDT 24 9227958 ps
T804 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.273147382 Apr 21 12:30:47 PM PDT 24 Apr 21 12:31:25 PM PDT 24 301274743 ps
T805 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1026030792 Apr 21 12:29:32 PM PDT 24 Apr 21 12:29:38 PM PDT 24 96543029 ps
T806 /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.743762571 Apr 21 12:30:30 PM PDT 24 Apr 21 12:30:37 PM PDT 24 52295832 ps
T807 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1448195297 Apr 21 12:28:41 PM PDT 24 Apr 21 12:28:45 PM PDT 24 54950006 ps
T808 /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2491519572 Apr 21 12:30:17 PM PDT 24 Apr 21 12:31:02 PM PDT 24 5583054724 ps
T809 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1805688970 Apr 21 12:28:49 PM PDT 24 Apr 21 12:31:10 PM PDT 24 28394105424 ps
T810 /workspace/coverage/xbar_build_mode/24.xbar_error_random.1973839987 Apr 21 12:29:51 PM PDT 24 Apr 21 12:29:56 PM PDT 24 71518367 ps
T93 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.926231363 Apr 21 12:28:43 PM PDT 24 Apr 21 12:33:05 PM PDT 24 54574460311 ps
T811 /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3251620173 Apr 21 12:30:10 PM PDT 24 Apr 21 12:30:25 PM PDT 24 7333485248 ps
T812 /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1453089570 Apr 21 12:29:09 PM PDT 24 Apr 21 12:29:16 PM PDT 24 2342609609 ps
T813 /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3363913861 Apr 21 12:29:32 PM PDT 24 Apr 21 12:29:43 PM PDT 24 3067205796 ps
T814 /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.970412031 Apr 21 12:30:25 PM PDT 24 Apr 21 12:30:36 PM PDT 24 4109073023 ps
T815 /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.864870169 Apr 21 12:28:58 PM PDT 24 Apr 21 12:29:00 PM PDT 24 11161276 ps
T816 /workspace/coverage/xbar_build_mode/48.xbar_random.3099861149 Apr 21 12:30:48 PM PDT 24 Apr 21 12:30:53 PM PDT 24 511776225 ps
T817 /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2357490448 Apr 21 12:29:14 PM PDT 24 Apr 21 12:29:15 PM PDT 24 10047313 ps
T236 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2171390105 Apr 21 12:30:16 PM PDT 24 Apr 21 12:36:52 PM PDT 24 289616767936 ps
T818 /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3139768585 Apr 21 12:30:04 PM PDT 24 Apr 21 12:30:12 PM PDT 24 64177780 ps
T819 /workspace/coverage/xbar_build_mode/22.xbar_same_source.1979039000 Apr 21 12:29:38 PM PDT 24 Apr 21 12:29:45 PM PDT 24 80036194 ps
T820 /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3148997627 Apr 21 12:29:14 PM PDT 24 Apr 21 12:29:56 PM PDT 24 22458786283 ps
T821 /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2105621068 Apr 21 12:29:44 PM PDT 24 Apr 21 12:29:52 PM PDT 24 2103486459 ps
T822 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3985617735 Apr 21 12:28:55 PM PDT 24 Apr 21 12:29:09 PM PDT 24 123580785 ps
T823 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2754443409 Apr 21 12:29:19 PM PDT 24 Apr 21 12:29:38 PM PDT 24 4249188363 ps
T824 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.976393803 Apr 21 12:30:21 PM PDT 24 Apr 21 12:30:29 PM PDT 24 2655333429 ps
T825 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.137948381 Apr 21 12:28:39 PM PDT 24 Apr 21 12:29:42 PM PDT 24 13818722649 ps
T826 /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3238234024 Apr 21 12:30:07 PM PDT 24 Apr 21 12:31:01 PM PDT 24 17538004114 ps
T827 /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2297830423 Apr 21 12:29:32 PM PDT 24 Apr 21 12:29:42 PM PDT 24 1483303594 ps
T828 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.162970227 Apr 21 12:29:50 PM PDT 24 Apr 21 12:29:58 PM PDT 24 55924091 ps
T829 /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2107984966 Apr 21 12:29:39 PM PDT 24 Apr 21 12:29:41 PM PDT 24 33297403 ps
T830 /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3859420292 Apr 21 12:30:06 PM PDT 24 Apr 21 12:30:10 PM PDT 24 656242782 ps
T831 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1890848269 Apr 21 12:30:17 PM PDT 24 Apr 21 12:30:27 PM PDT 24 685006414 ps
T832 /workspace/coverage/xbar_build_mode/7.xbar_error_random.1771646145 Apr 21 12:28:57 PM PDT 24 Apr 21 12:29:02 PM PDT 24 72773499 ps
T833 /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3891796592 Apr 21 12:29:48 PM PDT 24 Apr 21 12:29:54 PM PDT 24 5196534890 ps
T834 /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3218389630 Apr 21 12:29:37 PM PDT 24 Apr 21 12:29:45 PM PDT 24 974589873 ps
T835 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1507124297 Apr 21 12:29:48 PM PDT 24 Apr 21 12:29:59 PM PDT 24 130935964 ps
T148 /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.589335058 Apr 21 12:30:22 PM PDT 24 Apr 21 12:32:37 PM PDT 24 179481088957 ps
T836 /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3822551475 Apr 21 12:28:57 PM PDT 24 Apr 21 12:31:21 PM PDT 24 46058146204 ps
T837 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3593739165 Apr 21 12:28:49 PM PDT 24 Apr 21 12:28:54 PM PDT 24 1603391540 ps
T838 /workspace/coverage/xbar_build_mode/2.xbar_random.3666128563 Apr 21 12:28:38 PM PDT 24 Apr 21 12:28:53 PM PDT 24 4821071519 ps
T839 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.834968847 Apr 21 12:29:46 PM PDT 24 Apr 21 12:29:59 PM PDT 24 6737302814 ps
T840 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2391682003 Apr 21 12:28:45 PM PDT 24 Apr 21 12:28:48 PM PDT 24 15644374 ps
T841 /workspace/coverage/xbar_build_mode/2.xbar_smoke.54022362 Apr 21 12:28:41 PM PDT 24 Apr 21 12:28:43 PM PDT 24 9496446 ps
T842 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2126523156 Apr 21 12:29:10 PM PDT 24 Apr 21 12:29:19 PM PDT 24 83367843 ps
T843 /workspace/coverage/xbar_build_mode/25.xbar_random.168689006 Apr 21 12:29:51 PM PDT 24 Apr 21 12:29:58 PM PDT 24 468563081 ps
T844 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1639516706 Apr 21 12:29:30 PM PDT 24 Apr 21 12:29:35 PM PDT 24 68561213 ps
T845 /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1377172815 Apr 21 12:30:23 PM PDT 24 Apr 21 12:30:29 PM PDT 24 2983606942 ps
T846 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.4046748315 Apr 21 12:29:00 PM PDT 24 Apr 21 12:29:07 PM PDT 24 1188143556 ps
T847 /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2754151211 Apr 21 12:29:15 PM PDT 24 Apr 21 12:29:17 PM PDT 24 25822812 ps
T848 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1153645072 Apr 21 12:30:22 PM PDT 24 Apr 21 12:30:32 PM PDT 24 951116188 ps
T849 /workspace/coverage/xbar_build_mode/34.xbar_smoke.2150633294 Apr 21 12:30:10 PM PDT 24 Apr 21 12:30:12 PM PDT 24 121672862 ps
T850 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2084255550 Apr 21 12:30:09 PM PDT 24 Apr 21 12:30:23 PM PDT 24 57794363 ps
T212 /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3354078436 Apr 21 12:31:00 PM PDT 24 Apr 21 12:31:11 PM PDT 24 612958371 ps
T851 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.336241879 Apr 21 12:30:21 PM PDT 24 Apr 21 12:31:38 PM PDT 24 391233679 ps
T852 /workspace/coverage/xbar_build_mode/0.xbar_same_source.3300733576 Apr 21 12:28:40 PM PDT 24 Apr 21 12:28:51 PM PDT 24 1676950839 ps
T853 /workspace/coverage/xbar_build_mode/42.xbar_random.3226330011 Apr 21 12:30:43 PM PDT 24 Apr 21 12:30:52 PM PDT 24 1957224199 ps
T854 /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1995407656 Apr 21 12:29:48 PM PDT 24 Apr 21 12:29:53 PM PDT 24 302214847 ps
T114 /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2742137672 Apr 21 12:28:43 PM PDT 24 Apr 21 12:29:50 PM PDT 24 10199070610 ps
T855 /workspace/coverage/xbar_build_mode/19.xbar_smoke.1044012339 Apr 21 12:29:28 PM PDT 24 Apr 21 12:29:30 PM PDT 24 8315398 ps
T227 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3126512049 Apr 21 12:28:51 PM PDT 24 Apr 21 12:34:17 PM PDT 24 267282891849 ps
T856 /workspace/coverage/xbar_build_mode/23.xbar_random.1641591266 Apr 21 12:29:40 PM PDT 24 Apr 21 12:29:42 PM PDT 24 248021567 ps
T857 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2385489564 Apr 21 12:29:14 PM PDT 24 Apr 21 12:29:35 PM PDT 24 266435272 ps
T858 /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2184697088 Apr 21 12:30:00 PM PDT 24 Apr 21 12:30:08 PM PDT 24 7007430003 ps
T859 /workspace/coverage/xbar_build_mode/45.xbar_random.2204860733 Apr 21 12:30:51 PM PDT 24 Apr 21 12:31:05 PM PDT 24 5374965882 ps
T860 /workspace/coverage/xbar_build_mode/22.xbar_error_random.1147338164 Apr 21 12:29:39 PM PDT 24 Apr 21 12:29:49 PM PDT 24 1134281968 ps
T861 /workspace/coverage/xbar_build_mode/13.xbar_same_source.2195917710 Apr 21 12:29:10 PM PDT 24 Apr 21 12:29:14 PM PDT 24 39729405 ps
T862 /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4014832684 Apr 21 12:28:51 PM PDT 24 Apr 21 12:29:00 PM PDT 24 1511534613 ps
T863 /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3256861665 Apr 21 12:30:54 PM PDT 24 Apr 21 12:31:07 PM PDT 24 2667338135 ps
T864 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4073354752 Apr 21 12:28:41 PM PDT 24 Apr 21 12:29:13 PM PDT 24 5497547611 ps
T865 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3837977757 Apr 21 12:28:49 PM PDT 24 Apr 21 12:30:04 PM PDT 24 6309161421 ps
T866 /workspace/coverage/xbar_build_mode/7.xbar_random.2323899767 Apr 21 12:28:52 PM PDT 24 Apr 21 12:29:04 PM PDT 24 4755660474 ps
T867 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4213684547 Apr 21 12:29:35 PM PDT 24 Apr 21 12:30:45 PM PDT 24 727784368 ps
T868 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4195287939 Apr 21 12:30:47 PM PDT 24 Apr 21 12:32:04 PM PDT 24 4673959088 ps
T869 /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3553604229 Apr 21 12:28:52 PM PDT 24 Apr 21 12:29:03 PM PDT 24 2943186365 ps
T870 /workspace/coverage/xbar_build_mode/33.xbar_random.1347290534 Apr 21 12:30:08 PM PDT 24 Apr 21 12:30:10 PM PDT 24 8186926 ps
T871 /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1011647965 Apr 21 12:30:54 PM PDT 24 Apr 21 12:31:01 PM PDT 24 483288482 ps
T872 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2303370286 Apr 21 12:29:46 PM PDT 24 Apr 21 12:30:14 PM PDT 24 322270883 ps
T873 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.245333899 Apr 21 12:30:58 PM PDT 24 Apr 21 12:31:04 PM PDT 24 49053136 ps
T874 /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2304921265 Apr 21 12:29:54 PM PDT 24 Apr 21 12:30:14 PM PDT 24 27697872713 ps
T875 /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3962497311 Apr 21 12:30:08 PM PDT 24 Apr 21 12:32:16 PM PDT 24 15209348282 ps
T876 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3870584624 Apr 21 12:30:10 PM PDT 24 Apr 21 12:30:17 PM PDT 24 445087335 ps
T877 /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3015974947 Apr 21 12:29:38 PM PDT 24 Apr 21 12:29:45 PM PDT 24 63392066 ps
T878 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2425710248 Apr 21 12:30:25 PM PDT 24 Apr 21 12:31:13 PM PDT 24 185353969 ps
T879 /workspace/coverage/xbar_build_mode/9.xbar_random.1421984094 Apr 21 12:28:59 PM PDT 24 Apr 21 12:29:02 PM PDT 24 139755663 ps
T880 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.492807646 Apr 21 12:29:38 PM PDT 24 Apr 21 12:29:48 PM PDT 24 68141446 ps
T881 /workspace/coverage/xbar_build_mode/1.xbar_same_source.4205296862 Apr 21 12:28:36 PM PDT 24 Apr 21 12:28:40 PM PDT 24 1339020389 ps
T882 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.342645986 Apr 21 12:28:37 PM PDT 24 Apr 21 12:28:56 PM PDT 24 243884038 ps
T883 /workspace/coverage/xbar_build_mode/26.xbar_random.4132709001 Apr 21 12:30:06 PM PDT 24 Apr 21 12:30:22 PM PDT 24 83639419 ps
T884 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1199058155 Apr 21 12:30:04 PM PDT 24 Apr 21 12:31:50 PM PDT 24 196454033181 ps
T885 /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.113772446 Apr 21 12:29:04 PM PDT 24 Apr 21 12:29:06 PM PDT 24 8063548 ps
T886 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.4065721314 Apr 21 12:29:41 PM PDT 24 Apr 21 12:29:43 PM PDT 24 42735353 ps
T887 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.390034051 Apr 21 12:28:34 PM PDT 24 Apr 21 12:28:45 PM PDT 24 59175039 ps
T888 /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2414511056 Apr 21 12:29:46 PM PDT 24 Apr 21 12:30:53 PM PDT 24 35670345139 ps
T889 /workspace/coverage/xbar_build_mode/2.xbar_error_random.2156561690 Apr 21 12:28:40 PM PDT 24 Apr 21 12:28:45 PM PDT 24 41009040 ps
T890 /workspace/coverage/xbar_build_mode/38.xbar_smoke.1127857963 Apr 21 12:30:17 PM PDT 24 Apr 21 12:30:19 PM PDT 24 10312574 ps
T891 /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1267340738 Apr 21 12:29:46 PM PDT 24 Apr 21 12:29:52 PM PDT 24 1574221655 ps
T892 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.598952448 Apr 21 12:29:05 PM PDT 24 Apr 21 12:29:26 PM PDT 24 5183783205 ps
T893 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.734332554 Apr 21 12:29:27 PM PDT 24 Apr 21 12:34:17 PM PDT 24 49676525951 ps
T894 /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1901179448 Apr 21 12:29:38 PM PDT 24 Apr 21 12:30:30 PM PDT 24 432339623 ps
T895 /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3474875800 Apr 21 12:29:18 PM PDT 24 Apr 21 12:29:57 PM PDT 24 4058080760 ps
T896 /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3564111977 Apr 21 12:28:36 PM PDT 24 Apr 21 12:29:49 PM PDT 24 20347943629 ps
T897 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3603683046 Apr 21 12:28:40 PM PDT 24 Apr 21 12:29:00 PM PDT 24 253254167 ps
T124 /workspace/coverage/xbar_build_mode/8.xbar_stress_all.3261419425 Apr 21 12:28:56 PM PDT 24 Apr 21 12:30:34 PM PDT 24 7184414915 ps
T898 /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.807996966 Apr 21 12:29:13 PM PDT 24 Apr 21 12:29:15 PM PDT 24 15392903 ps
T899 /workspace/coverage/xbar_build_mode/25.xbar_error_random.2113958445 Apr 21 12:29:47 PM PDT 24 Apr 21 12:30:04 PM PDT 24 888635567 ps
T900 /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3010755204 Apr 21 12:30:02 PM PDT 24 Apr 21 12:31:39 PM PDT 24 21022612334 ps

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.670264686
Short name T15
Test name
Test status
Simulation time 9060126484 ps
CPU time 94.94 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 202956 kb
Host smart-0ddaa06e-52b1-41ac-8277-9223056fa1ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670264686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.670264686
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4224994117
Short name T45
Test name
Test status
Simulation time 95526259318 ps
CPU time 350.48 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:36:33 PM PDT 24
Peak memory 203856 kb
Host smart-6debab2d-d1b6-4ec3-b2fb-f81af03c57a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4224994117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.4224994117
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1376157137
Short name T215
Test name
Test status
Simulation time 65404055914 ps
CPU time 155.4 seconds
Started Apr 21 12:30:35 PM PDT 24
Finished Apr 21 12:33:11 PM PDT 24
Peak memory 203064 kb
Host smart-17c39a74-ebf6-46d0-ab97-9f63d61f035e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1376157137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1376157137
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.735797711
Short name T228
Test name
Test status
Simulation time 50063843409 ps
CPU time 192.4 seconds
Started Apr 21 12:30:58 PM PDT 24
Finished Apr 21 12:34:11 PM PDT 24
Peak memory 202944 kb
Host smart-47673160-7515-497b-9df4-8c98f6109cef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=735797711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo
w_rsp.735797711
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.764077630
Short name T222
Test name
Test status
Simulation time 51541465917 ps
CPU time 308.77 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:34:23 PM PDT 24
Peak memory 202944 kb
Host smart-01596392-49be-4a5f-806a-1655b50d3c87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=764077630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo
w_rsp.764077630
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.4174604926
Short name T1
Test name
Test status
Simulation time 9071757832 ps
CPU time 189.76 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:32:58 PM PDT 24
Peak memory 206760 kb
Host smart-5eaebd2b-8675-4045-ba12-9b0a825932f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4174604926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.4174604926
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.251604087
Short name T144
Test name
Test status
Simulation time 41290120124 ps
CPU time 309.17 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:34:58 PM PDT 24
Peak memory 203740 kb
Host smart-d407ddb7-3d45-43b1-9ab5-ab8e737c3cfb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=251604087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo
w_rsp.251604087
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2133722123
Short name T253
Test name
Test status
Simulation time 43450055 ps
CPU time 4.23 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201812 kb
Host smart-492fae62-43bf-472c-bf9e-64c7157ca823
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2133722123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2133722123
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1036814147
Short name T69
Test name
Test status
Simulation time 86876841822 ps
CPU time 307.22 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:34:13 PM PDT 24
Peak memory 203520 kb
Host smart-ed31d21b-5ddb-4994-9a57-02f55f981bb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1036814147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.1036814147
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2326323875
Short name T19
Test name
Test status
Simulation time 18198896059 ps
CPU time 112.29 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201924 kb
Host smart-0bea572b-0e07-45f5-ab69-f6d8344c6f4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2326323875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2326323875
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.629978573
Short name T13
Test name
Test status
Simulation time 522932659 ps
CPU time 63.52 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:31:14 PM PDT 24
Peak memory 204040 kb
Host smart-8e673843-fe62-4012-9be7-1643319d221a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=629978573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res
et_error.629978573
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.357877229
Short name T58
Test name
Test status
Simulation time 11526428611 ps
CPU time 56.93 seconds
Started Apr 21 12:29:36 PM PDT 24
Finished Apr 21 12:30:33 PM PDT 24
Peak memory 201948 kb
Host smart-5e1b5561-bbe6-4fa4-bfa9-9f3c85a96385
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=357877229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.357877229
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2983677636
Short name T154
Test name
Test status
Simulation time 19177147902 ps
CPU time 139.98 seconds
Started Apr 21 12:30:34 PM PDT 24
Finished Apr 21 12:32:54 PM PDT 24
Peak memory 203904 kb
Host smart-6bbb7b3d-aa74-4191-a120-0eae98fb06bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2983677636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.2983677636
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1444359996
Short name T9
Test name
Test status
Simulation time 432009239 ps
CPU time 34.7 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:35 PM PDT 24
Peak memory 202884 kb
Host smart-5b823512-fb25-410e-bd91-ec67b9f8a186
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1444359996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.1444359996
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.926231363
Short name T93
Test name
Test status
Simulation time 54574460311 ps
CPU time 260.89 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:33:05 PM PDT 24
Peak memory 203052 kb
Host smart-c3b37ffe-63d5-45a6-bd23-70b26aa98412
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=926231363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.926231363
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1898284833
Short name T169
Test name
Test status
Simulation time 27050416380 ps
CPU time 236.51 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:33:15 PM PDT 24
Peak memory 208188 kb
Host smart-16e9543f-fc56-4f4c-acd2-82d9d8ece514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1898284833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.1898284833
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1787938281
Short name T239
Test name
Test status
Simulation time 1604153376 ps
CPU time 63.69 seconds
Started Apr 21 12:30:36 PM PDT 24
Finished Apr 21 12:31:40 PM PDT 24
Peak memory 203984 kb
Host smart-378e5b19-ddf6-450d-8d7d-c96144cdb225
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1787938281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.1787938281
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.2975685484
Short name T35
Test name
Test status
Simulation time 29343633 ps
CPU time 1.98 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201912 kb
Host smart-bd38a540-9cdd-4a11-bd0d-137e5f2629f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2975685484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2975685484
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3056582770
Short name T92
Test name
Test status
Simulation time 11844387989 ps
CPU time 75.45 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 205608 kb
Host smart-1cdb718b-0809-41c0-a277-971c3e76901c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3056582770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.3056582770
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2933015311
Short name T235
Test name
Test status
Simulation time 34175376938 ps
CPU time 186.03 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:32:54 PM PDT 24
Peak memory 203100 kb
Host smart-b5f05519-f1b5-4226-bbf2-86ebde6b9478
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2933015311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.2933015311
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2969389711
Short name T243
Test name
Test status
Simulation time 1720818616 ps
CPU time 147.71 seconds
Started Apr 21 12:30:23 PM PDT 24
Finished Apr 21 12:32:52 PM PDT 24
Peak memory 206928 kb
Host smart-4c4a7675-efc0-4f14-aa16-c4eb75418ef5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2969389711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.2969389711
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1361833300
Short name T28
Test name
Test status
Simulation time 28775495234 ps
CPU time 114.67 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:31:45 PM PDT 24
Peak memory 201924 kb
Host smart-e2c5737f-8983-4339-95f7-1244c1d731e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361833300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1361833300
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1449507250
Short name T226
Test name
Test status
Simulation time 162530813431 ps
CPU time 311.02 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:33:54 PM PDT 24
Peak memory 203548 kb
Host smart-4b0d4523-9906-4e55-a2b5-fefff9615b52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1449507250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1449507250
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.965709353
Short name T675
Test name
Test status
Simulation time 15035012501 ps
CPU time 230.98 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:32:31 PM PDT 24
Peak memory 208464 kb
Host smart-423630ac-3036-415b-b5a4-9577ee7bc54c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=965709353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.965709353
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.401968863
Short name T414
Test name
Test status
Simulation time 133931929 ps
CPU time 27.8 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 202888 kb
Host smart-cd33ed69-610c-43d8-b886-a862e3c76dd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=401968863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.401968863
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.873822563
Short name T430
Test name
Test status
Simulation time 24469524 ps
CPU time 1.14 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:45 PM PDT 24
Peak memory 201800 kb
Host smart-a8fb0d50-5d0e-4a0a-9da6-ae8b1833a84c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873822563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.873822563
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.986212686
Short name T157
Test name
Test status
Simulation time 212346376 ps
CPU time 3.51 seconds
Started Apr 21 12:28:36 PM PDT 24
Finished Apr 21 12:28:40 PM PDT 24
Peak memory 201804 kb
Host smart-5afd70e7-802e-4c9f-9031-bfeb349d6310
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=986212686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.986212686
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.1553903923
Short name T797
Test name
Test status
Simulation time 401303522 ps
CPU time 3.4 seconds
Started Apr 21 12:28:38 PM PDT 24
Finished Apr 21 12:28:41 PM PDT 24
Peak memory 201900 kb
Host smart-9666a44f-6a97-48e7-98f9-099094eb8de0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1553903923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1553903923
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3361790482
Short name T306
Test name
Test status
Simulation time 39557362 ps
CPU time 4.84 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:47 PM PDT 24
Peak memory 201788 kb
Host smart-eb892f65-6768-4603-8250-391a7bc2080b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3361790482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3361790482
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1681180427
Short name T76
Test name
Test status
Simulation time 2932115165 ps
CPU time 8.84 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:28:52 PM PDT 24
Peak memory 201964 kb
Host smart-1b0d72d6-a0b2-45d5-b377-51913ca272e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681180427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1681180427
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4030109873
Short name T26
Test name
Test status
Simulation time 1025161790 ps
CPU time 7.85 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201836 kb
Host smart-f74daf3e-a724-47a1-bde8-c2bbe60decfb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4030109873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4030109873
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3963533179
Short name T565
Test name
Test status
Simulation time 36200297 ps
CPU time 3.9 seconds
Started Apr 21 12:28:36 PM PDT 24
Finished Apr 21 12:28:40 PM PDT 24
Peak memory 201864 kb
Host smart-1c8b211e-9fdf-4a6a-a25c-32e6cfbbc453
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963533179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3963533179
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.3300733576
Short name T852
Test name
Test status
Simulation time 1676950839 ps
CPU time 11.11 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201856 kb
Host smart-efb781a7-aa04-4c26-b7d3-5be9ebea4993
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3300733576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3300733576
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.4159034995
Short name T499
Test name
Test status
Simulation time 53437741 ps
CPU time 1.7 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:28:44 PM PDT 24
Peak memory 201852 kb
Host smart-711cb3e4-da9d-43c5-a6bc-4f94d585a63c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4159034995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4159034995
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2280130600
Short name T660
Test name
Test status
Simulation time 4130396849 ps
CPU time 8.61 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201960 kb
Host smart-a8d40bd8-c667-410e-8c1b-870860c0cbba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280130600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2280130600
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2086136750
Short name T482
Test name
Test status
Simulation time 673589895 ps
CPU time 5.48 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:49 PM PDT 24
Peak memory 201824 kb
Host smart-08a4b64a-649d-4576-8949-ce4a6a17c3a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2086136750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2086136750
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1920848439
Short name T765
Test name
Test status
Simulation time 15225266 ps
CPU time 1.31 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:28:44 PM PDT 24
Peak memory 201800 kb
Host smart-cad18f87-84f9-4767-95ba-046949160673
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920848439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1920848439
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2742137672
Short name T114
Test name
Test status
Simulation time 10199070610 ps
CPU time 65.74 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 203024 kb
Host smart-c5f1de3b-ab49-4ef0-8678-bb89a5c907cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2742137672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2742137672
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.309204326
Short name T282
Test name
Test status
Simulation time 737277170 ps
CPU time 2.75 seconds
Started Apr 21 12:28:28 PM PDT 24
Finished Apr 21 12:28:31 PM PDT 24
Peak memory 201844 kb
Host smart-d61c5305-f4bb-4b60-9254-fb7bbc05177a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=309204326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.309204326
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3831044872
Short name T118
Test name
Test status
Simulation time 183605952 ps
CPU time 23.19 seconds
Started Apr 21 12:28:28 PM PDT 24
Finished Apr 21 12:28:52 PM PDT 24
Peak memory 202784 kb
Host smart-8e06429d-1622-4e33-87fc-0aa297594c37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3831044872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3831044872
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3603683046
Short name T897
Test name
Test status
Simulation time 253254167 ps
CPU time 19.3 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 202816 kb
Host smart-24bde321-df64-4c54-a39f-552dce23ccc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3603683046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.3603683046
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3688870411
Short name T84
Test name
Test status
Simulation time 763593268 ps
CPU time 11.08 seconds
Started Apr 21 12:28:37 PM PDT 24
Finished Apr 21 12:28:49 PM PDT 24
Peak memory 201788 kb
Host smart-5bde58bd-58ff-4be4-a9d5-1ea9f66af067
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3688870411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3688870411
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.390034051
Short name T887
Test name
Test status
Simulation time 59175039 ps
CPU time 10.98 seconds
Started Apr 21 12:28:34 PM PDT 24
Finished Apr 21 12:28:45 PM PDT 24
Peak memory 201784 kb
Host smart-7c64417c-b6e5-4592-987d-67da10c0297f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=390034051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.390034051
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.889140634
Short name T83
Test name
Test status
Simulation time 27896143574 ps
CPU time 161.03 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:31:22 PM PDT 24
Peak memory 202952 kb
Host smart-d8d1ee71-86b0-406c-8570-01b489a17db3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=889140634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow
_rsp.889140634
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3850157376
Short name T193
Test name
Test status
Simulation time 16992629 ps
CPU time 1.98 seconds
Started Apr 21 12:28:39 PM PDT 24
Finished Apr 21 12:28:42 PM PDT 24
Peak memory 201848 kb
Host smart-82e5661b-a874-4259-a4d8-0a2f920b37ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3850157376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3850157376
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.3491035337
Short name T446
Test name
Test status
Simulation time 266324492 ps
CPU time 6.43 seconds
Started Apr 21 12:28:32 PM PDT 24
Finished Apr 21 12:28:39 PM PDT 24
Peak memory 201812 kb
Host smart-cfd6a182-7689-4ef1-ba5a-c2fe38be9895
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3491035337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3491035337
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.1919477496
Short name T443
Test name
Test status
Simulation time 885787313 ps
CPU time 8.33 seconds
Started Apr 21 12:28:44 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201804 kb
Host smart-0856b85c-1472-46fb-90d1-cf1c5669ed7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1919477496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1919477496
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3564111977
Short name T896
Test name
Test status
Simulation time 20347943629 ps
CPU time 72.16 seconds
Started Apr 21 12:28:36 PM PDT 24
Finished Apr 21 12:29:49 PM PDT 24
Peak memory 201900 kb
Host smart-66789bc9-85e7-4bbc-b023-a281d403f8d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564111977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3564111977
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.137948381
Short name T825
Test name
Test status
Simulation time 13818722649 ps
CPU time 61.92 seconds
Started Apr 21 12:28:39 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201940 kb
Host smart-9dfdce9d-a1d4-41b3-b85d-fd75c674c16e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=137948381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.137948381
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.599419394
Short name T408
Test name
Test status
Simulation time 37956119 ps
CPU time 4.02 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:28:45 PM PDT 24
Peak memory 201852 kb
Host smart-f24816cc-188e-4a5f-956c-3a333e9cb726
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599419394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.599419394
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.4205296862
Short name T881
Test name
Test status
Simulation time 1339020389 ps
CPU time 2.81 seconds
Started Apr 21 12:28:36 PM PDT 24
Finished Apr 21 12:28:40 PM PDT 24
Peak memory 201828 kb
Host smart-7fb0f8c6-bbdc-4a34-ba34-19b71c479b44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4205296862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4205296862
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3875938961
Short name T751
Test name
Test status
Simulation time 11319673 ps
CPU time 1.21 seconds
Started Apr 21 12:28:33 PM PDT 24
Finished Apr 21 12:28:34 PM PDT 24
Peak memory 201916 kb
Host smart-4060bca4-3601-4b95-ac7a-93e635bf2bf4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3875938961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3875938961
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2507204579
Short name T537
Test name
Test status
Simulation time 12358289900 ps
CPU time 8.77 seconds
Started Apr 21 12:28:29 PM PDT 24
Finished Apr 21 12:28:38 PM PDT 24
Peak memory 202040 kb
Host smart-c143869e-023f-4e36-be64-14ad70cf8a1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507204579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2507204579
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1408293257
Short name T722
Test name
Test status
Simulation time 1760037001 ps
CPU time 7.38 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201820 kb
Host smart-85e50c20-9e0c-4b68-a7a6-10e6c97ce6da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1408293257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1408293257
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2063767675
Short name T803
Test name
Test status
Simulation time 9227958 ps
CPU time 1.19 seconds
Started Apr 21 12:28:39 PM PDT 24
Finished Apr 21 12:28:41 PM PDT 24
Peak memory 201836 kb
Host smart-198131ac-f7b7-4c18-9cb2-a8b271f5b3a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063767675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2063767675
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3276337847
Short name T581
Test name
Test status
Simulation time 173605243 ps
CPU time 18.23 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201792 kb
Host smart-cb4f2621-cdb8-4a3a-b6d1-55f7d369fbe1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276337847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3276337847
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1819530497
Short name T313
Test name
Test status
Simulation time 5181116521 ps
CPU time 48.8 seconds
Started Apr 21 12:28:44 PM PDT 24
Finished Apr 21 12:29:34 PM PDT 24
Peak memory 202008 kb
Host smart-b8f2b639-69fa-4fb7-b4ab-ef794c52c489
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1819530497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1819530497
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.342645986
Short name T882
Test name
Test status
Simulation time 243884038 ps
CPU time 19.2 seconds
Started Apr 21 12:28:37 PM PDT 24
Finished Apr 21 12:28:56 PM PDT 24
Peak memory 202820 kb
Host smart-1b39d8a0-ef1d-42e0-875e-443566aed8cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=342645986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.342645986
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3311293914
Short name T311
Test name
Test status
Simulation time 769266393 ps
CPU time 11.96 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201804 kb
Host smart-c7e4a692-f2bd-4c85-8dd7-3b48f7344fad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3311293914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3311293914
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2594005456
Short name T519
Test name
Test status
Simulation time 1377643913 ps
CPU time 11.89 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:18 PM PDT 24
Peak memory 201812 kb
Host smart-3fea7c05-fbff-409b-b956-236e2466a86d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2594005456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2594005456
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1949214208
Short name T60
Test name
Test status
Simulation time 62205845738 ps
CPU time 123.16 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:31:10 PM PDT 24
Peak memory 202564 kb
Host smart-c537b12c-1e8e-4533-8e08-ef6766270389
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1949214208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.1949214208
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.520106789
Short name T268
Test name
Test status
Simulation time 506751819 ps
CPU time 10.08 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:18 PM PDT 24
Peak memory 201892 kb
Host smart-1111cdf3-0be7-408e-adb1-2aa4530c4e50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=520106789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.520106789
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.4086287324
Short name T270
Test name
Test status
Simulation time 75673109 ps
CPU time 5.64 seconds
Started Apr 21 12:28:59 PM PDT 24
Finished Apr 21 12:29:05 PM PDT 24
Peak memory 201880 kb
Host smart-55fa68a5-23d1-4853-9698-666148f69c2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086287324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4086287324
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2378070468
Short name T605
Test name
Test status
Simulation time 797474011 ps
CPU time 9.4 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201892 kb
Host smart-0c632bff-11b4-4e9f-bef8-736e7081cd41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2378070468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2378070468
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.792806722
Short name T142
Test name
Test status
Simulation time 46341000879 ps
CPU time 145.51 seconds
Started Apr 21 12:29:04 PM PDT 24
Finished Apr 21 12:31:30 PM PDT 24
Peak memory 201788 kb
Host smart-6ecdc771-0b2c-4c9a-88c9-2b8088cc51ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=792806722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.792806722
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.916239504
Short name T23
Test name
Test status
Simulation time 5670600875 ps
CPU time 39.53 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201944 kb
Host smart-ba201b2a-158d-40cc-b3b9-2142af32b969
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=916239504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.916239504
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3595827881
Short name T141
Test name
Test status
Simulation time 46443709 ps
CPU time 2.39 seconds
Started Apr 21 12:29:01 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 201796 kb
Host smart-2da8c6d8-2606-4d8c-b85e-e595fb06dece
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595827881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3595827881
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.4217325740
Short name T445
Test name
Test status
Simulation time 928365237 ps
CPU time 11.89 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201892 kb
Host smart-cdd6952a-7717-4229-b3e9-61d6c4906cf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4217325740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.4217325740
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1748945697
Short name T108
Test name
Test status
Simulation time 210025527 ps
CPU time 1.19 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201672 kb
Host smart-64ef5d0c-f856-4d9e-af4f-9cd729eed89b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1748945697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1748945697
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3528547758
Short name T787
Test name
Test status
Simulation time 1798313822 ps
CPU time 6.84 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201820 kb
Host smart-fc0c07fd-eeb9-4d3f-9d02-5828d3c9aec1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528547758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3528547758
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3551574148
Short name T289
Test name
Test status
Simulation time 1307033590 ps
CPU time 8.42 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201664 kb
Host smart-7ab68088-163f-45ee-ae60-d4ab0f5e959f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3551574148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3551574148
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.4111622543
Short name T51
Test name
Test status
Simulation time 10388446 ps
CPU time 1.19 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201680 kb
Host smart-607881dc-deb5-497d-bf7c-34c14317592b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111622543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.4111622543
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1514073209
Short name T356
Test name
Test status
Simulation time 42249089 ps
CPU time 3.4 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:11 PM PDT 24
Peak memory 201888 kb
Host smart-1816e13b-d709-4a7f-a0a9-797b1f0299ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1514073209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1514073209
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1187612244
Short name T533
Test name
Test status
Simulation time 242184339 ps
CPU time 20.78 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:25 PM PDT 24
Peak memory 201836 kb
Host smart-201aef1c-4e3c-4fea-8db7-3fd18e3b6a1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1187612244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1187612244
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3430492732
Short name T401
Test name
Test status
Simulation time 161030465 ps
CPU time 13.68 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:27 PM PDT 24
Peak memory 202920 kb
Host smart-3724f8c4-03fe-4a83-9d7e-06c11126b2c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3430492732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3430492732
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2126523156
Short name T842
Test name
Test status
Simulation time 83367843 ps
CPU time 8.73 seconds
Started Apr 21 12:29:10 PM PDT 24
Finished Apr 21 12:29:19 PM PDT 24
Peak memory 201796 kb
Host smart-26cc0283-1d9d-489d-9e23-9b093641c007
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2126523156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.2126523156
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3187657666
Short name T422
Test name
Test status
Simulation time 15857062 ps
CPU time 1.59 seconds
Started Apr 21 12:29:09 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201816 kb
Host smart-774cf7c1-7a2d-43a7-988c-903bd0b7d337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3187657666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3187657666
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1842568835
Short name T788
Test name
Test status
Simulation time 43789511 ps
CPU time 10.09 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 201816 kb
Host smart-426bc2f4-4780-42fe-b5bd-7666a276b90c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1842568835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1842568835
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.832707156
Short name T150
Test name
Test status
Simulation time 20907873875 ps
CPU time 55.53 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:30:03 PM PDT 24
Peak memory 201988 kb
Host smart-2e7e6b97-6f98-4325-8d4b-fce667ce2ed4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=832707156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.832707156
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2740364082
Short name T708
Test name
Test status
Simulation time 28914607 ps
CPU time 1.58 seconds
Started Apr 21 12:29:08 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201896 kb
Host smart-650e2825-6df3-4455-8594-282c605be7c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2740364082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2740364082
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2972712240
Short name T686
Test name
Test status
Simulation time 575555550 ps
CPU time 7.89 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201840 kb
Host smart-a40af80f-a4ac-46e1-b3e5-9512e9b44b15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2972712240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2972712240
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1186608619
Short name T201
Test name
Test status
Simulation time 593470114 ps
CPU time 9.04 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:13 PM PDT 24
Peak memory 201796 kb
Host smart-bcbf38d6-6965-4782-9e62-2b6319e3082c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186608619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1186608619
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.598952448
Short name T892
Test name
Test status
Simulation time 5183783205 ps
CPU time 20.63 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:26 PM PDT 24
Peak memory 201936 kb
Host smart-a301c676-5bac-471f-8b26-bb98a1b53978
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=598952448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.598952448
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1924717990
Short name T33
Test name
Test status
Simulation time 35505698497 ps
CPU time 125.11 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:31:08 PM PDT 24
Peak memory 202020 kb
Host smart-001c57a8-c48e-49c1-8158-5c67bb22bf18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1924717990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1924717990
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.900228063
Short name T107
Test name
Test status
Simulation time 25412273 ps
CPU time 2.34 seconds
Started Apr 21 12:29:04 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201892 kb
Host smart-6a69d89d-a86f-42e0-b2e4-98421a6a81ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900228063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.900228063
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.2940792665
Short name T21
Test name
Test status
Simulation time 572431201 ps
CPU time 3.27 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 201852 kb
Host smart-f9b2a910-24db-4aee-8e80-ad47d49d3cf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2940792665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2940792665
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.585837130
Short name T189
Test name
Test status
Simulation time 137300432 ps
CPU time 1.5 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201816 kb
Host smart-57a49762-d6f8-4bec-abb8-696f668036e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=585837130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.585837130
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3480670069
Short name T75
Test name
Test status
Simulation time 2794299858 ps
CPU time 9.66 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201868 kb
Host smart-b8b25060-1b3d-4d80-8e7f-685b161b8848
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480670069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3480670069
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3011360870
Short name T546
Test name
Test status
Simulation time 2011525923 ps
CPU time 6.49 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201836 kb
Host smart-3d352c8a-2d07-48d3-9fb2-bd8ceb493841
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3011360870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3011360870
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2224599643
Short name T634
Test name
Test status
Simulation time 8237127 ps
CPU time 1.09 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:05 PM PDT 24
Peak memory 201880 kb
Host smart-49b48844-fca6-4934-b9d0-ade3ead89187
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224599643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2224599643
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3485777025
Short name T214
Test name
Test status
Simulation time 10458991897 ps
CPU time 68.23 seconds
Started Apr 21 12:29:05 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 202928 kb
Host smart-3427668b-bba2-47a3-ac5b-49e703acbd7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3485777025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3485777025
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.502291843
Short name T767
Test name
Test status
Simulation time 261730728 ps
CPU time 35.51 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 203920 kb
Host smart-c2ae7bb8-69ff-402c-8624-a3352ec43c80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502291843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand
_reset.502291843
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.313999868
Short name T795
Test name
Test status
Simulation time 987684230 ps
CPU time 83.58 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:30:30 PM PDT 24
Peak memory 203812 kb
Host smart-2eb87fca-8c5e-49e1-b188-5706d81d3ec4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=313999868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res
et_error.313999868
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1328446422
Short name T425
Test name
Test status
Simulation time 1924618383 ps
CPU time 10.82 seconds
Started Apr 21 12:29:04 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201796 kb
Host smart-21f7abc5-5044-40ec-b031-7b36c525f1a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1328446422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1328446422
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.504437834
Short name T394
Test name
Test status
Simulation time 1421079054 ps
CPU time 6.98 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201816 kb
Host smart-6c4c5743-0033-4099-a9b3-7ba28e4e3d71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=504437834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.504437834
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2800356042
Short name T194
Test name
Test status
Simulation time 152013998 ps
CPU time 3.44 seconds
Started Apr 21 12:29:11 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201808 kb
Host smart-4a8471d0-efe0-4245-957f-1a4f43858d6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2800356042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2800356042
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3294551750
Short name T440
Test name
Test status
Simulation time 926008468 ps
CPU time 5.45 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:18 PM PDT 24
Peak memory 201884 kb
Host smart-1a7c2c54-913e-454a-ad26-21d464e78f27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3294551750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3294551750
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3022131008
Short name T400
Test name
Test status
Simulation time 29654369186 ps
CPU time 110.01 seconds
Started Apr 21 12:29:08 PM PDT 24
Finished Apr 21 12:30:59 PM PDT 24
Peak memory 201996 kb
Host smart-5474810d-0422-4a07-9676-334b9db4404a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022131008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3022131008
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3595030673
Short name T229
Test name
Test status
Simulation time 42364757008 ps
CPU time 148.23 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:31:35 PM PDT 24
Peak memory 201976 kb
Host smart-a36b61cf-7e54-452b-b84b-daf9345b44d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3595030673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3595030673
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.482155625
Short name T590
Test name
Test status
Simulation time 25241943 ps
CPU time 1.58 seconds
Started Apr 21 12:29:04 PM PDT 24
Finished Apr 21 12:29:06 PM PDT 24
Peak memory 201852 kb
Host smart-d0354b64-37b7-4987-892a-0a723f53b3d8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482155625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.482155625
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1002715541
Short name T623
Test name
Test status
Simulation time 20134083 ps
CPU time 2.39 seconds
Started Apr 21 12:29:07 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201892 kb
Host smart-0b289022-365c-4336-8b15-00db27b3f031
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002715541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1002715541
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.2359925495
Short name T688
Test name
Test status
Simulation time 28517082 ps
CPU time 1.16 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201816 kb
Host smart-7a7f010d-ee96-41a3-ae48-ee5b2972b05f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359925495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2359925495
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.4268566872
Short name T619
Test name
Test status
Simulation time 2146578769 ps
CPU time 10.3 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 201872 kb
Host smart-2a5c6f55-e665-4275-a878-591b5f536858
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268566872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4268566872
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.488257371
Short name T265
Test name
Test status
Simulation time 3077165073 ps
CPU time 11.45 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:26 PM PDT 24
Peak memory 201868 kb
Host smart-2ba8a605-70d1-45fd-8bbf-e7717403d05d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=488257371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.488257371
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.113772446
Short name T885
Test name
Test status
Simulation time 8063548 ps
CPU time 1.05 seconds
Started Apr 21 12:29:04 PM PDT 24
Finished Apr 21 12:29:06 PM PDT 24
Peak memory 201824 kb
Host smart-e4349beb-d31d-47f1-9c87-3bd0158835b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113772446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.113772446
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3474875800
Short name T895
Test name
Test status
Simulation time 4058080760 ps
CPU time 38.45 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 201864 kb
Host smart-229c9bc8-dbc3-4ff4-b8c3-74f3dbba6bf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3474875800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3474875800
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1562394947
Short name T234
Test name
Test status
Simulation time 12650855411 ps
CPU time 65.37 seconds
Started Apr 21 12:29:20 PM PDT 24
Finished Apr 21 12:30:26 PM PDT 24
Peak memory 201916 kb
Host smart-221b6841-c8b6-487c-869f-c7b9c1cf19df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1562394947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1562394947
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3814533062
Short name T750
Test name
Test status
Simulation time 39848280 ps
CPU time 7.73 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:29:23 PM PDT 24
Peak memory 201856 kb
Host smart-f7a703d9-ae9e-4850-9a5a-21acb9035309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3814533062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.3814533062
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1466746366
Short name T592
Test name
Test status
Simulation time 392990418 ps
CPU time 25.49 seconds
Started Apr 21 12:29:08 PM PDT 24
Finished Apr 21 12:29:34 PM PDT 24
Peak memory 202952 kb
Host smart-000471da-226e-4744-be0d-b56127269237
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1466746366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.1466746366
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1658923131
Short name T66
Test name
Test status
Simulation time 3617338423 ps
CPU time 7.45 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:21 PM PDT 24
Peak memory 201936 kb
Host smart-66ffd854-18ad-43a1-a897-4791e07ce21a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658923131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1658923131
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.690034370
Short name T80
Test name
Test status
Simulation time 55300003 ps
CPU time 1.85 seconds
Started Apr 21 12:29:08 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201856 kb
Host smart-4a8e08ad-ba32-4eda-8b7f-27f8ab5e2a20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=690034370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.690034370
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3426904462
Short name T525
Test name
Test status
Simulation time 26098277423 ps
CPU time 125.07 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:31:18 PM PDT 24
Peak memory 202016 kb
Host smart-fa40c379-e4c4-444f-be58-9a13effd937b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3426904462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3426904462
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.708836464
Short name T257
Test name
Test status
Simulation time 138822354 ps
CPU time 3.15 seconds
Started Apr 21 12:29:08 PM PDT 24
Finished Apr 21 12:29:12 PM PDT 24
Peak memory 201900 kb
Host smart-52a6316d-9abe-45d8-a71f-2bc8504ad9d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708836464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.708836464
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.4152758102
Short name T133
Test name
Test status
Simulation time 117214185 ps
CPU time 1.31 seconds
Started Apr 21 12:29:11 PM PDT 24
Finished Apr 21 12:29:12 PM PDT 24
Peak memory 201920 kb
Host smart-13032051-c43b-47b0-946f-07b4f918b689
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152758102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4152758102
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.2051839237
Short name T277
Test name
Test status
Simulation time 1109482902 ps
CPU time 8.02 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:21 PM PDT 24
Peak memory 201864 kb
Host smart-a15c9ffc-e751-4a15-83c8-4579f0738047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2051839237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2051839237
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3291476445
Short name T468
Test name
Test status
Simulation time 99397881856 ps
CPU time 127.85 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:31:21 PM PDT 24
Peak memory 202008 kb
Host smart-2ccefe99-0187-4d09-a5eb-1f79bc0abe6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291476445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3291476445
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3379823561
Short name T436
Test name
Test status
Simulation time 7476833887 ps
CPU time 44.77 seconds
Started Apr 21 12:29:11 PM PDT 24
Finished Apr 21 12:29:56 PM PDT 24
Peak memory 202020 kb
Host smart-a23c6a71-4177-433b-a088-b01bdb993ad1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3379823561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3379823561
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2595764431
Short name T492
Test name
Test status
Simulation time 34344705 ps
CPU time 3.33 seconds
Started Apr 21 12:29:10 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201800 kb
Host smart-8756d032-16c3-4607-93df-89b115bc39bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595764431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2595764431
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.2195917710
Short name T861
Test name
Test status
Simulation time 39729405 ps
CPU time 3.9 seconds
Started Apr 21 12:29:10 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201772 kb
Host smart-74d5a36d-0dff-4b6b-ad43-3c05043afad9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2195917710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2195917710
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.4122044823
Short name T578
Test name
Test status
Simulation time 62641187 ps
CPU time 1.58 seconds
Started Apr 21 12:29:10 PM PDT 24
Finished Apr 21 12:29:12 PM PDT 24
Peak memory 201916 kb
Host smart-67681ab7-c75d-4ce9-b97d-de4b4ee9d434
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4122044823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4122044823
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1453089570
Short name T812
Test name
Test status
Simulation time 2342609609 ps
CPU time 7.41 seconds
Started Apr 21 12:29:09 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 201880 kb
Host smart-dd8ecbc3-94d8-4bde-a551-cbb7beb68a5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453089570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1453089570
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4121849932
Short name T667
Test name
Test status
Simulation time 2369686627 ps
CPU time 8.1 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:23 PM PDT 24
Peak memory 201876 kb
Host smart-454e7bf5-a6b1-4d1c-b256-17b4ecb2227f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4121849932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4121849932
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1075284517
Short name T556
Test name
Test status
Simulation time 8931739 ps
CPU time 1.18 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 201888 kb
Host smart-51f9f77c-4e09-45c5-80d5-2e7569fc1748
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075284517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1075284517
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2061443711
Short name T44
Test name
Test status
Simulation time 3211981894 ps
CPU time 13.2 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:29:29 PM PDT 24
Peak memory 201848 kb
Host smart-58001cb8-b721-41a3-a4e6-b22ef0742725
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2061443711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2061443711
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2385489564
Short name T857
Test name
Test status
Simulation time 266435272 ps
CPU time 20.73 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:35 PM PDT 24
Peak memory 201788 kb
Host smart-93e72696-4713-4c3f-9703-15487440f875
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2385489564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2385489564
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2982348105
Short name T642
Test name
Test status
Simulation time 319554557 ps
CPU time 51.82 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 204112 kb
Host smart-242ae746-9954-4ac0-b6b0-6ac1fab399b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2982348105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.2982348105
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1770285684
Short name T461
Test name
Test status
Simulation time 4812538098 ps
CPU time 64.04 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 204968 kb
Host smart-cf04382d-48f2-40af-82e3-a9fd6fe857cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1770285684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.1770285684
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2216685428
Short name T195
Test name
Test status
Simulation time 1856842236 ps
CPU time 7.4 seconds
Started Apr 21 12:29:09 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 201812 kb
Host smart-8213efeb-3b3b-48f5-9366-e88e93a8c9f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2216685428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2216685428
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.682854774
Short name T726
Test name
Test status
Simulation time 1012012140 ps
CPU time 12.76 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:25 PM PDT 24
Peak memory 201804 kb
Host smart-93724403-272c-48c8-9daf-c5ccfc14d6b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682854774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.682854774
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2084675725
Short name T331
Test name
Test status
Simulation time 183366393 ps
CPU time 3.65 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:29:22 PM PDT 24
Peak memory 201808 kb
Host smart-9a005a00-853e-4a78-a787-9a024d21fcfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2084675725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2084675725
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.373040714
Short name T684
Test name
Test status
Simulation time 781615384 ps
CPU time 4.69 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:29:20 PM PDT 24
Peak memory 201812 kb
Host smart-bcbd5046-e0b5-4b19-83a2-d686665b78eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373040714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.373040714
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.3394278112
Short name T718
Test name
Test status
Simulation time 182270923 ps
CPU time 6.45 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:19 PM PDT 24
Peak memory 201832 kb
Host smart-7f446096-702a-4881-82a8-e4ed2df132a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3394278112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3394278112
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.459190226
Short name T416
Test name
Test status
Simulation time 4022973844 ps
CPU time 16.01 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:35 PM PDT 24
Peak memory 201880 kb
Host smart-d2095fee-8b85-41cd-9163-ae42a6f153a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=459190226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.459190226
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3842207559
Short name T120
Test name
Test status
Simulation time 14893830450 ps
CPU time 57.87 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 202024 kb
Host smart-765a2e2e-b7a4-42bb-ad06-e94cf28cc24c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3842207559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3842207559
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.897134020
Short name T674
Test name
Test status
Simulation time 75238857 ps
CPU time 5.79 seconds
Started Apr 21 12:29:17 PM PDT 24
Finished Apr 21 12:29:23 PM PDT 24
Peak memory 201800 kb
Host smart-e7dc0739-2323-4ae2-965c-245aa0752034
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897134020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.897134020
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.4254169891
Short name T441
Test name
Test status
Simulation time 805543789 ps
CPU time 9.37 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:23 PM PDT 24
Peak memory 201796 kb
Host smart-9bdf83bd-175e-4b6e-a216-93a8b8390eca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254169891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4254169891
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.3274713255
Short name T742
Test name
Test status
Simulation time 18553044 ps
CPU time 1.17 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 201812 kb
Host smart-9905d476-5a2a-4348-b9f1-04cfb1ef1dd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3274713255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3274713255
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2200374197
Short name T18
Test name
Test status
Simulation time 10693457913 ps
CPU time 11.15 seconds
Started Apr 21 12:29:16 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 202024 kb
Host smart-030e81a1-5207-41f2-856b-d18130010f12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200374197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2200374197
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.418592372
Short name T566
Test name
Test status
Simulation time 2458788104 ps
CPU time 9.56 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:22 PM PDT 24
Peak memory 201864 kb
Host smart-abedbe5b-c416-476c-904c-e05222833d75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=418592372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.418592372
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.807996966
Short name T898
Test name
Test status
Simulation time 15392903 ps
CPU time 0.96 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201892 kb
Host smart-8dfcb68c-5c22-4634-861c-d6d2ed0d211f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807996966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.807996966
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2171890050
Short name T594
Test name
Test status
Simulation time 815695663 ps
CPU time 18.93 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201912 kb
Host smart-4fa0cdec-3c38-4153-9962-24769677627c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2171890050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2171890050
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2065184792
Short name T358
Test name
Test status
Simulation time 5425909465 ps
CPU time 79.49 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:30:38 PM PDT 24
Peak memory 203004 kb
Host smart-955930fb-014a-4722-89d5-2b14cc797a72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2065184792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2065184792
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.773075868
Short name T241
Test name
Test status
Simulation time 494308505 ps
CPU time 49.26 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:30:09 PM PDT 24
Peak memory 204128 kb
Host smart-ed48b9e7-200d-4e23-af93-174bd2250b46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=773075868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand
_reset.773075868
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1157927192
Short name T95
Test name
Test status
Simulation time 15565871595 ps
CPU time 83.61 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 205268 kb
Host smart-87a174c6-fb57-4f4c-98da-b78188626ca5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1157927192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.1157927192
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.887464627
Short name T776
Test name
Test status
Simulation time 56442371 ps
CPU time 4.66 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 201884 kb
Host smart-1d120779-2786-483c-b6a7-453e79f80d66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=887464627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.887464627
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2754443409
Short name T823
Test name
Test status
Simulation time 4249188363 ps
CPU time 17.97 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201864 kb
Host smart-130d8347-4747-4381-873b-d30a18c9369d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2754443409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2754443409
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2265336196
Short name T221
Test name
Test status
Simulation time 51660959558 ps
CPU time 138.1 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:31:37 PM PDT 24
Peak memory 202704 kb
Host smart-54f8c3d3-bf4a-4d7f-8fed-393fe4954602
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2265336196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.2265336196
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1995407656
Short name T854
Test name
Test status
Simulation time 302214847 ps
CPU time 4.25 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:29:53 PM PDT 24
Peak memory 201864 kb
Host smart-449e4a65-be06-4742-b686-575fff6cf2d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1995407656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1995407656
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.4178260894
Short name T344
Test name
Test status
Simulation time 82339189 ps
CPU time 5.66 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:25 PM PDT 24
Peak memory 201804 kb
Host smart-4672cd82-5876-48aa-96bc-35319c3989cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178260894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4178260894
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.4029413799
Short name T136
Test name
Test status
Simulation time 964787105 ps
CPU time 10.69 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201816 kb
Host smart-5b870e89-c0cf-4f0d-9191-bf1788a8f9b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029413799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4029413799
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3148997627
Short name T820
Test name
Test status
Simulation time 22458786283 ps
CPU time 41.28 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:56 PM PDT 24
Peak memory 202036 kb
Host smart-8093ec6d-b527-4849-b44b-8609ce7f0026
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148997627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3148997627
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.110744147
Short name T387
Test name
Test status
Simulation time 12406544032 ps
CPU time 36.85 seconds
Started Apr 21 12:29:16 PM PDT 24
Finished Apr 21 12:29:53 PM PDT 24
Peak memory 201992 kb
Host smart-e7554f23-d285-4d64-a613-9aea4667ec83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=110744147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.110744147
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2754151211
Short name T847
Test name
Test status
Simulation time 25822812 ps
CPU time 2.03 seconds
Started Apr 21 12:29:15 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 201804 kb
Host smart-be7acf4b-2d16-4f18-b445-a59dafd5c201
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754151211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2754151211
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.3776466916
Short name T410
Test name
Test status
Simulation time 1412536543 ps
CPU time 12.75 seconds
Started Apr 21 12:29:21 PM PDT 24
Finished Apr 21 12:29:34 PM PDT 24
Peak memory 201796 kb
Host smart-f86b77e6-3e65-4484-9722-17298c70c976
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3776466916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3776466916
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3681993240
Short name T582
Test name
Test status
Simulation time 51979121 ps
CPU time 1.32 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201920 kb
Host smart-aeb0c321-0a4e-4992-abc1-24e98885c9b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681993240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3681993240
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2829010428
Short name T696
Test name
Test status
Simulation time 8593787852 ps
CPU time 10.8 seconds
Started Apr 21 12:29:13 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201996 kb
Host smart-c1416698-81a9-4cf3-adbf-5f9c0f26f57b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829010428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2829010428
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1763435376
Short name T717
Test name
Test status
Simulation time 1008275898 ps
CPU time 5.7 seconds
Started Apr 21 12:29:12 PM PDT 24
Finished Apr 21 12:29:18 PM PDT 24
Peak memory 201820 kb
Host smart-005107e6-f26c-40ae-87bc-bbc828dd7bf8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1763435376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1763435376
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2357490448
Short name T817
Test name
Test status
Simulation time 10047313 ps
CPU time 1.09 seconds
Started Apr 21 12:29:14 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201924 kb
Host smart-59db2d3e-5375-41e7-8a8f-137ab62761a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357490448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2357490448
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1901179448
Short name T894
Test name
Test status
Simulation time 432339623 ps
CPU time 51.07 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:30:30 PM PDT 24
Peak memory 202792 kb
Host smart-eb576bc6-cf89-438c-8dd7-8f84f8a7f2d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1901179448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1901179448
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3257839047
Short name T397
Test name
Test status
Simulation time 20379020195 ps
CPU time 111.89 seconds
Started Apr 21 12:29:20 PM PDT 24
Finished Apr 21 12:31:12 PM PDT 24
Peak memory 205020 kb
Host smart-3ddb7457-b047-4f29-a808-b62cd6c3c460
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257839047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3257839047
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3961018890
Short name T249
Test name
Test status
Simulation time 1165895256 ps
CPU time 14.99 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:37 PM PDT 24
Peak memory 202812 kb
Host smart-c35caeae-5867-4cc8-8422-fa309e268e0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3961018890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.3961018890
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2718068299
Short name T393
Test name
Test status
Simulation time 597531228 ps
CPU time 66.36 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 205460 kb
Host smart-f1ecb846-2224-4878-a12d-1652bbb82d51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2718068299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.2718068299
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3287650407
Short name T598
Test name
Test status
Simulation time 84650273 ps
CPU time 2.04 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:29:20 PM PDT 24
Peak memory 201816 kb
Host smart-e400d850-86d4-4df3-a107-59a024f1a786
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3287650407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3287650407
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.387290851
Short name T530
Test name
Test status
Simulation time 2116768407 ps
CPU time 17.72 seconds
Started Apr 21 12:29:20 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201884 kb
Host smart-3f1ec51a-fff4-48ab-9876-893d85136514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=387290851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.387290851
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3285325204
Short name T762
Test name
Test status
Simulation time 39074279789 ps
CPU time 305.25 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:34:25 PM PDT 24
Peak memory 203484 kb
Host smart-ba535853-0ac9-42fe-94a9-a3e88a331502
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3285325204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3285325204
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3087527899
Short name T319
Test name
Test status
Simulation time 64246353 ps
CPU time 5.7 seconds
Started Apr 21 12:29:24 PM PDT 24
Finished Apr 21 12:29:30 PM PDT 24
Peak memory 201764 kb
Host smart-e55615e9-65ba-468c-86ba-8a82afbc05b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087527899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3087527899
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.676852748
Short name T511
Test name
Test status
Simulation time 180126732 ps
CPU time 4.56 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201860 kb
Host smart-849429f9-6f4c-438d-8f2e-0f26862b32c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=676852748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.676852748
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.742647990
Short name T384
Test name
Test status
Simulation time 1696993061 ps
CPU time 13.53 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 201864 kb
Host smart-51b3600c-9e3e-4a63-ad72-cbf66eafb82a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742647990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.742647990
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2692336084
Short name T509
Test name
Test status
Simulation time 67096657309 ps
CPU time 142.4 seconds
Started Apr 21 12:29:17 PM PDT 24
Finished Apr 21 12:31:40 PM PDT 24
Peak memory 202024 kb
Host smart-5c465eca-0d07-4c68-bf35-1dba30869d70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692336084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2692336084
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1723359633
Short name T261
Test name
Test status
Simulation time 1908043817 ps
CPU time 11.15 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201796 kb
Host smart-0b3f8fa6-7297-4ac5-bbe0-4be64f9a989c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1723359633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1723359633
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4088375141
Short name T607
Test name
Test status
Simulation time 100958043 ps
CPU time 8.51 seconds
Started Apr 21 12:29:18 PM PDT 24
Finished Apr 21 12:29:27 PM PDT 24
Peak memory 201796 kb
Host smart-ba9a778a-bcbc-45ad-9a7a-18e489eda45d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088375141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4088375141
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.886082815
Short name T439
Test name
Test status
Simulation time 814508314 ps
CPU time 4.45 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:39 PM PDT 24
Peak memory 201856 kb
Host smart-49b44d67-7517-4041-8632-24f0c3ee3609
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=886082815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.886082815
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.35658775
Short name T421
Test name
Test status
Simulation time 10270383 ps
CPU time 1.04 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 201764 kb
Host smart-1405ea95-8bcc-4d9e-a820-10316ed11339
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35658775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.35658775
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1821412524
Short name T725
Test name
Test status
Simulation time 1293256012 ps
CPU time 6.41 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:26 PM PDT 24
Peak memory 201812 kb
Host smart-492b5040-dc80-4d2e-8ba4-0b241d095752
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821412524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1821412524
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.448400847
Short name T101
Test name
Test status
Simulation time 1955563043 ps
CPU time 5.35 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201844 kb
Host smart-021d7d2b-0505-461e-b25a-a30bdeb8dc23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=448400847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.448400847
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2307905315
Short name T760
Test name
Test status
Simulation time 9336855 ps
CPU time 1.2 seconds
Started Apr 21 12:29:17 PM PDT 24
Finished Apr 21 12:29:18 PM PDT 24
Peak memory 201788 kb
Host smart-799e7b32-7b8b-468a-bdcd-713c65c1e81a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307905315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2307905315
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.807464651
Short name T374
Test name
Test status
Simulation time 205621824 ps
CPU time 10.47 seconds
Started Apr 21 12:29:24 PM PDT 24
Finished Apr 21 12:29:35 PM PDT 24
Peak memory 201768 kb
Host smart-626cde1d-7279-4b35-a91c-b75654cc5611
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=807464651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.807464651
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.588149211
Short name T626
Test name
Test status
Simulation time 1568341270 ps
CPU time 33.42 seconds
Started Apr 21 12:29:19 PM PDT 24
Finished Apr 21 12:29:53 PM PDT 24
Peak memory 201892 kb
Host smart-569f3f15-99ac-4a28-94e6-c210facf59f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=588149211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.588149211
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4213684547
Short name T867
Test name
Test status
Simulation time 727784368 ps
CPU time 69.78 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:30:45 PM PDT 24
Peak memory 204660 kb
Host smart-4f20cc15-52ea-430d-97d1-7a7d843d19e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4213684547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.4213684547
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1946933035
Short name T596
Test name
Test status
Simulation time 12853351 ps
CPU time 1.34 seconds
Started Apr 21 12:29:29 PM PDT 24
Finished Apr 21 12:29:31 PM PDT 24
Peak memory 201864 kb
Host smart-75878060-38ef-4f6b-afd4-734c2d0306b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1946933035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1946933035
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2124173303
Short name T159
Test name
Test status
Simulation time 6894527541 ps
CPU time 16.78 seconds
Started Apr 21 12:29:29 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201952 kb
Host smart-a335f997-79c1-4016-9896-bcee08889c16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124173303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2124173303
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.734332554
Short name T893
Test name
Test status
Simulation time 49676525951 ps
CPU time 289.61 seconds
Started Apr 21 12:29:27 PM PDT 24
Finished Apr 21 12:34:17 PM PDT 24
Peak memory 203968 kb
Host smart-1326cc61-0a1b-4c0a-9217-8e0481d4c68a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=734332554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo
w_rsp.734332554
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.490273710
Short name T204
Test name
Test status
Simulation time 1053882572 ps
CPU time 4.15 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:29:35 PM PDT 24
Peak memory 201816 kb
Host smart-50b4e4b7-2a8d-45fe-a6d8-03aba1bd77c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=490273710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.490273710
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.4142506618
Short name T210
Test name
Test status
Simulation time 448198577 ps
CPU time 8.43 seconds
Started Apr 21 12:29:24 PM PDT 24
Finished Apr 21 12:29:33 PM PDT 24
Peak memory 201792 kb
Host smart-16d2dca4-1df6-401c-8a30-c6855e865f1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4142506618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4142506618
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1789956944
Short name T622
Test name
Test status
Simulation time 335719946 ps
CPU time 1.36 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 200400 kb
Host smart-b58bb5ff-7a9b-4cac-a069-184d7d7c9691
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1789956944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1789956944
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.931485380
Short name T758
Test name
Test status
Simulation time 19666261950 ps
CPU time 70.56 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201924 kb
Host smart-e9a262b1-48c2-4fb5-a4ab-f052dd3bd90a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=931485380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.931485380
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2690554043
Short name T704
Test name
Test status
Simulation time 25937332533 ps
CPU time 145.94 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:31:58 PM PDT 24
Peak memory 201940 kb
Host smart-ad3eb5bd-dd65-41a5-a977-d00dacd4ace6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2690554043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2690554043
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2024673817
Short name T134
Test name
Test status
Simulation time 40138337 ps
CPU time 2.76 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:26 PM PDT 24
Peak memory 201820 kb
Host smart-874e9849-8680-4607-ab5a-a04da8ebed63
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024673817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2024673817
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.1477676530
Short name T615
Test name
Test status
Simulation time 4347802055 ps
CPU time 10.79 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:33 PM PDT 24
Peak memory 201912 kb
Host smart-f2f551e0-1c9e-40f6-8889-aad2eecf9018
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1477676530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1477676530
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.168187226
Short name T365
Test name
Test status
Simulation time 26349681 ps
CPU time 1.06 seconds
Started Apr 21 12:29:27 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 201768 kb
Host smart-3ac2bd2c-e852-4712-b41c-27e8648f8458
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=168187226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.168187226
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2202918330
Short name T64
Test name
Test status
Simulation time 2357863008 ps
CPU time 8.18 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201868 kb
Host smart-ce031453-3be5-4f00-a2e9-46ac088ed45a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202918330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2202918330
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2297830423
Short name T827
Test name
Test status
Simulation time 1483303594 ps
CPU time 9.37 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201912 kb
Host smart-beb6916f-ab1c-4e28-8f01-488c009ff40e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2297830423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2297830423
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3088044016
Short name T520
Test name
Test status
Simulation time 10302923 ps
CPU time 1.37 seconds
Started Apr 21 12:29:25 PM PDT 24
Finished Apr 21 12:29:27 PM PDT 24
Peak memory 201816 kb
Host smart-5ec05d0e-8ed1-4c11-b139-ab066256d854
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088044016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3088044016
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.4025720041
Short name T472
Test name
Test status
Simulation time 2437642514 ps
CPU time 41.85 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:30:20 PM PDT 24
Peak memory 203016 kb
Host smart-8c153ed2-5034-404e-b473-fbfc1ae2c955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4025720041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4025720041
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3713110678
Short name T323
Test name
Test status
Simulation time 373234608 ps
CPU time 5.21 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 201808 kb
Host smart-9b341148-5938-4fc9-9584-8d0e5afbf8a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3713110678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3713110678
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1659408855
Short name T180
Test name
Test status
Simulation time 3654142798 ps
CPU time 44.82 seconds
Started Apr 21 12:29:27 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 203928 kb
Host smart-4801eed8-4d74-423f-99a2-ea6fa36899bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1659408855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.1659408855
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2096576919
Short name T72
Test name
Test status
Simulation time 418108622 ps
CPU time 20.91 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 202860 kb
Host smart-6c84b9f5-a8ee-4505-98e3-5f01b8013d83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2096576919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2096576919
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1669767532
Short name T710
Test name
Test status
Simulation time 819727144 ps
CPU time 11.33 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201804 kb
Host smart-2c9659fb-0b7b-4775-8e5c-87054b8c8011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1669767532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1669767532
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1131741333
Short name T48
Test name
Test status
Simulation time 50376314 ps
CPU time 8.96 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201860 kb
Host smart-0b4128f1-35fa-4108-8eb4-626738912d19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1131741333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1131741333
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.868048312
Short name T225
Test name
Test status
Simulation time 27955584150 ps
CPU time 133.58 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:31:45 PM PDT 24
Peak memory 202020 kb
Host smart-8d85e5f1-fcd5-408a-ac70-536ba0bc102e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=868048312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.868048312
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3858269561
Short name T506
Test name
Test status
Simulation time 1056377751 ps
CPU time 8.9 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201916 kb
Host smart-0e850ad0-a08b-4d2c-bd6d-691be34caa23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3858269561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3858269561
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.903051983
Short name T290
Test name
Test status
Simulation time 17469866 ps
CPU time 1.72 seconds
Started Apr 21 12:29:31 PM PDT 24
Finished Apr 21 12:29:33 PM PDT 24
Peak memory 201912 kb
Host smart-eeb2385f-e9f0-46b9-88a2-69f7999c6655
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903051983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.903051983
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1550531936
Short name T575
Test name
Test status
Simulation time 3953022475 ps
CPU time 16.08 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201860 kb
Host smart-99336c16-3e15-4e48-9b31-acdb8d48dd29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1550531936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1550531936
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.647337476
Short name T73
Test name
Test status
Simulation time 10378184649 ps
CPU time 42.33 seconds
Started Apr 21 12:29:25 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201992 kb
Host smart-43c8c294-74d7-48e2-afe1-7d2c727562f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=647337476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.647337476
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3855151752
Short name T187
Test name
Test status
Simulation time 1496974924 ps
CPU time 5.49 seconds
Started Apr 21 12:29:36 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201812 kb
Host smart-6fcf7d7a-a652-4a6d-9513-5334df4dfe2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3855151752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3855151752
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.958526847
Short name T801
Test name
Test status
Simulation time 27123631 ps
CPU time 1.57 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:24 PM PDT 24
Peak memory 201816 kb
Host smart-95b7020a-320a-4262-a3d8-9aecd3e7b1fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958526847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.958526847
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.248629703
Short name T444
Test name
Test status
Simulation time 907668605 ps
CPU time 12.82 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:29:39 PM PDT 24
Peak memory 201772 kb
Host smart-a1d54b15-6455-4336-b467-0856386b225d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=248629703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.248629703
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.2183927650
Short name T481
Test name
Test status
Simulation time 73217582 ps
CPU time 1.44 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201928 kb
Host smart-ebc29c4a-d46b-4100-bd1f-6543cf27c78d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2183927650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2183927650
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.926802298
Short name T645
Test name
Test status
Simulation time 1438281473 ps
CPU time 6.2 seconds
Started Apr 21 12:29:21 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 201896 kb
Host smart-c872b273-037b-48fb-bbca-fd66fb4b5e25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=926802298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.926802298
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4280914349
Short name T680
Test name
Test status
Simulation time 5483550230 ps
CPU time 9.68 seconds
Started Apr 21 12:29:23 PM PDT 24
Finished Apr 21 12:29:33 PM PDT 24
Peak memory 201980 kb
Host smart-99869549-696a-4c3f-bcb0-c89fd8b611c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4280914349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4280914349
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2790863827
Short name T748
Test name
Test status
Simulation time 9045978 ps
CPU time 1.02 seconds
Started Apr 21 12:29:29 PM PDT 24
Finished Apr 21 12:29:30 PM PDT 24
Peak memory 201892 kb
Host smart-9e8d462c-1679-4d37-9e5e-c1a2e0846d20
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790863827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2790863827
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2476239466
Short name T113
Test name
Test status
Simulation time 10528984704 ps
CPU time 50.31 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:31:18 PM PDT 24
Peak memory 201596 kb
Host smart-675fee1c-8931-4d95-ad73-285a0dee50cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2476239466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2476239466
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1904857511
Short name T324
Test name
Test status
Simulation time 165182418 ps
CPU time 1.65 seconds
Started Apr 21 12:29:31 PM PDT 24
Finished Apr 21 12:29:33 PM PDT 24
Peak memory 201784 kb
Host smart-14cc22d9-9ee0-411c-9dd5-a114d89f1437
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1904857511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1904857511
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4291489885
Short name T121
Test name
Test status
Simulation time 6058186672 ps
CPU time 65.75 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:30:33 PM PDT 24
Peak memory 203940 kb
Host smart-14a76dc2-488a-4282-adb1-d8cc2854d262
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4291489885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.4291489885
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3309006742
Short name T720
Test name
Test status
Simulation time 3644947838 ps
CPU time 70.47 seconds
Started Apr 21 12:29:25 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 204620 kb
Host smart-17cb973f-83d8-4508-8dbb-bba1e8173008
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3309006742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3309006742
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2434950411
Short name T190
Test name
Test status
Simulation time 26599519 ps
CPU time 1.21 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:40 PM PDT 24
Peak memory 201892 kb
Host smart-d6a82c05-150f-4767-a42f-17654730e35a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2434950411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2434950411
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1786137925
Short name T285
Test name
Test status
Simulation time 603051586 ps
CPU time 10.25 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201860 kb
Host smart-458a6c94-8ad0-48b5-8e71-47da51e9fb8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786137925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1786137925
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1118492903
Short name T705
Test name
Test status
Simulation time 108936150372 ps
CPU time 241.67 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:33:34 PM PDT 24
Peak memory 203404 kb
Host smart-63e2b902-e1d9-4dbd-a1e4-26a361bb53df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1118492903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.1118492903
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.258150109
Short name T186
Test name
Test status
Simulation time 51384040 ps
CPU time 1.15 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:29:36 PM PDT 24
Peak memory 201892 kb
Host smart-31621afb-46b2-4175-adc6-7d4bf1f91476
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258150109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.258150109
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.2850874619
Short name T783
Test name
Test status
Simulation time 63608224 ps
CPU time 6.07 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201788 kb
Host smart-e03c9caa-97bc-45ff-955f-b5c3ab7dd76e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2850874619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2850874619
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3808452568
Short name T652
Test name
Test status
Simulation time 498612952 ps
CPU time 7.45 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201672 kb
Host smart-1be547de-d45f-4b05-938b-28fd8e617301
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3808452568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3808452568
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2304921265
Short name T874
Test name
Test status
Simulation time 27697872713 ps
CPU time 19.45 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 201928 kb
Host smart-fedb2649-3da6-4153-96fd-44d16b3e265b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304921265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2304921265
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.140092417
Short name T739
Test name
Test status
Simulation time 1336076542 ps
CPU time 10.48 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201904 kb
Host smart-10794ef5-a373-488e-9ce0-5c6d5007795d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=140092417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.140092417
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.600637084
Short name T396
Test name
Test status
Simulation time 217626585 ps
CPU time 5.41 seconds
Started Apr 21 12:29:22 PM PDT 24
Finished Apr 21 12:29:28 PM PDT 24
Peak memory 201792 kb
Host smart-e238e72d-ad2b-4429-9acd-128c0269dd0f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600637084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.600637084
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3500935326
Short name T168
Test name
Test status
Simulation time 837594587 ps
CPU time 11.08 seconds
Started Apr 21 12:29:41 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201848 kb
Host smart-6ee3221d-0742-4bb5-8f67-0faf0297a529
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3500935326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3500935326
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.1044012339
Short name T855
Test name
Test status
Simulation time 8315398 ps
CPU time 1.15 seconds
Started Apr 21 12:29:28 PM PDT 24
Finished Apr 21 12:29:30 PM PDT 24
Peak memory 201888 kb
Host smart-fb9a57cb-0964-434a-81fd-a92dc24a295f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1044012339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1044012339
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3936238082
Short name T625
Test name
Test status
Simulation time 2851495938 ps
CPU time 11.01 seconds
Started Apr 21 12:29:53 PM PDT 24
Finished Apr 21 12:30:05 PM PDT 24
Peak memory 201752 kb
Host smart-6b06d07f-e3aa-440b-95ee-9371b8560c1d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936238082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3936238082
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1867710365
Short name T548
Test name
Test status
Simulation time 1461799671 ps
CPU time 10.39 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:29:37 PM PDT 24
Peak memory 201900 kb
Host smart-1a66d093-77b1-4ef9-8682-68ce59c8d449
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1867710365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1867710365
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1328617866
Short name T418
Test name
Test status
Simulation time 10532907 ps
CPU time 1.13 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:29:32 PM PDT 24
Peak memory 201804 kb
Host smart-3842be28-4529-430b-a84c-5e80037f0598
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328617866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1328617866
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.2909837248
Short name T17
Test name
Test status
Simulation time 20237035 ps
CPU time 1.8 seconds
Started Apr 21 12:29:31 PM PDT 24
Finished Apr 21 12:29:34 PM PDT 24
Peak memory 201836 kb
Host smart-a578b7c0-78d7-4af5-afc7-10462a1db03a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2909837248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2909837248
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1026030792
Short name T805
Test name
Test status
Simulation time 96543029 ps
CPU time 5.36 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201772 kb
Host smart-5e8fd024-597c-4262-9742-d990e9f157c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1026030792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1026030792
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3454299266
Short name T735
Test name
Test status
Simulation time 1193328235 ps
CPU time 164.23 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:32:17 PM PDT 24
Peak memory 206124 kb
Host smart-29fd6cdf-d19f-4ab7-8d7d-d2fb73e6d333
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454299266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.3454299266
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1782213328
Short name T573
Test name
Test status
Simulation time 573151035 ps
CPU time 51 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:31:33 PM PDT 24
Peak memory 203896 kb
Host smart-5992bce2-16fb-4d95-9c2a-d34d82bb29f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1782213328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1782213328
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3416532967
Short name T335
Test name
Test status
Simulation time 293639609 ps
CPU time 5.29 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201908 kb
Host smart-4532fabc-7c5e-4531-8fd6-4f7a2b72492b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3416532967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3416532967
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1752672208
Short name T491
Test name
Test status
Simulation time 102477222 ps
CPU time 1.66 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 201780 kb
Host smart-be3d08ab-8184-4606-b635-d5ea1f922e01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752672208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1752672208
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2374473898
Short name T676
Test name
Test status
Simulation time 58232427273 ps
CPU time 314.58 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:34:00 PM PDT 24
Peak memory 204044 kb
Host smart-ccef83b2-8fa3-406a-9cbf-f2ee906aaad7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2374473898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.2374473898
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1414968544
Short name T775
Test name
Test status
Simulation time 59053475 ps
CPU time 3.25 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:28:44 PM PDT 24
Peak memory 201848 kb
Host smart-56271c06-39f8-4da3-9e29-355deed786c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1414968544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1414968544
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.2156561690
Short name T889
Test name
Test status
Simulation time 41009040 ps
CPU time 4.12 seconds
Started Apr 21 12:28:40 PM PDT 24
Finished Apr 21 12:28:45 PM PDT 24
Peak memory 201816 kb
Host smart-67781bae-af9a-4343-8a29-3d0046fe560a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2156561690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2156561690
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.3666128563
Short name T838
Test name
Test status
Simulation time 4821071519 ps
CPU time 15.19 seconds
Started Apr 21 12:28:38 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201932 kb
Host smart-0c175e12-c3d4-4812-9720-b8b215ca47b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3666128563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3666128563
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.684145818
Short name T477
Test name
Test status
Simulation time 20299505106 ps
CPU time 66.3 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201980 kb
Host smart-ded9cefe-c9da-45db-94c1-026491edd2a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=684145818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.684145818
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.109540053
Short name T300
Test name
Test status
Simulation time 21594894752 ps
CPU time 112.44 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 202000 kb
Host smart-d7882d2d-e193-412c-a60b-6253e84d3848
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=109540053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.109540053
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3493092160
Short name T562
Test name
Test status
Simulation time 76416279 ps
CPU time 7.51 seconds
Started Apr 21 12:28:39 PM PDT 24
Finished Apr 21 12:28:47 PM PDT 24
Peak memory 201812 kb
Host smart-52fdbdac-a376-4c21-8872-1be6cce08510
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493092160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3493092160
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.799828281
Short name T280
Test name
Test status
Simulation time 1829408246 ps
CPU time 6.63 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 201776 kb
Host smart-1109efe0-777f-4c11-8af5-a2c98e654411
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=799828281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.799828281
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.54022362
Short name T841
Test name
Test status
Simulation time 9496446 ps
CPU time 1.19 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:43 PM PDT 24
Peak memory 201884 kb
Host smart-3c079cfc-5949-454b-9623-c18cff8ddabe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54022362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.54022362
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4223672737
Short name T473
Test name
Test status
Simulation time 4823757390 ps
CPU time 10.25 seconds
Started Apr 21 12:28:38 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 202020 kb
Host smart-59d6c221-9933-4367-ab43-1d92aaca940f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223672737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4223672737
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2982705130
Short name T192
Test name
Test status
Simulation time 969772403 ps
CPU time 7.24 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 201820 kb
Host smart-6bffd092-0ff4-4730-a7dd-990c38e40848
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2982705130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2982705130
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1460090424
Short name T39
Test name
Test status
Simulation time 10129665 ps
CPU time 1.61 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:43 PM PDT 24
Peak memory 201792 kb
Host smart-4bedf681-94c9-4d40-b5d1-efc893190bb3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460090424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1460090424
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2256094813
Short name T71
Test name
Test status
Simulation time 5371737181 ps
CPU time 51.33 seconds
Started Apr 21 12:28:37 PM PDT 24
Finished Apr 21 12:29:29 PM PDT 24
Peak memory 204776 kb
Host smart-0e1983f2-e8fa-4e32-bd5f-a64fda4992cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256094813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2256094813
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4073354752
Short name T864
Test name
Test status
Simulation time 5497547611 ps
CPU time 30.92 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:29:13 PM PDT 24
Peak memory 201908 kb
Host smart-bd2f05e6-99c3-4dee-bbca-3f2cb0a70cba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4073354752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4073354752
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3666152308
Short name T6
Test name
Test status
Simulation time 2258592047 ps
CPU time 104.84 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:30:26 PM PDT 24
Peak memory 206204 kb
Host smart-5cf91845-852f-4942-886e-38ed6c5dd677
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3666152308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3666152308
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2495669581
Short name T459
Test name
Test status
Simulation time 1750445693 ps
CPU time 69.17 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 203880 kb
Host smart-22028b48-a5ab-4c1a-9660-5a9ac33e9f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2495669581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.2495669581
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1448195297
Short name T807
Test name
Test status
Simulation time 54950006 ps
CPU time 3.2 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:45 PM PDT 24
Peak memory 201792 kb
Host smart-a0f331a1-1bfe-4034-a2f5-2c10b9cae102
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448195297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1448195297
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3502718875
Short name T630
Test name
Test status
Simulation time 319213489 ps
CPU time 2.48 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201816 kb
Host smart-f1eaf1fd-c9b4-45d5-96ec-6ff5a9e1e10d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502718875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3502718875
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3922461298
Short name T633
Test name
Test status
Simulation time 26740334821 ps
CPU time 195.81 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:32:48 PM PDT 24
Peak memory 203040 kb
Host smart-25a79a89-d7f0-41b7-9f09-fece0a64bd2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3922461298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3922461298
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.290736670
Short name T284
Test name
Test status
Simulation time 12923980 ps
CPU time 1.12 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:36 PM PDT 24
Peak memory 201856 kb
Host smart-8fd60ffe-2b18-496e-b0b1-dd2b37cdfd1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=290736670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.290736670
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.3889035437
Short name T662
Test name
Test status
Simulation time 2406359533 ps
CPU time 12.16 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201848 kb
Host smart-bf82e7d6-3cc3-4a02-98cf-e1e660c4705f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889035437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3889035437
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.906365906
Short name T269
Test name
Test status
Simulation time 3072383790 ps
CPU time 11.69 seconds
Started Apr 21 12:29:31 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201876 kb
Host smart-ab222e0d-9dc2-4b00-9b10-4447592cdf80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=906365906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.906365906
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2580082667
Short name T528
Test name
Test status
Simulation time 14176079134 ps
CPU time 92.18 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:31:07 PM PDT 24
Peak memory 201940 kb
Host smart-d0e9607b-a04b-4323-8754-64bb7325a6b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2580082667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2580082667
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1865353296
Short name T340
Test name
Test status
Simulation time 99471328 ps
CPU time 7.78 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201844 kb
Host smart-95e9bd1c-d533-4e89-b95e-2f0df81c9de5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865353296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1865353296
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3770547702
Short name T716
Test name
Test status
Simulation time 812619946 ps
CPU time 9.44 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201792 kb
Host smart-478cfdf8-db42-4a41-9f38-7ffe2c3a60e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3770547702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3770547702
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.3639755079
Short name T173
Test name
Test status
Simulation time 68782006 ps
CPU time 1.51 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201908 kb
Host smart-587f8c13-d3fc-4252-949b-d2631a46b688
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3639755079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3639755079
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3309350336
Short name T677
Test name
Test status
Simulation time 2113346953 ps
CPU time 10.06 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201904 kb
Host smart-39cd316d-e081-45e5-a233-5df13af89ba7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309350336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3309350336
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3363913861
Short name T813
Test name
Test status
Simulation time 3067205796 ps
CPU time 11.13 seconds
Started Apr 21 12:29:32 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201896 kb
Host smart-9e982292-406f-4365-86ca-043c20a3afec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3363913861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3363913861
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2599683420
Short name T106
Test name
Test status
Simulation time 8816736 ps
CPU time 1.15 seconds
Started Apr 21 12:29:26 PM PDT 24
Finished Apr 21 12:29:27 PM PDT 24
Peak memory 201804 kb
Host smart-b2ed0935-843f-410a-b27d-c08ee05f77ae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599683420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2599683420
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3807788661
Short name T287
Test name
Test status
Simulation time 220410115 ps
CPU time 8.73 seconds
Started Apr 21 12:29:36 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201808 kb
Host smart-680a1224-6e1e-405e-90ff-6c5d87d98ac1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3807788661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3807788661
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3062720187
Short name T651
Test name
Test status
Simulation time 156275366 ps
CPU time 16.62 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 201892 kb
Host smart-6411c8c1-47ff-49f6-a33e-c255a6412fb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3062720187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3062720187
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.957053855
Short name T505
Test name
Test status
Simulation time 470213417 ps
CPU time 42 seconds
Started Apr 21 12:29:27 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 204136 kb
Host smart-01035408-1222-4649-876b-10148924c01b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=957053855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.957053855
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3620089126
Short name T529
Test name
Test status
Simulation time 5988857471 ps
CPU time 133.05 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:32:56 PM PDT 24
Peak memory 205352 kb
Host smart-17a6f3b1-ee1a-4faa-b051-9ed8987eed7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3620089126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.3620089126
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1639516706
Short name T844
Test name
Test status
Simulation time 68561213 ps
CPU time 4.37 seconds
Started Apr 21 12:29:30 PM PDT 24
Finished Apr 21 12:29:35 PM PDT 24
Peak memory 201780 kb
Host smart-fb027462-7454-4a56-b1dd-7bfd3ac888ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1639516706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1639516706
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3529756342
Short name T198
Test name
Test status
Simulation time 100295502 ps
CPU time 2.59 seconds
Started Apr 21 12:29:36 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 201816 kb
Host smart-9517ec43-ed3d-4cd3-9e6f-36519bfb95ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3529756342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3529756342
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2241283608
Short name T47
Test name
Test status
Simulation time 44827358084 ps
CPU time 336.87 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:35:28 PM PDT 24
Peak memory 203040 kb
Host smart-1ad50ca6-26a2-4b1f-bfb5-de112e182dd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2241283608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2241283608
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3678701691
Short name T258
Test name
Test status
Simulation time 1635765027 ps
CPU time 5.05 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201800 kb
Host smart-9ff22dc1-58ab-4b84-9d2b-b683df3228a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3678701691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3678701691
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.217499740
Short name T614
Test name
Test status
Simulation time 745760630 ps
CPU time 8.98 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201856 kb
Host smart-068033c8-7bc9-461a-88d4-f7fa27670258
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=217499740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.217499740
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.3867654526
Short name T781
Test name
Test status
Simulation time 3667056046 ps
CPU time 10.49 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201960 kb
Host smart-b7864d4b-4d03-46c6-9a51-25f0dc884111
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3867654526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3867654526
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2993598414
Short name T727
Test name
Test status
Simulation time 38430949359 ps
CPU time 114.42 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:31:33 PM PDT 24
Peak memory 201988 kb
Host smart-8db12ecd-6da7-4a9a-a712-2dc94f35cb73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993598414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2993598414
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1552548711
Short name T167
Test name
Test status
Simulation time 9166624663 ps
CPU time 56.87 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:30:43 PM PDT 24
Peak memory 201968 kb
Host smart-3d710b06-b069-4a9e-8dd3-3dff3eef13ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1552548711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1552548711
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2481543229
Short name T534
Test name
Test status
Simulation time 133675782 ps
CPU time 5.25 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201888 kb
Host smart-bfeee7f1-e3b8-4357-aba9-c7728a4bbf2f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481543229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2481543229
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.475336730
Short name T695
Test name
Test status
Simulation time 989089666 ps
CPU time 4.85 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201908 kb
Host smart-d558d263-b826-4818-81ae-d36ea417655d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=475336730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.475336730
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.4156498524
Short name T40
Test name
Test status
Simulation time 11793035 ps
CPU time 1.1 seconds
Started Apr 21 12:29:34 PM PDT 24
Finished Apr 21 12:29:36 PM PDT 24
Peak memory 201840 kb
Host smart-b1901333-2224-4b3b-ac61-60adba5e6480
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4156498524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4156498524
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.788426649
Short name T338
Test name
Test status
Simulation time 7454854723 ps
CPU time 8.37 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201956 kb
Host smart-7eab6a58-a79a-402a-bfe5-740dc1b52175
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=788426649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.788426649
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3120785669
Short name T476
Test name
Test status
Simulation time 3045744282 ps
CPU time 7.47 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:30:56 PM PDT 24
Peak memory 201736 kb
Host smart-ce74e23d-8a78-49e3-b90e-dbf09921be5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3120785669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3120785669
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.100653811
Short name T488
Test name
Test status
Simulation time 21876342 ps
CPU time 1.11 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201804 kb
Host smart-d6f99f40-6638-47f9-a05a-e732b06845d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100653811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.100653811
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3780197089
Short name T281
Test name
Test status
Simulation time 937580574 ps
CPU time 7.2 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:29:40 PM PDT 24
Peak memory 201908 kb
Host smart-dc01c718-2c8e-4095-84b1-9eb2974aebab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3780197089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3780197089
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2156097156
Short name T471
Test name
Test status
Simulation time 823947931 ps
CPU time 21.09 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:30:02 PM PDT 24
Peak memory 201904 kb
Host smart-99d8c6ef-7cde-4ad3-b415-1ab165d18524
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2156097156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2156097156
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3820399279
Short name T38
Test name
Test status
Simulation time 4858287883 ps
CPU time 151.06 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:32:08 PM PDT 24
Peak memory 206388 kb
Host smart-0371b691-b1e6-45b4-b744-52e1c7834011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820399279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.3820399279
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1012036150
Short name T558
Test name
Test status
Simulation time 10020035502 ps
CPU time 120.72 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:31:40 PM PDT 24
Peak memory 204936 kb
Host smart-258ab094-dc75-4327-8ca1-bc417d53184e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012036150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.1012036150
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2107984966
Short name T829
Test name
Test status
Simulation time 33297403 ps
CPU time 1.89 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201808 kb
Host smart-0d08c889-8b44-404b-aecc-2e714e98477b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2107984966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2107984966
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1143899127
Short name T658
Test name
Test status
Simulation time 366703689 ps
CPU time 8.22 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:49 PM PDT 24
Peak memory 201896 kb
Host smart-78539a75-fb3c-4f58-95ef-2c162a50bcc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1143899127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1143899127
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1148028258
Short name T36
Test name
Test status
Simulation time 2941786146 ps
CPU time 15.63 seconds
Started Apr 21 12:29:35 PM PDT 24
Finished Apr 21 12:29:51 PM PDT 24
Peak memory 201840 kb
Host smart-766631cd-768f-4102-8c23-8489cbb1d2db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1148028258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.1148028258
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3015974947
Short name T877
Test name
Test status
Simulation time 63392066 ps
CPU time 5.45 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201804 kb
Host smart-1ddacffc-207d-4ba9-b56a-13df9f87b3fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3015974947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3015974947
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1147338164
Short name T860
Test name
Test status
Simulation time 1134281968 ps
CPU time 9.54 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:49 PM PDT 24
Peak memory 201672 kb
Host smart-336bf4d2-550c-4b2e-b4b6-725289a8e1ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1147338164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1147338164
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.3545913152
Short name T125
Test name
Test status
Simulation time 92887491 ps
CPU time 2.64 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201816 kb
Host smart-b4e2f184-d776-4cdc-b7b4-a34d298f0de1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545913152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3545913152
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2796268971
Short name T407
Test name
Test status
Simulation time 24606292166 ps
CPU time 102.7 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:31:23 PM PDT 24
Peak memory 201936 kb
Host smart-1fb45ab3-10f8-49c2-9a9f-6ddbace06aad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796268971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2796268971
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.341396992
Short name T579
Test name
Test status
Simulation time 98088946812 ps
CPU time 102.37 seconds
Started Apr 21 12:29:33 PM PDT 24
Finished Apr 21 12:31:16 PM PDT 24
Peak memory 202036 kb
Host smart-251a63c8-8013-4862-aec1-e82bcb59a2a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=341396992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.341396992
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.270419419
Short name T454
Test name
Test status
Simulation time 24358078 ps
CPU time 1.35 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:40 PM PDT 24
Peak memory 201852 kb
Host smart-af27ea9e-4670-4cd1-8a87-53bce774a564
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270419419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.270419419
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1979039000
Short name T819
Test name
Test status
Simulation time 80036194 ps
CPU time 6.01 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201796 kb
Host smart-e6fe03e9-528a-41fe-b6f2-b82c30877c42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979039000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1979039000
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.1397948208
Short name T690
Test name
Test status
Simulation time 13666547 ps
CPU time 1.21 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201796 kb
Host smart-15388849-4ffe-4447-970a-274420a4f68f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1397948208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1397948208
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2102745732
Short name T685
Test name
Test status
Simulation time 8935455959 ps
CPU time 15.06 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201916 kb
Host smart-6d0786dc-e808-4330-af73-15e0c7a1f2c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102745732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2102745732
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1566090460
Short name T693
Test name
Test status
Simulation time 5692351614 ps
CPU time 6.32 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201936 kb
Host smart-01c263d0-8089-4643-ac0a-a33173f37a74
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1566090460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1566090460
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.351919552
Short name T43
Test name
Test status
Simulation time 8038340 ps
CPU time 1.04 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:39 PM PDT 24
Peak memory 201780 kb
Host smart-82f25b25-98a4-45ac-9a78-9977cfe2c7f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351919552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.351919552
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3895151603
Short name T449
Test name
Test status
Simulation time 1019892580 ps
CPU time 59.93 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 204104 kb
Host smart-8a4b27f4-8eca-483d-ae03-78623a4f3641
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3895151603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3895151603
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.4065721314
Short name T886
Test name
Test status
Simulation time 42735353 ps
CPU time 1.23 seconds
Started Apr 21 12:29:41 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201776 kb
Host smart-ce5a0521-7548-463a-9982-9c541b5c54c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4065721314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4065721314
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1804576950
Short name T178
Test name
Test status
Simulation time 135693365 ps
CPU time 12.42 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:30:55 PM PDT 24
Peak memory 201652 kb
Host smart-7cd720d2-671c-447f-a87b-2760a93e42b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804576950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1804576950
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1455511354
Short name T242
Test name
Test status
Simulation time 9042767080 ps
CPU time 138.07 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:31:58 PM PDT 24
Peak memory 207316 kb
Host smart-a7ba69b9-03cd-4ab6-b990-6403bfc81654
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1455511354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.1455511354
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.546164773
Short name T42
Test name
Test status
Simulation time 761052464 ps
CPU time 3.9 seconds
Started Apr 21 12:29:42 PM PDT 24
Finished Apr 21 12:29:46 PM PDT 24
Peak memory 201788 kb
Host smart-07c98f31-9700-4f00-92f9-b715c3fe171e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=546164773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.546164773
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3017919272
Short name T170
Test name
Test status
Simulation time 64607525 ps
CPU time 9.89 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201668 kb
Host smart-001b0749-963c-4b57-833c-cfc62f48cc00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3017919272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3017919272
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3239680901
Short name T610
Test name
Test status
Simulation time 29635462120 ps
CPU time 214.79 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:33:12 PM PDT 24
Peak memory 203052 kb
Host smart-c4b70b92-3d61-4b5e-bf67-9cc1d8bdc0a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3239680901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.3239680901
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3681335851
Short name T628
Test name
Test status
Simulation time 2066902679 ps
CPU time 12.47 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 201836 kb
Host smart-0730a4f4-026d-4c77-9a20-a485c83b940c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681335851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3681335851
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.2968782818
Short name T260
Test name
Test status
Simulation time 419536827 ps
CPU time 5.78 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:30:00 PM PDT 24
Peak memory 201712 kb
Host smart-20711d06-a992-4744-80de-f234315ff3ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2968782818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2968782818
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1641591266
Short name T856
Test name
Test status
Simulation time 248021567 ps
CPU time 1.9 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:42 PM PDT 24
Peak memory 201896 kb
Host smart-84b7b1d2-4045-496f-917b-f8a6ef4941ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1641591266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1641591266
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3329834964
Short name T513
Test name
Test status
Simulation time 19484611795 ps
CPU time 60.65 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:30:57 PM PDT 24
Peak memory 201936 kb
Host smart-0107279e-f4f0-4559-81f4-ccf88c5b0cdc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329834964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3329834964
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.79199241
Short name T56
Test name
Test status
Simulation time 37728427882 ps
CPU time 91.62 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 202040 kb
Host smart-e59679b9-58a9-43e5-925c-b1bc55f9cd65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=79199241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.79199241
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3266691195
Short name T747
Test name
Test status
Simulation time 65028232 ps
CPU time 6.3 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:44 PM PDT 24
Peak memory 201824 kb
Host smart-6dde028f-a652-45e5-b6b7-94f6b4506c92
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266691195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3266691195
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.4077709961
Short name T777
Test name
Test status
Simulation time 129043475 ps
CPU time 5.54 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201668 kb
Host smart-2f42b18e-45e2-49f1-b8e4-65c6ce492a03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4077709961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4077709961
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.62918139
Short name T552
Test name
Test status
Simulation time 292800905 ps
CPU time 1.53 seconds
Started Apr 21 12:29:41 PM PDT 24
Finished Apr 21 12:29:43 PM PDT 24
Peak memory 201864 kb
Host smart-65939165-7990-4e2d-b4b7-2622ac8ee201
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62918139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.62918139
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2105621068
Short name T821
Test name
Test status
Simulation time 2103486459 ps
CPU time 7.5 seconds
Started Apr 21 12:29:44 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201904 kb
Host smart-090ae293-843b-4c9a-a510-01325ca156f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105621068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2105621068
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3218389630
Short name T834
Test name
Test status
Simulation time 974589873 ps
CPU time 7.14 seconds
Started Apr 21 12:29:37 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201816 kb
Host smart-a8fd528d-64f3-45d4-ac01-f116045291bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3218389630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3218389630
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3163764872
Short name T618
Test name
Test status
Simulation time 9255583 ps
CPU time 1 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201836 kb
Host smart-1b5d5d7f-acf7-4101-91bc-baaa4b6452f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163764872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3163764872
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2951745322
Short name T205
Test name
Test status
Simulation time 576414534 ps
CPU time 28.16 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201860 kb
Host smart-307ba69a-cd36-4ca1-88c8-72a223e0b7b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2951745322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2951745322
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1016893923
Short name T521
Test name
Test status
Simulation time 487171026 ps
CPU time 9.78 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:30:00 PM PDT 24
Peak memory 201868 kb
Host smart-cebff23a-3679-42d6-a887-404df26b9c68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1016893923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1016893923
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1718388503
Short name T644
Test name
Test status
Simulation time 466963280 ps
CPU time 36.7 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:30:25 PM PDT 24
Peak memory 204020 kb
Host smart-899f1f5f-a7a2-4c8b-9630-b4e733a9cf6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1718388503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1718388503
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.939074084
Short name T20
Test name
Test status
Simulation time 463128536 ps
CPU time 28.16 seconds
Started Apr 21 12:29:44 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 203824 kb
Host smart-415f2da9-dd97-4a6c-8415-35f59064d1c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=939074084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res
et_error.939074084
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3777176398
Short name T438
Test name
Test status
Simulation time 4018545578 ps
CPU time 10.49 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:29:56 PM PDT 24
Peak memory 201876 kb
Host smart-922477b4-c510-4e36-b4a8-b8ec12ed5271
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3777176398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3777176398
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3785749292
Short name T3
Test name
Test status
Simulation time 1739037778 ps
CPU time 19.62 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 201888 kb
Host smart-1a611ace-87c1-4e16-8b42-766b47b11687
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3785749292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3785749292
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3683729120
Short name T220
Test name
Test status
Simulation time 174946077261 ps
CPU time 377.03 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:36:22 PM PDT 24
Peak memory 204032 kb
Host smart-7045eb6b-6e32-404f-8348-4e3c89eb9459
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3683729120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3683729120
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.906595831
Short name T386
Test name
Test status
Simulation time 41466390 ps
CPU time 2.41 seconds
Started Apr 21 12:29:52 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201884 kb
Host smart-8fff2325-1f59-4140-9872-efd2ed7807b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=906595831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.906595831
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1973839987
Short name T810
Test name
Test status
Simulation time 71518367 ps
CPU time 4.01 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:29:56 PM PDT 24
Peak memory 201884 kb
Host smart-22bb807b-8981-45dc-a7d4-2cd4ea3c68b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973839987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1973839987
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.608359011
Short name T174
Test name
Test status
Simulation time 362410893 ps
CPU time 6.72 seconds
Started Apr 21 12:29:41 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 202088 kb
Host smart-4b2fcbdd-5b2f-493b-bca9-7e522387501a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=608359011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.608359011
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.896549086
Short name T119
Test name
Test status
Simulation time 30618532891 ps
CPU time 62.28 seconds
Started Apr 21 12:29:43 PM PDT 24
Finished Apr 21 12:30:46 PM PDT 24
Peak memory 202212 kb
Host smart-b1ea53a2-cbd5-4b63-b4b6-3052b804ce83
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=896549086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.896549086
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.141645594
Short name T572
Test name
Test status
Simulation time 10580419439 ps
CPU time 49.71 seconds
Started Apr 21 12:29:42 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201932 kb
Host smart-bc7da3e1-3c6d-4ff8-acfd-46913d349512
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=141645594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.141645594
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3408553166
Short name T432
Test name
Test status
Simulation time 204629230 ps
CPU time 6.99 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201804 kb
Host smart-7768dcda-8b49-4ee0-932e-78680b3d1295
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408553166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3408553166
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3901600722
Short name T286
Test name
Test status
Simulation time 165786659 ps
CPU time 5.48 seconds
Started Apr 21 12:29:58 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201892 kb
Host smart-ab72f384-8606-4c54-a113-0cfe6f46a515
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3901600722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3901600722
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2622452410
Short name T593
Test name
Test status
Simulation time 10782595 ps
CPU time 1.25 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:40 PM PDT 24
Peak memory 201816 kb
Host smart-aff2af66-e484-4bbb-858f-aac93367b31c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622452410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2622452410
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.797389133
Short name T512
Test name
Test status
Simulation time 2139109204 ps
CPU time 6.04 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 201804 kb
Host smart-7c984928-56b2-465c-a263-2b1b1d6cc892
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=797389133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.797389133
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.702679000
Short name T731
Test name
Test status
Simulation time 680427913 ps
CPU time 6.02 seconds
Started Apr 21 12:29:41 PM PDT 24
Finished Apr 21 12:29:47 PM PDT 24
Peak memory 201924 kb
Host smart-c9f29fdf-3152-45d5-9fd3-7b6aab3587a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=702679000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.702679000
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2298503838
Short name T647
Test name
Test status
Simulation time 16110356 ps
CPU time 0.96 seconds
Started Apr 21 12:29:39 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201792 kb
Host smart-068d2575-c690-43e9-bba6-53903a7ae68a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298503838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2298503838
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2005075624
Short name T122
Test name
Test status
Simulation time 11789451444 ps
CPU time 39.79 seconds
Started Apr 21 12:30:04 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 201952 kb
Host smart-e886eed4-479e-4dcb-ada4-5e002fef7b23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2005075624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2005075624
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3119057542
Short name T207
Test name
Test status
Simulation time 551278950 ps
CPU time 35.68 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:30:25 PM PDT 24
Peak memory 201844 kb
Host smart-301d84ec-8371-402b-b4f9-f102ba7939b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3119057542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3119057542
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1507124297
Short name T835
Test name
Test status
Simulation time 130935964 ps
CPU time 9.83 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:29:59 PM PDT 24
Peak memory 202816 kb
Host smart-4523cb2a-e8d6-4fd2-97f0-8077d5e5e2a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1507124297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.1507124297
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1235759590
Short name T224
Test name
Test status
Simulation time 8308342575 ps
CPU time 58.04 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 204668 kb
Host smart-81a9d39a-7928-45eb-8909-b75caeff7f86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1235759590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.1235759590
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3430616905
Short name T299
Test name
Test status
Simulation time 9179236 ps
CPU time 0.97 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:29:51 PM PDT 24
Peak memory 201780 kb
Host smart-61fac3e2-63da-4169-bcd5-3925bc8a3cf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3430616905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3430616905
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.492807646
Short name T880
Test name
Test status
Simulation time 68141446 ps
CPU time 8.93 seconds
Started Apr 21 12:29:38 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 201832 kb
Host smart-bc041560-82fe-4fe9-baaf-1ed587376d19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=492807646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.492807646
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3314244240
Short name T442
Test name
Test status
Simulation time 520117513 ps
CPU time 4.52 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:29:59 PM PDT 24
Peak memory 201796 kb
Host smart-bd89c6f8-840c-49dc-a48a-ffa832c555c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3314244240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3314244240
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.2113958445
Short name T899
Test name
Test status
Simulation time 888635567 ps
CPU time 16.51 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201868 kb
Host smart-8aa35331-506c-40eb-85e7-0a58103b7b09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2113958445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2113958445
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.168689006
Short name T843
Test name
Test status
Simulation time 468563081 ps
CPU time 5.73 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:29:58 PM PDT 24
Peak memory 201796 kb
Host smart-8585b3b3-6cc3-45f4-9d5f-4cc483df80e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=168689006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.168689006
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.4249598167
Short name T354
Test name
Test status
Simulation time 33601882118 ps
CPU time 79.4 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 201880 kb
Host smart-5f074e7a-0c50-43ec-8675-819710f458a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249598167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4249598167
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2414511056
Short name T888
Test name
Test status
Simulation time 35670345139 ps
CPU time 67.15 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:30:53 PM PDT 24
Peak memory 201888 kb
Host smart-1b1272a0-53f3-41ec-a51e-91eec25d0067
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2414511056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2414511056
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3084106545
Short name T357
Test name
Test status
Simulation time 86396268 ps
CPU time 4.98 seconds
Started Apr 21 12:29:44 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201804 kb
Host smart-b77700e5-a416-419e-9596-6fc7b8f4fcd2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084106545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3084106545
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.1305077937
Short name T527
Test name
Test status
Simulation time 29257912 ps
CPU time 2.68 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:49 PM PDT 24
Peak memory 201828 kb
Host smart-13bc9583-a22f-48be-ae64-3ab3c824724c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1305077937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1305077937
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.926567003
Short name T539
Test name
Test status
Simulation time 55854374 ps
CPU time 1.53 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 201792 kb
Host smart-38d0d50f-f942-4dd7-972f-0d213ccd3585
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926567003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.926567003
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2184697088
Short name T858
Test name
Test status
Simulation time 7007430003 ps
CPU time 7.39 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201996 kb
Host smart-b18f2a05-8fe4-4f3a-8714-587383a3a7e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184697088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2184697088
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3891796592
Short name T833
Test name
Test status
Simulation time 5196534890 ps
CPU time 5.87 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201980 kb
Host smart-6a6da463-081b-4573-bd52-fac046da0898
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3891796592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3891796592
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3428312679
Short name T561
Test name
Test status
Simulation time 8651714 ps
CPU time 1.04 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:47 PM PDT 24
Peak memory 201804 kb
Host smart-6dd32b46-c656-499e-a060-75fd0798c44e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428312679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3428312679
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2691091791
Short name T233
Test name
Test status
Simulation time 6145021663 ps
CPU time 29.7 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 202964 kb
Host smart-bd8ebd5c-b31e-4830-a3d9-a83a7906f984
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2691091791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2691091791
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1097918743
Short name T661
Test name
Test status
Simulation time 15707462138 ps
CPU time 23.63 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:30 PM PDT 24
Peak memory 201992 kb
Host smart-33f6f761-deef-4cda-b4d8-6fc28caa32a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1097918743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1097918743
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.926939486
Short name T171
Test name
Test status
Simulation time 7002294295 ps
CPU time 152.01 seconds
Started Apr 21 12:29:53 PM PDT 24
Finished Apr 21 12:32:25 PM PDT 24
Peak memory 204796 kb
Host smart-c63c3dd9-fa73-42cd-b52d-f96022adb141
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926939486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res
et_error.926939486
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3100508826
Short name T291
Test name
Test status
Simulation time 502456054 ps
CPU time 7.89 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201804 kb
Host smart-8666f51a-6602-405c-8289-0cf3efb90169
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3100508826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3100508826
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3924809600
Short name T681
Test name
Test status
Simulation time 385901188 ps
CPU time 8.91 seconds
Started Apr 21 12:29:53 PM PDT 24
Finished Apr 21 12:30:02 PM PDT 24
Peak memory 201904 kb
Host smart-0f8e2f3a-b9fa-471c-928f-7993c64255f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3924809600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3924809600
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.890065650
Short name T498
Test name
Test status
Simulation time 59564146 ps
CPU time 2.58 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201800 kb
Host smart-4d3ee4b5-c729-4fd6-b0a3-9dee19e6e44a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890065650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.890065650
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.4132709001
Short name T883
Test name
Test status
Simulation time 83639419 ps
CPU time 9.82 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 201848 kb
Host smart-cac9794f-fa56-4d66-9461-1483c5269b76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4132709001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4132709001
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1642668944
Short name T30
Test name
Test status
Simulation time 26365878241 ps
CPU time 120.17 seconds
Started Apr 21 12:29:58 PM PDT 24
Finished Apr 21 12:31:59 PM PDT 24
Peak memory 202012 kb
Host smart-12ec355c-74d8-4765-8523-a90d7953bac5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642668944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1642668944
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.4223083325
Short name T433
Test name
Test status
Simulation time 17205120983 ps
CPU time 118.96 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:31:54 PM PDT 24
Peak memory 202028 kb
Host smart-904221b6-2e64-414b-a2d8-9c872f2639e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4223083325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4223083325
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.900559522
Short name T789
Test name
Test status
Simulation time 102966927 ps
CPU time 4.72 seconds
Started Apr 21 12:29:43 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 201912 kb
Host smart-b13bb63f-6dee-42d6-979d-4cb56190b4c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900559522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.900559522
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.4111372180
Short name T639
Test name
Test status
Simulation time 705391754 ps
CPU time 4.69 seconds
Started Apr 21 12:31:13 PM PDT 24
Finished Apr 21 12:31:18 PM PDT 24
Peak memory 201676 kb
Host smart-b1c3796e-8c55-437c-8563-78069e5453d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111372180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4111372180
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.995267276
Short name T378
Test name
Test status
Simulation time 15755340 ps
CPU time 1.1 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201804 kb
Host smart-fcf0db73-b180-4365-8f4e-2a25df991999
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=995267276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.995267276
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3199938305
Short name T447
Test name
Test status
Simulation time 5161085385 ps
CPU time 6.26 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:53 PM PDT 24
Peak memory 202040 kb
Host smart-b5c16ad5-f41d-4223-936a-6f7df21997c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199938305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3199938305
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1267340738
Short name T891
Test name
Test status
Simulation time 1574221655 ps
CPU time 5.27 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201852 kb
Host smart-5ee636f3-76ed-4718-9fd6-c2c6f2360071
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1267340738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1267340738
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1814235972
Short name T337
Test name
Test status
Simulation time 22162263 ps
CPU time 1.09 seconds
Started Apr 21 12:30:59 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201676 kb
Host smart-22a6a8d2-44d1-494d-be11-e91487508764
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814235972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1814235972
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.905932774
Short name T554
Test name
Test status
Simulation time 2973431786 ps
CPU time 13.92 seconds
Started Apr 21 12:29:40 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201868 kb
Host smart-164a2537-50c3-4fde-9319-d1f64916dbd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=905932774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.905932774
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1915027360
Short name T4
Test name
Test status
Simulation time 1159053144 ps
CPU time 9.9 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201788 kb
Host smart-d772f3a4-f420-4955-88b1-8be114ab3eef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1915027360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1915027360
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1960622366
Short name T244
Test name
Test status
Simulation time 5349370771 ps
CPU time 48.01 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:48 PM PDT 24
Peak memory 203672 kb
Host smart-30f162a4-d36c-4c38-96cc-4ae4a285722f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960622366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.1960622366
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3105926745
Short name T25
Test name
Test status
Simulation time 240892120 ps
CPU time 5.49 seconds
Started Apr 21 12:29:55 PM PDT 24
Finished Apr 21 12:30:01 PM PDT 24
Peak memory 201812 kb
Host smart-e952c4ca-0ac7-47af-9f9b-0295413688b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3105926745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3105926745
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.162970227
Short name T828
Test name
Test status
Simulation time 55924091 ps
CPU time 7.58 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:29:58 PM PDT 24
Peak memory 201792 kb
Host smart-2fd56acb-257c-4b9b-a636-c426857068ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=162970227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.162970227
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.27355094
Short name T217
Test name
Test status
Simulation time 17546622788 ps
CPU time 113.8 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:31:41 PM PDT 24
Peak memory 201972 kb
Host smart-e8dd5bff-43bb-4a7e-a43f-1f9cbbbfd3f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27355094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow
_rsp.27355094
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3674067426
Short name T518
Test name
Test status
Simulation time 1123826740 ps
CPU time 9.69 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201796 kb
Host smart-b30fc7bb-2d93-4c8c-94b6-3f633b3c88b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3674067426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3674067426
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.104914638
Short name T542
Test name
Test status
Simulation time 1198385318 ps
CPU time 8.64 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201812 kb
Host smart-cfa292bc-0246-4967-850f-5caa8aed2149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104914638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.104914638
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.846773777
Short name T673
Test name
Test status
Simulation time 379347312 ps
CPU time 8.14 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:29:58 PM PDT 24
Peak memory 201924 kb
Host smart-7ebb234f-97eb-4427-9c05-d2fda60d6269
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=846773777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.846773777
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1258284855
Short name T359
Test name
Test status
Simulation time 14705956517 ps
CPU time 63.07 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:30:55 PM PDT 24
Peak memory 201924 kb
Host smart-ddee0b78-008b-4466-b073-5fbd86b28a0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258284855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1258284855
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4053803098
Short name T177
Test name
Test status
Simulation time 12559654450 ps
CPU time 50.1 seconds
Started Apr 21 12:29:53 PM PDT 24
Finished Apr 21 12:30:43 PM PDT 24
Peak memory 202032 kb
Host smart-34c17afd-17fe-435d-823a-b022f31b34d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4053803098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4053803098
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.527554914
Short name T429
Test name
Test status
Simulation time 108534225 ps
CPU time 6.44 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:09 PM PDT 24
Peak memory 201848 kb
Host smart-3cfa3010-ac47-4a36-9783-58d0a8924ded
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527554914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.527554914
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.3441579729
Short name T719
Test name
Test status
Simulation time 113031966 ps
CPU time 2.08 seconds
Started Apr 21 12:31:11 PM PDT 24
Finished Apr 21 12:31:14 PM PDT 24
Peak memory 201672 kb
Host smart-0bef6e2f-b41e-4fbd-8502-3622a3af9f2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3441579729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3441579729
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1113731374
Short name T536
Test name
Test status
Simulation time 39779593 ps
CPU time 1.64 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:03 PM PDT 24
Peak memory 201804 kb
Host smart-777187ad-de6c-479c-82ce-95d588a71e13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1113731374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1113731374
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.834968847
Short name T839
Test name
Test status
Simulation time 6737302814 ps
CPU time 12.44 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:29:59 PM PDT 24
Peak memory 201972 kb
Host smart-3e4d3b8b-faa3-473f-b9eb-c9eb2ddd697a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=834968847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.834968847
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4162047381
Short name T24
Test name
Test status
Simulation time 4112666766 ps
CPU time 10.56 seconds
Started Apr 21 12:29:44 PM PDT 24
Finished Apr 21 12:29:55 PM PDT 24
Peak memory 201904 kb
Host smart-530526b3-0cbe-4f47-bf34-05997d5d2fba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4162047381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4162047381
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4271084107
Short name T796
Test name
Test status
Simulation time 9809461 ps
CPU time 1.13 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:29:50 PM PDT 24
Peak memory 201820 kb
Host smart-20cae717-977a-41f8-ad3f-a5cc43b3fd0d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271084107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4271084107
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3217485544
Short name T375
Test name
Test status
Simulation time 678287965 ps
CPU time 38.46 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 202816 kb
Host smart-19c009b7-3c83-4663-ac75-31fc71091843
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3217485544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3217485544
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3524550267
Short name T602
Test name
Test status
Simulation time 113177847 ps
CPU time 7.58 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201888 kb
Host smart-7bbcda39-53ac-4fdd-bb06-dfe3996e5571
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3524550267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3524550267
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.361536027
Short name T50
Test name
Test status
Simulation time 194657595 ps
CPU time 38.49 seconds
Started Apr 21 12:29:45 PM PDT 24
Finished Apr 21 12:30:24 PM PDT 24
Peak memory 203816 kb
Host smart-b217ea1d-0d82-4627-b0d2-c6fab635e10d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361536027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.361536027
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.520297872
Short name T736
Test name
Test status
Simulation time 1568016960 ps
CPU time 45.5 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 203840 kb
Host smart-d298bb72-c43d-474e-97aa-f0ec06a7aa2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=520297872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res
et_error.520297872
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2676433084
Short name T388
Test name
Test status
Simulation time 50888391 ps
CPU time 4.7 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:29:53 PM PDT 24
Peak memory 201908 kb
Host smart-119cdbd0-d814-47dc-959d-d2d5bf99287e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676433084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2676433084
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1854808862
Short name T81
Test name
Test status
Simulation time 621113619 ps
CPU time 4.4 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201876 kb
Host smart-536af4af-2d93-4cba-a92d-4e11f72f9e19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1854808862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1854808862
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2418802199
Short name T216
Test name
Test status
Simulation time 77035883037 ps
CPU time 344.5 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:35:46 PM PDT 24
Peak memory 202948 kb
Host smart-551265e1-d9ea-4cbb-b25d-6fb17e173c8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2418802199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2418802199
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2867580774
Short name T791
Test name
Test status
Simulation time 475618150 ps
CPU time 4.83 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201860 kb
Host smart-5a0aef09-5dee-4c4c-8f1a-c4deeee2a66e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2867580774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2867580774
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.2407623675
Short name T256
Test name
Test status
Simulation time 14910698 ps
CPU time 1.49 seconds
Started Apr 21 12:29:55 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 201884 kb
Host smart-4f5b3e8b-0c7b-4735-9a08-b563b5612ba8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2407623675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2407623675
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.849243374
Short name T635
Test name
Test status
Simulation time 2161002239 ps
CPU time 15.36 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201968 kb
Host smart-883a8528-1edb-4483-b36f-0872310b3878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=849243374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.849243374
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.153505236
Short name T544
Test name
Test status
Simulation time 5334822364 ps
CPU time 13.25 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201940 kb
Host smart-44bd54b8-f4ea-4740-9027-2f550d040f82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=153505236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.153505236
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3783561532
Short name T295
Test name
Test status
Simulation time 56965057 ps
CPU time 3.35 seconds
Started Apr 21 12:29:58 PM PDT 24
Finished Apr 21 12:30:01 PM PDT 24
Peak memory 201844 kb
Host smart-4d066397-d401-437f-864d-f74911911eea
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783561532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3783561532
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3166442919
Short name T137
Test name
Test status
Simulation time 49058505 ps
CPU time 5.25 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:30:02 PM PDT 24
Peak memory 201892 kb
Host smart-2a6555ef-f1a9-4502-a367-033a7825c671
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3166442919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3166442919
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.3039854159
Short name T559
Test name
Test status
Simulation time 51984700 ps
CPU time 1.26 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:29:48 PM PDT 24
Peak memory 201892 kb
Host smart-c5d264f4-e820-4ee3-b6e4-b54dde07ee24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3039854159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3039854159
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1911602147
Short name T571
Test name
Test status
Simulation time 2639484855 ps
CPU time 12.66 seconds
Started Apr 21 12:29:48 PM PDT 24
Finished Apr 21 12:30:01 PM PDT 24
Peak memory 201876 kb
Host smart-7bc4f722-387e-4521-9e25-583ca1100660
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911602147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1911602147
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2957594844
Short name T262
Test name
Test status
Simulation time 4949258885 ps
CPU time 13.98 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201780 kb
Host smart-8ffe8f42-dde2-4c65-8fdc-3adad20eda54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2957594844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2957594844
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2825508263
Short name T208
Test name
Test status
Simulation time 13992561 ps
CPU time 1.31 seconds
Started Apr 21 12:29:47 PM PDT 24
Finished Apr 21 12:29:49 PM PDT 24
Peak memory 201800 kb
Host smart-d4741bae-70d0-4dc3-be01-b31c50dbe075
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825508263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2825508263
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3374352895
Short name T643
Test name
Test status
Simulation time 1960102935 ps
CPU time 29.23 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:30:26 PM PDT 24
Peak memory 201796 kb
Host smart-9cdc0359-585c-482f-ac2b-6e460ea981bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3374352895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3374352895
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.303126193
Short name T348
Test name
Test status
Simulation time 58267254 ps
CPU time 3.06 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 201888 kb
Host smart-80f7eb95-7768-4742-89a5-03337766cfae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=303126193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.303126193
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2303370286
Short name T872
Test name
Test status
Simulation time 322270883 ps
CPU time 27.51 seconds
Started Apr 21 12:29:46 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 203956 kb
Host smart-07b5374c-756f-4698-88ff-26686c1ab04e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2303370286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.2303370286
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.924558695
Short name T254
Test name
Test status
Simulation time 7818514 ps
CPU time 2.29 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:30:05 PM PDT 24
Peak memory 201720 kb
Host smart-85bcbdad-0838-43f7-b8f2-305f68b05205
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=924558695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res
et_error.924558695
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.569536638
Short name T740
Test name
Test status
Simulation time 167260091 ps
CPU time 3.76 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:06 PM PDT 24
Peak memory 201888 kb
Host smart-ef2cc012-1c56-4bc0-bef2-b26620d45938
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=569536638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.569536638
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2174228100
Short name T350
Test name
Test status
Simulation time 59489374 ps
CPU time 2.23 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201816 kb
Host smart-23f9fdff-e397-4d19-9d1b-a643dec6914a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2174228100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2174228100
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2609079353
Short name T353
Test name
Test status
Simulation time 19264290025 ps
CPU time 37.55 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 202012 kb
Host smart-3ebddb55-1d25-4501-b21d-e00d480a9ae1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2609079353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.2609079353
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.560876395
Short name T304
Test name
Test status
Simulation time 24993771 ps
CPU time 1.18 seconds
Started Apr 21 12:29:52 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201800 kb
Host smart-0dec034f-adb5-4296-8d3a-02fe461c5d87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=560876395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.560876395
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1457486621
Short name T700
Test name
Test status
Simulation time 22367563 ps
CPU time 1.22 seconds
Started Apr 21 12:31:04 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201664 kb
Host smart-317afabe-5332-4516-8993-fca2d93c7da6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1457486621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1457486621
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.47539526
Short name T746
Test name
Test status
Simulation time 1201159410 ps
CPU time 8.33 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201884 kb
Host smart-8c4bd06e-85c7-444d-b8de-6d2a0ba32f3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47539526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.47539526
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1199058155
Short name T884
Test name
Test status
Simulation time 196454033181 ps
CPU time 105.12 seconds
Started Apr 21 12:30:04 PM PDT 24
Finished Apr 21 12:31:50 PM PDT 24
Peak memory 202044 kb
Host smart-ad1daf6c-ae82-4051-8036-bfe9f83ea296
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199058155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1199058155
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3010755204
Short name T900
Test name
Test status
Simulation time 21022612334 ps
CPU time 95.57 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:31:39 PM PDT 24
Peak memory 202020 kb
Host smart-3583e2fd-ce28-4c9e-832f-d3a784613351
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3010755204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3010755204
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.89385574
Short name T37
Test name
Test status
Simulation time 223159321 ps
CPU time 6.21 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201892 kb
Host smart-c4ac0531-9da7-45f9-98b6-1034db5e4650
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89385574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.89385574
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.3463650020
Short name T771
Test name
Test status
Simulation time 2715443957 ps
CPU time 9.35 seconds
Started Apr 21 12:29:54 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201832 kb
Host smart-39b2e64d-aee2-4a63-a8c7-beedfd4b2d5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463650020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3463650020
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.1996798550
Short name T135
Test name
Test status
Simulation time 15667126 ps
CPU time 1.33 seconds
Started Apr 21 12:29:49 PM PDT 24
Finished Apr 21 12:29:51 PM PDT 24
Peak memory 201672 kb
Host smart-d5ebc9a8-43f1-4998-9209-5a89ce4243f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1996798550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1996798550
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2317508141
Short name T474
Test name
Test status
Simulation time 12359438511 ps
CPU time 11.18 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:30:02 PM PDT 24
Peak memory 201968 kb
Host smart-e4a8225b-1220-48ad-9d2b-74ba91aa43bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317508141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2317508141
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1096901968
Short name T298
Test name
Test status
Simulation time 1688893046 ps
CPU time 7.14 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 201808 kb
Host smart-81854c97-7674-47bb-899b-546e0f1b9ba3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1096901968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1096901968
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3992749099
Short name T342
Test name
Test status
Simulation time 9231069 ps
CPU time 1.24 seconds
Started Apr 21 12:29:59 PM PDT 24
Finished Apr 21 12:30:01 PM PDT 24
Peak memory 201820 kb
Host smart-e4f411d8-e1b5-4598-9e6a-320ca9eb8f4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992749099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3992749099
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2556474528
Short name T699
Test name
Test status
Simulation time 8626095793 ps
CPU time 72.4 seconds
Started Apr 21 12:29:56 PM PDT 24
Finished Apr 21 12:31:09 PM PDT 24
Peak memory 202940 kb
Host smart-bca75a40-7276-493f-80a9-04ce79f62a51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556474528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2556474528
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1171952170
Short name T191
Test name
Test status
Simulation time 158838102 ps
CPU time 12.68 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:18 PM PDT 24
Peak memory 201884 kb
Host smart-a22f27ad-cafb-40a0-a45a-c3ad33e895c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1171952170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1171952170
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4269436981
Short name T248
Test name
Test status
Simulation time 746403763 ps
CPU time 104.26 seconds
Started Apr 21 12:29:59 PM PDT 24
Finished Apr 21 12:31:43 PM PDT 24
Peak memory 204308 kb
Host smart-ed3c9fd3-76cd-4062-898b-f9ab1e3fe110
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4269436981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.4269436981
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.494969080
Short name T627
Test name
Test status
Simulation time 290875023 ps
CPU time 28.66 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 203120 kb
Host smart-8fadfe12-42f3-4a97-9d5a-f00e5f883cf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494969080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res
et_error.494969080
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.1370663609
Short name T516
Test name
Test status
Simulation time 4171948407 ps
CPU time 9.23 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201904 kb
Host smart-9dcc6e34-5621-496f-986c-ea5369baa956
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370663609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1370663609
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2391682003
Short name T840
Test name
Test status
Simulation time 15644374 ps
CPU time 2.6 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 201920 kb
Host smart-7fde22b1-f6ed-4a1c-a2e9-ac0f02e379d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2391682003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2391682003
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1501517193
Short name T729
Test name
Test status
Simulation time 464909618 ps
CPU time 6.23 seconds
Started Apr 21 12:28:47 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201788 kb
Host smart-de9bc61b-4311-4795-a0d3-c70004596f9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1501517193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1501517193
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1569616327
Short name T409
Test name
Test status
Simulation time 1180765952 ps
CPU time 10.51 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201852 kb
Host smart-744088eb-c4ef-441d-8eb7-0e789961dc67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569616327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1569616327
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.3810568995
Short name T132
Test name
Test status
Simulation time 4792533761 ps
CPU time 9.06 seconds
Started Apr 21 12:28:33 PM PDT 24
Finished Apr 21 12:28:43 PM PDT 24
Peak memory 201920 kb
Host smart-6c23e684-9874-4a6c-9786-8e3c4664412d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810568995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3810568995
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3479809274
Short name T793
Test name
Test status
Simulation time 33133086848 ps
CPU time 147.19 seconds
Started Apr 21 12:28:37 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201940 kb
Host smart-c948f536-67f4-4143-bc87-69449fa54ba6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479809274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3479809274
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2639200087
Short name T369
Test name
Test status
Simulation time 11581793100 ps
CPU time 74.63 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:30:00 PM PDT 24
Peak memory 202040 kb
Host smart-a5fab41c-4bc9-4aa2-94be-7e792aa76d7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2639200087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2639200087
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1991258870
Short name T370
Test name
Test status
Simulation time 169689903 ps
CPU time 4.74 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201892 kb
Host smart-f214001d-51e4-47af-b77a-29618513ea69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991258870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1991258870
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.2017306665
Short name T139
Test name
Test status
Simulation time 1204691046 ps
CPU time 9.12 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:28:55 PM PDT 24
Peak memory 201844 kb
Host smart-8ee22695-a30e-4348-8985-b2d9766e9153
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2017306665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2017306665
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3044062560
Short name T110
Test name
Test status
Simulation time 11650521 ps
CPU time 1.22 seconds
Started Apr 21 12:28:44 PM PDT 24
Finished Apr 21 12:28:46 PM PDT 24
Peak memory 201892 kb
Host smart-7d8c52c5-d57b-433e-a3a0-ca1e5b8cd7d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3044062560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3044062560
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2734471016
Short name T707
Test name
Test status
Simulation time 2912018959 ps
CPU time 9.65 seconds
Started Apr 21 12:28:42 PM PDT 24
Finished Apr 21 12:28:52 PM PDT 24
Peak memory 201964 kb
Host smart-511fac6d-a660-49a9-a8b3-6f7af96e1554
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734471016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2734471016
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3107610117
Short name T523
Test name
Test status
Simulation time 2054697979 ps
CPU time 12.07 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:55 PM PDT 24
Peak memory 201824 kb
Host smart-ca11784d-7c7d-4a61-8423-890fd9312020
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3107610117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3107610117
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1878003726
Short name T366
Test name
Test status
Simulation time 19866551 ps
CPU time 1.36 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:43 PM PDT 24
Peak memory 201732 kb
Host smart-3a63cb4e-e90e-4322-b359-e26b3edff349
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878003726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1878003726
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2268129130
Short name T352
Test name
Test status
Simulation time 585026615 ps
CPU time 10.24 seconds
Started Apr 21 12:28:52 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201776 kb
Host smart-70d0280a-a11e-4837-9d8e-67ad39838138
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2268129130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2268129130
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2864007596
Short name T543
Test name
Test status
Simulation time 1728953292 ps
CPU time 51 seconds
Started Apr 21 12:28:47 PM PDT 24
Finished Apr 21 12:29:39 PM PDT 24
Peak memory 204256 kb
Host smart-cee47ef9-6cce-4ade-8e40-2d5049a9b1af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2864007596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2864007596
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1708585787
Short name T714
Test name
Test status
Simulation time 1046185214 ps
CPU time 145.39 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:31:09 PM PDT 24
Peak memory 204928 kb
Host smart-a1d82cd3-ad57-4690-a599-1b3fad3eb871
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1708585787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.1708585787
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3007627027
Short name T611
Test name
Test status
Simulation time 181543461 ps
CPU time 31.72 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:29:17 PM PDT 24
Peak memory 202804 kb
Host smart-cca7e0b7-18de-4292-b1a2-200c4af8d157
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3007627027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3007627027
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1596388659
Short name T754
Test name
Test status
Simulation time 72825923 ps
CPU time 7.26 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201840 kb
Host smart-61a12b14-9283-437c-bd3c-9285884be2cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1596388659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1596388659
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.860345793
Short name T90
Test name
Test status
Simulation time 1240320399 ps
CPU time 20.96 seconds
Started Apr 21 12:29:57 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 201920 kb
Host smart-4e4cb42b-644c-4745-95c5-3bc7125a4387
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=860345793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.860345793
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2454516267
Short name T329
Test name
Test status
Simulation time 8306081567 ps
CPU time 15.32 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:30:18 PM PDT 24
Peak memory 201940 kb
Host smart-89588356-619e-4481-8005-5fc68c92fdd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2454516267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.2454516267
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.446915468
Short name T574
Test name
Test status
Simulation time 516094657 ps
CPU time 8.57 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 201668 kb
Host smart-2a176bc2-ce1e-4bef-8bb6-92ff083da7ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=446915468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.446915468
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.2050443217
Short name T730
Test name
Test status
Simulation time 601944790 ps
CPU time 7.89 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201852 kb
Host smart-b4e8b00a-98c8-4ac2-a057-07f2cbfd8a7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2050443217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2050443217
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.2103642585
Short name T785
Test name
Test status
Simulation time 53093496 ps
CPU time 4.39 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201852 kb
Host smart-22d2b76e-8b34-4a9f-9443-58cf5c68a29e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2103642585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2103642585
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.753755804
Short name T411
Test name
Test status
Simulation time 132869190406 ps
CPU time 113.22 seconds
Started Apr 21 12:29:59 PM PDT 24
Finished Apr 21 12:31:53 PM PDT 24
Peak memory 201932 kb
Host smart-f8a95774-12bf-45dd-a6bf-df678389ad01
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=753755804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.753755804
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1590551863
Short name T659
Test name
Test status
Simulation time 26672722860 ps
CPU time 123.94 seconds
Started Apr 21 12:29:58 PM PDT 24
Finished Apr 21 12:32:02 PM PDT 24
Peak memory 201928 kb
Host smart-6a877b06-7d80-4e31-8872-40cb329f37b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1590551863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1590551863
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.102912461
Short name T531
Test name
Test status
Simulation time 13848361 ps
CPU time 1.48 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201672 kb
Host smart-f1d247d1-f690-43c9-84e0-aa226a560269
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102912461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.102912461
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.1954741329
Short name T376
Test name
Test status
Simulation time 611476391 ps
CPU time 4.36 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:06 PM PDT 24
Peak memory 201912 kb
Host smart-63f01e89-75a5-4f4b-b05e-4c797487235a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954741329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1954741329
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.3226990152
Short name T297
Test name
Test status
Simulation time 18492400 ps
CPU time 1.34 seconds
Started Apr 21 12:29:55 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 201816 kb
Host smart-f98e5b06-e57e-46bf-af8a-574fd039ffbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3226990152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3226990152
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3689450373
Short name T391
Test name
Test status
Simulation time 2665535787 ps
CPU time 10.79 seconds
Started Apr 21 12:29:55 PM PDT 24
Finished Apr 21 12:30:06 PM PDT 24
Peak memory 201876 kb
Host smart-fe4d416d-f791-4ced-b935-96ddf0cc0e35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689450373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3689450373
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3498274277
Short name T346
Test name
Test status
Simulation time 1030697036 ps
CPU time 5.36 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 201764 kb
Host smart-15974712-1606-4651-b31f-f9a5aaa53b09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3498274277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3498274277
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2970262473
Short name T638
Test name
Test status
Simulation time 10261123 ps
CPU time 1.13 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201684 kb
Host smart-d88df5bc-c954-4440-9eaa-edf8c2d16cfa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970262473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2970262473
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1896606368
Short name T470
Test name
Test status
Simulation time 3819965919 ps
CPU time 55.57 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:56 PM PDT 24
Peak memory 203548 kb
Host smart-d329612a-e662-4feb-be02-ca22ddd10b36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1896606368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1896606368
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3005231771
Short name T606
Test name
Test status
Simulation time 10274438446 ps
CPU time 35.36 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 202020 kb
Host smart-ef96816b-3e65-423d-86c5-f36bab792d66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3005231771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3005231771
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2824276350
Short name T326
Test name
Test status
Simulation time 2557114717 ps
CPU time 123.91 seconds
Started Apr 21 12:29:51 PM PDT 24
Finished Apr 21 12:31:56 PM PDT 24
Peak memory 205668 kb
Host smart-18b441f6-0490-4651-ac66-e1a18758eafe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2824276350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.2824276350
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2311627542
Short name T668
Test name
Test status
Simulation time 38684597 ps
CPU time 4.37 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:30:06 PM PDT 24
Peak memory 201792 kb
Host smart-d7ff811b-b7d3-4ba5-ab91-3fc414587b6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2311627542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.2311627542
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4124930017
Short name T334
Test name
Test status
Simulation time 38676374 ps
CPU time 3.76 seconds
Started Apr 21 12:29:50 PM PDT 24
Finished Apr 21 12:29:54 PM PDT 24
Peak memory 201920 kb
Host smart-f4933668-006b-44ff-95ee-98cccf90a379
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4124930017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4124930017
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.4209330156
Short name T130
Test name
Test status
Simulation time 795654869 ps
CPU time 9.49 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201860 kb
Host smart-369541df-f475-4745-99b0-ecef4b594822
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4209330156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.4209330156
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1306287744
Short name T599
Test name
Test status
Simulation time 39997173644 ps
CPU time 260.15 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:34:23 PM PDT 24
Peak memory 204472 kb
Host smart-3034beb0-39c3-4428-bb8b-0a4be01ad542
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1306287744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1306287744
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3859420292
Short name T830
Test name
Test status
Simulation time 656242782 ps
CPU time 3.95 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201868 kb
Host smart-c34dc13f-ef0e-4764-a184-b4a9eee0a6b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3859420292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3859420292
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.2225126544
Short name T504
Test name
Test status
Simulation time 51095979 ps
CPU time 1.46 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201672 kb
Host smart-dc17012e-edb3-4fe1-9cd3-d0c3e5958e94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2225126544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2225126544
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.638820249
Short name T538
Test name
Test status
Simulation time 790770161 ps
CPU time 12.11 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 201872 kb
Host smart-000d054b-2640-46b4-9251-9509628c5887
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=638820249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.638820249
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3808864920
Short name T318
Test name
Test status
Simulation time 43170962579 ps
CPU time 160.31 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:32:42 PM PDT 24
Peak memory 201928 kb
Host smart-83149d4f-ca83-49dc-9538-31693902986e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808864920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3808864920
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1351998332
Short name T327
Test name
Test status
Simulation time 19336115952 ps
CPU time 97.41 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:31:41 PM PDT 24
Peak memory 201936 kb
Host smart-ae58f2e5-dca2-444f-aa8d-9f24e457db8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1351998332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1351998332
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3139768585
Short name T818
Test name
Test status
Simulation time 64177780 ps
CPU time 7.87 seconds
Started Apr 21 12:30:04 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201676 kb
Host smart-51a64642-6784-45b6-b229-6dcfbeb806f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139768585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3139768585
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.2294293438
Short name T61
Test name
Test status
Simulation time 1258140381 ps
CPU time 8.77 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201892 kb
Host smart-3e6770e0-fbc0-45fc-a7d9-55f22db40dc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2294293438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2294293438
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3911489582
Short name T612
Test name
Test status
Simulation time 34561799 ps
CPU time 1.32 seconds
Started Apr 21 12:29:57 PM PDT 24
Finished Apr 21 12:29:59 PM PDT 24
Peak memory 201804 kb
Host smart-de850362-11e4-47cc-881d-be33593bfa18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3911489582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3911489582
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3422192558
Short name T59
Test name
Test status
Simulation time 3675045123 ps
CPU time 8.2 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201952 kb
Host smart-acdba5a4-36eb-4be7-9002-4dd4a8adeb87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422192558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3422192558
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.600606054
Short name T587
Test name
Test status
Simulation time 1151716529 ps
CPU time 8.36 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201668 kb
Host smart-bc5602ef-a54b-4c50-8508-d19e8abd20ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=600606054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.600606054
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.290599123
Short name T206
Test name
Test status
Simulation time 12930768 ps
CPU time 1.29 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 201828 kb
Host smart-8e8f6f2e-370b-4f34-bd72-a20e94fdae42
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290599123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.290599123
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.397937691
Short name T310
Test name
Test status
Simulation time 971634541 ps
CPU time 13.76 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201820 kb
Host smart-978be967-4626-49ad-9fbe-3648a86f2d6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=397937691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.397937691
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3837093565
Short name T336
Test name
Test status
Simulation time 231037434 ps
CPU time 16.85 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 201880 kb
Host smart-8a2d5ff2-37d9-45b4-8457-ad75f428b91f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3837093565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3837093565
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1520557104
Short name T238
Test name
Test status
Simulation time 97808452 ps
CPU time 14.96 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 202876 kb
Host smart-656e7d8c-9743-4398-ad60-d9fca082b87b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1520557104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1520557104
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.664345362
Short name T105
Test name
Test status
Simulation time 89233538 ps
CPU time 9.22 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 201776 kb
Host smart-5f40b54f-f6a1-479c-ab77-d9441d778df8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=664345362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res
et_error.664345362
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4094599339
Short name T328
Test name
Test status
Simulation time 254491004 ps
CPU time 3.71 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 201832 kb
Host smart-c9118626-93db-4e29-bab3-5757b2cae8a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4094599339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4094599339
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2084255550
Short name T850
Test name
Test status
Simulation time 57794363 ps
CPU time 13.53 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 201680 kb
Host smart-0b1136ce-bd57-41e0-8e8a-b94354d7f06e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2084255550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2084255550
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3571630946
Short name T88
Test name
Test status
Simulation time 69173667204 ps
CPU time 153.85 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:32:42 PM PDT 24
Peak memory 203060 kb
Host smart-575b9919-65b1-47ba-ab4d-a164971d0ada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3571630946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.3571630946
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2667810366
Short name T296
Test name
Test status
Simulation time 49565689 ps
CPU time 3.86 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201896 kb
Host smart-2855a1e5-66c5-423c-a0cd-ff08151031e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2667810366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2667810366
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.300719478
Short name T532
Test name
Test status
Simulation time 285037333 ps
CPU time 7.37 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201772 kb
Host smart-bacb699b-524d-46c3-b96d-b7995857f27f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=300719478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.300719478
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.3758616195
Short name T419
Test name
Test status
Simulation time 115289496 ps
CPU time 5.69 seconds
Started Apr 21 12:30:03 PM PDT 24
Finished Apr 21 12:30:09 PM PDT 24
Peak memory 201816 kb
Host smart-49bc48cb-8fb8-42c3-be37-3e8335ef5025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3758616195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3758616195
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3376219684
Short name T507
Test name
Test status
Simulation time 28861582651 ps
CPU time 116.12 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:32:03 PM PDT 24
Peak memory 201932 kb
Host smart-f251b4cd-7ca3-4168-809e-9628e1760897
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376219684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3376219684
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1124272050
Short name T57
Test name
Test status
Simulation time 15858736377 ps
CPU time 72.72 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:31:19 PM PDT 24
Peak memory 201956 kb
Host smart-90c14b09-3235-408c-9f8f-92f5fda42613
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1124272050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1124272050
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1713627301
Short name T405
Test name
Test status
Simulation time 363937344 ps
CPU time 7.37 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:16 PM PDT 24
Peak memory 201888 kb
Host smart-7b38a345-7010-4b3a-bf56-504c461e9e5d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713627301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1713627301
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1892298743
Short name T465
Test name
Test status
Simulation time 181617291 ps
CPU time 4.95 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201780 kb
Host smart-c796420e-a4c4-4f79-8124-711df56d4501
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1892298743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1892298743
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1513891695
Short name T140
Test name
Test status
Simulation time 13771585 ps
CPU time 1.26 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201892 kb
Host smart-a247cd5c-22bd-44ff-b0a3-564b39fbf827
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513891695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1513891695
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2082549895
Short name T339
Test name
Test status
Simulation time 8579005016 ps
CPU time 11.14 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 202020 kb
Host smart-7b599d5c-e47d-46f6-b301-5f04c1094e54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082549895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2082549895
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1377172815
Short name T845
Test name
Test status
Simulation time 2983606942 ps
CPU time 6.06 seconds
Started Apr 21 12:30:23 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201960 kb
Host smart-2642b8bc-7756-419a-80a6-5b5d565a9a5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1377172815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1377172815
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1842585297
Short name T692
Test name
Test status
Simulation time 11157534 ps
CPU time 1.12 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:03 PM PDT 24
Peak memory 201888 kb
Host smart-55f1242a-bd2c-4c21-a8b8-531aa134f5d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842585297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1842585297
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3418366719
Short name T126
Test name
Test status
Simulation time 1320128557 ps
CPU time 31.03 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:40 PM PDT 24
Peak memory 201868 kb
Host smart-4aa1bf6d-2506-4c1b-b479-386ef6db5870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3418366719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3418366719
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4046133951
Short name T451
Test name
Test status
Simulation time 4233909722 ps
CPU time 67.25 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 202876 kb
Host smart-8c094821-6b1e-4e20-91af-11970d4af4cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046133951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4046133951
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.817501877
Short name T745
Test name
Test status
Simulation time 224522321 ps
CPU time 25.56 seconds
Started Apr 21 12:30:02 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 203980 kb
Host smart-ea455ba0-9214-4bff-94e0-ae4ee6f71927
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=817501877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand
_reset.817501877
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2513271264
Short name T104
Test name
Test status
Simulation time 1616213039 ps
CPU time 57.59 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 205076 kb
Host smart-c5feb028-88ed-40c3-ae66-82db0d7adb98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2513271264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2513271264
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1367980944
Short name T330
Test name
Test status
Simulation time 60695309 ps
CPU time 2.45 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:08 PM PDT 24
Peak memory 201812 kb
Host smart-a397e0a5-d644-47c6-a257-831cc40ee7e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1367980944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1367980944
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3646581735
Short name T131
Test name
Test status
Simulation time 743085914 ps
CPU time 9.79 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201788 kb
Host smart-6f5de606-c13b-407d-88e3-3b9d89e601e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3646581735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3646581735
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1943296938
Short name T218
Test name
Test status
Simulation time 39235852241 ps
CPU time 249.26 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:34:12 PM PDT 24
Peak memory 203824 kb
Host smart-87b1a0e6-8efc-48db-82e0-4d90f3fde2d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1943296938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1943296938
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3448798041
Short name T382
Test name
Test status
Simulation time 242652645 ps
CPU time 3.64 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:09 PM PDT 24
Peak memory 201860 kb
Host smart-adbdf5dd-0f37-4b39-a3db-954719a2404b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3448798041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3448798041
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.2991209355
Short name T744
Test name
Test status
Simulation time 73940699 ps
CPU time 6.75 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201784 kb
Host smart-ebde53ec-4bdc-4e3b-aa9a-965300e99568
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2991209355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2991209355
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.1347290534
Short name T870
Test name
Test status
Simulation time 8186926 ps
CPU time 1.07 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201796 kb
Host smart-b1f1ac57-f054-4ea7-8ef9-b3dcfaa70c3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1347290534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1347290534
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3968785425
Short name T799
Test name
Test status
Simulation time 66021563589 ps
CPU time 50.12 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:31:08 PM PDT 24
Peak memory 201948 kb
Host smart-17d153a0-da96-486c-bfdf-8cb0ec81177b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968785425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3968785425
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3037555232
Short name T601
Test name
Test status
Simulation time 12801902185 ps
CPU time 91.61 seconds
Started Apr 21 12:30:00 PM PDT 24
Finished Apr 21 12:31:33 PM PDT 24
Peak memory 201972 kb
Host smart-13e09ead-ebc9-48ab-a92a-8ededb331cf9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3037555232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3037555232
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2849340080
Short name T484
Test name
Test status
Simulation time 24455432 ps
CPU time 2.46 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 201888 kb
Host smart-ff54f566-a187-4a01-92f2-cb5b49ef0f29
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849340080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2849340080
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1505077246
Short name T315
Test name
Test status
Simulation time 3971030456 ps
CPU time 9.51 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201840 kb
Host smart-bc8a6bd3-a6f9-4d55-ad8e-a8636e18b6e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1505077246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1505077246
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3898243414
Short name T779
Test name
Test status
Simulation time 134711071 ps
CPU time 1.33 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:03 PM PDT 24
Peak memory 201812 kb
Host smart-702e87b3-fad9-42b8-be74-4d96ed874d69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3898243414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3898243414
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3033845025
Short name T307
Test name
Test status
Simulation time 10962144420 ps
CPU time 9.91 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201924 kb
Host smart-a9b89b4d-a941-4e10-8a44-7a5c8a0c9d09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033845025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3033845025
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.123249657
Short name T129
Test name
Test status
Simulation time 1445855341 ps
CPU time 8.71 seconds
Started Apr 21 12:30:01 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201820 kb
Host smart-e9d2b5c8-586a-48e3-92d3-cf88b4c367cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=123249657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.123249657
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1110980096
Short name T431
Test name
Test status
Simulation time 16328617 ps
CPU time 1.14 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201800 kb
Host smart-c13833bd-f98c-4b66-bc85-9829161180a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110980096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1110980096
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3962497311
Short name T875
Test name
Test status
Simulation time 15209348282 ps
CPU time 127.47 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:32:16 PM PDT 24
Peak memory 202944 kb
Host smart-8e6695da-f7b1-4c24-9030-54224150c917
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3962497311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3962497311
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3775317138
Short name T550
Test name
Test status
Simulation time 3205216604 ps
CPU time 51.19 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201944 kb
Host smart-b558acb5-472b-4fc1-aa8a-2c74daec7dd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3775317138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3775317138
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1172335068
Short name T251
Test name
Test status
Simulation time 517611587 ps
CPU time 80.01 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:31:45 PM PDT 24
Peak memory 204324 kb
Host smart-635ca16c-9a3d-4cfa-aab4-0192122cf4c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1172335068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1172335068
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3870584624
Short name T876
Test name
Test status
Simulation time 445087335 ps
CPU time 6.04 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201804 kb
Host smart-d128b5ef-3c00-4739-84b0-ba28d86487eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3870584624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3870584624
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3877901171
Short name T464
Test name
Test status
Simulation time 2140824221 ps
CPU time 10.41 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:20 PM PDT 24
Peak memory 201792 kb
Host smart-44922e23-6196-4f3d-aa04-054c890a9fae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3877901171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3877901171
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3656622296
Short name T97
Test name
Test status
Simulation time 85145180680 ps
CPU time 312.63 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:35:20 PM PDT 24
Peak memory 203664 kb
Host smart-f3019538-ff87-4140-82ac-7ae2d2e13cf1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3656622296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.3656622296
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2901851913
Short name T305
Test name
Test status
Simulation time 1089214865 ps
CPU time 9 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 201800 kb
Host smart-8b8297d4-743a-44d7-9b41-755006a6082b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2901851913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2901851913
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.1746221463
Short name T649
Test name
Test status
Simulation time 99633719 ps
CPU time 2.62 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201792 kb
Host smart-d932ba21-71d0-4ad5-a7e7-30bcc2f79d70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1746221463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1746221463
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.3381842410
Short name T698
Test name
Test status
Simulation time 4616883078 ps
CPU time 13.62 seconds
Started Apr 21 12:30:15 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201924 kb
Host smart-9d5648f1-172f-468b-b984-91579a3f0aac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3381842410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3381842410
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1913475822
Short name T372
Test name
Test status
Simulation time 44013024331 ps
CPU time 71.64 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:31:18 PM PDT 24
Peak memory 201944 kb
Host smart-518d454d-c044-4a29-92d1-18e6866b9439
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913475822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1913475822
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3238234024
Short name T826
Test name
Test status
Simulation time 17538004114 ps
CPU time 53.16 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 202044 kb
Host smart-dec73e4b-e051-495e-ba85-0de193355ded
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3238234024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3238234024
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.77213239
Short name T312
Test name
Test status
Simulation time 170851311 ps
CPU time 7.78 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:20 PM PDT 24
Peak memory 201888 kb
Host smart-6fa8fb18-ad0d-4f4a-bee6-87abdd2f2973
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77213239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.77213239
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2545817072
Short name T377
Test name
Test status
Simulation time 13078942 ps
CPU time 1.48 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 201784 kb
Host smart-acce4e70-f5c5-4007-825c-5cffc92526ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2545817072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2545817072
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.2150633294
Short name T849
Test name
Test status
Simulation time 121672862 ps
CPU time 1.47 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:12 PM PDT 24
Peak memory 201924 kb
Host smart-fc057e50-41e9-404f-914a-4dcdb4c6f162
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2150633294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2150633294
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.4161356820
Short name T100
Test name
Test status
Simulation time 2613629625 ps
CPU time 9.22 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 201844 kb
Host smart-63638bb9-2627-4bc9-ae3c-a936d371fa82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161356820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4161356820
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3251620173
Short name T811
Test name
Test status
Simulation time 7333485248 ps
CPU time 14.43 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:25 PM PDT 24
Peak memory 201936 kb
Host smart-ee168907-9dc7-4153-8ebc-df7b57841d1b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3251620173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3251620173
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.235239281
Short name T146
Test name
Test status
Simulation time 8811713 ps
CPU time 1.21 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:11 PM PDT 24
Peak memory 201796 kb
Host smart-dc355e3e-8c74-452b-9001-d2a7579d5697
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235239281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.235239281
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1100941028
Short name T665
Test name
Test status
Simulation time 1784251093 ps
CPU time 27.8 seconds
Started Apr 21 12:30:05 PM PDT 24
Finished Apr 21 12:30:33 PM PDT 24
Peak memory 202116 kb
Host smart-6a656e78-c3b7-462f-b9b3-a51b2aa4db08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1100941028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1100941028
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3313654828
Short name T209
Test name
Test status
Simulation time 5947953130 ps
CPU time 51.74 seconds
Started Apr 21 12:30:35 PM PDT 24
Finished Apr 21 12:31:27 PM PDT 24
Peak memory 201980 kb
Host smart-1155e97c-e307-4ae2-b85c-0454fe0f261e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313654828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3313654828
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1576735340
Short name T800
Test name
Test status
Simulation time 2336164658 ps
CPU time 53.41 seconds
Started Apr 21 12:30:07 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 203888 kb
Host smart-e1ba5180-fb2e-4819-a3c9-280d8dcc1e4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576735340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.1576735340
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3379373487
Short name T600
Test name
Test status
Simulation time 1951571373 ps
CPU time 49.52 seconds
Started Apr 21 12:30:11 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 203300 kb
Host smart-00d7d196-ec39-4f81-bac8-c24927b8a7fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379373487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.3379373487
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1612209897
Short name T115
Test name
Test status
Simulation time 2459660003 ps
CPU time 12.29 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 201860 kb
Host smart-b1515c55-3bc2-4c29-a8e7-15e8a17b0857
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1612209897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1612209897
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1160593646
Short name T10
Test name
Test status
Simulation time 517693668 ps
CPU time 6.39 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:16 PM PDT 24
Peak memory 201816 kb
Host smart-9fc95817-cd24-42fc-9331-6c977b470d42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1160593646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1160593646
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2149657749
Short name T230
Test name
Test status
Simulation time 26390071788 ps
CPU time 74.33 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:31:27 PM PDT 24
Peak memory 201924 kb
Host smart-8d2a2db7-e42f-4e0f-9502-fd910c8a4993
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2149657749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2149657749
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1787616804
Short name T321
Test name
Test status
Simulation time 523656982 ps
CPU time 7.7 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 201892 kb
Host smart-c8cd7351-cfa2-4a26-bc7b-c709923c4852
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1787616804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1787616804
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3981621073
Short name T670
Test name
Test status
Simulation time 1012742136 ps
CPU time 5.4 seconds
Started Apr 21 12:30:08 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 201852 kb
Host smart-dfc3efcf-6110-46ad-a033-a5372962631b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3981621073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3981621073
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2514880770
Short name T669
Test name
Test status
Simulation time 63039442 ps
CPU time 7.04 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:17 PM PDT 24
Peak memory 201792 kb
Host smart-54e975fb-5741-4c04-980b-76e0f468b511
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2514880770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2514880770
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.589335058
Short name T148
Test name
Test status
Simulation time 179481088957 ps
CPU time 134.68 seconds
Started Apr 21 12:30:22 PM PDT 24
Finished Apr 21 12:32:37 PM PDT 24
Peak memory 201904 kb
Host smart-9e048179-a7d5-4fa6-8c0c-763e525bc9b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=589335058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.589335058
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3696171765
Short name T508
Test name
Test status
Simulation time 14610008532 ps
CPU time 109.7 seconds
Started Apr 21 12:30:13 PM PDT 24
Finished Apr 21 12:32:03 PM PDT 24
Peak memory 202028 kb
Host smart-59e12cea-0b48-4d02-9a25-b468026a68f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3696171765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3696171765
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.386611098
Short name T609
Test name
Test status
Simulation time 43867148 ps
CPU time 4.27 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201804 kb
Host smart-8de88419-5e9c-4254-9e52-98b8a097bb87
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386611098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.386611098
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.300480698
Short name T450
Test name
Test status
Simulation time 6142834269 ps
CPU time 11.26 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:21 PM PDT 24
Peak memory 201960 kb
Host smart-07287ad9-84c2-4f35-9e14-d19b861b00c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=300480698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.300480698
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.4079910765
Short name T381
Test name
Test status
Simulation time 12106935 ps
CPU time 1.11 seconds
Started Apr 21 12:30:09 PM PDT 24
Finished Apr 21 12:30:10 PM PDT 24
Peak memory 201800 kb
Host smart-b2b57732-bc3b-4655-b9b5-291cdbcc6ad4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4079910765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4079910765
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.433117792
Short name T588
Test name
Test status
Simulation time 4486108951 ps
CPU time 8.88 seconds
Started Apr 21 12:30:06 PM PDT 24
Finished Apr 21 12:30:16 PM PDT 24
Peak memory 201996 kb
Host smart-76130df8-b08e-4205-b4b2-deb6b7db2f3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=433117792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.433117792
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2729034025
Short name T14
Test name
Test status
Simulation time 1470899773 ps
CPU time 6.93 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 201804 kb
Host smart-811c4a62-8a80-4cf1-8002-2448f1a067e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2729034025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2729034025
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.946956200
Short name T278
Test name
Test status
Simulation time 9820636 ps
CPU time 1.17 seconds
Started Apr 21 12:30:11 PM PDT 24
Finished Apr 21 12:30:13 PM PDT 24
Peak memory 201860 kb
Host smart-e888fa3e-cc28-46f5-82b2-05b05effce24
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946956200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.946956200
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1174460210
Short name T453
Test name
Test status
Simulation time 443013612 ps
CPU time 28.93 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 202828 kb
Host smart-dd5c0dd2-269a-430f-a5a9-bd4deffaef67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174460210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1174460210
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2581040870
Short name T341
Test name
Test status
Simulation time 489659433 ps
CPU time 39.94 seconds
Started Apr 21 12:30:20 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 202796 kb
Host smart-4fbe0d17-36e0-4e8f-8d70-6493db8ea4d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581040870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2581040870
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.373723019
Short name T163
Test name
Test status
Simulation time 941813262 ps
CPU time 157.59 seconds
Started Apr 21 12:30:15 PM PDT 24
Finished Apr 21 12:32:53 PM PDT 24
Peak memory 206828 kb
Host smart-b94a5e51-97c7-4af1-b968-38a6c87edf89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373723019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand
_reset.373723019
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3077350325
Short name T701
Test name
Test status
Simulation time 544713167 ps
CPU time 51.35 seconds
Started Apr 21 12:30:15 PM PDT 24
Finished Apr 21 12:31:07 PM PDT 24
Peak memory 204104 kb
Host smart-f74b2e9a-941f-43b5-9941-5266adabbfad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3077350325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3077350325
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2508045633
Short name T435
Test name
Test status
Simulation time 338500184 ps
CPU time 4.27 seconds
Started Apr 21 12:30:10 PM PDT 24
Finished Apr 21 12:30:15 PM PDT 24
Peak memory 201916 kb
Host smart-7a0ab63f-d07a-4376-8331-7ceac35ef415
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2508045633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2508045633
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.675393410
Short name T363
Test name
Test status
Simulation time 198064986 ps
CPU time 11.1 seconds
Started Apr 21 12:30:27 PM PDT 24
Finished Apr 21 12:30:38 PM PDT 24
Peak memory 201872 kb
Host smart-92c20236-a14b-4afb-9b6f-591a4c65180e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=675393410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.675393410
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.29819366
Short name T200
Test name
Test status
Simulation time 490602736 ps
CPU time 9.95 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201792 kb
Host smart-3954a733-b70c-4588-94b0-ddb2ef35b8d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29819366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.29819366
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2392044361
Short name T390
Test name
Test status
Simulation time 819589220 ps
CPU time 12.36 seconds
Started Apr 21 12:30:15 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201896 kb
Host smart-44c01821-bb55-4111-a753-b507f7d38926
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2392044361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2392044361
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2019659345
Short name T426
Test name
Test status
Simulation time 260529710 ps
CPU time 5.87 seconds
Started Apr 21 12:30:11 PM PDT 24
Finished Apr 21 12:30:18 PM PDT 24
Peak memory 201800 kb
Host smart-4daeaee9-1e26-48f1-9a22-444ecda523a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2019659345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2019659345
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3761941331
Short name T79
Test name
Test status
Simulation time 9854998473 ps
CPU time 46.78 seconds
Started Apr 21 12:30:18 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201940 kb
Host smart-6e8faf7b-3523-46c4-9f5d-e53f01c1d714
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761941331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3761941331
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2491519572
Short name T808
Test name
Test status
Simulation time 5583054724 ps
CPU time 43.93 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:31:02 PM PDT 24
Peak memory 202048 kb
Host smart-b551d2d3-84f9-476b-afd7-b7356ced970c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2491519572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2491519572
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2952287584
Short name T545
Test name
Test status
Simulation time 63228710 ps
CPU time 5.18 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201772 kb
Host smart-e71cbc2c-d0b8-4756-b3c9-baaddb76c90c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952287584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2952287584
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.1098387199
Short name T569
Test name
Test status
Simulation time 225487316 ps
CPU time 2.82 seconds
Started Apr 21 12:30:18 PM PDT 24
Finished Apr 21 12:30:21 PM PDT 24
Peak memory 201812 kb
Host smart-58b54672-77d7-40b2-a674-4cee7fe1a4e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1098387199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1098387199
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.788628074
Short name T31
Test name
Test status
Simulation time 34444774 ps
CPU time 1.17 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:14 PM PDT 24
Peak memory 201808 kb
Host smart-0352779c-cfa5-4d67-973a-5a528061c5cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=788628074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.788628074
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.549126030
Short name T181
Test name
Test status
Simulation time 2624729612 ps
CPU time 8.69 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:21 PM PDT 24
Peak memory 201920 kb
Host smart-1a1a37cc-dd0e-4c05-8438-578d6f181956
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=549126030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.549126030
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.245378110
Short name T68
Test name
Test status
Simulation time 4739323001 ps
CPU time 10.53 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 201920 kb
Host smart-f3918825-f630-42e8-95aa-3006b400c47f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=245378110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.245378110
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2061385007
Short name T657
Test name
Test status
Simulation time 13425481 ps
CPU time 1.24 seconds
Started Apr 21 12:30:27 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201876 kb
Host smart-4e1cd9aa-c380-466c-9930-08239faeedc9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061385007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2061385007
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2807683724
Short name T89
Test name
Test status
Simulation time 4831051348 ps
CPU time 51.25 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:31:24 PM PDT 24
Peak memory 203632 kb
Host smart-aefad131-90d6-433b-b791-45e15a11dd76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2807683724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2807683724
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2946707237
Short name T255
Test name
Test status
Simulation time 152559492 ps
CPU time 9.75 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:49 PM PDT 24
Peak memory 201900 kb
Host smart-e3f54292-1cc5-4dcd-9845-4cefca21c55c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946707237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2946707237
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1196779080
Short name T475
Test name
Test status
Simulation time 1369249472 ps
CPU time 115.67 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:32:28 PM PDT 24
Peak memory 206616 kb
Host smart-87183db6-a050-43b1-9cea-97939c0cf0f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196779080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.1196779080
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2307821179
Short name T495
Test name
Test status
Simulation time 1672633647 ps
CPU time 150.22 seconds
Started Apr 21 12:30:16 PM PDT 24
Finished Apr 21 12:32:47 PM PDT 24
Peak memory 207560 kb
Host smart-44ae9e91-0ec5-40fd-bbbc-5bf9e01209d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2307821179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.2307821179
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1698530215
Short name T567
Test name
Test status
Simulation time 112325334 ps
CPU time 8.1 seconds
Started Apr 21 12:30:27 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 201784 kb
Host smart-6e3ed8ce-2062-4b42-a400-74e7f94f3c7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698530215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1698530215
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1890848269
Short name T831
Test name
Test status
Simulation time 685006414 ps
CPU time 9.12 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201816 kb
Host smart-da025a02-5953-4676-9da6-3b80beafaf41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1890848269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1890848269
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2171390105
Short name T236
Test name
Test status
Simulation time 289616767936 ps
CPU time 396.53 seconds
Started Apr 21 12:30:16 PM PDT 24
Finished Apr 21 12:36:52 PM PDT 24
Peak memory 205080 kb
Host smart-d6ebc803-988c-45b9-a633-cb829c5f3043
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2171390105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.2171390105
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1847600397
Short name T109
Test name
Test status
Simulation time 460308128 ps
CPU time 7.65 seconds
Started Apr 21 12:30:12 PM PDT 24
Finished Apr 21 12:30:20 PM PDT 24
Peak memory 201808 kb
Host smart-01f90775-a488-4b5a-b0af-3130e5ed90e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847600397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1847600397
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.1769271235
Short name T697
Test name
Test status
Simulation time 1460113865 ps
CPU time 13.4 seconds
Started Apr 21 12:30:18 PM PDT 24
Finished Apr 21 12:30:31 PM PDT 24
Peak memory 201832 kb
Host smart-b279e58f-dd78-44ba-b24c-74e7a40e94b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769271235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1769271235
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.4001946066
Short name T308
Test name
Test status
Simulation time 685020715 ps
CPU time 8.51 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201796 kb
Host smart-17e8b3e5-fe03-4462-8b19-fea6b527ed49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4001946066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.4001946066
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.555548279
Short name T737
Test name
Test status
Simulation time 100947840796 ps
CPU time 104.79 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:32:24 PM PDT 24
Peak memory 201932 kb
Host smart-1a220c13-9e3b-4d36-9f79-2b166c7dde4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=555548279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.555548279
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1829368884
Short name T98
Test name
Test status
Simulation time 2500309405 ps
CPU time 20.29 seconds
Started Apr 21 12:30:13 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201620 kb
Host smart-c1d7a5d0-54bd-4eec-abbe-930e98db6a28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1829368884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1829368884
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3399533663
Short name T49
Test name
Test status
Simulation time 137540327 ps
CPU time 8.78 seconds
Started Apr 21 12:30:18 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201836 kb
Host smart-16bf9769-6282-45c9-8389-7105df6e8011
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399533663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3399533663
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3266625129
Short name T301
Test name
Test status
Simulation time 8223065 ps
CPU time 1.08 seconds
Started Apr 21 12:30:27 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201796 kb
Host smart-0205b56a-7c15-4d1d-aec8-6cf858395acf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3266625129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3266625129
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.2407208426
Short name T646
Test name
Test status
Simulation time 337074295 ps
CPU time 1.66 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201800 kb
Host smart-9a461312-89aa-408f-9169-e3fdd18683b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2407208426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2407208426
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2725721212
Short name T423
Test name
Test status
Simulation time 2410309459 ps
CPU time 7.23 seconds
Started Apr 21 12:30:15 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 201904 kb
Host smart-1a8f7787-24ac-4114-8bb5-f817c40caddb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725721212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2725721212
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.970412031
Short name T814
Test name
Test status
Simulation time 4109073023 ps
CPU time 10.59 seconds
Started Apr 21 12:30:25 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 201960 kb
Host smart-5f811315-a737-4aa5-be04-d9464567dae4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=970412031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.970412031
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2417415992
Short name T595
Test name
Test status
Simulation time 11630310 ps
CPU time 1.03 seconds
Started Apr 21 12:30:22 PM PDT 24
Finished Apr 21 12:30:23 PM PDT 24
Peak memory 201860 kb
Host smart-2fb6d830-b5d8-437e-b298-4385bb079b01
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417415992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2417415992
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.4035000292
Short name T183
Test name
Test status
Simulation time 81851552 ps
CPU time 9.12 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 201796 kb
Host smart-79723bf6-795a-476f-9335-a2a07b8eb182
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4035000292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4035000292
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2297634521
Short name T564
Test name
Test status
Simulation time 46761477 ps
CPU time 2.43 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201784 kb
Host smart-3246411d-4efe-4c2c-a06d-39c4b9004d8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2297634521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2297634521
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2739948920
Short name T541
Test name
Test status
Simulation time 331066605 ps
CPU time 37.66 seconds
Started Apr 21 12:30:34 PM PDT 24
Finished Apr 21 12:31:12 PM PDT 24
Peak memory 204220 kb
Host smart-b2d75e6d-90c0-492c-93f3-871d9e1fabde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739948920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.2739948920
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1903021301
Short name T7
Test name
Test status
Simulation time 352181745 ps
CPU time 38.78 seconds
Started Apr 21 12:30:44 PM PDT 24
Finished Apr 21 12:31:23 PM PDT 24
Peak memory 203184 kb
Host smart-70d7f945-67a9-4921-ae22-437faaa9ffbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903021301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.1903021301
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4167145133
Short name T613
Test name
Test status
Simulation time 108709878 ps
CPU time 1.88 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:35 PM PDT 24
Peak memory 201480 kb
Host smart-8c96342c-42f7-4382-8ee5-f36be6362504
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4167145133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4167145133
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.489969318
Short name T629
Test name
Test status
Simulation time 6277394150 ps
CPU time 20.79 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:31:16 PM PDT 24
Peak memory 201920 kb
Host smart-f2b1f371-8a00-4cb7-9f3c-b9eecdde63fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=489969318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.489969318
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3461773733
Short name T197
Test name
Test status
Simulation time 5140730291 ps
CPU time 22.1 seconds
Started Apr 21 12:30:19 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201936 kb
Host smart-53ce7adc-f2c6-4a9a-9e9e-24093adc5f0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3461773733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3461773733
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3510488876
Short name T671
Test name
Test status
Simulation time 478832763 ps
CPU time 4.88 seconds
Started Apr 21 12:30:23 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201796 kb
Host smart-cd5b35aa-6276-4441-9115-112155e4a9a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510488876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3510488876
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2013879855
Short name T764
Test name
Test status
Simulation time 1043565395 ps
CPU time 8.92 seconds
Started Apr 21 12:30:23 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201852 kb
Host smart-cafd93a7-b892-4bed-bc8d-defb156e6198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2013879855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2013879855
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.4010545711
Short name T55
Test name
Test status
Simulation time 2147910664 ps
CPU time 7.96 seconds
Started Apr 21 12:30:13 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 201688 kb
Host smart-857e48e5-efc8-46e0-b907-c12700fb7096
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010545711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.4010545711
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2815415645
Short name T460
Test name
Test status
Simulation time 62404794304 ps
CPU time 67.97 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:31:26 PM PDT 24
Peak memory 201968 kb
Host smart-44de6a26-6efd-41ac-b5be-20367504cef5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815415645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2815415645
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.124788813
Short name T67
Test name
Test status
Simulation time 18237437196 ps
CPU time 71.63 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:31:29 PM PDT 24
Peak memory 202024 kb
Host smart-d3fa4c08-7719-4a15-ad21-6ad84840be52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=124788813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.124788813
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2869512651
Short name T769
Test name
Test status
Simulation time 42006573 ps
CPU time 2.6 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:31 PM PDT 24
Peak memory 201860 kb
Host smart-c424e3db-5a9d-45d3-8439-360b21a04dab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869512651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2869512651
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.3335498408
Short name T780
Test name
Test status
Simulation time 716370754 ps
CPU time 9.26 seconds
Started Apr 21 12:30:20 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201820 kb
Host smart-80919445-8582-4a99-a895-faec7409b4e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335498408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3335498408
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.1127857963
Short name T890
Test name
Test status
Simulation time 10312574 ps
CPU time 1.1 seconds
Started Apr 21 12:30:17 PM PDT 24
Finished Apr 21 12:30:19 PM PDT 24
Peak memory 201820 kb
Host smart-839e4103-090c-4183-91e9-f8ee482c6b18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1127857963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1127857963
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.22423847
Short name T687
Test name
Test status
Simulation time 1465664732 ps
CPU time 7.87 seconds
Started Apr 21 12:30:33 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201892 kb
Host smart-ded55f1e-566f-4a54-8445-15ac80f5b191
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.22423847
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1495224776
Short name T682
Test name
Test status
Simulation time 2204826551 ps
CPU time 12.41 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201856 kb
Host smart-1cdb1b15-707f-47f0-b851-7f2c1cb4acfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1495224776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1495224776
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.887550873
Short name T117
Test name
Test status
Simulation time 9118036 ps
CPU time 1.06 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 201800 kb
Host smart-3ad52829-7595-45c3-a247-317282988999
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887550873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.887550873
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2895649864
Short name T489
Test name
Test status
Simulation time 1290213651 ps
CPU time 20.66 seconds
Started Apr 21 12:30:20 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 202848 kb
Host smart-361a0b0d-1074-4111-af80-da617c9f0719
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2895649864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2895649864
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1563508250
Short name T759
Test name
Test status
Simulation time 992620017 ps
CPU time 27.72 seconds
Started Apr 21 12:30:18 PM PDT 24
Finished Apr 21 12:30:46 PM PDT 24
Peak memory 201788 kb
Host smart-b859f600-4417-4543-8bb3-70b549933230
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1563508250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1563508250
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.336241879
Short name T851
Test name
Test status
Simulation time 391233679 ps
CPU time 76.99 seconds
Started Apr 21 12:30:21 PM PDT 24
Finished Apr 21 12:31:38 PM PDT 24
Peak memory 204040 kb
Host smart-00c5f454-99d6-4a67-860c-5099f188fb62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=336241879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand
_reset.336241879
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.335618161
Short name T428
Test name
Test status
Simulation time 201475077 ps
CPU time 28.75 seconds
Started Apr 21 12:30:41 PM PDT 24
Finished Apr 21 12:31:10 PM PDT 24
Peak memory 203016 kb
Host smart-c4b336f6-9f93-482d-8a82-bf3ee2d76115
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=335618161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res
et_error.335618161
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1153645072
Short name T848
Test name
Test status
Simulation time 951116188 ps
CPU time 9.8 seconds
Started Apr 21 12:30:22 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201820 kb
Host smart-fc5e8323-be4d-495d-93d4-c7b2a74c9165
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1153645072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1153645072
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3985410966
Short name T85
Test name
Test status
Simulation time 1637136612 ps
CPU time 19.75 seconds
Started Apr 21 12:30:21 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201796 kb
Host smart-c42acbce-d3da-4feb-80cb-f83e458322fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3985410966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3985410966
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2160670647
Short name T196
Test name
Test status
Simulation time 3206042978 ps
CPU time 18.33 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:58 PM PDT 24
Peak memory 201924 kb
Host smart-53c12893-e2d9-436b-ae63-3ec1999d1328
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2160670647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.2160670647
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.579196394
Short name T713
Test name
Test status
Simulation time 342881182 ps
CPU time 4.9 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201784 kb
Host smart-9f2c618c-4112-4eef-98d0-3ee40c067a81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=579196394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.579196394
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.2961119972
Short name T778
Test name
Test status
Simulation time 689506870 ps
CPU time 4.47 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:45 PM PDT 24
Peak memory 201884 kb
Host smart-4f78ddf6-2f9f-48c8-a5e1-3c8437e32c62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2961119972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2961119972
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.2715194924
Short name T479
Test name
Test status
Simulation time 48988761 ps
CPU time 3.95 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 201892 kb
Host smart-a9cf70d2-6c54-4022-86cf-082d57c1f4a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2715194924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2715194924
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.801019347
Short name T53
Test name
Test status
Simulation time 11410617906 ps
CPU time 48.94 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:31:16 PM PDT 24
Peak memory 201808 kb
Host smart-51d0fdc8-601a-43a1-b109-ec72d468baee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=801019347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.801019347
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1262380079
Short name T332
Test name
Test status
Simulation time 74379907470 ps
CPU time 143.65 seconds
Started Apr 21 12:30:22 PM PDT 24
Finished Apr 21 12:32:46 PM PDT 24
Peak memory 201940 kb
Host smart-59430e50-55e4-416e-9c6c-36e2186e6f1c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1262380079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1262380079
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.743762571
Short name T806
Test name
Test status
Simulation time 52295832 ps
CPU time 6.2 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 201820 kb
Host smart-d2f62716-a5c8-4089-b0b5-a7bf97c89826
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743762571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.743762571
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.4119565354
Short name T367
Test name
Test status
Simulation time 287448972 ps
CPU time 3.45 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201904 kb
Host smart-b5f2af74-81f0-42fb-87ca-e7b636916ea4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4119565354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.4119565354
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.1966516880
Short name T753
Test name
Test status
Simulation time 17233060 ps
CPU time 0.96 seconds
Started Apr 21 12:30:21 PM PDT 24
Finished Apr 21 12:30:22 PM PDT 24
Peak memory 201816 kb
Host smart-08b41d7d-2247-4891-b8d8-f7d2ab6570a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1966516880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1966516880
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1377618407
Short name T94
Test name
Test status
Simulation time 8777273493 ps
CPU time 9.04 seconds
Started Apr 21 12:30:44 PM PDT 24
Finished Apr 21 12:30:53 PM PDT 24
Peak memory 202020 kb
Host smart-a950e3fc-aab2-446a-93ea-7a5aee67a3fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377618407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1377618407
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.522169258
Short name T656
Test name
Test status
Simulation time 2384125141 ps
CPU time 6.38 seconds
Started Apr 21 12:30:20 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201916 kb
Host smart-e0ba6469-a0ee-443b-bdac-9b118b1295ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=522169258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.522169258
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2852140261
Short name T276
Test name
Test status
Simulation time 9826161 ps
CPU time 1.2 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201892 kb
Host smart-a3bfd377-3826-41b5-9a80-216351a46744
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852140261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2852140261
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2926844068
Short name T65
Test name
Test status
Simulation time 3330944368 ps
CPU time 36.31 seconds
Started Apr 21 12:30:34 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 201856 kb
Host smart-98a57ecb-5860-4c13-b765-b56665b27ce5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2926844068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2926844068
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.278512210
Short name T103
Test name
Test status
Simulation time 158381136 ps
CPU time 13.87 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:30:57 PM PDT 24
Peak memory 201724 kb
Host smart-b349355b-c2c9-49c8-94cd-48f72c418f8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278512210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.278512210
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1080643040
Short name T161
Test name
Test status
Simulation time 424748893 ps
CPU time 37.4 seconds
Started Apr 21 12:30:20 PM PDT 24
Finished Apr 21 12:30:58 PM PDT 24
Peak memory 204272 kb
Host smart-94618679-20e8-4cf5-a6e6-943021f32e8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1080643040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.1080643040
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.349254602
Short name T733
Test name
Test status
Simulation time 884710057 ps
CPU time 59.23 seconds
Started Apr 21 12:30:31 PM PDT 24
Finished Apr 21 12:31:31 PM PDT 24
Peak memory 204356 kb
Host smart-47753255-3de4-4229-acf3-965f8e9ca238
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=349254602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.349254602
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3695326908
Short name T577
Test name
Test status
Simulation time 176014003 ps
CPU time 3.83 seconds
Started Apr 21 12:30:25 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201864 kb
Host smart-ae501f06-67d8-48b5-966d-a13605798c50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3695326908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3695326908
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.373649031
Short name T678
Test name
Test status
Simulation time 1039346634 ps
CPU time 18.49 seconds
Started Apr 21 12:28:48 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201804 kb
Host smart-ff0e4ea6-e679-40c1-b0f7-25443302fdf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373649031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.373649031
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3126512049
Short name T227
Test name
Test status
Simulation time 267282891849 ps
CPU time 325.11 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:34:17 PM PDT 24
Peak memory 203580 kb
Host smart-14b91d10-88fc-47bc-92d2-4b9c034758c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3126512049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3126512049
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3593739165
Short name T837
Test name
Test status
Simulation time 1603391540 ps
CPU time 4.93 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201812 kb
Host smart-8942cad9-2de9-40ac-a218-81ef5217784b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3593739165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3593739165
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.1917238895
Short name T252
Test name
Test status
Simulation time 248551328 ps
CPU time 8.39 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201800 kb
Host smart-81494aac-64d8-4dfd-9c17-41918fbf5dec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1917238895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1917238895
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.3212307649
Short name T185
Test name
Test status
Simulation time 1379166339 ps
CPU time 14.28 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:29:01 PM PDT 24
Peak memory 201888 kb
Host smart-a11aaa73-f329-43e0-8466-b761e8e31114
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3212307649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3212307649
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3822551475
Short name T836
Test name
Test status
Simulation time 46058146204 ps
CPU time 143.24 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:31:21 PM PDT 24
Peak memory 201924 kb
Host smart-f14977a8-1e77-4868-aa81-27c2ba191683
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822551475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3822551475
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1549647006
Short name T756
Test name
Test status
Simulation time 8604414372 ps
CPU time 54.32 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:29:41 PM PDT 24
Peak memory 201920 kb
Host smart-ca7323b7-9f82-48a0-9ec7-b711a1edf165
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1549647006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1549647006
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1837601486
Short name T604
Test name
Test status
Simulation time 61221612 ps
CPU time 2.09 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:28:57 PM PDT 24
Peak memory 201804 kb
Host smart-555af2db-da8b-4d75-93d8-47bd8081060f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837601486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1837601486
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3528143845
Short name T617
Test name
Test status
Simulation time 1516641149 ps
CPU time 5.26 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201900 kb
Host smart-728ce6aa-9cf3-41a0-9b7b-352f0a1dcb4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3528143845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3528143845
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1537400444
Short name T457
Test name
Test status
Simulation time 19496793 ps
CPU time 1 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:50 PM PDT 24
Peak memory 201840 kb
Host smart-48348b2c-7604-4a4f-8e42-99c7d99469d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1537400444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1537400444
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2874994272
Short name T316
Test name
Test status
Simulation time 2464843357 ps
CPU time 9.01 seconds
Started Apr 21 12:28:43 PM PDT 24
Finished Apr 21 12:28:52 PM PDT 24
Peak memory 201960 kb
Host smart-f219e066-97c5-4b1a-b011-6c8045e4aa81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874994272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2874994272
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.570216890
Short name T111
Test name
Test status
Simulation time 2012136215 ps
CPU time 9.25 seconds
Started Apr 21 12:28:48 PM PDT 24
Finished Apr 21 12:28:58 PM PDT 24
Peak memory 201904 kb
Host smart-d6a291ec-5461-4521-9eef-73bb53f7259d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=570216890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.570216890
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.117331480
Short name T398
Test name
Test status
Simulation time 12308578 ps
CPU time 1.39 seconds
Started Apr 21 12:28:41 PM PDT 24
Finished Apr 21 12:28:43 PM PDT 24
Peak memory 201792 kb
Host smart-cac0a588-d5d8-4f52-9e27-b44c6d40656d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117331480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.117331480
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3986499134
Short name T78
Test name
Test status
Simulation time 2323028902 ps
CPU time 25.61 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:23 PM PDT 24
Peak memory 201928 kb
Host smart-e7fdfd8c-7fe1-491f-bc6b-f26542f2b65f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3986499134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3986499134
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1012785968
Short name T497
Test name
Test status
Simulation time 776553996 ps
CPU time 28.5 seconds
Started Apr 21 12:28:50 PM PDT 24
Finished Apr 21 12:29:19 PM PDT 24
Peak memory 201804 kb
Host smart-af908f77-a517-4b60-83af-3d615f8e55b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012785968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1012785968
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3985617735
Short name T822
Test name
Test status
Simulation time 123580785 ps
CPU time 13.24 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:09 PM PDT 24
Peak memory 202812 kb
Host smart-df38c629-6375-462b-a679-7418a489c3ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3985617735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.3985617735
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2815460747
Short name T757
Test name
Test status
Simulation time 1995737942 ps
CPU time 57.76 seconds
Started Apr 21 12:28:53 PM PDT 24
Finished Apr 21 12:29:51 PM PDT 24
Peak memory 203908 kb
Host smart-e9ed8c8d-f7aa-4067-9326-2114b07c479c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2815460747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.2815460747
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1497482207
Short name T583
Test name
Test status
Simulation time 369209337 ps
CPU time 6.42 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:29:01 PM PDT 24
Peak memory 201804 kb
Host smart-1a4882cf-7549-4cc8-b1bb-c126a0f670c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1497482207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1497482207
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4237555938
Short name T763
Test name
Test status
Simulation time 24355802 ps
CPU time 3.13 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201804 kb
Host smart-c3ce8f62-32cb-4436-972d-d14e446ef053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4237555938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4237555938
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3187768596
Short name T774
Test name
Test status
Simulation time 40186732153 ps
CPU time 195.14 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:33:46 PM PDT 24
Peak memory 203168 kb
Host smart-d44941a7-468b-4935-b271-20a2c8abe556
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3187768596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.3187768596
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1431550401
Short name T679
Test name
Test status
Simulation time 192115153 ps
CPU time 1.74 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:02 PM PDT 24
Peak memory 201804 kb
Host smart-0acd453b-7571-4f65-8735-7b9c67ae7e69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1431550401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1431550401
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2150163311
Short name T469
Test name
Test status
Simulation time 6867698851 ps
CPU time 12.01 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201912 kb
Host smart-5cc89fab-3e64-4856-a884-53066c81336c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2150163311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2150163311
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2956969667
Short name T380
Test name
Test status
Simulation time 100125056 ps
CPU time 4.29 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 201804 kb
Host smart-068d5b9f-d341-4966-b6d6-6a79a959fa0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2956969667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2956969667
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.4207559543
Short name T724
Test name
Test status
Simulation time 24476156231 ps
CPU time 56.8 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:31:53 PM PDT 24
Peak memory 202024 kb
Host smart-d819bcd2-521f-40a2-a4e3-28ddad45038c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207559543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4207559543
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3197265997
Short name T188
Test name
Test status
Simulation time 17117765548 ps
CPU time 73.02 seconds
Started Apr 21 12:30:46 PM PDT 24
Finished Apr 21 12:32:00 PM PDT 24
Peak memory 202024 kb
Host smart-6492c433-795d-404b-872c-4087ed3f6060
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3197265997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3197265997
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1001895748
Short name T164
Test name
Test status
Simulation time 329653070 ps
CPU time 8 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201808 kb
Host smart-3041b2da-4acc-43d6-adcf-cc8befe34ad8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001895748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1001895748
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.3746264509
Short name T54
Test name
Test status
Simulation time 1371650138 ps
CPU time 12.86 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 201788 kb
Host smart-11138aad-e4bc-40b6-bdcd-8698d32a515b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746264509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3746264509
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.1857411208
Short name T738
Test name
Test status
Simulation time 33135841 ps
CPU time 1.22 seconds
Started Apr 21 12:30:37 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201876 kb
Host smart-0e1cb443-a6e5-45b4-b147-1bf85cacbe1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1857411208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1857411208
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2718730713
Short name T641
Test name
Test status
Simulation time 14941338730 ps
CPU time 10.67 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:51 PM PDT 24
Peak memory 202024 kb
Host smart-d06e71e4-2265-41c2-a4b3-5a61113857d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718730713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2718730713
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.898788249
Short name T362
Test name
Test status
Simulation time 1327647669 ps
CPU time 5.57 seconds
Started Apr 21 12:30:22 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201820 kb
Host smart-0f953785-22ce-4c6d-b18d-a77b12e12d1e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=898788249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.898788249
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1274834260
Short name T551
Test name
Test status
Simulation time 16548644 ps
CPU time 1.33 seconds
Started Apr 21 12:30:19 PM PDT 24
Finished Apr 21 12:30:21 PM PDT 24
Peak memory 201892 kb
Host smart-39ca8860-2803-45bd-8250-0f1db7e2ab6e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274834260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1274834260
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2970960838
Short name T11
Test name
Test status
Simulation time 11471361643 ps
CPU time 110.84 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:32:18 PM PDT 24
Peak memory 202956 kb
Host smart-5bdf4644-c8e3-42dd-9737-acfa2f853fc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2970960838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2970960838
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1878257123
Short name T749
Test name
Test status
Simulation time 3064300674 ps
CPU time 28.45 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:52 PM PDT 24
Peak memory 201844 kb
Host smart-c21ba5ae-9f27-47ba-9ef9-a7456471c24d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1878257123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1878257123
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2425710248
Short name T878
Test name
Test status
Simulation time 185353969 ps
CPU time 47.46 seconds
Started Apr 21 12:30:25 PM PDT 24
Finished Apr 21 12:31:13 PM PDT 24
Peak memory 204784 kb
Host smart-8729f0d8-12ee-458c-8c31-3cff70551ddc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2425710248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2425710248
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.25366493
Short name T568
Test name
Test status
Simulation time 140976789 ps
CPU time 5.62 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201888 kb
Host smart-840aef87-00ec-4d6c-949f-d8825576e474
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25366493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.25366493
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4198377925
Short name T325
Test name
Test status
Simulation time 740004603 ps
CPU time 7.51 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:31:04 PM PDT 24
Peak memory 201904 kb
Host smart-2d3c023f-0fa1-40b7-af29-08467018ef17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4198377925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4198377925
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3022157994
Short name T86
Test name
Test status
Simulation time 110133428685 ps
CPU time 256.12 seconds
Started Apr 21 12:30:23 PM PDT 24
Finished Apr 21 12:34:40 PM PDT 24
Peak memory 204020 kb
Host smart-add853db-1225-4e3b-884b-5d7db8e2ebf7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3022157994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.3022157994
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.499488576
Short name T360
Test name
Test status
Simulation time 120371152 ps
CPU time 5.1 seconds
Started Apr 21 12:30:44 PM PDT 24
Finished Apr 21 12:30:49 PM PDT 24
Peak memory 201792 kb
Host smart-be281921-64d5-4626-bc05-cdd77b49962b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=499488576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.499488576
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.1548688057
Short name T143
Test name
Test status
Simulation time 1250240778 ps
CPU time 10.53 seconds
Started Apr 21 12:30:25 PM PDT 24
Finished Apr 21 12:30:36 PM PDT 24
Peak memory 201796 kb
Host smart-59cf8f77-a902-4eef-871e-2f5b41bbdb72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1548688057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1548688057
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2757419319
Short name T483
Test name
Test status
Simulation time 273032306 ps
CPU time 3.92 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201840 kb
Host smart-5a1ac6a0-5be4-482a-a844-6518ff4f7be4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2757419319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2757419319
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2359563590
Short name T648
Test name
Test status
Simulation time 43070005743 ps
CPU time 143.35 seconds
Started Apr 21 12:30:21 PM PDT 24
Finished Apr 21 12:32:44 PM PDT 24
Peak memory 202040 kb
Host smart-8ee4af7d-003d-4bd1-94de-41b8e7876623
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359563590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2359563590
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3081519474
Short name T271
Test name
Test status
Simulation time 14865579916 ps
CPU time 93.75 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:32:30 PM PDT 24
Peak memory 201976 kb
Host smart-3b5ab4c3-65e0-4f0c-9bd9-d0abdbb043d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3081519474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3081519474
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1080040008
Short name T333
Test name
Test status
Simulation time 23197408 ps
CPU time 2.36 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201804 kb
Host smart-37e4d127-61c3-4c32-9a57-26b45a2473bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080040008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1080040008
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2867080626
Short name T172
Test name
Test status
Simulation time 4248267979 ps
CPU time 10.97 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201856 kb
Host smart-8afc0cc9-a929-4e93-8695-d074ad3ec47d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2867080626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2867080626
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.264183600
Short name T138
Test name
Test status
Simulation time 179236012 ps
CPU time 1.51 seconds
Started Apr 21 12:30:25 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 201796 kb
Host smart-97c95bdb-6a23-4398-af00-b846fac93bda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=264183600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.264183600
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.976393803
Short name T824
Test name
Test status
Simulation time 2655333429 ps
CPU time 6.81 seconds
Started Apr 21 12:30:21 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 202148 kb
Host smart-f40e9e74-af61-4fa5-92d0-6a04225dc0be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=976393803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.976393803
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2853507636
Short name T283
Test name
Test status
Simulation time 825006984 ps
CPU time 6.86 seconds
Started Apr 21 12:30:24 PM PDT 24
Finished Apr 21 12:30:32 PM PDT 24
Peak memory 201904 kb
Host smart-f9866e26-1305-4d77-8c5b-d9d4497358b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2853507636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2853507636
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.286666635
Short name T52
Test name
Test status
Simulation time 10176708 ps
CPU time 1.29 seconds
Started Apr 21 12:30:33 PM PDT 24
Finished Apr 21 12:30:35 PM PDT 24
Peak memory 201848 kb
Host smart-1b25aa81-f727-4cb7-a833-ad56fd50344a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286666635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.286666635
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1482076703
Short name T560
Test name
Test status
Simulation time 481406312 ps
CPU time 5.05 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:30:31 PM PDT 24
Peak memory 201812 kb
Host smart-8fd06fb5-d597-416b-8e61-cc65528dbadc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482076703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1482076703
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2932724077
Short name T792
Test name
Test status
Simulation time 2683245362 ps
CPU time 32.07 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201904 kb
Host smart-e632f881-18b5-4eec-85d0-aa6aff2d252b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2932724077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2932724077
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1682244006
Short name T179
Test name
Test status
Simulation time 2693790117 ps
CPU time 96.58 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:32:22 PM PDT 24
Peak memory 204420 kb
Host smart-184fa489-4037-40f1-9681-36844cdcaefd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1682244006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.1682244006
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.726531731
Short name T240
Test name
Test status
Simulation time 367143429 ps
CPU time 41.22 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:31:25 PM PDT 24
Peak memory 203908 kb
Host smart-be31e4b4-69fc-4770-830f-1db027aee1a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=726531731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res
et_error.726531731
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.285902805
Short name T275
Test name
Test status
Simulation time 113035259 ps
CPU time 6.64 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:48 PM PDT 24
Peak memory 201696 kb
Host smart-9f90e01d-8947-4102-9f6b-f3c661aadeba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=285902805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.285902805
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.712759800
Short name T580
Test name
Test status
Simulation time 63534874 ps
CPU time 1.96 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:30:56 PM PDT 24
Peak memory 201816 kb
Host smart-8b7ada61-e95c-49ce-b8d8-79fb499db2ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712759800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.712759800
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3293014719
Short name T232
Test name
Test status
Simulation time 33910212126 ps
CPU time 189.26 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:33:55 PM PDT 24
Peak memory 202940 kb
Host smart-81e33dcb-2b28-4f21-abc3-92aa61ab402e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3293014719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.3293014719
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.308408450
Short name T616
Test name
Test status
Simulation time 304506662 ps
CPU time 3.55 seconds
Started Apr 21 12:30:46 PM PDT 24
Finished Apr 21 12:30:50 PM PDT 24
Peak memory 201888 kb
Host smart-13f7c647-917a-45ec-bbee-4a1cd7e1937a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=308408450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.308408450
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3333833792
Short name T343
Test name
Test status
Simulation time 1469152844 ps
CPU time 10.81 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:43 PM PDT 24
Peak memory 201832 kb
Host smart-d5de1a2e-0568-4d7a-b3f3-b1f32878e0e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3333833792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3333833792
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.3226330011
Short name T853
Test name
Test status
Simulation time 1957224199 ps
CPU time 8.81 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:30:52 PM PDT 24
Peak memory 201780 kb
Host smart-0aad9c81-c1b0-4ad0-a9e2-1af2cf0fb968
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3226330011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3226330011
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2399676598
Short name T385
Test name
Test status
Simulation time 235080258062 ps
CPU time 128.17 seconds
Started Apr 21 12:30:51 PM PDT 24
Finished Apr 21 12:32:59 PM PDT 24
Peak memory 201916 kb
Host smart-827df71e-a1b3-4091-9522-62d746ad4040
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399676598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2399676598
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.274121810
Short name T123
Test name
Test status
Simulation time 27640919905 ps
CPU time 188.92 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:33:41 PM PDT 24
Peak memory 201984 kb
Host smart-27837dd0-dc2a-427d-960f-52d9b7e4eeee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=274121810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.274121810
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2130578586
Short name T770
Test name
Test status
Simulation time 59722454 ps
CPU time 4.07 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201912 kb
Host smart-a5574c74-75bc-4ba3-91f9-3a63ba483400
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130578586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2130578586
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3806664301
Short name T264
Test name
Test status
Simulation time 80688633 ps
CPU time 4.22 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201796 kb
Host smart-8eac9906-479b-4dad-b7a1-de9e9037edff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3806664301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3806664301
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2756080001
Short name T151
Test name
Test status
Simulation time 104053494 ps
CPU time 1.46 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201876 kb
Host smart-097e63c6-9515-4a77-bfdb-2b0ee6e0c79c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2756080001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2756080001
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2707027239
Short name T77
Test name
Test status
Simulation time 2447559976 ps
CPU time 8.86 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:38 PM PDT 24
Peak memory 201876 kb
Host smart-79ad904f-06d2-4d9a-9b33-e6aeee48a696
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707027239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2707027239
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3018846146
Short name T503
Test name
Test status
Simulation time 570764773 ps
CPU time 5.07 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:38 PM PDT 24
Peak memory 201856 kb
Host smart-e21ed7dc-0a67-42c2-9dfc-5d139c1d56cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3018846146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3018846146
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3739085528
Short name T437
Test name
Test status
Simulation time 8938955 ps
CPU time 1.18 seconds
Started Apr 21 12:30:27 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 201820 kb
Host smart-2d67c001-c32b-4360-aef3-092a51a1e863
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739085528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3739085528
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.3222860055
Short name T585
Test name
Test status
Simulation time 1312017869 ps
CPU time 13.87 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:43 PM PDT 24
Peak memory 201924 kb
Host smart-44c4b03d-2d6a-42e5-818d-4821d67e220d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3222860055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3222860055
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2695439086
Short name T16
Test name
Test status
Simulation time 3269002819 ps
CPU time 22.25 seconds
Started Apr 21 12:30:37 PM PDT 24
Finished Apr 21 12:31:00 PM PDT 24
Peak memory 201940 kb
Host smart-907633b1-a486-4949-a3f6-57680040b76c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2695439086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2695439086
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1266804139
Short name T5
Test name
Test status
Simulation time 2882429185 ps
CPU time 99.46 seconds
Started Apr 21 12:30:33 PM PDT 24
Finished Apr 21 12:32:13 PM PDT 24
Peak memory 204808 kb
Host smart-65e908c2-2094-43c1-ba31-3c4c8e5374f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1266804139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1266804139
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.455153820
Short name T272
Test name
Test status
Simulation time 139403071 ps
CPU time 7.01 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 201800 kb
Host smart-e92ff63a-8519-4248-b4bf-132b0ba80366
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=455153820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.455153820
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2045195183
Short name T41
Test name
Test status
Simulation time 226088821 ps
CPU time 4.95 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:35 PM PDT 24
Peak memory 201896 kb
Host smart-e48d4305-2436-459c-8e6a-b77974e8a04d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045195183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2045195183
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.933521830
Short name T347
Test name
Test status
Simulation time 10072850 ps
CPU time 1.17 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:30:50 PM PDT 24
Peak memory 201844 kb
Host smart-175c7037-86b8-4541-bff0-2af454f4f0eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=933521830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.933521830
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1340258537
Short name T694
Test name
Test status
Simulation time 771045272 ps
CPU time 11.04 seconds
Started Apr 21 12:30:28 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201800 kb
Host smart-382abf0c-b0dd-4ec7-86f2-dab460d3ab92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1340258537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1340258537
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.2203843712
Short name T211
Test name
Test status
Simulation time 561730721 ps
CPU time 10.16 seconds
Started Apr 21 12:30:29 PM PDT 24
Finished Apr 21 12:30:40 PM PDT 24
Peak memory 201916 kb
Host smart-de5caa70-9900-4cd3-b791-f8d1522468b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2203843712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2203843712
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.758070586
Short name T415
Test name
Test status
Simulation time 12282254529 ps
CPU time 36.01 seconds
Started Apr 21 12:30:30 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 201940 kb
Host smart-eb6451a2-7af6-41a9-91f8-e0e5e1adee21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=758070586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.758070586
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1097170265
Short name T712
Test name
Test status
Simulation time 25562971114 ps
CPU time 145.92 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:32:52 PM PDT 24
Peak memory 201976 kb
Host smart-6db0e35a-5995-4091-839b-2d907d99bea7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1097170265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1097170265
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2801166775
Short name T156
Test name
Test status
Simulation time 130005374 ps
CPU time 3.07 seconds
Started Apr 21 12:30:51 PM PDT 24
Finished Apr 21 12:30:55 PM PDT 24
Peak memory 201888 kb
Host smart-78f675ff-0bc9-4b9f-a74a-abb07958292b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801166775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2801166775
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.2329232650
Short name T424
Test name
Test status
Simulation time 1619857097 ps
CPU time 13.73 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:54 PM PDT 24
Peak memory 201888 kb
Host smart-d913cc63-dd80-4070-967c-3a930a79ec08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2329232650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2329232650
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3020521817
Short name T608
Test name
Test status
Simulation time 116753582 ps
CPU time 1.57 seconds
Started Apr 21 12:30:38 PM PDT 24
Finished Apr 21 12:30:40 PM PDT 24
Peak memory 201764 kb
Host smart-37fcff30-1dbd-45c5-876d-f894fffbfed9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3020521817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3020521817
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1375201180
Short name T349
Test name
Test status
Simulation time 3262691116 ps
CPU time 13.07 seconds
Started Apr 21 12:30:34 PM PDT 24
Finished Apr 21 12:30:47 PM PDT 24
Peak memory 201984 kb
Host smart-16023af0-1ea2-4d02-8862-627462c0d8a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375201180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1375201180
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3856163873
Short name T487
Test name
Test status
Simulation time 1638095421 ps
CPU time 12.31 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:31:10 PM PDT 24
Peak memory 201920 kb
Host smart-b87148d5-7fa0-4beb-b659-2a386582ce4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3856163873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3856163873
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2398268461
Short name T351
Test name
Test status
Simulation time 30711666 ps
CPU time 1.1 seconds
Started Apr 21 12:30:26 PM PDT 24
Finished Apr 21 12:30:28 PM PDT 24
Peak memory 201808 kb
Host smart-4fa8bf13-9415-42c6-a6a1-30e38fe54bd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398268461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2398268461
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2848466311
Short name T355
Test name
Test status
Simulation time 522023996 ps
CPU time 77.81 seconds
Started Apr 21 12:30:31 PM PDT 24
Finished Apr 21 12:31:50 PM PDT 24
Peak memory 204708 kb
Host smart-3a15f43a-49f6-4b79-97a6-11d1dbf182a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2848466311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2848466311
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3379425880
Short name T203
Test name
Test status
Simulation time 2419007256 ps
CPU time 46.05 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:40 PM PDT 24
Peak memory 201864 kb
Host smart-0fd0c260-5016-47b9-9446-885583ed7372
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379425880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3379425880
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2994474506
Short name T127
Test name
Test status
Simulation time 4868443877 ps
CPU time 119.34 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:32:43 PM PDT 24
Peak memory 204580 kb
Host smart-d2bf772e-f799-405e-9b6b-05bec7047192
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2994474506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.2994474506
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4195287939
Short name T868
Test name
Test status
Simulation time 4673959088 ps
CPU time 76.37 seconds
Started Apr 21 12:30:47 PM PDT 24
Finished Apr 21 12:32:04 PM PDT 24
Peak memory 204628 kb
Host smart-81ae26b0-0f16-4e9f-81f1-a534e6755f7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195287939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.4195287939
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3758152853
Short name T303
Test name
Test status
Simulation time 122527112 ps
CPU time 6.27 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:38 PM PDT 24
Peak memory 201828 kb
Host smart-592ef766-02de-4040-ab1c-0914a8760820
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3758152853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3758152853
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2933813900
Short name T650
Test name
Test status
Simulation time 480863806 ps
CPU time 10.62 seconds
Started Apr 21 12:30:38 PM PDT 24
Finished Apr 21 12:30:49 PM PDT 24
Peak memory 201836 kb
Host smart-7e2b0ff4-b2fd-4790-97ca-1a46e029a822
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2933813900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2933813900
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.444580988
Short name T490
Test name
Test status
Simulation time 17934744764 ps
CPU time 36.26 seconds
Started Apr 21 12:30:33 PM PDT 24
Finished Apr 21 12:31:09 PM PDT 24
Peak memory 201972 kb
Host smart-438c8a11-d867-412a-86ed-7ca83cf9c85c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=444580988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo
w_rsp.444580988
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2501693999
Short name T202
Test name
Test status
Simulation time 35827097 ps
CPU time 2.32 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:30:59 PM PDT 24
Peak memory 201864 kb
Host smart-324959ef-3fbc-4a13-80da-4fbe512e1ed2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501693999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2501693999
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.2311318558
Short name T413
Test name
Test status
Simulation time 40884731 ps
CPU time 1.66 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201884 kb
Host smart-4a4afb56-637d-4443-893a-00adbb3074c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2311318558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2311318558
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.1893236651
Short name T798
Test name
Test status
Simulation time 173405487 ps
CPU time 3.81 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:37 PM PDT 24
Peak memory 201812 kb
Host smart-cef61ae0-0f6c-4ff5-bb0e-1ee6bbe7514d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1893236651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1893236651
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3851745795
Short name T723
Test name
Test status
Simulation time 62558230283 ps
CPU time 166.29 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:33:28 PM PDT 24
Peak memory 201984 kb
Host smart-15c95438-8c6c-4ed2-8364-7df5ba4689e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851745795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3851745795
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2293485303
Short name T584
Test name
Test status
Simulation time 16668510196 ps
CPU time 90.65 seconds
Started Apr 21 12:30:52 PM PDT 24
Finished Apr 21 12:32:23 PM PDT 24
Peak memory 202028 kb
Host smart-623c1021-a1aa-423b-8010-4052000f4d4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2293485303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2293485303
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2742464905
Short name T732
Test name
Test status
Simulation time 83274293 ps
CPU time 6.99 seconds
Started Apr 21 12:30:34 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201904 kb
Host smart-891c4157-68af-4e29-9fb0-608688026c0f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742464905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2742464905
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.1302067994
Short name T501
Test name
Test status
Simulation time 121303578 ps
CPU time 6.08 seconds
Started Apr 21 12:30:38 PM PDT 24
Finished Apr 21 12:30:45 PM PDT 24
Peak memory 201800 kb
Host smart-14c7e29b-5a3d-4d1f-8064-97c17054561b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1302067994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1302067994
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1086269782
Short name T540
Test name
Test status
Simulation time 10006891 ps
CPU time 1.25 seconds
Started Apr 21 12:30:32 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 201928 kb
Host smart-5142d5d3-f42a-40c0-a338-9aa97bb17fdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1086269782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1086269782
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.914164014
Short name T743
Test name
Test status
Simulation time 2925304962 ps
CPU time 9.4 seconds
Started Apr 21 12:30:31 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201940 kb
Host smart-02d7560a-0366-4dc3-b822-53ea230ed342
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=914164014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.914164014
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1663775891
Short name T663
Test name
Test status
Simulation time 2679307137 ps
CPU time 12.84 seconds
Started Apr 21 12:30:52 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201960 kb
Host smart-ab258787-4958-4f9b-b89b-13a4529e7c34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1663775891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1663775891
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2899211991
Short name T640
Test name
Test status
Simulation time 22499435 ps
CPU time 1.15 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:30:57 PM PDT 24
Peak memory 201700 kb
Host smart-7fb33f9b-1705-41db-a1a7-63a8c1a6cdce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899211991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2899211991
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.578713390
Short name T32
Test name
Test status
Simulation time 4284714583 ps
CPU time 22.21 seconds
Started Apr 21 12:30:36 PM PDT 24
Finished Apr 21 12:30:59 PM PDT 24
Peak memory 201980 kb
Host smart-3043cb58-dc8f-4199-95bb-32acd95d4800
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=578713390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.578713390
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3569118223
Short name T766
Test name
Test status
Simulation time 1044494798 ps
CPU time 36.57 seconds
Started Apr 21 12:31:01 PM PDT 24
Finished Apr 21 12:31:37 PM PDT 24
Peak memory 201836 kb
Host smart-82bbe4f4-7ca0-40b5-ac5b-60352f1bb466
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3569118223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3569118223
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3905911955
Short name T153
Test name
Test status
Simulation time 8265259884 ps
CPU time 129.69 seconds
Started Apr 21 12:30:47 PM PDT 24
Finished Apr 21 12:32:57 PM PDT 24
Peak memory 205780 kb
Host smart-4456fc90-dc0d-4fb1-81fc-2740c47f0b12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905911955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3905911955
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3759342169
Short name T8
Test name
Test status
Simulation time 859466512 ps
CPU time 86.37 seconds
Started Apr 21 12:31:02 PM PDT 24
Finished Apr 21 12:32:29 PM PDT 24
Peak memory 204212 kb
Host smart-3c2b15fc-d82a-4c3c-9204-f1968791cb4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3759342169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3759342169
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3636925976
Short name T620
Test name
Test status
Simulation time 3224898661 ps
CPU time 13.17 seconds
Started Apr 21 12:30:31 PM PDT 24
Finished Apr 21 12:30:45 PM PDT 24
Peak memory 201856 kb
Host smart-5fc25bc2-18d2-4e4a-ba8b-dd87c734f34b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3636925976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3636925976
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.79345858
Short name T149
Test name
Test status
Simulation time 1240431618 ps
CPU time 7.63 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:48 PM PDT 24
Peak memory 201896 kb
Host smart-45c5de17-47b8-424d-9bae-c2fae0f4ab08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79345858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.79345858
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4007189889
Short name T576
Test name
Test status
Simulation time 30542910 ps
CPU time 1.92 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201780 kb
Host smart-cd6b103e-001b-4949-85dd-d9bec87ff341
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4007189889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4007189889
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.3585137060
Short name T493
Test name
Test status
Simulation time 1038925338 ps
CPU time 10.1 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:51 PM PDT 24
Peak memory 201812 kb
Host smart-d6ee5d38-b403-42bd-89e0-736f390c7e8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585137060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3585137060
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.2204860733
Short name T859
Test name
Test status
Simulation time 5374965882 ps
CPU time 14.26 seconds
Started Apr 21 12:30:51 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201860 kb
Host smart-277a231a-7501-4853-bee5-fa0766556472
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2204860733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2204860733
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.979831725
Short name T786
Test name
Test status
Simulation time 30613211338 ps
CPU time 119.56 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:32:48 PM PDT 24
Peak memory 201956 kb
Host smart-a16402eb-56d9-49cc-87cf-10c061475bf9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=979831725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.979831725
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2565066438
Short name T412
Test name
Test status
Simulation time 8499222775 ps
CPU time 47.23 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:31:43 PM PDT 24
Peak memory 201932 kb
Host smart-33f0c4b5-6132-42f4-9bb8-4796aa21d591
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2565066438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2565066438
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.4052883846
Short name T184
Test name
Test status
Simulation time 55489528 ps
CPU time 5.6 seconds
Started Apr 21 12:30:52 PM PDT 24
Finished Apr 21 12:30:57 PM PDT 24
Peak memory 201892 kb
Host smart-2fe62faa-487f-438c-b26a-550d85519193
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052883846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.4052883846
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.340362735
Short name T155
Test name
Test status
Simulation time 46588596 ps
CPU time 2.67 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:30:46 PM PDT 24
Peak memory 201920 kb
Host smart-aaa1a2cb-d226-4d9a-8410-6a4e8498a721
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=340362735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.340362735
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.1955093908
Short name T654
Test name
Test status
Simulation time 229292771 ps
CPU time 1.4 seconds
Started Apr 21 12:30:40 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 201916 kb
Host smart-682fae8c-aaa7-4c67-bcc1-3f9689121b04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1955093908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1955093908
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1313146667
Short name T761
Test name
Test status
Simulation time 1972959089 ps
CPU time 8.93 seconds
Started Apr 21 12:30:53 PM PDT 24
Finished Apr 21 12:31:02 PM PDT 24
Peak memory 201708 kb
Host smart-e5a236e1-161b-43d4-8a00-8adb1c18dfa7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313146667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1313146667
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.808532743
Short name T320
Test name
Test status
Simulation time 1353600837 ps
CPU time 7.82 seconds
Started Apr 21 12:30:37 PM PDT 24
Finished Apr 21 12:30:45 PM PDT 24
Peak memory 201804 kb
Host smart-58050077-571b-4049-98ad-f46e11613490
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=808532743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.808532743
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1028335942
Short name T404
Test name
Test status
Simulation time 10581469 ps
CPU time 1.12 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:41 PM PDT 24
Peak memory 201796 kb
Host smart-700c8cbd-9d91-4086-8992-a05227767d3a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028335942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1028335942
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1512691804
Short name T467
Test name
Test status
Simulation time 2136439630 ps
CPU time 27.53 seconds
Started Apr 21 12:31:03 PM PDT 24
Finished Apr 21 12:31:31 PM PDT 24
Peak memory 201944 kb
Host smart-6025717e-82a4-417f-b3ec-d119809d4b92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1512691804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1512691804
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1370756369
Short name T666
Test name
Test status
Simulation time 178575764 ps
CPU time 4.46 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201696 kb
Host smart-fdb0f6b1-5ddf-4579-bb44-d7ccb6fb3e64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370756369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1370756369
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.368286900
Short name T689
Test name
Test status
Simulation time 3954003995 ps
CPU time 54.95 seconds
Started Apr 21 12:30:35 PM PDT 24
Finished Apr 21 12:31:30 PM PDT 24
Peak memory 204276 kb
Host smart-098eefb5-c2a3-425b-aabf-ef123739d21b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=368286900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand
_reset.368286900
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1665953394
Short name T466
Test name
Test status
Simulation time 251332222 ps
CPU time 51.08 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:31:35 PM PDT 24
Peak memory 203160 kb
Host smart-e45407fb-1348-46b6-8e3e-d10b21f43d71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1665953394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1665953394
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2736451344
Short name T755
Test name
Test status
Simulation time 1892799560 ps
CPU time 8.76 seconds
Started Apr 21 12:30:36 PM PDT 24
Finished Apr 21 12:30:46 PM PDT 24
Peak memory 201808 kb
Host smart-cd3418cd-bb94-49f1-b498-bc9f1596f761
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2736451344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2736451344
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2580110137
Short name T314
Test name
Test status
Simulation time 47104672 ps
CPU time 8.65 seconds
Started Apr 21 12:31:07 PM PDT 24
Finished Apr 21 12:31:16 PM PDT 24
Peak memory 201880 kb
Host smart-7bf5edfc-73f5-4fbe-912b-03a5f14916cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2580110137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2580110137
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4117630025
Short name T82
Test name
Test status
Simulation time 48750787067 ps
CPU time 72.07 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:31:55 PM PDT 24
Peak memory 201936 kb
Host smart-58d75b75-ccc8-4045-8266-119e5c079ec5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4117630025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.4117630025
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.884470160
Short name T631
Test name
Test status
Simulation time 81632593 ps
CPU time 6.24 seconds
Started Apr 21 12:30:44 PM PDT 24
Finished Apr 21 12:30:51 PM PDT 24
Peak memory 201812 kb
Host smart-8ac73e75-0af9-4a23-92c8-5ebeb28b6ed5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=884470160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.884470160
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.2562929493
Short name T74
Test name
Test status
Simulation time 1211339531 ps
CPU time 8.19 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:31:04 PM PDT 24
Peak memory 201880 kb
Host smart-71fd1521-c58b-463c-bd46-22609fdf1b74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562929493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2562929493
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.1895220537
Short name T399
Test name
Test status
Simulation time 2622382356 ps
CPU time 14.19 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:30:57 PM PDT 24
Peak memory 201852 kb
Host smart-fe1d35d6-00ae-43ac-8a76-ea31b16c63b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1895220537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1895220537
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1574988008
Short name T402
Test name
Test status
Simulation time 32550394710 ps
CPU time 126.64 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:33:14 PM PDT 24
Peak memory 202024 kb
Host smart-26a0e14b-19b8-454c-8f2a-a8bb80ad6ff8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574988008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1574988008
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3256861665
Short name T863
Test name
Test status
Simulation time 2667338135 ps
CPU time 12.41 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:07 PM PDT 24
Peak memory 201916 kb
Host smart-10a704fc-b626-41c3-b6a9-17d865aa0f47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3256861665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3256861665
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2692076454
Short name T116
Test name
Test status
Simulation time 17551997 ps
CPU time 2.09 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:30:48 PM PDT 24
Peak memory 201812 kb
Host smart-77174f5b-3275-4115-8040-7757253d16d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692076454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2692076454
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.1317070361
Short name T288
Test name
Test status
Simulation time 124776286 ps
CPU time 1.83 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:30:46 PM PDT 24
Peak memory 201796 kb
Host smart-fe0a00c7-4cb9-4015-aa2b-0eaf292aa228
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1317070361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1317070361
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.197031106
Short name T147
Test name
Test status
Simulation time 14270101 ps
CPU time 1.07 seconds
Started Apr 21 12:30:38 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201804 kb
Host smart-f139f167-122f-4ace-8e81-5bd35fecf073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=197031106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.197031106
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2087966676
Short name T515
Test name
Test status
Simulation time 1708760503 ps
CPU time 8.28 seconds
Started Apr 21 12:30:44 PM PDT 24
Finished Apr 21 12:30:53 PM PDT 24
Peak memory 201900 kb
Host smart-222910da-f6ba-4d52-b465-0f13e95ed716
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087966676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2087966676
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2460887885
Short name T99
Test name
Test status
Simulation time 1666198391 ps
CPU time 10.35 seconds
Started Apr 21 12:30:59 PM PDT 24
Finished Apr 21 12:31:09 PM PDT 24
Peak memory 201836 kb
Host smart-010a2fd6-eb17-47fd-8b3a-7dc163e01920
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2460887885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2460887885
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3176880588
Short name T802
Test name
Test status
Simulation time 10750607 ps
CPU time 1.1 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:30:56 PM PDT 24
Peak memory 201908 kb
Host smart-b370ed08-f878-4981-9288-590638ade6f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176880588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3176880588
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3223420568
Short name T112
Test name
Test status
Simulation time 12604898896 ps
CPU time 60.99 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:31:58 PM PDT 24
Peak memory 203028 kb
Host smart-b50db830-4f68-4894-823a-6ec1b9d04735
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3223420568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3223420568
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2188123140
Short name T452
Test name
Test status
Simulation time 489438898 ps
CPU time 33.46 seconds
Started Apr 21 12:30:41 PM PDT 24
Finished Apr 21 12:31:15 PM PDT 24
Peak memory 201808 kb
Host smart-b79c0b66-1813-423a-b448-10641d0d056e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188123140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2188123140
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3743697494
Short name T500
Test name
Test status
Simulation time 78538556 ps
CPU time 10.83 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:31:07 PM PDT 24
Peak memory 201776 kb
Host smart-575ca8de-e822-46c7-9745-63fb5909c2db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3743697494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.3743697494
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4042919954
Short name T309
Test name
Test status
Simulation time 261600802 ps
CPU time 7.29 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:31:02 PM PDT 24
Peak memory 201912 kb
Host smart-d1a78052-635e-45f9-924a-e654934f1036
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4042919954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4042919954
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3283878132
Short name T553
Test name
Test status
Simulation time 32665808 ps
CPU time 3.41 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:04 PM PDT 24
Peak memory 201804 kb
Host smart-3d691a9c-2099-4a79-b3da-73846a3eef76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3283878132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3283878132
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.4021235191
Short name T231
Test name
Test status
Simulation time 47924073433 ps
CPU time 147.65 seconds
Started Apr 21 12:31:08 PM PDT 24
Finished Apr 21 12:33:36 PM PDT 24
Peak memory 202924 kb
Host smart-20b45ac7-58fd-470e-bf43-595790f81e2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4021235191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.4021235191
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1586736128
Short name T345
Test name
Test status
Simulation time 19982237 ps
CPU time 1.02 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:30:47 PM PDT 24
Peak memory 201852 kb
Host smart-71aa4d02-7880-449e-ae9e-57775ec94a52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1586736128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1586736128
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.1060939611
Short name T603
Test name
Test status
Simulation time 753593062 ps
CPU time 10.79 seconds
Started Apr 21 12:30:55 PM PDT 24
Finished Apr 21 12:31:07 PM PDT 24
Peak memory 201864 kb
Host smart-1099a515-bfa2-4d68-8437-641f7a517163
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1060939611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1060939611
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.672317016
Short name T462
Test name
Test status
Simulation time 1453636478 ps
CPU time 3.75 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201800 kb
Host smart-09aa7112-ead8-4877-8c68-051484b6962a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=672317016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.672317016
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4174687309
Short name T586
Test name
Test status
Simulation time 38414711820 ps
CPU time 144.87 seconds
Started Apr 21 12:30:59 PM PDT 24
Finished Apr 21 12:33:24 PM PDT 24
Peak memory 201928 kb
Host smart-2f280b0e-355b-4a7f-b013-d2eae3048079
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174687309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.4174687309
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2989635624
Short name T768
Test name
Test status
Simulation time 29747480122 ps
CPU time 147.74 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:33:10 PM PDT 24
Peak memory 201916 kb
Host smart-66b052db-1cb2-4672-8aa9-3a37cef9af5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2989635624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2989635624
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.365418412
Short name T2
Test name
Test status
Simulation time 329561517 ps
CPU time 7.69 seconds
Started Apr 21 12:30:58 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 201860 kb
Host smart-097f544f-340a-460f-9431-415c84404e9a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365418412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.365418412
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.4258395916
Short name T734
Test name
Test status
Simulation time 54820437 ps
CPU time 1.99 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:42 PM PDT 24
Peak memory 202108 kb
Host smart-3b5df2bb-44f7-498d-a718-13e79fc56f3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4258395916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.4258395916
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.106769566
Short name T434
Test name
Test status
Simulation time 10205659 ps
CPU time 1.19 seconds
Started Apr 21 12:30:58 PM PDT 24
Finished Apr 21 12:30:59 PM PDT 24
Peak memory 201912 kb
Host smart-1335af17-99ae-4708-9349-2c5b45a718e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106769566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.106769566
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.806890895
Short name T427
Test name
Test status
Simulation time 3425758633 ps
CPU time 7.16 seconds
Started Apr 21 12:30:41 PM PDT 24
Finished Apr 21 12:30:49 PM PDT 24
Peak memory 201868 kb
Host smart-844b6f7b-bd58-478f-8f97-271038dac0dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=806890895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.806890895
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3509696115
Short name T395
Test name
Test status
Simulation time 2265517930 ps
CPU time 5.97 seconds
Started Apr 21 12:30:42 PM PDT 24
Finished Apr 21 12:30:49 PM PDT 24
Peak memory 201876 kb
Host smart-b033182e-c5f8-4eba-a02b-1d3af65a58e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3509696115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3509696115
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2195074823
Short name T182
Test name
Test status
Simulation time 7951243 ps
CPU time 1.16 seconds
Started Apr 21 12:30:43 PM PDT 24
Finished Apr 21 12:30:44 PM PDT 24
Peak memory 201808 kb
Host smart-b32a84ca-3783-426f-814f-26201bd72978
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195074823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2195074823
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3844231100
Short name T152
Test name
Test status
Simulation time 294156255 ps
CPU time 33.31 seconds
Started Apr 21 12:30:50 PM PDT 24
Finished Apr 21 12:31:24 PM PDT 24
Peak memory 203844 kb
Host smart-71c98267-a118-4552-8488-fe235ae9dccb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3844231100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3844231100
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1255035764
Short name T389
Test name
Test status
Simulation time 3870637387 ps
CPU time 10.9 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201900 kb
Host smart-fe1764e1-3f90-4612-885d-f3ebc64a3dbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1255035764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1255035764
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.273147382
Short name T804
Test name
Test status
Simulation time 301274743 ps
CPU time 37 seconds
Started Apr 21 12:30:47 PM PDT 24
Finished Apr 21 12:31:25 PM PDT 24
Peak memory 204076 kb
Host smart-c0fc03e3-2caf-4b84-a96b-a41688777361
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273147382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.273147382
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2784349980
Short name T250
Test name
Test status
Simulation time 5647166966 ps
CPU time 126.77 seconds
Started Apr 21 12:31:03 PM PDT 24
Finished Apr 21 12:33:10 PM PDT 24
Peak memory 204632 kb
Host smart-8db4cb39-396a-40a6-9448-7f00600ffc6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2784349980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2784349980
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1378209969
Short name T46
Test name
Test status
Simulation time 418767929 ps
CPU time 7.88 seconds
Started Apr 21 12:30:39 PM PDT 24
Finished Apr 21 12:30:48 PM PDT 24
Peak memory 201820 kb
Host smart-001717cf-83e6-4ade-be25-44df81796599
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1378209969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1378209969
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3025084976
Short name T456
Test name
Test status
Simulation time 1091539054 ps
CPU time 17.35 seconds
Started Apr 21 12:30:53 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 201852 kb
Host smart-1353b5e4-e781-412d-b53d-e9bd1790e277
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3025084976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3025084976
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2759419293
Short name T219
Test name
Test status
Simulation time 39376369541 ps
CPU time 197.92 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:34:06 PM PDT 24
Peak memory 202956 kb
Host smart-2bf04d79-81b1-40df-a33e-71a243bea365
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2759419293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.2759419293
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1515385678
Short name T373
Test name
Test status
Simulation time 53610718 ps
CPU time 3.32 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:30:58 PM PDT 24
Peak memory 201672 kb
Host smart-79953dd3-1f7d-4ecf-8813-bad73c544cbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1515385678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1515385678
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.2768570394
Short name T721
Test name
Test status
Simulation time 110639009 ps
CPU time 4.35 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:30:50 PM PDT 24
Peak memory 201832 kb
Host smart-9b40f391-3e63-4455-871a-1f92108298a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2768570394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2768570394
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3099861149
Short name T816
Test name
Test status
Simulation time 511776225 ps
CPU time 4.95 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:30:53 PM PDT 24
Peak memory 201788 kb
Host smart-af7139e6-e7d1-47e8-8344-eebf2669e279
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099861149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3099861149
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.331292368
Short name T145
Test name
Test status
Simulation time 37802218579 ps
CPU time 96.91 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:32:22 PM PDT 24
Peak memory 201936 kb
Host smart-974b11bd-5d86-4ec3-807d-08ded19f2fca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=331292368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.331292368
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3710629644
Short name T279
Test name
Test status
Simulation time 6037738958 ps
CPU time 34.39 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:35 PM PDT 24
Peak memory 201920 kb
Host smart-2ee2ba18-7f80-4a65-9b46-a226246a1bd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3710629644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3710629644
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1130711834
Short name T653
Test name
Test status
Simulation time 283863267 ps
CPU time 8.8 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:09 PM PDT 24
Peak memory 201788 kb
Host smart-d0a5eb22-2916-40a3-a5c3-8053de2bad59
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130711834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1130711834
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.337459181
Short name T636
Test name
Test status
Simulation time 1150266873 ps
CPU time 10.9 seconds
Started Apr 21 12:30:53 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201856 kb
Host smart-8d38c0bf-6fd3-4192-8b69-ec69b8061f5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337459181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.337459181
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.2694661596
Short name T624
Test name
Test status
Simulation time 12596659 ps
CPU time 1.25 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:30:56 PM PDT 24
Peak memory 201672 kb
Host smart-eddc56c3-f0b4-4faf-b56c-99d8264b2db7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2694661596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2694661596
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1610723220
Short name T535
Test name
Test status
Simulation time 15284618343 ps
CPU time 8.86 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 201928 kb
Host smart-c46dc99e-64de-449e-9efc-d38bd7b73ada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610723220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1610723220
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1264420403
Short name T752
Test name
Test status
Simulation time 15024333106 ps
CPU time 14.6 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:31:12 PM PDT 24
Peak memory 201928 kb
Host smart-4be098ec-38fe-422d-860e-bbe59f354e94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1264420403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1264420403
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1418809895
Short name T784
Test name
Test status
Simulation time 9581746 ps
CPU time 1.02 seconds
Started Apr 21 12:31:15 PM PDT 24
Finished Apr 21 12:31:17 PM PDT 24
Peak memory 201792 kb
Host smart-d96a1965-0bc8-4f95-9470-43903b6ae10e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418809895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1418809895
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.808188329
Short name T91
Test name
Test status
Simulation time 20104335426 ps
CPU time 134.23 seconds
Started Apr 21 12:30:45 PM PDT 24
Finished Apr 21 12:32:59 PM PDT 24
Peak memory 202956 kb
Host smart-436b175f-fbc8-4c85-ae42-002456b8c4a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=808188329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.808188329
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.959232491
Short name T379
Test name
Test status
Simulation time 522680132 ps
CPU time 8.32 seconds
Started Apr 21 12:30:53 PM PDT 24
Finished Apr 21 12:31:02 PM PDT 24
Peak memory 201840 kb
Host smart-8f83efab-0c54-468e-8833-8c3a5bb4fc81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959232491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.959232491
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2999660659
Short name T237
Test name
Test status
Simulation time 460462595 ps
CPU time 54.63 seconds
Started Apr 21 12:31:11 PM PDT 24
Finished Apr 21 12:32:06 PM PDT 24
Peak memory 203996 kb
Host smart-675384a5-765f-44db-980a-a511710a76e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2999660659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.2999660659
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3563236640
Short name T245
Test name
Test status
Simulation time 233913782 ps
CPU time 38.13 seconds
Started Apr 21 12:30:49 PM PDT 24
Finished Apr 21 12:31:27 PM PDT 24
Peak memory 205384 kb
Host smart-e7e391ae-31d8-4b12-a3f1-862c3d365621
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3563236640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3563236640
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.245333899
Short name T873
Test name
Test status
Simulation time 49053136 ps
CPU time 5.1 seconds
Started Apr 21 12:30:58 PM PDT 24
Finished Apr 21 12:31:04 PM PDT 24
Peak memory 201892 kb
Host smart-85ebfafe-3fcf-48e4-af8b-86f8b7e638c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=245333899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.245333899
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.545196679
Short name T96
Test name
Test status
Simulation time 282057303 ps
CPU time 5.24 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:00 PM PDT 24
Peak memory 201668 kb
Host smart-b8bf3d71-013f-47a5-ae1b-661264a62852
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=545196679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.545196679
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1011647965
Short name T871
Test name
Test status
Simulation time 483288482 ps
CPU time 6.85 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:01 PM PDT 24
Peak memory 201848 kb
Host smart-102a9017-5fee-44bf-a390-909622474f27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1011647965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1011647965
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2277086731
Short name T160
Test name
Test status
Simulation time 3261021470 ps
CPU time 6.76 seconds
Started Apr 21 12:31:04 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 201916 kb
Host smart-3b14e681-84f9-416d-905b-25543a8e8052
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2277086731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2277086731
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.1012938203
Short name T563
Test name
Test status
Simulation time 2380075408 ps
CPU time 11.05 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201724 kb
Host smart-3ad6a1b8-62cb-4fca-aa45-9090033ecc05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1012938203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1012938203
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2811821755
Short name T392
Test name
Test status
Simulation time 30694901027 ps
CPU time 37.1 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:31:25 PM PDT 24
Peak memory 201940 kb
Host smart-002853ca-2d42-4985-9487-c893f567732a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811821755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2811821755
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4228277211
Short name T371
Test name
Test status
Simulation time 4008770057 ps
CPU time 28.71 seconds
Started Apr 21 12:30:56 PM PDT 24
Finished Apr 21 12:31:25 PM PDT 24
Peak memory 201864 kb
Host smart-66b8fd62-8586-44a7-b33b-96e63ec875d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4228277211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4228277211
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2794058852
Short name T526
Test name
Test status
Simulation time 102168934 ps
CPU time 2.97 seconds
Started Apr 21 12:30:48 PM PDT 24
Finished Apr 21 12:30:51 PM PDT 24
Peak memory 201904 kb
Host smart-f394ffc2-8cfd-48c3-9d3b-317cd30c5438
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794058852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2794058852
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.1621695349
Short name T549
Test name
Test status
Simulation time 173214569 ps
CPU time 2.87 seconds
Started Apr 21 12:30:57 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 201892 kb
Host smart-a914c04b-9175-4684-b0ca-505760e54bc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1621695349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1621695349
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.4196694984
Short name T317
Test name
Test status
Simulation time 87778711 ps
CPU time 1.58 seconds
Started Apr 21 12:30:53 PM PDT 24
Finished Apr 21 12:30:55 PM PDT 24
Peak memory 201856 kb
Host smart-c415d23b-8d4b-4d46-974e-64e0b6e1a369
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4196694984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4196694984
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2653018205
Short name T655
Test name
Test status
Simulation time 2073702628 ps
CPU time 10.49 seconds
Started Apr 21 12:30:54 PM PDT 24
Finished Apr 21 12:31:05 PM PDT 24
Peak memory 201664 kb
Host smart-cb2afec4-2e38-4a8d-96c2-66688e3f6866
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653018205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2653018205
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.532870230
Short name T361
Test name
Test status
Simulation time 8677760160 ps
CPU time 11.11 seconds
Started Apr 21 12:30:47 PM PDT 24
Finished Apr 21 12:30:59 PM PDT 24
Peak memory 201936 kb
Host smart-a93e4ec9-e497-4f3a-85aa-452dba47f5bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=532870230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.532870230
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1891556398
Short name T448
Test name
Test status
Simulation time 8226570 ps
CPU time 1.01 seconds
Started Apr 21 12:31:11 PM PDT 24
Finished Apr 21 12:31:12 PM PDT 24
Peak memory 201836 kb
Host smart-0b4b0e99-14b3-48f2-bd1b-48e235187451
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891556398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1891556398
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.24580983
Short name T637
Test name
Test status
Simulation time 68003440 ps
CPU time 6.23 seconds
Started Apr 21 12:30:47 PM PDT 24
Finished Apr 21 12:30:54 PM PDT 24
Peak memory 201820 kb
Host smart-5228001d-6a43-4d51-83b2-bd0844c0bcb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24580983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.24580983
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.435189972
Short name T417
Test name
Test status
Simulation time 3994049636 ps
CPU time 58.19 seconds
Started Apr 21 12:30:59 PM PDT 24
Finished Apr 21 12:31:58 PM PDT 24
Peak memory 201752 kb
Host smart-d15832bf-6886-4bca-9480-a56d88b88e7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=435189972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.435189972
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.876529675
Short name T62
Test name
Test status
Simulation time 13275392861 ps
CPU time 214 seconds
Started Apr 21 12:31:06 PM PDT 24
Finished Apr 21 12:34:40 PM PDT 24
Peak memory 204748 kb
Host smart-5890ce46-1849-4518-8e0c-b24cdbaee079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=876529675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand
_reset.876529675
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2708258444
Short name T368
Test name
Test status
Simulation time 184331841 ps
CPU time 11.78 seconds
Started Apr 21 12:31:25 PM PDT 24
Finished Apr 21 12:31:37 PM PDT 24
Peak memory 201904 kb
Host smart-b3453fb0-57df-432d-a71d-cadce7702e1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2708258444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2708258444
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3354078436
Short name T212
Test name
Test status
Simulation time 612958371 ps
CPU time 10.38 seconds
Started Apr 21 12:31:00 PM PDT 24
Finished Apr 21 12:31:11 PM PDT 24
Peak memory 201812 kb
Host smart-23210a37-ede7-4db0-82ce-d43f1916c426
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3354078436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3354078436
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1184623027
Short name T383
Test name
Test status
Simulation time 222827814 ps
CPU time 5.76 seconds
Started Apr 21 12:28:44 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201800 kb
Host smart-c6e008c5-b0cb-40c1-b486-403e2e2fa78b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1184623027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1184623027
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3580867488
Short name T502
Test name
Test status
Simulation time 23037689182 ps
CPU time 140.74 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 202996 kb
Host smart-bcb5a908-cb98-4d0d-a4d4-15c3a37225b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3580867488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3580867488
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1429128398
Short name T458
Test name
Test status
Simulation time 81838880 ps
CPU time 5.8 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:28:58 PM PDT 24
Peak memory 201812 kb
Host smart-52e0e44c-c2c2-47e3-89cf-3c20f023051b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1429128398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1429128398
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.1469255164
Short name T480
Test name
Test status
Simulation time 294307651 ps
CPU time 3.63 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201832 kb
Host smart-c0209249-ec63-436a-a1e1-533bc6490c86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1469255164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1469255164
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1512710743
Short name T294
Test name
Test status
Simulation time 683032708 ps
CPU time 11.97 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:28:59 PM PDT 24
Peak memory 201876 kb
Host smart-3edaf2c8-0cad-4643-bb8f-2eac45d1b262
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1512710743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1512710743
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1673029666
Short name T267
Test name
Test status
Simulation time 32979162501 ps
CPU time 143.79 seconds
Started Apr 21 12:28:52 PM PDT 24
Finished Apr 21 12:31:16 PM PDT 24
Peak memory 201916 kb
Host smart-6ed3db40-0774-4d87-a216-d9e0c759f48b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673029666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1673029666
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3539268863
Short name T266
Test name
Test status
Simulation time 11879731017 ps
CPU time 88.9 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:30:25 PM PDT 24
Peak memory 201944 kb
Host smart-00aacd4f-2b7c-4d92-b095-9f4bac9135f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3539268863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3539268863
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.4226950473
Short name T672
Test name
Test status
Simulation time 200122821 ps
CPU time 3.6 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201888 kb
Host smart-e0b67ef3-8af2-4f08-8038-90818e51047c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226950473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4226950473
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.10906205
Short name T683
Test name
Test status
Simulation time 72832488 ps
CPU time 3.51 seconds
Started Apr 21 12:28:50 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201896 kb
Host smart-2df6b32c-58b5-4f55-b54a-c9f51be03823
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10906205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.10906205
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.2245510047
Short name T292
Test name
Test status
Simulation time 89430231 ps
CPU time 1.53 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:58 PM PDT 24
Peak memory 201808 kb
Host smart-640d38d5-21ac-4d1d-8abf-79a212d46985
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2245510047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2245510047
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2159362845
Short name T166
Test name
Test status
Simulation time 2015230323 ps
CPU time 7.96 seconds
Started Apr 21 12:28:53 PM PDT 24
Finished Apr 21 12:29:01 PM PDT 24
Peak memory 201824 kb
Host smart-f0c1878c-8088-4dc5-bca4-5de26fafc0e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159362845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2159362845
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1541300771
Short name T162
Test name
Test status
Simulation time 2781867842 ps
CPU time 13.57 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:29:05 PM PDT 24
Peak memory 201884 kb
Host smart-310b60b5-11ba-4d34-8d02-bfc25ca41716
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1541300771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1541300771
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4294669067
Short name T557
Test name
Test status
Simulation time 14180494 ps
CPU time 1.08 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:57 PM PDT 24
Peak memory 201884 kb
Host smart-ef5feda5-c223-47a7-b275-6fba440dc305
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294669067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4294669067
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3837977757
Short name T865
Test name
Test status
Simulation time 6309161421 ps
CPU time 74.44 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 203256 kb
Host smart-888054eb-c45f-403d-a55d-4f168354ca25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3837977757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3837977757
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4179121579
Short name T510
Test name
Test status
Simulation time 404602889 ps
CPU time 51.17 seconds
Started Apr 21 12:28:47 PM PDT 24
Finished Apr 21 12:29:38 PM PDT 24
Peak memory 202828 kb
Host smart-c0aa09c0-60b4-4c5e-afbd-78e03dca9053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4179121579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4179121579
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3099670645
Short name T597
Test name
Test status
Simulation time 936527580 ps
CPU time 152.32 seconds
Started Apr 21 12:28:46 PM PDT 24
Finished Apr 21 12:31:18 PM PDT 24
Peak memory 204064 kb
Host smart-838ea854-f522-4984-9047-06adbade2abd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099670645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3099670645
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3894913045
Short name T247
Test name
Test status
Simulation time 223919653 ps
CPU time 15.35 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 201668 kb
Host smart-bed4c4e7-e1e1-4d31-848f-ce6257cf7953
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3894913045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.3894913045
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1820535972
Short name T158
Test name
Test status
Simulation time 157280626 ps
CPU time 1.99 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:57 PM PDT 24
Peak memory 201832 kb
Host smart-b2000537-a9d2-4ae6-a0f7-328dbeab4792
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1820535972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1820535972
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3381013289
Short name T322
Test name
Test status
Simulation time 98068925 ps
CPU time 8.88 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:58 PM PDT 24
Peak memory 201816 kb
Host smart-c6aa24f9-ce78-4b2f-90b5-58473213f4d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3381013289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3381013289
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2660481839
Short name T773
Test name
Test status
Simulation time 5347341409 ps
CPU time 41.97 seconds
Started Apr 21 12:28:48 PM PDT 24
Finished Apr 21 12:29:31 PM PDT 24
Peak memory 201920 kb
Host smart-0e577574-89d6-442a-a7f9-a79596596ab8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2660481839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2660481839
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2819526753
Short name T547
Test name
Test status
Simulation time 629020149 ps
CPU time 4.39 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:28:56 PM PDT 24
Peak memory 201892 kb
Host smart-5cd13d08-5a6a-406d-975b-ed05385bdc48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819526753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2819526753
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.3718460293
Short name T496
Test name
Test status
Simulation time 1092675835 ps
CPU time 7.55 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:05 PM PDT 24
Peak memory 201912 kb
Host smart-aedbe748-1da6-4387-80c1-119392785900
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3718460293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3718460293
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.90580846
Short name T455
Test name
Test status
Simulation time 948426232 ps
CPU time 10.48 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201832 kb
Host smart-37ba4796-dca2-41fa-968c-86f1114277a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90580846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.90580846
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1805688970
Short name T809
Test name
Test status
Simulation time 28394105424 ps
CPU time 140.27 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:31:10 PM PDT 24
Peak memory 201916 kb
Host smart-e8f1b7b5-6398-4ce5-8b23-f9843b93f5eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805688970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1805688970
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2890370092
Short name T102
Test name
Test status
Simulation time 8664326354 ps
CPU time 55.12 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:52 PM PDT 24
Peak memory 201940 kb
Host smart-2e38874d-266a-4071-b656-83e2c9afc169
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2890370092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2890370092
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3958824063
Short name T691
Test name
Test status
Simulation time 16873679 ps
CPU time 1.16 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:28:58 PM PDT 24
Peak memory 201864 kb
Host smart-f8d9b516-041f-4dbc-86a9-f563752c75fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958824063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3958824063
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.887723760
Short name T176
Test name
Test status
Simulation time 715551491 ps
CPU time 8.87 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201836 kb
Host smart-b305c32e-5bca-4af2-95ca-a1fe6bf43741
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=887723760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.887723760
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.1336724874
Short name T175
Test name
Test status
Simulation time 41263029 ps
CPU time 1.42 seconds
Started Apr 21 12:28:45 PM PDT 24
Finished Apr 21 12:28:46 PM PDT 24
Peak memory 201804 kb
Host smart-1929124b-48ef-490b-af8a-1bf6b6d74ca8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1336724874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1336724874
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4014832684
Short name T862
Test name
Test status
Simulation time 1511534613 ps
CPU time 8.09 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201872 kb
Host smart-fe912521-52fa-4b84-bc56-228c81f727f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014832684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4014832684
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.916818091
Short name T570
Test name
Test status
Simulation time 2972942645 ps
CPU time 7.65 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:04 PM PDT 24
Peak memory 201864 kb
Host smart-5890f966-7f24-4419-ada8-a8b8797ceec3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=916818091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.916818091
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.110479305
Short name T273
Test name
Test status
Simulation time 11750294 ps
CPU time 1.01 seconds
Started Apr 21 12:28:52 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201816 kb
Host smart-32b95973-9578-4afc-bcb2-d92b230c51a5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110479305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.110479305
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1639949734
Short name T782
Test name
Test status
Simulation time 474109801 ps
CPU time 10.26 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201812 kb
Host smart-4dd63b9d-4c39-422c-a49f-aab39bafde00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1639949734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1639949734
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1067645313
Short name T263
Test name
Test status
Simulation time 189456535 ps
CPU time 17.35 seconds
Started Apr 21 12:28:50 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201796 kb
Host smart-d52b0571-dc5f-4689-b4f3-29d5667be365
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067645313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1067645313
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.385032744
Short name T485
Test name
Test status
Simulation time 690281399 ps
CPU time 128.68 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:31:06 PM PDT 24
Peak memory 206876 kb
Host smart-c43fd613-c800-43a4-b81c-d5a763989baa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=385032744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.385032744
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.4135129662
Short name T715
Test name
Test status
Simulation time 215438037 ps
CPU time 15.79 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:13 PM PDT 24
Peak memory 201792 kb
Host smart-1636380f-49ef-4539-ab2f-7f61441f62fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4135129662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.4135129662
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3520911774
Short name T27
Test name
Test status
Simulation time 192138388 ps
CPU time 3.61 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:59 PM PDT 24
Peak memory 201788 kb
Host smart-959bf158-cef8-45ad-a05b-8145e407e01a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3520911774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3520911774
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3566090215
Short name T213
Test name
Test status
Simulation time 136638701 ps
CPU time 1.94 seconds
Started Apr 21 12:28:53 PM PDT 24
Finished Apr 21 12:28:56 PM PDT 24
Peak memory 201792 kb
Host smart-92aedccc-4e59-4f1c-874a-88a210cce056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3566090215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3566090215
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4007261934
Short name T591
Test name
Test status
Simulation time 22527799293 ps
CPU time 81.55 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:30:20 PM PDT 24
Peak memory 201936 kb
Host smart-32b7dc83-2a60-4b26-921b-841653e9aad1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4007261934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.4007261934
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3410167902
Short name T406
Test name
Test status
Simulation time 43151896 ps
CPU time 4.37 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:28:59 PM PDT 24
Peak memory 201848 kb
Host smart-8ca71eb8-0e1c-4314-bdc6-687f9da33779
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3410167902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3410167902
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.1771646145
Short name T832
Test name
Test status
Simulation time 72773499 ps
CPU time 4.95 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201788 kb
Host smart-b8090877-feca-4657-8368-aa49fa92d9e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1771646145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1771646145
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.2323899767
Short name T866
Test name
Test status
Simulation time 4755660474 ps
CPU time 11.61 seconds
Started Apr 21 12:28:52 PM PDT 24
Finished Apr 21 12:29:04 PM PDT 24
Peak memory 201968 kb
Host smart-5cee8b89-51a6-46d3-8742-5b2d56dfbbad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323899767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2323899767
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3830530799
Short name T274
Test name
Test status
Simulation time 33138207223 ps
CPU time 21.05 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:29:15 PM PDT 24
Peak memory 201940 kb
Host smart-5f0035a8-bbbf-4240-a6ca-1cf9f208346f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830530799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3830530799
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.352299978
Short name T728
Test name
Test status
Simulation time 1937107600 ps
CPU time 7.85 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:57 PM PDT 24
Peak memory 201852 kb
Host smart-b3d21bd1-3bcc-4768-acab-383120839767
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=352299978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.352299978
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3987845433
Short name T522
Test name
Test status
Simulation time 10162462 ps
CPU time 1.03 seconds
Started Apr 21 12:28:50 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201900 kb
Host smart-fe136087-76ca-4fce-8a89-73498b2825e7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987845433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3987845433
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2190208700
Short name T702
Test name
Test status
Simulation time 119179493 ps
CPU time 2.97 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:01 PM PDT 24
Peak memory 201784 kb
Host smart-f1c8db50-0594-407a-acc0-c0e7cdc6b990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2190208700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2190208700
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2541216109
Short name T293
Test name
Test status
Simulation time 65491300 ps
CPU time 1.4 seconds
Started Apr 21 12:28:51 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 201824 kb
Host smart-a229380a-75c9-47cb-b5c5-94f8d3a3c655
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2541216109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2541216109
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.380433972
Short name T34
Test name
Test status
Simulation time 2934175131 ps
CPU time 8.93 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:05 PM PDT 24
Peak memory 201860 kb
Host smart-e58370a3-04b6-4711-a959-833958b7dd50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=380433972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.380433972
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3553604229
Short name T869
Test name
Test status
Simulation time 2943186365 ps
CPU time 10.59 seconds
Started Apr 21 12:28:52 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 201920 kb
Host smart-cc4ab9d4-beea-4135-aa0c-32041f5b4827
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3553604229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3553604229
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3624541475
Short name T517
Test name
Test status
Simulation time 9700039 ps
CPU time 1.11 seconds
Started Apr 21 12:28:49 PM PDT 24
Finished Apr 21 12:28:51 PM PDT 24
Peak memory 201820 kb
Host smart-efd8e489-b052-4283-8a48-ec6f6709e8c7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624541475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3624541475
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2929964226
Short name T486
Test name
Test status
Simulation time 1837750604 ps
CPU time 38.4 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:29:36 PM PDT 24
Peak memory 203024 kb
Host smart-133171e7-bec0-4d67-abcd-38470b9f5b42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2929964226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2929964226
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4259203821
Short name T741
Test name
Test status
Simulation time 18212677637 ps
CPU time 83.73 seconds
Started Apr 21 12:28:54 PM PDT 24
Finished Apr 21 12:30:18 PM PDT 24
Peak memory 203420 kb
Host smart-2bd781c3-41c0-4f89-92a6-7d8ec738e152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4259203821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4259203821
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2596501742
Short name T706
Test name
Test status
Simulation time 1319571632 ps
CPU time 113.66 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:30:50 PM PDT 24
Peak memory 204264 kb
Host smart-cd865fcd-777c-410b-9e75-f1972c7e6584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596501742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.2596501742
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3792875664
Short name T664
Test name
Test status
Simulation time 168478377 ps
CPU time 13.25 seconds
Started Apr 21 12:29:01 PM PDT 24
Finished Apr 21 12:29:14 PM PDT 24
Peak memory 201876 kb
Host smart-60b3540e-0079-44cd-83b6-a08127ef3f09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3792875664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.3792875664
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2329590475
Short name T790
Test name
Test status
Simulation time 248561094 ps
CPU time 7.39 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:29:06 PM PDT 24
Peak memory 201784 kb
Host smart-462e9953-33d5-4f2a-aabb-91070f07a217
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2329590475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2329590475
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1587070219
Short name T223
Test name
Test status
Simulation time 3001059775 ps
CPU time 12.11 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201924 kb
Host smart-35e365f5-9f57-4cba-8068-3a38b21ffd51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1587070219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1587070219
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1160820949
Short name T165
Test name
Test status
Simulation time 21500633701 ps
CPU time 140.47 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:31:19 PM PDT 24
Peak memory 202016 kb
Host smart-8025a5d2-9c9f-40d5-b6bf-521dee956b42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1160820949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1160820949
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1955000516
Short name T478
Test name
Test status
Simulation time 160537465 ps
CPU time 2.85 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:04 PM PDT 24
Peak memory 201908 kb
Host smart-d0740d6b-fafd-482c-9b74-b8744a4c6bea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1955000516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1955000516
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.3880950844
Short name T711
Test name
Test status
Simulation time 185496510 ps
CPU time 6.1 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 201868 kb
Host smart-beb90c3d-660d-45bf-be25-cc06f9163d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3880950844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3880950844
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1297797470
Short name T794
Test name
Test status
Simulation time 621275637 ps
CPU time 5.8 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:06 PM PDT 24
Peak memory 201916 kb
Host smart-2c9d8565-3bad-443c-820b-71fd4ca04e09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1297797470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1297797470
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3602656447
Short name T555
Test name
Test status
Simulation time 21502977623 ps
CPU time 35.35 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:31 PM PDT 24
Peak memory 201940 kb
Host smart-c067c8f9-b470-4e63-a9c0-bea1d4f0079c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602656447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3602656447
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2201550348
Short name T29
Test name
Test status
Simulation time 13932358650 ps
CPU time 100.06 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:30:39 PM PDT 24
Peak memory 201920 kb
Host smart-f2afa496-b4b8-4ed7-8b90-f6b6b93ff268
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2201550348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2201550348
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1780698202
Short name T709
Test name
Test status
Simulation time 119533989 ps
CPU time 5.24 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201892 kb
Host smart-c352aed8-2824-4031-99dd-a5fb5a55effa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780698202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1780698202
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.445853922
Short name T632
Test name
Test status
Simulation time 1081239319 ps
CPU time 12.47 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:09 PM PDT 24
Peak memory 201840 kb
Host smart-da5c198d-053e-46b4-ac12-5dd885e18aaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=445853922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.445853922
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.778177882
Short name T63
Test name
Test status
Simulation time 89618265 ps
CPU time 1.24 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:56 PM PDT 24
Peak memory 201836 kb
Host smart-636410b2-86a1-402f-8485-21d4b6220737
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=778177882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.778177882
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.46196360
Short name T494
Test name
Test status
Simulation time 7135621806 ps
CPU time 11.75 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 202040 kb
Host smart-575dbee0-3427-4168-b034-fc26c617ae8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=46196360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.46196360
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.426661023
Short name T589
Test name
Test status
Simulation time 1521750744 ps
CPU time 11.44 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:29:10 PM PDT 24
Peak memory 201800 kb
Host smart-ed1a9db8-0787-494c-a7cd-9f99cbca4184
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=426661023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.426661023
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1708923101
Short name T463
Test name
Test status
Simulation time 13680307 ps
CPU time 1.03 seconds
Started Apr 21 12:28:53 PM PDT 24
Finished Apr 21 12:28:54 PM PDT 24
Peak memory 201784 kb
Host smart-3e2ca1d5-de92-4bf9-a6af-23c2008d5c14
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708923101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1708923101
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.3261419425
Short name T124
Test name
Test status
Simulation time 7184414915 ps
CPU time 97.21 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:30:34 PM PDT 24
Peak memory 203028 kb
Host smart-a7e55e16-ff79-4867-889d-09903ac3bde6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3261419425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3261419425
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.686747884
Short name T364
Test name
Test status
Simulation time 504992178 ps
CPU time 37.35 seconds
Started Apr 21 12:28:56 PM PDT 24
Finished Apr 21 12:29:34 PM PDT 24
Peak memory 201812 kb
Host smart-09829129-a7b9-4602-8270-4bf0f4217c8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=686747884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.686747884
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2802446750
Short name T524
Test name
Test status
Simulation time 542761402 ps
CPU time 56.55 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 204204 kb
Host smart-c7c4e3ce-175b-456f-90cd-77ff68fadfee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2802446750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.2802446750
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.878383952
Short name T703
Test name
Test status
Simulation time 121065362 ps
CPU time 4.91 seconds
Started Apr 21 12:28:57 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201904 kb
Host smart-b4430092-62cc-4268-b5ad-fa378e720149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=878383952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.878383952
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.4046748315
Short name T846
Test name
Test status
Simulation time 1188143556 ps
CPU time 6.02 seconds
Started Apr 21 12:29:00 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201820 kb
Host smart-855b6ad7-d31b-4d5c-b427-b390f1ff54e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046748315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4046748315
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.314605009
Short name T621
Test name
Test status
Simulation time 359667660 ps
CPU time 4.61 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201888 kb
Host smart-4b1f1196-1a1b-42c8-82e2-73aad3992605
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=314605009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.314605009
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.121205430
Short name T259
Test name
Test status
Simulation time 59641194 ps
CPU time 4.37 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:29:08 PM PDT 24
Peak memory 201796 kb
Host smart-31613e8d-26e0-4ea2-80ea-11efd242c2e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=121205430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.121205430
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1421984094
Short name T879
Test name
Test status
Simulation time 139755663 ps
CPU time 2.75 seconds
Started Apr 21 12:28:59 PM PDT 24
Finished Apr 21 12:29:02 PM PDT 24
Peak memory 201708 kb
Host smart-86b3dfd5-a85d-46c8-b2e7-b34ed047d995
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1421984094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1421984094
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1571094675
Short name T22
Test name
Test status
Simulation time 70163499026 ps
CPU time 63.48 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:30:07 PM PDT 24
Peak memory 202024 kb
Host smart-816e0d4e-5ba9-418b-be65-712e1f0ff066
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571094675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1571094675
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.525166433
Short name T128
Test name
Test status
Simulation time 35431729179 ps
CPU time 144.97 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:31:27 PM PDT 24
Peak memory 202012 kb
Host smart-893bacba-5897-4213-9a46-48a621e8be69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=525166433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.525166433
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2418301092
Short name T199
Test name
Test status
Simulation time 41372985 ps
CPU time 3.58 seconds
Started Apr 21 12:28:59 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 201900 kb
Host smart-c8f6706f-95d4-4a67-aea4-0a7ee676b6c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418301092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2418301092
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.934342145
Short name T70
Test name
Test status
Simulation time 560972899 ps
CPU time 8.58 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:12 PM PDT 24
Peak memory 201800 kb
Host smart-f6a103ba-1e0a-4f6c-8431-7f644abd4946
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=934342145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.934342145
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.2273581324
Short name T420
Test name
Test status
Simulation time 13272565 ps
CPU time 0.98 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:28:56 PM PDT 24
Peak memory 201748 kb
Host smart-7fe35e23-0755-4305-9c56-b49618b851f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2273581324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2273581324
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4074087377
Short name T403
Test name
Test status
Simulation time 3008970591 ps
CPU time 8.52 seconds
Started Apr 21 12:28:55 PM PDT 24
Finished Apr 21 12:29:04 PM PDT 24
Peak memory 201864 kb
Host smart-ca0ee985-1885-457e-b6c2-5fb319e70f9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074087377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4074087377
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.4129856359
Short name T514
Test name
Test status
Simulation time 2054135339 ps
CPU time 7.18 seconds
Started Apr 21 12:29:01 PM PDT 24
Finished Apr 21 12:29:09 PM PDT 24
Peak memory 201900 kb
Host smart-714d50e8-82ee-41b8-bac5-2c2a81ea7bdc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4129856359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4129856359
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.864870169
Short name T815
Test name
Test status
Simulation time 11161276 ps
CPU time 1.28 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:29:00 PM PDT 24
Peak memory 201796 kb
Host smart-7b8ebc67-3ed1-48ff-801b-7b72e62725a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864870169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.864870169
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.1205398737
Short name T87
Test name
Test status
Simulation time 5133299354 ps
CPU time 86.2 seconds
Started Apr 21 12:29:02 PM PDT 24
Finished Apr 21 12:30:29 PM PDT 24
Peak memory 202968 kb
Host smart-c3fa1a08-a36d-48ff-8ac5-009b9999a390
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1205398737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1205398737
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1553360784
Short name T302
Test name
Test status
Simulation time 207168939 ps
CPU time 3.83 seconds
Started Apr 21 12:28:59 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 201796 kb
Host smart-851a19ee-69be-4f00-885f-02096a784f66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1553360784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1553360784
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1230938077
Short name T12
Test name
Test status
Simulation time 3107097408 ps
CPU time 103.27 seconds
Started Apr 21 12:29:06 PM PDT 24
Finished Apr 21 12:30:50 PM PDT 24
Peak memory 205156 kb
Host smart-ab564640-3f34-4e19-a22a-8e2e9693862f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230938077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1230938077
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1280703468
Short name T246
Test name
Test status
Simulation time 1008616650 ps
CPU time 63.62 seconds
Started Apr 21 12:28:58 PM PDT 24
Finished Apr 21 12:30:03 PM PDT 24
Peak memory 204464 kb
Host smart-4ca5b636-98b3-464a-8b49-b3124911c492
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1280703468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.1280703468
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4023845976
Short name T772
Test name
Test status
Simulation time 165742277 ps
CPU time 3.81 seconds
Started Apr 21 12:29:03 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 201836 kb
Host smart-dafc71f8-f367-4db7-a5ce-fcfc0cd1bb1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023845976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4023845976
Directory /workspace/9.xbar_unmapped_addr/latest
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