Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 398 1 T3 6 T14 1 T15 8
all_values[1] 414 1 T3 5 T4 1 T14 1
all_values[2] 394 1 T3 3 T15 10 T24 2
all_values[3] 401 1 T1 1 T3 8 T4 2
all_values[4] 425 1 T3 5 T14 1 T15 8
all_values[5] 435 1 T3 7 T14 1 T15 8
all_values[6] 409 1 T3 6 T15 5 T25 1
all_values[7] 447 1 T3 8 T4 1 T14 1
all_values[8] 413 1 T3 6 T15 3 T18 1
all_values[9] 404 1 T3 6 T15 2 T24 2
all_values[10] 402 1 T3 7 T15 1 T18 1
all_values[11] 421 1 T3 5 T4 1 T15 4
all_values[12] 397 1 T3 4 T14 1 T15 3
all_values[13] 423 1 T1 1 T3 6 T4 2
all_values[14] 417 1 T3 6 T4 1 T15 6
all_values[15] 368 1 T1 1 T3 2 T15 6
all_values[16] 413 1 T3 3 T4 2 T14 1
all_values[17] 437 1 T3 5 T15 8 T131 1
all_values[18] 402 1 T3 6 T15 6 T24 1
all_values[19] 392 1 T3 9 T15 1 T18 1
all_values[20] 422 1 T3 4 T15 2 T24 1
all_values[21] 397 1 T3 3 T14 1 T15 4
all_values[22] 371 1 T3 5 T4 1 T14 1
all_values[23] 440 1 T3 7 T15 5 T18 1
all_values[24] 419 1 T3 5 T14 1 T15 4
all_values[25] 391 1 T3 5 T14 1 T15 5
all_values[26] 408 1 T3 4 T15 5 T28 1

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