Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T4	2		T15	8		T50	7
all_values[1]	435	1			T15	7		T50	2		T188	4
all_values[2]	455	1			T1	2		T15	8		T50	3
all_values[3]	453	1			T15	4		T50	2		T188	3
all_values[4]	469	1			T1	2		T15	5		T50	4
all_values[5]	481	1			T1	2		T4	1		T15	7
all_values[6]	415	1			T15	3		T50	1		T188	6
all_values[7]	442	1			T1	1		T3	1		T15	3
all_values[8]	438	1			T3	1		T4	1		T15	5
all_values[9]	432	1			T1	1		T15	1		T50	4
all_values[10]	436	1			T15	2		T50	3		T188	3
all_values[11]	464	1			T1	2		T15	2		T50	3
all_values[12]	474	1			T1	1		T3	1		T4	1
all_values[13]	419	1			T15	10		T50	3		T188	3
all_values[14]	476	1			T15	4		T50	3		T188	1
all_values[15]	428	1			T3	1		T15	5		T50	6
all_values[16]	410	1			T15	8		T50	2		T33	1
all_values[17]	475	1			T1	3		T15	8		T50	2
all_values[18]	420	1			T15	2		T50	7		T188	1
all_values[19]	483	1			T1	1		T15	9		T50	2
all_values[20]	447	1			T1	1		T3	1		T15	6
all_values[21]	445	1			T1	1		T4	1		T15	4
all_values[22]	466	1			T1	2		T4	1		T15	9
all_values[23]	460	1			T3	1		T15	5		T50	4
all_values[24]	436	1			T1	1		T15	4		T50	1
all_values[25]	416	1			T1	3		T15	6		T50	6
all_values[26]	437	1			T4	1		T15	5		T50	6