Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	504	1			T4	1		T13	1		T12	1
all_values[1]	467	1			T4	1		T17	1		T55	1
all_values[2]	434	1			T4	2		T17	1		T55	4
all_values[3]	435	1			T4	1		T17	2		T55	2
all_values[4]	455	1			T12	1		T55	4		T34	8
all_values[5]	430	1			T4	1		T13	1		T55	2
all_values[6]	448	1			T4	2		T12	1		T17	1
all_values[7]	436	1			T4	2		T12	2		T17	1
all_values[8]	466	1			T4	2		T12	1		T55	1
all_values[9]	478	1			T4	3		T17	2		T34	9
all_values[10]	413	1			T4	4		T17	1		T55	1
all_values[11]	428	1			T17	1		T55	2		T34	2
all_values[12]	476	1			T4	1		T13	1		T17	2
all_values[13]	470	1			T4	1		T55	3		T34	7
all_values[14]	464	1			T12	1		T17	1		T34	6
all_values[15]	450	1			T55	3		T34	8		T37	1
all_values[16]	489	1			T4	2		T17	1		T55	2
all_values[17]	495	1			T12	1		T17	1		T55	2
all_values[18]	427	1			T4	3		T17	1		T55	2
all_values[19]	481	1			T4	2		T12	1		T17	1
all_values[20]	456	1			T4	4		T17	1		T55	1
all_values[21]	462	1			T17	1		T55	2		T34	3
all_values[22]	484	1			T4	3		T17	2		T34	1
all_values[23]	497	1			T4	1		T34	4		T35	1
all_values[24]	504	1			T4	3		T12	1		T34	7
all_values[25]	454	1			T4	1		T12	1		T55	2
all_values[26]	440	1			T4	1		T12	2		T55	2